P-GaN gate and manufacturing method thereof
By growing the cap layer during the production process of the P-GaN gate and using its protection when etching the TiN layer, the etching damage problem is solved, and the reliability and surface quality of the device are improved.
Patent Information
- Application Number
- CN202510410305.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-06-17
AI Technical Summary
The existing P-GaN gate manufacturing methods are prone to etching damage during the etching process, affecting device performance.
The cap layer is grown in the MOCVD reactor and the protection of the cap layer is used to avoid damage to the P-GaN layer when etching the TiN layer, and the electric field edge distribution is adjusted to improve the gate resistance to breakdown.
The surface quality of the P-GaN gate and the reliability of the device are improved, and the negative impact of TiN layer production on on-resistance, maximum current and reliability are avoided.
Smart Images
Figure CN120166760A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of HEMT, and particularly relates to a P-GaN gate and a manufacturing method thereof. Background Art
[0002] With the development of semiconductor materials, semiconductor materials have evolved from the first-generation semiconductor materials represented by silicon, to the second-generation semiconductor materials represented by gallium arsenide and indium phosphide, and now to the third-generation wide-bandgap semiconductor materials represented by gallium nitride (GaN) and silicon carbide (SiC). Among them, HEMT (High Electron Mobility Transistor) is a typical device using gallium nitride materials.
[0003] Existing conventional HEMTs are all depletion-type. When actually used, a negative gate voltage needs to be applied to the gate to turn off the device, which increases the design cost during chip design. Therefore, how to achieve an enhancement-mode GaN HEMT has always been a difficult point in the research of this field.
[0004] Currently, researchers use a series of methods such as recessed gate technology, P-GaN gate technology, fluoride ion implantation technology, and Cascode structure to achieve enhancement-mode HEMT devices.
[0005] However, in the actual implementation of recessed gate technology, the etching depth needs to be precisely controlled, and the etching depth greatly reduces the electron mobility at the channel, resulting in device performance degradation; fluoride ion implantation technology also has great instability; in addition, the Cascode structure increases the complexity of the circuit and requires silicon-based devices for assistance, limiting the application environment of the device. Compared with the above three technologies, P-GaN gate technology is relatively mature and has been commercialized.
[0006] In the existing P-GaN gate technology, when preparing the p-GaN gate, etching damage will occur during the etching of p-GaN, and the surface roughness of the AlGaN layer in the source-drain region after etching is relatively large, which has a negative impact on the on-resistance, maximum current, and reliability of the device, thus affecting the device performance. Summary of the Invention
[0007] In view of the deficiencies of the background art, the present invention provides a P-GaN gate and a manufacturing method thereof. The technical problem to be solved is that the existing P-GaN gate manufacturing method will cause etching damage to the P-GaN gate, affecting the device performance.
[0008] To solve the above technical problems, in a first aspect, the present invention provides the following technical solution: a P-GaN gate includes a GaN channel layer, an AlGaN barrier layer is provided on the upper surface of the GaN channel layer, a P-GaN layer is provided in a gate preset area on the upper surface of the AlGaN barrier layer, a capping layer is provided on the upper surface of the P-GaN layer, and a groove is provided in the capping layer, the groove extends downward from the upper surface of the capping layer to the upper surface of the P-GaN layer, and a TiN layer is provided on the upper surface of the capping layer and in the groove.
[0009] In a certain embodiment of the first aspect, the material of the capping layer is Si3N4, and the thickness of the capping layer is between 3 nm and 500 nm.
[0010] In a certain embodiment of the first aspect, the thickness of the TiN layer is between 10 nm and 200 nm.
[0011] In a second aspect, the present invention also provides a manufacturing method of a P-GaN gate, including the following steps: S1: In an MOCVD reactor, after growing a P-GaN layer on the upper surface of the AlGaN barrier layer of the stacked GaN channel layer and AlGaN barrier layer, in-situ grow a capping layer on the upper surface of the P-GaN layer; S2: In an MOCVD reactor, activate the P-GaN layer; S3: Make a first photoresist layer on the upper surface of the capping layer, and then transfer the preset pattern on the mask plate to the first photoresist layer through an exposure and development process; S4: Etch the capping layer along the preset pattern position on the first photoresist layer, and the etching end point is the upper surface of the P-GaN layer; S5: Remove the first photoresist layer; S6: Deposit a TiN layer on the upper surface of the capping layer and the P-GaN layer corresponding to the preset pattern; S7: Deposit a dielectric layer on the upper surface of the TiN layer; S8: Etch the dielectric layer to remove the dielectric layer corresponding to the working area on the P-GaN layer; S9: Etch the corresponding TiN layer along the removed dielectric layer; S10: Etch the corresponding capping layer along the removed TiN layer; S11: Etch the corresponding P-GaN layer along the removed capping layer; S12: Etch the remaining dielectric layer.
[0012] In a certain embodiment of the second aspect, the material of the capping layer grown in step S1 is Si3N4; the growth thickness of the capping layer is between 3 nm and 500 nm, the growth temperature is between 600 °C and 1100 °C, and the growth pressure is between 40 torr and 500 torr; during actual growth, in an atmosphere of N2 and / or H2, SiH4 and NH3 are reacted to form Si3N4.
[0013] In a certain embodiment of the second aspect, in step S2, the temperature in the MOCVD reactor is reduced to 800 °C, and then the P-GaN layer is activated in a pure N2 atmosphere.
[0014] In a certain embodiment of the second aspect, in step S6, PVD is used to deposit the TiN layer, where the deposition thickness of the TiN layer is between 10 nm and 200 nm, the deposition temperature is between 200 °C and 400 °C, and the deposition pressure is between 40 torr and 500 torr.
[0015] In a certain embodiment of the second aspect, in step S7, PEVCD is used to deposit the dielectric layer, and the dielectric layer is a single SiO2 layer or a single Si3N4 layer or a composite layer formed by sequentially laminating an SiO2 layer and an Si3N4 layer; the deposition thickness of the dielectric layer is between 100 nm and 2000 nm, and the deposition temperature is between 300 °C and 500 °C.
[0016] In a certain embodiment of the second aspect, in step S8, an ICP device is used for etching, and the etching gas includes SF6; In step S9, Cl2 or BCl3 is used for ICP etching of the TiN layer; In step S10, the capping layer is etched by using SF6 gas through ICP.
[0017] In a certain embodiment of the second aspect, in step S12, the remaining dielectric layer is etched away by using a BHF wet etching process.
[0018] The beneficial effects of the present invention compared with the prior art are as follows: First, for the manufacturing method of the present invention, after the P-GaN layer is fabricated in MOCVD, the capping layer is grown in situ, which simplifies the manufacturing process and can improve the manufacturing efficiency; Second, when etching the TiN layer, through the protection of the capping layer, on the one hand, it can ensure that the contact surface between the P-GaN layer in the gate preset area and the capping layer is not damaged, and on the other hand, it can adjust the electric field edge distribution of the P-GaN layer in the gate preset area, improve the gate breakdown resistance, and thus improve the reliability of the device; Finally, the present invention provides a capping layer. When the TiN layer is fabricated, the capping layer can protect the surface of the P-GaN layer in the source and drain regions of the device from being affected by the fabrication of the TiN layer, thereby protecting the AlGaN barrier layer, improving the surface quality of the AlGaN barrier layer, and avoiding the impact of the TiN layer fabrication on the on-resistance, maximum current, and reliability of the device. For the P-GaN of the present invention, after fabrication, the surface quality of the P-GaN layer and the AlGaN barrier layer is high, and the reliability of the device is good. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 Schematic structural diagram of the present invention in the embodiment; Figure 2 Schematic structural diagram after the capping layer is fabricated; Figure 3 For Figure 2 Schematic structural diagram after the first photoresist layer is fabricated; Figure 4 For Figure 3 Schematic structural diagram after pattern transfer; Figure 5 For Figure 4 Schematic structural diagram after the capping layer is etched; Figure 6 For removing Figure 5 Schematic structural diagram after the first photoresist layer on is removed; Figure 7 For Figure 6 Schematic structural diagram after the TiN layer is fabricated; Figure 8 For Figure 7 Schematic structural diagram after the dielectric layer is fabricated; Figure 9 For Figure 8 Schematic structural diagram after the second photoresist layer is fabricated; Figure 10 For Figure 9 Schematic structural diagram after the dielectric layer is etched; Figure 11 For Figure 10 Schematic structural diagram after the TiN layer is etched; Figure 12 For Figure 11 Schematic structural diagram after the capping layer is etched; Figure 13 For Figure 12 Schematic structural diagram after the P-GaN layer is etched; Figure 14 Schematic structural diagram of the composite dielectric layer in the embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0020] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present invention in a schematic manner, so they only show the components related to the present invention.
[0021] Embodiment 1 As Figure 1 shown, this embodiment provides a P-GaN gate, including a GaN channel layer 1. An AlGaN barrier layer 2 is provided on the upper surface of the GaN channel layer 1. A P-GaN layer 3 is provided in the gate preset area on the upper surface of the AlGaN barrier layer 2. A capping layer 4 is provided on the upper surface of the P-GaN layer 3, and a groove is provided on the capping layer 4. The groove extends downward from the upper surface of the capping layer to the upper surface of the P-GaN layer. A TiN layer 5 is provided on the upper surface of the capping layer 4 and in the groove.
[0022] It should be noted that although the groove is not marked in the attached Figure 1 drawings, for those skilled in the art, the position of the groove can be known based on a part of the TiN layer 5 on the AlGaN barrier layer 2.
[0023] In addition, the upper surface of the AlGaN barrier layer 2 can be divided into a working area and a gate preset area. Among them, the area corresponding to the P-GaN layer 3 in the attached Figure 1 drawings is the gate preset area, and the remaining area on the upper surface of the AlGaN barrier layer 2 is the working area.
[0024] Specifically, in this embodiment, the material of the capping layer 4 is Si3N4, and the thickness of the capping layer 4 is between 3 nm and 500 nm. Exemplarily, the thickness of the capping layer 5 can be 5 nm, 10 nm, or 20 nm.
[0025] Specifically, in this embodiment, the thickness of the TiN layer 5 is between 10 nm and 200 nm. Exemplarily, the thickness of the TiN layer 5 can be 30 nm or 50 nm.
[0026] In addition, the beneficial effects of the P-GaN gate in this embodiment compared with the existing structure are described in Embodiment 2.
[0027] Embodiment 2 In order to make the surface quality of the fabricated P-GaN gate better and the reliability of the device higher, this embodiment provides a method for fabricating a P-GaN gate, including the following steps: S1: In a MOCVD reactor, after growing the P-GaN layer 3 on the upper surface of the AlGaN barrier layer 2 of the stacked GaN channel layer 1 and AlGaN barrier layer 2, the capping layer 4 is grown in situ on the upper surface of the P-GaN layer 3; The device structure after growing the capping layer 4 is as Figure 2as shown; Specifically, in step S1, the material of the capping layer 4 grown in step S1 is Si3N4; the growth thickness of the capping layer 4 is between 3 nm and 500 nm, the growth temperature is between 600 °C and 1100 °C, and the growth pressure is between 40 torr and 500 torr; during actual growth, in an atmosphere of N2 and / or H2, SiH4 and NH3 are reacted to form Si3N4; Exemplarily, during actual implementation, the growth thickness of the capping layer 4 can be 5 nm, 10 nm or 20 nm; During actual implementation, in step S1, by in-situ depositing the capping layer 4 in the MOCVD reactor, on the one hand, the manufacturing process is simplified and the manufacturing efficiency is improved; on the other hand, in subsequent construction, the formation of the TiN layer of the gate and the etching of the P-GaN layer of the source / drain region can be achieved through a self-alignment process.
[0028] S2: Activate the P-GaN layer 3 in the MOCVD reactor; Specifically, in step S2, the temperature in the MOCVD reactor is reduced to 800 °C, and then the P-GaN layer is activated in a pure N2 atmosphere.
[0029] During actual activation, the method of the present invention first fabricates the capping layer 4, which can protect the surface of the P-GaN layer 3 from damage during the activation process, and can improve the material quality of the P-GaN layer 3, especially the quality of the surface morphology.
[0030] S3: Fabricate a first photoresist layer 8 on the upper surface of the capping layer 4. The structure of the fabricated first photoresist layer 8 is as Figure 3 shown, and then the preset pattern on the photomask plate is transferred to the first photoresist layer through an exposure and development process, thereby exposing the gate position on the P-GaN layer 3. The image after the transfer of the preset image is as Figure 4 shown.
[0031] Specifically, in step S3, the first photoresist layer 8 can be fabricated on the upper surface of the capping layer 4 by a spin coater, and the exposure and development process can use existing processes to achieve pattern transfer.
[0032] S4: Etch the capping layer 3 along the preset pattern position on the first photoresist layer 8, and the etching end point is the upper surface of the P-GaN layer 3; the structure of the etched capping layer 3 is as Figure 5 shown; Specifically, in step S4, the capping layer 4 can be etched by ICP using SF6 gas to expose the P-GaN layer 3 corresponding to the gate.
[0033] S5: Remove the first photoresist layer 8; the device structure after performing step S5 is asFigure 6 as shown
[0034] S6: Deposit a TiN layer 5 on the upper surfaces of the capping layer 4 and the P-GaN layer 3 corresponding to the preset pattern; The device structure after performing step S6 is as Figure 7 shown Specifically, in step S6, PVD is used to deposit the TiN layer 5, where the deposition thickness of the TiN layer 5 is between 10 nm and 200 nm, the deposition temperature is between 200 °C and 400 °C, and the deposition pressure is between 40 torr and 500 torr; Exemplarily, the deposition thickness of the TiN layer 5 can be 30 nm, 50 nm or 70 nm.
[0035] S7: Deposit a dielectric layer 6 on the upper surface of the TiN layer 5; The device structure after performing step S7 is as Figure 8 shown Specifically, in step S7, PEVCD is used to deposit the dielectric layer 6, and the dielectric layer 6 is a single SiO2 layer or a single Si3N4 layer or a composite layer formed by sequentially laminating an SiO2 layer and an Si3N4 layer. At this time, the structure of the composite layer is as Figure 14 shown; Where the deposition thickness of the dielectric layer 6 is between 100 nm and 2000 nm, and the deposition temperature is between 300 °C and 500.
[0036] S8: Etch the dielectric layer 6 to remove the dielectric layer 6 corresponding to the working area on the P-GaN layer 3; Specifically, in step S8, as Figure 9 shown, first fabricate a second photoresist layer 7 on the upper surface of the dielectric layer 6, then use the exposure and development process to transfer the area of the dielectric layer 6 to be removed to the second photoresist layer 7, and then use the second photoresist layer 7 as a mask to etch the dielectric layer 6. The structure of the dielectric layer 6 after etching is as Figure 10 shown, and finally remove the second photoresist layer 7; In addition, when etching the dielectric layer 6, an ICP device is used for etching, and the etching gas includes SF6. Since the etching rate of SF6 for the TiN layer 5 is low and the etching selectivity is large, it can be ensured that all the dielectric layer 6 to be etched can be etched completely.
[0037] S9: Etch the corresponding TiN layer 5 along the removed dielectric layer 6; The device structure after performing step S9 is as Figure 11 shown Specifically, in step S9, Cl2 or BCl3 is used to perform ICP etching on the TiN layer 5; It should be noted that Cl2 or BCl3 has a large etching selectivity for the capping layer 4, and it can be ensured that the TiN layer 5 to be etched can be completely etched; In addition, when etching the TiN layer 5, the capping layer 4 can prevent damage to the P-GaN layer 3. Without the in-situ protection of the capping layer 4, the surface of the P-GaN layer 3 will become rough during the etching process of the TiN layer 5, thereby affecting the surface roughness of the working area of the AlGaN barrier layer 2, and further affecting the current uniformity and reliability of the device.
[0038] S10: Etch the corresponding capping layer 4 along the removed TiN layer 5; The schematic diagram of the device structure after performing step S10 is as Figure 12 shown; In actual implementation, the self-alignment process in step S9 can be continued to etch the capping layer 4. More specifically, the capping layer 4 can be etched by ICP using SF6 gas.
[0039] S11: Etch the corresponding P-GaN layer along the removed capping layer; The device structure after performing step S11 is as Figure 13 shown.
[0040] S12: Etch the remaining dielectric layer; Specifically, in step S12, the remaining dielectric layer is etched using the BHF wet etching process. At this time, the corresponding device structure is as Figure 1 shown.
[0041] Combining the above content, in the manufacturing method of the present invention, the capping layer 4 is grown in-situ after the P-GaN layer 3 is fabricated in MOCVD, which simplifies the manufacturing process and improves the manufacturing efficiency; Secondly, when etching the TiN layer 5, through the protection of the capping layer 4, on the one hand, it can ensure that the contact surface between the P-GaN layer 3 in the gate preset area and the capping layer 4 is not damaged. On the other hand, it can adjust the electric field edge distribution of the P-GaN layer 3 in the gate preset area, improve the gate breakdown resistance, and thus improve the reliability of the device; Finally, in the present invention, by setting the capping layer 4, when fabricating the TiN layer 5, through the protection of the capping layer 4, the surface of the P-GaN layer in the source-drain region of the device can be prevented from being affected by the fabrication of the TiN layer 5, thereby protecting the AlGaN barrier layer, improving the surface quality of the AlGaN barrier layer, and avoiding the influence of the TiN layer fabrication on the on-resistance, maximum current, and reliability of the device.
[0042] Based on the inspiration of the present invention, through the above description, relevant workers can make various changes and modifications within the scope of not deviating from the technical idea of the present invention. The technical scope of the present invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.
Claims
1. A P-GaN gate, characterized in that: It comprises a GaN channel layer, wherein an AlGaN barrier layer is arranged on the upper surface of the GaN channel layer, a P-GaN layer is arranged in a gate preset region on the upper surface of the AlGaN barrier layer, a cap layer is arranged on the upper surface of the P-GaN layer, and a groove is arranged on the cap layer, the groove extends downward from the upper surface of the cap layer to the upper surface of the P-GaN layer, and a TiN layer is arranged on the upper surface of the cap layer and in the groove.
2. A P-GaN gate according to claim 1, characterized in that: The material of the capping layer is Si3N4, and the thickness of the capping layer is between 3nm and 500nm.
3. The P-GaN gate according to claim 1, characterized in that: The thickness of the TiN layer is between 10 nm and 200 nm.
4. A method for manufacturing a P-GaN gate, characterized in that: The following steps are involved: S1: in an MOCVD reactor, after a P-GaN layer is grown on an upper surface of an AlGaN barrier layer of a stacked GaN channel layer and an AlGaN barrier layer, a cap layer is in-situ grown on an upper surface of the P-GaN layer; S2: Activate the P-GaN layer in the MOCVD reactor; S3: forming a first photoresist layer on the upper surface of the cap layer, and then transferring the preset pattern on the mask plate to the first photoresist layer through an exposure and development process; S4: etching the cap layer along a preset pattern position on the first photoresist layer, with the etching end point being the upper surface of the P-GaN layer; S5: removing the first photoresist layer; S6: depositing a TiN layer on the upper surface of the cap layer and the P-GaN layer corresponding to the preset pattern; S7: depositing a dielectric layer on the upper surface of the TiN layer; S8: etching the dielectric layer to remove the dielectric layer corresponding to the working area on the P-GaN layer; S9: Etching away the corresponding TiN layer along the removed dielectric layer; S10: etching away the corresponding cap layer along the removed TiN layer; S11: Etching the corresponding P-GaN layer along the removed cap layer; S12: Etching away the remaining dielectric layer.
5. The method for manufacturing a P-GaN gate according to claim 4, characterized in that: The material of the capping layer grown in step S1 is Si3N4; the growth thickness of the capping layer is between 3nm and 500nm, the growth temperature is between 600℃ and 1100℃, and the growth pressure is between 40torr and 500torr; during the actual growth, SiH4 and NH3 are reacted to generate Si3N4 in an atmosphere of N2 and / or H2.
6. The method for manufacturing a P-GaN gate according to claim 4, characterized in that: In step S2, the temperature in the MOCVD reactor is lowered to 800°C, and then the P-GaN layer is activated in a pure N2 atmosphere.
7. The method for manufacturing a P-GaN gate according to claim 4, characterized in that: In step S6 , PVD is used to deposit a TiN layer, wherein the deposition thickness of the TiN layer is between 10 nm and 200 nm, the deposition temperature is between 200° C. and 400° C., and the deposition pressure is between 40 torr and 500 torr.
8. A method for manufacturing a P-GaN gate according to any one of claims 4 to 7, characterized in that: In step S7, PEVCD is used to deposit a dielectric layer, which is a single SiO2 layer or a single Si3N4 layer or a composite layer formed by sequentially stacking SiO2 layers and Si3N4 layers; wherein the deposition thickness of the dielectric layer is between 100nm and 2000nm, and the deposition temperature is between 300℃ and 500℃.
9. The method for manufacturing a P-GaN gate according to claim 8, characterized in that: In step S8, an ICP device is used for etching, wherein the etching gas includes SF6; In step S9, the TiN layer is ICP etched using Cl2 or BCl3; In step S10, the cap layer is ICP etched using SF6 gas.
10. The method for manufacturing a P-GaN gate according to claim 9, characterized in that: In step S12, the remaining dielectric layer is etched away using a BHF wet etching process.