Super junction power semiconductor device and method for manufacturing super junction power semiconductor device

Abstract

The present disclosure relates to a super junction power semiconductor device (20) comprising a substrate (1), a plurality of core structures (4) and a plurality of annular shell structures (5). Each core structure (4) has a cylindrical shape extending in a direction perpendicular to the main surface of the substrate (1) and comprises a first semiconductor material of a first conductivity type. Each shell structure (5) surrounds an outer side of one of the core structures (4) and comprises a second semiconductor material of a second conductivity type. The present disclosure further relates to a method (30) for manufacturing a super junction power semiconductor device (20).

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of manufacturing the same, and more particularly to a novel method that includes selectively grown superjunction nanostructures for power semiconductor devices. Background Art

[0002] Wide bandgap (WBG) semiconductor materials such as silicon carbide (SiC) have advantageous properties including high critical electric fields and electron mobility or high-frequency switching. Thus, they yield much larger Baliga figures of merit (BFOM) compared to commonly used semiconductor materials such as silicon, making them good candidates for power semiconductor devices such as power MISFETs. These advantages enable several applications for energy efficiency and power transportation.

[0003] Currently, most commercial power SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are based on cell designs with planar channels aligned to the silicon (Si) face, i.e., on the SiC (0001) wafer surface. However, the increase in junction FET (JFET) resistance as the injector is scaled down and the low inversion channel mobility impede the increase in current density in such switches.

[0004] As an alternative approach, trench MOSFETs including dry-etched U-shaped channels enable low on-resistance due to the lack of a JFET region and high cell density. Particularly for SiC channel devices, the trench MOSFET architecture allows optimizing carrier mobility by designing channels with respect to different crystal planes and improving gate dielectric layer control. Despite carrier transport using different crystal planes, when using conventional manufacturing techniques, the trench pitch and cell width of known trench MOSFET devices are still quite large. This in turn prohibits higher cell density and thus prohibits an increase in current density of the finished semiconductor power device. In addition, single-crystalline SiC wafers are relatively expensive, further hindering the widespread adoption of the above methods on a large scale.

[0005] Therefore, novel processing methods and device architectures that can achieve higher current in a smaller area, i.e., increase current density, are desirable. In addition, integrating such architectures in a wide range of widely available and price-competitive substrates such as Si, gallium nitride (GaN), 4H-SiC, or polycrystalline SiC substrates would be desirable. Summary of the Invention

[0006] Embodiments of the present disclosure relate to a superjunction power semiconductor device including a substrate, a plurality of core structures, and a plurality of annular shell structures, and a method of manufacturing a superjunction power semiconductor device.

[0007] According to a first aspect of the present disclosure, a superjunction power semiconductor device is provided. The device includes:

[0008] - a substrate;

[0009] - a plurality of core structures, each core structure having a cylindrical shape extending in a direction perpendicular to a main surface of the substrate and including a first semiconductor material of a first conductivity type; and

[0010] - a plurality of annular shell structures, each shell structure surrounding one of the core structures on an outer side thereof and including a second semiconductor material of a second conductivity type.

[0011] The proposed device concept is based on vertically oriented, preferably very narrow, superjunction structures that can be selectively grown from suitable semiconductor materials, including WBG semiconductor materials. Due to their small size and vertical orientation, these structures are also referred to as nanowires or nanocolumns. Such superjunction structures far exceed conventional trench designs and allow for improved pitch scaling (i.e., higher current on a smaller area) and integration on a variety of widely available substrates due to the proposed selective growth technique.

[0012] According to at least one embodiment, the device further includes a dielectric layer disposed on the main surface of the substrate. The plurality of shell structures surrounding the plurality of core structures are embedded in the dielectric layer. Embedding the superjunction structures in the dielectric layer has several advantages compared to conventional superjunction structures formed directly in a bulk semiconductor material. First, it reduces the amount of semiconductor material required to implement the device. Second, the individual superjunction structures are electrically insulated from each other. Third, at least a plurality of portions of the dielectric layer can also be used as a growth template for generating the core structures and / or the annular shell structures, and / or as a support structure for carrying terminal contacts.

[0013] According to at least one embodiment, the dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is disposed between the substrate and the second sublayer, and the first sublayer includes a plurality of channels between the substrate and the second sublayer. The second sublayer includes a lower portion of each of at least a plurality of the shell structures. The device further includes a plurality of plug structures, each plug structure including a third semiconductor material of a second conductivity type and disposed in a region of one of the channels to contact the main surface of the substrate and a corresponding one of the shell structures. The above structure realizes electrical contact between the shell structure and the substrate of the device. At the same time, the channels can be used to implement a defect filter.

[0014] According to at least one embodiment, the device further includes a plurality of channel regions formed in each of the shell structures, each channel region including a fourth semiconductor material of a first conductivity type and disposed in the control layer of the device. The device further includes at least one gate structure disposed in the control layer, the at least one gate structure being electrically insulated from each of the shell structures and surrounding at least a portion thereof. The above device includes a so-called fully surrounding gate structure, which provides very high electric field control over the channel regions. The channel regions can be used to implement various known power semiconductor switching units, such as MOSFETs.

[0015] According to different embodiments, the substrate can be one of a Si, SiC, or GaN semiconductor substrate. The first semiconductor material can include: a p-type semiconductor material, particularly Si; or a p-type WBG semiconductor material, particularly SiC, GaN, or gallium oxide (Ga x O y ), particularly gallium sesquioxide (Ga2O3). The second semiconductor material can include: an n-type semiconductor material, particularly Si; an n-type WBG semiconductor material, particularly SiC, GaN, Ga x O y , particularly Ga2O3; or n-type diamond.

[0016] The above substrate materials are widely available. At least some of these substrate materials are significantly cheaper than single-crystal SiC wafers. In addition, the specific semiconductor materials for the core end unit structures are also widely available and can be processed with conventional semiconductor processing equipment.

[0017] According to different embodiments, the core structure and / or the shell structure can extend in a direction perpendicular to the main surface of the substrate over a length of 1 to 100 μm, particularly over a length of 3 to 15 μm. The core structure can have a diameter of 25 nm to 5 μm, particularly 0.1 to 5 μm. The annular unit structure can have a thickness of 0.1 to 5 μm. A plurality of core structures can be arranged in a regular pattern, particularly in an array structure, and the spacing distance between the plurality of core structures is less than 1 μm and / or within a range of 1.1 to 2.5 times the total diameter of one of the core structures surrounded by one of the shell structures.

[0018] The above dimensions and configurations are suitable for manufacturing semiconductor power switching devices with high density, high voltage, and / or high current. For example, a length of 1 to 100 μm is suitable for implementing semiconductor switching devices with a switching voltage of 1.2 to 3.3 kV at the device level. A core structure with a diameter of approximately 25 nm is particularly suitable for heteroepitaxy, and a larger diameter is suitable for higher currents and / or homoepitaxy. The current density is also affected by the doping concentration of the semiconductor material used. Preferably, the wall thickness of the shell structure can be similar to the diameter of the core structure and / or the diameter of any plug structure, for example, having a ratio of 1:1.

[0019] In at least one embodiment, a plurality of core structures and / or a plurality of shell structures are electrically connected in parallel to form a multi-unit field effect transistor (FET), particularly a metal-insulator-semiconductor field effect transistor (MISFET), MOSFET, insulated gate bipolar transistor (IGBT), and / or JFET.

[0020] According to a second aspect of the present disclosure, a method for manufacturing a superjunction power semiconductor device is provided. The method includes:

[0021] - Providing a growth substrate;

[0022] - Providing a plurality of vertical growth masks on the growth substrate;

[0023] - Selectively growing a first semiconductor material in the plurality of vertical growth masks to form corresponding plurality of core structures in a direction perpendicular to the main surface of the growth substrate;

[0024] - At least partially removing the plurality of vertical growth masks, thereby exposing the vertical surfaces of the plurality of core structures; and

[0025] - Selectively growing a second semiconductor material on the vertical surfaces of the plurality of core structures to form corresponding plurality of shell structures surrounding the respective core structures.

[0026] Among other things, the above method steps enable the fabrication of a core-shell superjunction structure as detailed above with respect to the first aspect, for example, for implementing a nanowire-based superjunction power MOSFET.

[0027] Instead of fabricating the device in a conventional top-down manner, such as for manufacturing a conventional trench gate MOSFET, the disclosed manufacturing method is based on a bottom-up approach that is based on selective epitaxy. This in turn enables the advantageous use of materials in forming high-density power devices as detailed above with respect to the first aspect.

[0028] Multiple vertical growth masks can be formed in a two-step process. In at least one embodiment, in a first stage, a growth seed mask layer having a plurality of first openings is first formed, the plurality of first openings corresponding to the pitch distances between a plurality of core structures. Thereafter, a core structure mask layer having a plurality of second openings is formed, each second opening being disposed in a region corresponding to a respective first opening and being wider than the respective first opening. Such a bilayer structure enables the implementation of a defect filter for a subsequent selective growth stage. In addition, it allows for the removal of only an upper portion of the vertical growth mask, for example, by using different materials for the sublayers and performing selective etching.

[0029] Similarly, a plurality of core structures can also be formed in a two-step process. In at least one embodiment, in a first stage, a plurality of plug structures are formed by selectively growing a third semiconductor material, particularly n-type SiC, including impurities of a first conductivity type, directly on a growth substrate within a plurality of vertical growth masks. Thereafter, a main portion of the plurality of core structures is formed by selectively growing a first semiconductor material, particularly p-type SiC, including impurities of a second conductivity type, within the plurality of vertical growth masks, either as a separate step or in a continuous vertical growth process with a changed dopant profile.

[0030] In at least one embodiment, the formation of a plurality of shell structures includes: covering a top surface of the plurality of core structures with a growth-inhibiting material, the growth-inhibiting material being particularly one of silicon dioxide (SiO2), silicon nitride (SiN), or aluminum oxide (Al2O3); removing an upper portion of the plurality of vertical growth masks, particularly the core structure mask, such that a remaining lower portion of the plurality of vertical growth masks, particularly the growth seed mask, covers the growth substrate; and thereafter, forming a plurality of shell structures by selectively growing a second semiconductor material, particularly n-type SiC, including impurities of a first conductivity type, in a radial direction. The above steps enable a controlled radial growth of the shell structures.

[0031] The present disclosure includes several aspects of a novel architecture for high-density semiconductor devices, particularly superjunction power semiconductor devices. Each feature described with respect to one of these aspects is also disclosed herein with respect to the other aspects, even if the corresponding feature is not explicitly mentioned in the context of a particular aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The following drawings are provided for further understanding. In the drawings, elements having the same structure and / or function may be referenced by the same reference numerals, even if they are part of different embodiments and / or have different configurations. It will be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0033] Figure 1is a schematic cross-sectional view through a single cell of a power semiconductor switching device.

[0034] Figure 2 is a perspective view of a power semiconductor device including a plurality of nanocolumns.

[0035] Figures 3A to 3N Shows various stages of manufacturing a power semiconductor device.

[0036] Figure 4 Shows in the form of a flow chart the steps of a method for manufacturing a superjunction power semiconductor device. Detailed Description

[0037] Figure 1 Shows a cross-section through cell 10 of a power semiconductor device or a similar semiconductor device. A complete semiconductor device typically may include a relatively large number of similar cells, which are electrically connected in parallel to achieve the desired functions, including the desired rated current. However, for the sake of simplicity of presentation, Figure 1 only a single cell 10 is shown and described below.

[0038] Cell 10 includes a substrate 1, which acts as a carrier substrate and also provides a bottom electrical contact as described later.

[0039] A dielectric layer 2 is arranged on the upper main surface of the substrate 1. The dielectric layer 2 can be formed of SiO2 or any other suitable insulating material. In the described embodiment, the dielectric layer 2 includes several sublayers 2a to 2c as described later.

[0040] A superjunction structure 3 is embedded in the dielectric layer 2. The superjunction structure 3 includes a core structure 4 and a shell structure 5, the latter surrounding the former on the outside thereof. In the described embodiment, the core structure 4 has a cylindrical shape, which is surrounded by an annular shell structure. However, in other embodiments, an elongated, fin-shaped or striped core structure 4 may be surrounded by a corresponding shell structure. In the case where the superjunction structure 3 is substantially cylindrical, it is also referred to as a nanowire or a nanocolumn.

[0041] The core structure 4 is made of a first semiconductor material of a first conductivity type, in particular a WBG semiconductor material, such as p-type SiC. The shell structure 5 is made of a different second semiconductor material of a second conductivity type, such as n-type SiC. Preferably, most of the charge carriers in the superjunction structure 3 balance each other.

[0042] The superjunction structure 3 further includes a plug structure 6 at the lower end portion of the core structure 4. The plug structure 6 is made of a third semiconductor material of the second conductivity type. For example, the second semiconductor material and the third semiconductor material may be the same. The plug structure 6 electrically connects the material of the shell structure 5 to the material of the substrate 1. For this purpose, a relatively narrow channel or opening 13 is formed in the lowest sublayer 2a of the dielectric layer 2. The opening 13 can also serve as a defect filter for the semiconductor material of the superjunction structure 3 during the growth stage as described later.

[0043] The superjunction structure 3 further includes a channel region 7. The channel region 7 forms part of the shell structure 5. In Figure 1 the embodiment shown, the channel region 7 is arranged in the upper part of the annular shell structure 5. Since the channel region 7 can be used to control the current flow through the superjunction structure 3, the plane including the channel region 7 is also referred to as the control layer. The channel region 7 can have a thickness of 100 to 1000 nm. It can be formed by the following steps: injecting a suitable dopant substance (such as Al or B) into the upper part of the shell structure 5, for example, to form a p-type region within the n-type semiconductor material of the shell structure 5. This can be achieved, for example, by ion implantation.

[0044] The conductivity of the channel region 7 is controlled by the surrounding gate structure 8. The gate structure 8 should partially overlap the channel region 7 on both sides. It can have a thickness of 200 to 1500 nm. In the embodiment shown, the gate structure 8 is buried in the dielectric layer 2. In particular, it is arranged between the two upper sublayers 2b and 2c of the dielectric layer. The gate structure 8 is electrically insulated from the shell structure 5 including the channel region 7 by a relatively thin gate insulation portion 9. For example, the gate insulation portion 9 can be formed by a film produced by selective oxidation or deposition of an insulating material.

[0045] To contact the respective upper and lower end portions of the superjunction structure 3, a drain electrode 11 is formed on the lower second main surface of the substrate 1. Additionally, a source electrode 12 is formed on the upper surface of the cell 10, which upper surface includes the upper surface of the uppermost sublayer 2c of the dielectric layer 2 and the upper end portion of the superjunction structure 3 itself.

[0046] Figure 2 A perspective view of a power semiconductor device 20 is shown, which power semiconductor device includes a plurality of switching cells, such as those described above with respect to Figure 1The described unit 10. These switching units are arranged in a regular pattern, particularly in an array structure with a grid or pitch distance d. In the described embodiment, the pitch distance can be about 1 μm or less. Each unit includes the superjunction structure 3 detailed above. As previously discussed, these superjunction structures take the form of nanowires or nanocolumns. To achieve a high current density, the pitch distance d can be selected to be only slightly larger than the total diameter of the corresponding superjunction structure 3, for example, having a ratio of 1.1:1 to 2.5:1.

[0047] As can be seen in Figure 2 the front portion of, a single cylindrical gate structure 8 surrounds the channel region of each of the superjunction structures 3. These so-called fully-depleted surround gate structures 8 are interconnected by a metal layer 15. As detailed above, the fully-depleted surround gate structures 8 are embedded between a sublayer 2b and a sublayer 2c formed of a dielectric material. In the depicted embodiment, the metal layer 15 is thinner than the vertical thickness of the fully-depleted surround gate structures 8. However, it can also have the same thickness, thereby essentially causing the homogeneous metal layer 15 to act as a common gate structure 8 for all the superjunction structures 3.

[0048] In Figure 2 the embodiment shown, the upper end portions of the superjunction structures 3 slightly extend beyond the top surface of the uppermost sublayer 2c of the dielectric material. These end portions are directly embedded in the metal material of the source electrode 12 formed thereon. Outside the array of the superjunction structures 3, the dielectric material is even thicker and forms a termination region 16. A gate runner 17 is formed on the upper surface of the termination region 16, which serves as an external contact for the metal layer 15 and the gate structure 8.

[0049] Figure 2 It is further shown that the substrate 1 can include a plurality of sublayers. In the shown embodiment, the lower sublayer 1a can be formed of a wafer material (such as a silicon wafer). On its upper surface, an epitaxial growth layer forms a second, upper sublayer 1b. For example, polycrystalline SiC can be grown on the lower sublayer 1a as a seed material for growing the superjunction structures 3. In this case, the upper sublayer 1b filters out growth defects. In other embodiments, the upper sublayer 1b itself can form part of a finished semiconductor device 20. For example, the upper sublayer 1b can act as part of a drift layer. In still other embodiments, the upper sublayer 1b can be completely omitted.

[0050] Figures 3A to 3N Stages of manufacturing a superjunction semiconductor device (such as Figure 2 the superjunction power semiconductor device 20 shown in

[0051] In Figure 3AIn the first stage shown, a substrate 1 is provided. As detailed above, the substrate 1 itself includes two sub-layers 1a and 1b. In the described embodiment, the first sub-layer 1a is a silicon wafer. The sub-layer 1b is an epitaxially grown silicon carbide layer. The substrate 1 is covered with a first dielectric layer 21. As Figure 1 shown, the first dielectric layer 21 covers the upper surface of the sub-layer 1b of the substrate 1. The first dielectric layer 21 may consist essentially of silicon oxide SiO x (specifically SiO2), silicon nitride SiN, or Al2O3.

[0052] As Figure 3B shown, multiple portions of the first dielectric layer 21 may be removed to form a number of openings 13. The openings 13 may be formed at regular intervals to form an array or other regular structure on the upper surface of the substrate 1. Conventional photolithography, for example, may be used to form such openings 13. Alternatively, dielectric material may be deposited only in the regions between the intended openings 13 using, for example, an appropriate selective deposition method. The material of the underlying substrate 1 or its uppermost sub-layer 1b serves as a growth seed. In the described embodiment, the openings 13 may have a cross-section of 25 nm. Channels of this diameter effectively serve as defect filters for selectively growing a core structure on a substrate comprising different semiconductor materials and / or crystal configurations, for example, for growing a SiC superjunction structure on a Si wafer using heteroepitaxy. Thus, the first dielectric layer 21 is also referred to as a growth seed mask layer. In the case of using homoepitaxy, for example, in order to grow a SiC superjunction structure on a SiC wafer or epitaxial layer, the openings 13 may be wider and may correspond, for example, in diameter to the diameter of the core structure 4 to be formed later.

[0053] Figure 3C shows a further stage of the manufacturing process. At this stage, the upper surface of the device under manufacture has been covered with a dielectric material to form a second dielectric layer 22. The second dielectric layer 22 is used to form a growth mask for the actual core structure and is therefore also referred to as a core structure mask layer. The second dielectric layer 22 may consist essentially of SiO x (specifically SiO2), SiN or Al2O3. If selective etching is employed later, the materials of the first dielectric layer 21 and the second dielectric layer may be different. The second dielectric layer 22 may be planarized using commonly known semiconductor processing methods.

[0054] Figure 3D shows the situation after the material of the second dielectric layer 22 has been structured. This may be achieved, for example, using conventional photolithography and selective etching. As can be seen in Figure 3DAs can be seen, a number of hollow vertically growing templates or masks 23 are formed. The vertically growing mask 23 includes an opening 13 in the first dielectric layer 21 and a wider opening 24 in the second dielectric layer 22. The vertically growing mask 23 is used to selectively grow a suitable semiconductor material, such as a WBG semiconductor material, which will later form the core structure 4.

[0055] In Figure 3E the first selective growth stage shown, the plug structure 6 is formed by selective area epitaxy. This can be achieved in particular by selectively growing (i.e., depositing) the semiconductor material only inside the vertically growing mask 23, while growth is inhibited in other areas covered by the material of the growth template (i.e., the first dielectric layer 21 and the second dielectric layer 22).

[0056] As shown, the plug structure 6 is grown inside the bottom portions of the opening 13 in the first dielectric layer 21 and the opening 24 in the second dielectric layer 22. In the described embodiment, the plug structure 6 is formed by depositing an n-type SiC material.

[0057] Thereafter, the remainder of the core structure 4 is grown on the upper end portion of the plug structure 6. The growth of the main part 4a of the core structure 4 can be implemented as a separate selective growth step or can be carried out with a modified dopant profile in a continuous selective growth stage. In the described embodiment, a p-type semiconductor material is selectively grown to form the main part 4a of the core structure 4. Figure 3F The finished core structure 4 is shown in

[0058] In Figure 3G the situation shown, the upper end portion of the core structure 4 has been capped with a capping element 25. In the described embodiment, this is achieved by filling the remaining portion of the opening 24 in the second dielectric layer 22 with a dielectric material. The capping element 25 can be formed by depositing a growth inhibiting material (such as, SiO2, SiN or Al2O3).

[0059] Figure 3H The device in manufacture is shown after the remaining material of the second dielectric layer 22 has been removed. This can be achieved, for example, by a selective etching process and exposes the vertical surfaces 26 on each of the previously formed core structures 4.

[0060] In Figure 3IIn the subsequent stage shown, starting from each of the vertical surfaces 26, the shell structure 5 grows radially outward. This step can again be implemented using a suitable selective growth method, which either uses homoepitaxy (e.g., forming a SiC shell on a SiC core) or heteroepitaxy (e.g., forming a GaN shell on a SiC core, forming a diamond shell on a SiC core, or forming a SiC shell on a Si core). Since both the capping element 25 and the first dielectric layer include growth-inhibiting materials, the shell structure 5 grows only on the vertical surfaces 26, and not on the top of the first dielectric layer 21 covering the substrate 1 or on the top or side of the capping element 25. In the described embodiment, an n-type SiC material is used to grow the shell structure 5, thereby completing a plurality of superjunction structures 3, which include p-type core structures 4 and n-type shell structures 5.

[0061] In Figure 3J the situation depicted, the capping element 25 has been removed, e.g., by selective etching.

[0062] Figure 3K The situation after implanting the channel region 7 in the shell structure 5 is shown. For this purpose, ions of a suitable substance of the first conduction type are implanted from the top surface of the superjunction structure 3. This is indicated by the dashed arrow shown in Figure 3K . Suitable substances for p-type implantation include, for example, Al and B. Note the fact that the additional charge carriers implanted by means of ion implantation do not significantly affect the electrical properties of the core structure 4. However, they do overcompensate the charge concentration in the shell structure 5, thereby changing it from an n-type semiconductor material to a p-type semiconductor material.

[0063] In Figure 3L the subsequent processing state shown, a third dielectric layer 27 is formed and can be planarized. In the depicted embodiment, a suitable dielectric layer is deposited in the regions between the respective superjunction structures 3. The third dielectric layer 27 can consist essentially of SiO x (in particular SiO2), SiN or Al2O3. It can be the same material as that of the second dielectric layer 22. The third dielectric layer 27 serves as a base for the gate electrodes to be formed later and corresponds to Figure 1 the second sublayer 2b of the embodiment shown in

[0064] The gate insulation structure 9 can be formed, for example, by selectively oxidizing or controllably depositing a dielectric material on the exposed portions of the vertical surfaces 26 of the shell structure 5.

[0065] In Figure 3MIn a further processing stage as shown, a metal material has been deposited on the top surface of the third dielectric layer 27 and optionally planarized to form the gate structure 8. In the described embodiment, the gate structure 8 substantially covers the entire surface of the third dielectric layer 27, thereby forming a fully surrounding gate structure 14 as shown in Figure 2 .

[0066] In the Figure 3N depicted scenario, the upper surface of the gate structure 8 has been covered by a fourth dielectric layer 28 corresponding to the Figure 1 third sublayer 2c. This, together with the third dielectric layer 27 and the gate insulating portion 9, completes the insulation of the gate structure 8.

[0067] Thereafter, as further shown in Figure 3N , a source electrode 12 can be formed on the planarized top surface of the device under fabrication. Similarly, a drain electrode 11 ( Figure 3N not shown in

[0068] Figure 4 ) can be formed on the opposite main surface of the substrate 1 (i.e., on the back side of the lower sublayer 1b).

[0069] Shown is a method 30 for manufacturing a superjunction power semiconductor device, the method including steps S31 to S35.

[0070] In step S31, a growth substrate is provided, such as the substrate 1 including sublayers 1a and 1b. Figure 3A In step S32, a plurality of vertically growing masks 23 are formed on the growth substrate 1. This can be achieved by the method steps detailed above with respect to

[0071] to FIG. 3d, or alternatively can be implemented using additive manufacturing techniques. Figure 3E and Figure 3F . For example, an n-type plug structure 6 can be formed first, followed by forming the p-type main portion 4a of the core structure.

[0072] In step S34, at least a portion of the plurality of vertically growing masks is removed, thereby exposing the vertical surfaces of the plurality of core structures. This can be achieved, for example, by the selective etching method described above with respect to Figure 3G and Figure 3H , or by other suitable methods, such as controlling the length of the etching step to achieve the desired material removal depth.

[0073] In step S35, a second semiconductor material (such as an n-type semiconductor material) is selectively grown on the previously exposed vertical surfaces of the plurality of core structures to form a plurality of shell structures surrounding the respective core structures. This effectively produces a plurality of superjunction structures. As described above with respect to Figure 3I the selective growth can be restricted to the desired surfaces by covering the other surfaces with a dielectric material. Alternatively, the second semiconductor material can be grown on all the surfaces of the device under fabrication, with the unnecessary portions of the deposited second semiconductor material being removed later.

[0074] This is followed by performing additional process steps, for example, to create additional functional regions within the resulting superjunction structures and / or metal contact regions, as detailed above with respect to Figures 3J to 3N the details.

[0075] A novel device architecture and manufacturing method have been described with respect to superjunction power semiconductor devices. However, the use of the described architecture and manufacturing method is not limited to power semiconductor devices, but can also be employed in other regular, cell-based, very dense semiconductor devices. Such devices can include photovoltaic cells and sensor devices (such as image sensors) as well as other optical devices (such as matrix displays).

[0076] Note the fact that the embodiments shown in Figures 1 to 4 are only exemplary embodiments of the improved device structure and its implementation method. They do not constitute a complete list of all embodiments of the improved device and method. For example, the actual devices and manufacturing methods can differ from the described embodiments in terms of the materials used, processing steps and parameters, dimensions, and circuit configurations.

[0077] Reference numerals

[0078] 1 Substrate

[0079] 1a, 1b Sub-layers of the substrate

[0080] 2 Dielectric layer

[0081] 2a to 2c Sub-layers of the dielectric layer

[0082] 3 Superjunction structure

[0083] 4 Core structure

[0084] 4a Main portion of the core structure

[0085] 5 Shell structure

[0086] 6 Plug structure

[0087] 7 Channel region

[0088] 8 Gate structure

[0089] 9 Gate insulating part

[0090] 10 Cell

[0091] 11 Drain electrode

[0092] 12 Source electrode

[0093] 13 (First) opening

[0094] 15 Metal layer

[0095] 16 Terminal region

[0096] 17 Gate runner

[0097] 20 Power semiconductor device

[0098] 21 First dielectric layer (growth seed mask layer)

[0099] 22 Second dielectric layer (core structure mask layer)

[0100] 23 Vertical growth mask

[0101] 24 (Second) opening

[0102] 25 Capping element

[0103] 26 Vertical surface

[0104] 27 Third dielectric layer

[0105] 28 Fourth dielectric layer

[0106] 30 Manufacturing method

[0107] d Spacing distance

Claims

1. A superjunction power semiconductor device (20), comprising: - Substrate (1); - A plurality of core structures (4), each core structure (4) having a cylindrical shape extending in a direction perpendicular to the main surface of the substrate (1) and comprising a first semiconductor material of a first conductivity type; And - A plurality of annular shell structures (5), each shell structure (5) surrounding one of the core structures (4) on the outside and comprising a second semiconductor material of a second conductivity type.

2. The device (20) according to claim 1, further comprising a dielectric layer (2) disposed on the main surface of the substrate (1), wherein, The plurality of shell structures (5) surrounding the plurality of core structures (4) are embedded in the dielectric layer (2).

3. The device (20) according to claim 2, wherein, - The dielectric layer (2) comprises at least a first sub-layer (2a) and a second sub-layer (2b); - The first sub-layer (2a) is arranged between the substrate (1) and the second sub-layer (2b), and the first sub-layer (2a) comprises a plurality of channels between the substrate (1) and the second sub-layer (2b); - The second sub-layer (2b) comprises at least the lower part of each of the plurality of shell structures (5); and - The device (20) further comprises a plurality of plug structures (6), each plug structure (6) comprising a third semiconductor material of the second conductivity type and arranged in the region of one of the channels so as to contact the main surface of the substrate (1) and a corresponding one of the shell structures (5).

4. The device (20) according to claims 1 to 3, further comprising: - A plurality of channel regions (7) formed in each of the shell structures (5), each channel region (7) comprising a fourth semiconductor material of the first conductivity type and arranged in the control layer of the device (20); And - At least one gate structure (8) arranged in the control layer, the at least one gate structure (8) being electrically insulated from each of the shell structures (5) and surrounding at least a part thereof.

5. The device (20) according to claim 4, wherein, The at least one gate structure (8) is buried in the dielectric layer (2), in particular between the second sub-layer (2b) according to claim 3 and a third sub-layer (2c) of the dielectric layer (2).

6. The device (20) according to any one of claims 1 to 5, wherein: - The substrate (1) is one of a silicon Si, single-crystalline or polycrystalline silicon carbide SiC, or gallium nitride GaN semiconductor substrate; - The first semiconductor material includes: a p-type semiconductor material, particularly Si; or a p-type wide bandgap (WBG) semiconductor material, particularly SiC, GaN, or gallium oxide Ga x O y , particularly gallium(III) oxide Ga2O3; and / or - The second semiconductor material includes: an n-type semiconductor material, particularly Si; an n-type WBG semiconductor material, particularly SiC, GaN, Ga x O y , particularly Ga2O3; or n-type diamond.

7. The device (20) according to any one of claims 1 to 6, wherein: - The core structure (4) and / or the shell structure (5) extend in a direction perpendicular to the main surface of the substrate (1) over a length of 1 to 100 μm, in particular over a length of 3 to 15 μm; - The core structure (4) has a diameter of 25 nm to 5 μm, in particular 0.1 to 5 μm; - The shell structure (5) has a thickness of 0.1 to 5 μm; and / or - The plurality of core structures (4) are arranged in a regular pattern, in particular in an array structure, the pitch distance (d) of the plurality of core structures (4) being less than 1 μm and / or in the range of 1.1 to 2.5 times the total diameter of one of the core structures (4) surrounded by one of the shell structures (5).

8. The device (20) according to any one of claims 1 to 7, further comprising at least one of the following: - A drain electrode (11), which is formed on the second main surface of the substrate (1); - A source electrode (12), which is formed on the dielectric layer (1), in particular on the third sub-layer (2c) of the dielectric layer (2) according to claim 5, and interconnects the upper ends of each of the plurality of core structures (5); and / or - A gate electrode electrically connected to at least one gate structure (8), in particular to at least one gate structure (8) according to claim 4 or 5.

9. The device (20) according to any one of claims 1 to 8, wherein The plurality of core structures (4) and / or the plurality of shell structures (5) are electrically connected in parallel to form a multi-unit field effect transistor FET, in particular a metal-insulator-semiconductor field effect transistor MISFET, a metal-oxide-semiconductor field effect transistor MOSFET, an insulated gate bipolar transistor IGBT, and / or a junction gate field effect transistor JFET.

10. A method (30) for manufacturing a superjunction power semiconductor device (20), in particular the device (20) according to any one of claims 1 to 9, the method comprising: - Providing (S31) a growth substrate (1); - Forming (S32) a plurality of vertically growing masks (23) on the growth substrate (1); - Selectively growing (S33) a first semiconductor material in the plurality of vertically growing masks (23) to form corresponding plurality of core structures (4) in a direction perpendicular to the main surface of the growth substrate (1); - At least partially removing (S34) the plurality of vertically growing masks (23), thereby exposing the vertical surfaces (26) of the plurality of core structures (4); and - Selectively growing (S35) a second semiconductor material on the vertical surfaces (26) of the plurality of core structures (4) to form corresponding plurality of shell structures (5) surrounding the respective core structures (4).

11. The method (30) according to claim 10, wherein Forming (S32) the plurality of vertically growing masks (23) includes: - Forming a growth seed mask layer (21) having a plurality of first openings (13), the plurality of first openings corresponding to the pitch distance (d) between the plurality of core structures (4); and - Forming a core structure mask layer (22) having a plurality of second openings (24), each second opening (24) being disposed in a region corresponding to the respective first opening (13) and being wider than the respective first opening (13).

12. The method according to claim 10 or 11, wherein Forming the plurality of core structures (4) includes: - Forming a plurality of plug structures (6) by selectively growing a third semiconductor material, in particular n-type silicon carbide SiC, including impurities of a first conductivity type, directly on the growth substrate (1) in the plurality of vertically growing masks (23); and - Thereafter, forming the main portions (4a) of the plurality of core structures (4) by selectively growing a first semiconductor material, in particular p-type SiC, including impurities of a second conductivity type, in the plurality of vertically growing masks (23).

13. The method (30) according to any one of claims 10 to 12, wherein Forming the plurality of shell structures (5) includes: - Covering the top surfaces of the plurality of core structures (4) with a growth inhibiting material, the growth inhibiting material being in particular one of SiO2, SiN, or Al2O3; - Removing an upper portion of the plurality of vertically growing masks (23), in particular the core structure mask layer (22) according to claim 11, such that the remaining lower portion of the plurality of vertically growing masks (23), in particular the growth seed mask layer (21) according to claim 11, covers the growth substrate (1); and - Thereafter, forming the plurality of shell structures (5) by selectively growing a second semiconductor material, in particular n-type SiC, including impurities of the first conductivity type, in a radial direction.

14. The method (30) according to any one of claims 10 to 13, further comprising: - Inject a dopant substance into the control layer of the device (20), in particular one of aluminum Al or boron B ions by ion implantation, to form a channel region (7) in each of the plurality of shell structures (5); - Electrically insulate the outer surface of each of the shell structures (5) at least in a region corresponding to the channel region (7); And - Form at least one gate structure (8) within the control layer, the gate structure (8) surrounding the insulated channel regions (7) of the plurality of shell structures (5).

15. The method (30) according to any one of claims 10 to 14, further comprising at least one of the following: - Depositing a first conductive layer on a second major surface of the growth substrate (1) to form a common drain electrode (11) of the device (20); - Depositing a second conductive layer on a planarized first dielectric layer (27) surrounding a lower portion of the plurality of shell structures (5) to form a common gate structure (8) of the device; and / or - Depositing a third conductive layer on the top surface of the second dielectric layer (28), in particular on the top surface of the common gate structure (8), on the top surface of the dielectric layer (28) to form the common source electrode (12) of the device (20).

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