Switching element

Abstract

A switching element in which electric field concentration in the outer peripheral portion of an element portion of the switching element is relaxed, the switching element having a gate electrode disposed in a trench, the element portion provided with the trench having a central portion and an outer peripheral portion, the element portion having an n-type source region, the element part and the outer peripheral part have a p-type body region, an n-type drift region, and a plurality of p-type electric field relaxation regions disposed at intervals in the lateral direction of the semiconductor substrate in a depth range including the lower end of each of the trenches or in a depth range below the lower end of each of the trenches. The drift regions are distributed in the intervals between the electric field relaxation regions, and the value (Wp / Wn) obtained by dividing the width (Wp) of each of the electric field relaxation regions in the lateral direction by the width (Wn) of the intervals between the electric field relaxation regions is greater in the outer peripheral portion than in the central portion.

Description

[0001] Cross-reference to related applications

[0002] This application is a related application of Japanese Patent Application No. 2022-195543 filed on December 7, 2022, claims priority based on this Japanese patent application, and incorporates by reference all the contents described in this Japanese patent application as the contents constituting this specification. Technical field

[0003] The technology disclosed in this specification relates to a switching element. Background art

[0004] A switching element having a trench-type gate electrode is disclosed in Japanese Patent Publication No. 2015-167208. When the switching element is turned off, the drift region is depleted and an electric field is generated within the drift region. In such a switching element, the electric field tends to concentrate at the lower end of the trench. To suppress the electric field concentration at the lower end of the trench, a technique of providing a p-type electric field relaxation region is known. The electric field relaxation region is disposed in a depth range including the lower end of the trench or in a depth range below the lower end of the trench. If the electric field relaxation region is provided, the depletion layer easily expands toward the periphery of the lower end of the trench, and the electric field concentration at the lower end of the trench is alleviated. Summary of the invention

[0005] It can be seen that even in a switching element provided with an electric field relaxation region, the electric field tends to concentrate at the lower end of the trench in the outer peripheral portion of the element portion (i.e., the portion provided with the trench). In this specification, a technique for alleviating the electric field concentration in the outer peripheral portion of the element portion is proposed.

[0006] The switching element disclosed in this specification has: a semiconductor substrate, on the upper surface of which a plurality of trenches are provided; a gate insulating film covering the inner surfaces of the trenches; and a gate electrode disposed in the trenches and insulated from the semiconductor substrate by the gate insulating film. The portion of the semiconductor substrate where the plurality of trenches are provided is the element portion. The element portion has a central portion and a peripheral portion. The element portion has an n-type source region that abuts the gate insulating film on the side surfaces of each of the trenches. The element portion and the peripheral portion have a body region, a drift region, and an electric field relaxation region. The body region is a p-type region that abuts the gate insulating film on the side surfaces of each of the trenches. The drift region is an n-type region disposed below the body region, separated from the source region by the body region, and abuts the gate insulating film on the side surfaces of each of the trenches. The electric field relaxation regions are a plurality of p-type regions disposed in a depth range including the lower ends of each of the trenches or in a depth range below the lower ends of each of the trenches, connected to the body region, and disposed at intervals in the lateral direction of the semiconductor substrate. The drift region is distributed within the intervals between the electric field relaxation regions. The value Wp / Wn obtained by dividing the width Wp in the lateral direction of each of the electric field relaxation regions by the width Wn of the intervals between each of the electric field relaxation regions is larger in the peripheral portion than in the central portion.

[0007] In this switching element, the electric field at the lower ends of each of the trenches is relaxed by the electric field relaxation regions. Further, the electric field relaxation regions are configured such that the value Wp / Wn is larger in the peripheral portion than in the central portion. That is, in the depth range of the electric field relaxation regions, the ratio of the p-type regions is larger in the peripheral portion than in the element portion. Therefore, in the peripheral portion, the depletion layer is more likely to expand from the electric field relaxation regions to the surroundings compared to the element portion. Accordingly, the electric field concentration at the lower ends of the trenches in the peripheral portion is effectively relaxed. Thus, according to this switching element, the electric field concentration in the peripheral portion of the element portion can be relaxed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a top view of the switching element as viewed from above.

[0009] Figure 2 is a cross-sectional perspective view of the central portion 60a.

[0010] Figure 3 is a longitudinal cross-sectional view of the central portion 60a along the x direction (i.e., Figure 1 the longitudinal cross-sectional view of III-III).

[0011] Figure 4 is a longitudinal cross-sectional view of the peripheral portion 60b along the x direction (i.e., Figure 1 the longitudinal cross-sectional view of IV-IV).

[0012] Figure 5 is a longitudinal sectional view of the central portion 60a along the y direction (i.e., Figure 1 longitudinal sectional view of V-V).

[0013] Figure 6 is a longitudinal sectional view of the outer peripheral portion 60b along the y direction (i.e., Figure 1 longitudinal sectional view of VI-VI).

[0014] Figure 7 is a sectional perspective view of the switching element of Modification 1.

[0015] Figure 8 is a sectional perspective view of the switching element of Modification 2.

[0016] Figure 9 is a sectional perspective view of the switching element of Modification 3. DETAILED DESCRIPTION

[0017] A switching element of an example disclosed in this specification may also further include: a source electrode (22) that covers the upper surface of the semiconductor substrate in the central portion and the outer peripheral portion and is in contact with the body region and the source region; and an insulating layer (28) that covers the upper surface of the source electrode in the outer peripheral portion.

[0018] According to this structure, it is possible to suppress the application of a high electric field to the gate insulating film in the outer peripheral portion in a high-temperature environment.

[0019] In the switching element of an example disclosed in this specification, the outer peripheral portion may not have the source region.

[0020] According to this structure, by suppressing the current flowing in the outer peripheral portion, the operation of the switching element can be stabilized.

[0021] As Figure 1As shown, the switching element 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 can also be made of other semiconductors such as Si and GaN. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, the direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction. An anode electrode 22 and a plurality of electrode pads 23 are provided on the upper surface 12a of the semiconductor substrate 12. The plurality of electrode pads 23 include an electrode pad for controlling the gate potential, an electrode pad for outputting the potential of the anode electrode 22, an electrode pad for outputting the temperature of the semiconductor substrate 12, and the like. Within the range covered by the anode electrode 22, a plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in the y direction. The trenches 14 are arranged at intervals in the x direction. Within the range where the plurality of trenches 14 are provided, the main part of the switching element 10 is formed. Hereinafter, the range of the semiconductor substrate 12 where a plurality of trenches 14 are provided when looking down at the semiconductor substrate 12 from above (i.e., the range overlapping with the anode electrode 22) is referred to as the element portion 60. The element portion 60 has a central portion 60a and a peripheral portion 60b. The peripheral portion 60b is provided around the central portion 60a.

[0022] Figures 2 to 4 Shows the structure of the element portion 60. More specifically, Figure 2 , 3 shows the structure of the central portion 60a, Figure 4 shows the structure of the peripheral portion 60b. In addition, in Figure 2 the anode electrode 22 is omitted. As Figures 2 to 4 shown, the inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. The anode electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20.

[0023] The anode electrode 22 is made of AlSi. As Figure 3 shown, within the central portion 60a, the anode electrode 22 is covered with a Ni layer 26. Although not shown, the Ni layer 26 is connected to an external electrode block by solder. As Figure 4 shown, within the peripheral portion 60b, the anode electrode 22 is covered with an insulating resin layer 28 (for example, a polyimide layer). The insulating resin layer 28 has a low thermal conductivity. Therefore, the central portion 60a has higher heat dissipation than the peripheral portion 60b.

[0024] As Figures 2 to 4 shown, a drain electrode 24 is provided below the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0025] As Figures 2 to 4 shown, the semiconductor substrate 12 has a plurality of source regions 40, a body region 42, a drift region 44, a drain region 46, and a plurality of electric field relaxation regions 48.

[0026] Each source region 40 is an n-type region having a high n-type impurity concentration. As Figure 2 , 3 shown, each source region 40 is disposed within a range sandwiched by the trenches 14. Each source region 40 is in ohmic contact with the source electrode 22. Each source region 40 contacts the gate insulating film 16 on the side surface of the trench 14. The source region 40 is provided in the central portion 60a. As Figure 4 shown, the source region 40 is not provided in the peripheral portion 60b.

[0027] As Figures 2 to 4 shown, the body region 42 extends across the central portion 60a and the peripheral portion 60b. The body region 42 has a plurality of contact regions 42a and a low-concentration region 42b having a lower p-type impurity concentration than each contact region 42a. Each contact region 42a is disposed within a range sandwiched by the trenches 14. Each contact region 42a is in ohmic contact with the source electrode 22. The low-concentration region 42b abuts against the plurality of source regions 40 and the plurality of contact regions 42a from below. The low-concentration region 42b abuts against the gate insulating film 16 on the side surface of the trench 14. In the central portion 60a, the low-concentration region 42b abuts against the gate insulating film 16 below each source region 40.

[0028] As Figures 2 to 4 shown, the drift region 44 extends across the central portion 60a and the peripheral portion 60b. The drift region 44 is an n-type region having an n-type impurity concentration lower than that of the source region 40. The drift region 44 extends across the lower portions of the plurality of trenches 14. As Figure 2 shown, the upper end portion of the drift region 44 extends into the range between the respective trenches 14. The drift region 44 abuts against the low-concentration region 42b from below within the range between the respective trenches 14. The drift region 44 abuts against the gate insulating film 16 below the low-concentration region 42b.

[0029] As Figures 2 to 4 shown, the drain region 46 extends across the central portion 60a and the peripheral portion 60b. The drain region 46 is an n-type region having an n-type impurity concentration higher than that of the drift region 44. The drain region 46 abuts against the drift region 44 from below. The drain region 46 is in ohmic contact with the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.

[0030] As Figures 2 to 4As shown, a plurality of electric field relaxation regions 48 are provided in the central portion 60a and the outer peripheral portion 60b. Each electric field relaxation region 48 is disposed within the range surrounded by the drift region 44. Each electric field relaxation region 48 is disposed at a position lower than the low-concentration region 42b with a space therebetween. The drift region 44 is distributed in the space between each electric field relaxation region 48 and the low-concentration region 42b. Each electric field relaxation region 48 extends linearly in the x direction. Each electric field relaxation region 48 is disposed at intervals in the y direction. The drift region 44 is distributed in each interval between the electric field relaxation regions 48. Hereinafter, the drift region 44 in each interval between the electric field relaxation regions 48 is referred to as an interval portion 44a. Each electric field relaxation region 48 is disposed in the z direction within the range including the lower end of the trench 14. Therefore, each electric field relaxation region 48 abuts on the gate insulating film 16 at the lower end of each trench 14.

[0031] As Figure 2 shown, the semiconductor substrate 12 has a p-type connection region 52. The connection region 52 connects the electric field relaxation region 48 and the low-concentration region 42b. In addition, Figure 2 one connection region 52 is illustrated, but at least one connection region 52 is provided for each electric field relaxation region 48. Therefore, the potential of each electric field relaxation region 48 is substantially equal to the potential of the body region 42.

[0032] In Figure 5 , 6 , reference numeral Wp denotes the width in the y direction of each electric field relaxation region 48, and reference numeral Wn denotes the width in the y direction of each interval between the electric field relaxation regions 48 (i.e., the width of the interval portion 44a). As Figure 5 , 6 shown, for the central portion 60a, the width Wp of the electric field relaxation region 48 is narrower than that of the outer peripheral portion 60b. In addition, for the central portion 60a, the width Wn of the interval portion 44a is wider than that of the outer peripheral portion 60b. Therefore, for the central portion 60a, the value Wp / Wn obtained by dividing the width Wp by the width Wn is smaller than that of the outer peripheral portion 60b. The value Wp / Wn represents the ratio of the electric field relaxation region 48 to the interval portion 44a within the range in the z direction where the electric field relaxation region 48 exists.

[0033] Next, the operation of the switching element 10 will be described. The switching element 10 is used in a state where a voltage is applied in a direction in which the drain electrode 24 is at a higher potential than the source electrode 22. When a potential equal to or higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the body region 42 near the gate insulating film 16, and the source region 40 and the drift region 44 are connected through the channel. Therefore, electrons flow from the source electrode 22 through the source region 40 and the channel to the drift region 44. The electrons flowing from the channel to the drift region 44 flow through the spacer portion 44a to the lower drift region 44 of the electric field relaxation region 48. The electrons flow from the drift region 44 through the drain region 46 to the drain electrode 24. Thus, when a potential equal to or higher than the gate threshold is applied to the gate electrode 18, the switching element 10 conducts.

[0034] As described above, when the switching element 10 conducts, electrons pass through the spacer portion 44a. In the central portion 60a, which is the main part of the element portion 60, the value of Wp / Wn is small. Therefore, within the depth range where the electric field relaxation region 48 exists, the ratio of the spacer portion 44a (i.e., the n-type region) is large. Therefore, in the central portion 60a, the resistance of the spacer portion 44a is small. Therefore, in the central portion 60a, electrons can flow with low loss. In addition, in the peripheral portion 60b, the value of Wp / Wn is large, and the resistance of the spacer portion 44a is large. However, compared with the central portion 60a, fewer electrons flow in the peripheral portion 60b. In particular, in this embodiment, since the source region 40 is not provided in the peripheral portion 60b, very few electrons flow through the spacer portion 44a within the peripheral portion 60b. Therefore, even if the resistance of the spacer portion 44a is large in the peripheral portion 60b, not much loss is generated. Therefore, the on-resistance of the switching element 10 is low.

[0035] In addition, in the manufacturing process, it is difficult to form the trench 14 with high precision over the entire element portion 60, and the shape accuracy of the trench 14 is likely to be reduced in the peripheral portion 60b. Therefore, if a high current flows through the peripheral portion 60b, abnormalities are likely to occur in the peripheral portion 60b. In the switching element 10 of the embodiment, since the source region 40 is not provided in the peripheral portion 60b, almost no current flows through the peripheral portion 60b. Thereby, stable operation of the switching element 10 is achieved.

[0036] If the potential of the gate electrode 18 is reduced to a potential less than the gate threshold, the channel disappears and the switching element 10 is turned off. When the switching element 10 is turned off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44. In addition, the electric field relaxation region 48 has substantially the same potential as the body region 42, so a reverse voltage is also applied to the pn junction at the interface between the electric field relaxation region 48 and the drift region 44. Therefore, the depletion layer extends from the body region 42 and the electric field relaxation region 48 toward the drift region 44. Through the depleted drift region 44, the voltage between the drain electrode 24 and the source electrode 22 is maintained. The depletion layer extending from the electric field relaxation region 48 toward the drift region 44 depletes the drift region 44 around the lower end of the trench 14. In this way, by depleting the drift region 44 around the lower end of the trench 14, the electric field concentration in the gate insulating film 16 covering the lower end of the trench 14 is suppressed.

[0037] In addition, since there is no trench 14 outside the element portion 60, the electric field is particularly likely to concentrate at the lower end of the trench 14 in the peripheral portion 60b. In contrast, in the switching element 10 of the embodiment, the value of Wp / Wn is large in the peripheral portion 60b, and the ratio of the electric field relaxation region 48 (i.e., the p-type region) to the spacer portion 44a (i.e., the n-type region) is large. Therefore, in the peripheral portion 60b, the depletion layer easily extends from the electric field relaxation region 48 to its surroundings. Therefore, in the peripheral portion 60b, the effect of alleviating the electric field concentration in the electric field relaxation region 48 is higher than that in the central portion 60a. Therefore, the electric field concentration at the lower end of the trench 14 in the peripheral portion 60b can be suppressed. In addition, as described above, the heat dissipation property of the peripheral portion 60b is lower than that of the central portion 60a, and the peripheral portion 60b is more likely to become high temperature than the central portion 60a. If a high electric field is applied to the gate insulating film 16 in a high-temperature state, the gate insulating film 16 is likely to deteriorate. By suppressing the electric field concentration toward the gate insulating film 16 in the peripheral portion 60b that is likely to become high temperature, the deterioration of the gate insulating film 16 can be more effectively suppressed.

[0038] In addition, in the above embodiment, the electric field relaxation region 48 extends linearly in the x direction (i.e., the direction intersecting the trench 14) and is arranged at intervals in the y direction. However, the electric field relaxation region 48 may also extend linearly in the y direction (i.e., the direction parallel to the trench 14) and be arranged at intervals in the x direction. In this case, the electric field relaxation region 48 may be arranged between the respective trenches 14 in the x direction as Figure 7 or may be arranged at a position overlapping the respective trenches 14 (i.e., the lower part of the trench 14) in the x direction as Figure 8 In Figure 7 , 8In the structure, by making the value Wp / Wn in the outer peripheral portion 60b larger than that in the central portion 60a, it is also possible to suppress the electric field concentration in the outer peripheral portion 60b toward the gate insulating film 16.

[0039] In addition, in the above-described embodiment, the electric field relaxation region 48 is disposed in the depth range including the lower end of the trench 14, but the electric field relaxation region 48 may also be disposed in the depth range below the lower end of the trench 14. For example, when the electric field relaxation region 48 extends linearly in a direction intersecting the trench 14, it may be as Figure 9 such that the electric field relaxation region 48 is disposed at a position below the lower end of the trench 14. Further, even when Figure 7 , 8 as shown, the electric field relaxation region 48 extends linearly in parallel with the trench 14, the electric field relaxation region 48 may be disposed at a position below the lower end of the trench 14. Even when the electric field relaxation region 48 is disposed at a position below the lower end of the trench 14, it is possible to suppress the electric field concentration at the lower end of the trench 14.

[0040] In addition, in the above-described embodiment, the source region 40 is not provided in the outer peripheral portion 60b, but the source region 40 may also be provided in the outer peripheral portion 60b.

[0041] In addition, in the above-described embodiment, the width Wp is wider in the outer peripheral portion 60b than in the central portion 60a, and the width Wn is narrower in the outer peripheral portion 60b than in the central portion 60a. However, as long as the condition that the value Wp / Wn in the outer peripheral portion 60b is greater than the value Wp / Wn in the central portion 60a is satisfied, the widths Wp and Wn in the central portion 60a and the outer peripheral portion 60b can be set arbitrarily. For example, the width Wp in the outer peripheral portion 60b may be wider than the width Wp in the central portion 60a, and the width Wn in the outer peripheral portion 60b may be equal to the width Wn in the central portion 60a.

[0042] In addition, for example, the width Wp in the outer peripheral portion 60b may be equal to the width Wp in the central portion 60a, and the width Wn in the outer peripheral portion 60b may be narrower than the width Wn in the central portion 60a.

[0043] As described above, the embodiments have been described in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes technologies obtained by various modifications and changes to the above-exemplified specific examples. The technical elements described in this specification or the drawings exhibit technical effects alone or through various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technologies exemplified in this specification or the drawings achieve multiple objects at the same time, and achieving one of the objects itself has technical utility.

Claims

1. A switching element, having: a semiconductor substrate, with a plurality of trenches (14) provided on the upper surface; A gate insulating film (16) covering the inner surface of the trench; and A gate electrode (18) disposed in the trench and insulated from the semiconductor substrate by the gate insulating film, A portion of the semiconductor substrate in which the plurality of trenches are provided is an element portion (60), The element portion has a central portion (60a) and a peripheral portion (60b), The element portion has an n-type source region (40) that abuts the gate insulating film on the side surfaces of the respective trenches, The element portion and the peripheral portion have: A p-type body region (42) that abuts the gate insulating film on the side surfaces of the respective trenches, An n-type drift region (44) disposed below the body region and separated from the source region by the body region, and abutting the gate insulating film on the side surfaces of the respective trenches; and A plurality of p-type electric field relaxation regions (48) disposed in a depth range including the lower ends of the respective trenches or in a depth range below the lower ends of the respective trenches, connected to the body region, and disposed at intervals in the lateral direction of the semiconductor substrate, The drift regions are distributed in the intervals between the electric field relaxation regions, For a value Wp / Wn obtained by dividing the lateral width Wp of each of the electric field relaxation regions by the width Wn of the interval between the electric field relaxation regions, it is larger in the peripheral portion than in the central portion.

2. The switching element according to claim 1, further having: a source electrode (22), covering the upper surface of the semiconductor substrate in the central portion and the peripheral portion, and being in contact with the body region and the source region; and an insulating layer (28), covering the upper surface of the source electrode in the peripheral portion.

3. The switching element according to claim 1 or 2, wherein the peripheral portion does not have the source region.

Images