Method for manufacturing semiconductor device, and semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device and a semiconductor device, wherein the semiconductor device can be transported and processed by using the same device as a wafer before processing by suppressing reduction of the diameter of the wafer. A method for manufacturing a semiconductor according to the present disclosure includes: forming a semiconductor element structure on a second main surface of a wafer having a first main surface and the second main surface facing each other; a step for grinding the outer peripheral portion of the second main surface of the wafer on which the semiconductor element structure has been formed to the midway in the thickness direction from the second main surface toward the first main surface; a step of dividing the wafer in a direction perpendicular to the thickness direction at a position where the depth from the second main surface is shallower than the depth at which the outer peripheral portion of the wafer has been ground, and dividing a first divided wafer that does not include the semiconductor element structure from the wafer; a step for grinding the outer peripheral portion of the split surface of the first split wafer; and a step for forming a semiconductor element structure on the split surface of the first split wafer after the outer peripheral portion of the split surface is ground.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] Patent Document 1 discloses a technique for reducing the substrate cost by using a sliced wafer as a substrate for epitaxial growth.

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2021-52178

[0004] However, in the above method, bevel cutting of the wafer before slicing is required. Since the wafer diameter is reduced due to this bevel cutting, there are problems that it is impossible to use the same apparatus as that for the wafer before processing for transfer and processing, or that the apparatus needs to be adjusted to cope with the change in the wafer diameter. Summary of the Invention

[0005] In order to solve the above problems, an object of the present disclosure is to provide a method for manufacturing a semiconductor device and a semiconductor device that can use the same apparatus as that for the wafer before processing for transfer and processing by suppressing reduction of the wafer diameter.

[0006] A first aspect of the present disclosure is preferably a method for manufacturing a semiconductor device, including the following steps: a step of forming a semiconductor element structure on a second main surface of a wafer having a first main surface and a second main surface facing each other; a step of grinding an outer peripheral portion of the second main surface of the wafer on which the semiconductor element structure is formed to a midway position in the thickness direction from the second main surface toward the first main surface; a step of dividing the wafer in a direction perpendicular to the thickness direction at a position where the depth from the second main surface is shallower than the depth at which the outer peripheral portion of the wafer is ground, to divide a first divided wafer that does not include the semiconductor element structure from the wafer; a step of grinding an outer peripheral portion of a dividing surface of the first divided wafer; and a step of forming a semiconductor element structure on the dividing surface of the first divided wafer after grinding the outer peripheral portion of the dividing surface.

[0007] A second aspect of the present disclosure is preferably a semiconductor device including: a first divided wafer having a first main surface and a second main surface facing each other, and having a semiconductor element structure on the second main surface; and a second divided wafer bonded to the first main surface of the first divided wafer, and having an unbonded region formed at an outer peripheral portion of a bonding interface between the first divided wafer and the second divided wafer.

[0008] A third aspect of the present disclosure is preferably a semiconductor device including: a first divided wafer having a first main surface and a second main surface facing each other; an epitaxial film formed on the second main surface of the first divided wafer; and a semiconductor element structure formed on the epitaxial film, and a cross section of the first divided wafer being a convex structure.

[0009] A fourth aspect of the present disclosure is preferably a semiconductor device including a first divided wafer having a first main surface and a second main surface facing each other, a semiconductor element structure on the second main surface, and a convex cross-section of the first divided wafer.

[0010] According to the first to fourth aspects of the present disclosure, by suppressing the reduction in wafer diameter, it is possible to carry and process the wafer using the same device as before processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. is a diagram showing a semiconductor device according to Embodiment 1 of the present disclosure.

[0012] Figure 2 FIG. is a diagram showing a grinding process according to Embodiment 1 of the present disclosure.

[0013] Figure 3 FIG. is a diagram showing a dicing process according to Embodiment 1 of the present disclosure.

[0014] Figure 4 FIG. is a diagram showing a bonding process according to Embodiment 1 of the present disclosure.

[0015] Figure 5 FIG. is an enlarged view of a bonding process according to Embodiment 1 of the present disclosure.

[0016] Figure 6 FIG. is a diagram showing a chamfering process according to Embodiment 1 of the present disclosure.

[0017] Figure 7 FIG. is a diagram showing an element formation process according to Embodiment 1 of the present disclosure.

[0018] Figure 8 FIG. is a diagram showing a semiconductor device according to the first comparative example.

[0019] Figure 9 FIG. is a diagram showing a dicing process according to the first comparative example.

[0020] Figure 10 FIG. is a diagram showing a chamfering process according to the second comparative example.

[0021] Figure 11 FIG. is a diagram showing a dicing process according to the second comparative example.

[0022] Figure 12 FIG. is a diagram showing a modified example of a grinding process according to Embodiment 1 of the present disclosure.

[0023] Figure 13 FIG. is a diagram showing a first modified example of a bonding process according to Embodiment 1 of the present disclosure.

[0024] Figure 14 It is a diagram showing a second modification example of the bonding process according to Embodiment 1 of the present disclosure.

[0025] Figure 15 It is a diagram showing a modification example of the chamfering process according to Embodiment 1 of the present disclosure.

[0026] Figure 16 It is a diagram showing the thick film process according to Embodiment 2 of the present disclosure.

[0027] Figure 17 It is a diagram showing the chamfering process according to Embodiment 2 of the present disclosure.

[0028] Figure 18 It is a diagram showing the element formation process according to Embodiment 2 of the present disclosure.

[0029] Figure 19 It is a diagram showing a modification example of the chamfering process according to Embodiment 2 of the present disclosure.

[0030] Figure 20 It is a diagram showing the chamfering process according to Embodiment 3 of the present disclosure.

[0031] Figure 21 It is a diagram showing the element formation process according to Embodiment 3 of the present disclosure.

[0032] Figure 22 It is a diagram showing a modification example of the chamfering process according to Embodiment 3 of the present disclosure.

[0033] Figure 23 It is a diagram showing a grinding process implemented by a device in which a grinding wheel is mounted on a rotary edge processing machine.

[0034] Figure 24 It is shown accompanying Figure 23 the grinding process and showing the notch loss caused thereby.

[0035] Explanation of reference numerals

[0036] 12…Wafer; 14…Semiconductor element structure; 16…Wafer; 16a…Wafer; 18…Divided wafer; 20…Divided wafer; 20a…Divided wafer; 20b…Divided wafer; 22…Divided wafer; 24…Amorphous layer; 26…Unbonded region; 30…Divided wafer; 30a…Divided wafer; 30b…Divided wafer; 30c…Divided wafer; 32…Epitaxial film; 34…Epitaxial film; 34a…Epitaxial film; 100…Semiconductor device; 102…Semiconductor device; 102a…Semiconductor device; 104b…Semiconductor device; 108…Semiconductor device; 114…Semiconductor device; 118…Semiconductor device; 128…Semiconductor device; 500…Semiconductor device; 502…Wafer; 504…Semiconductor element structure; 506…Divided wafer; 508…Divided wafer; 510…Divided wafer; 514…Divided wafer; 516…Divided wafer. Detailed implementation

[0037] Implementation 1

[0038] [Processing method of the semiconductor device according to Embodiment 1 of the present disclosure]

[0039] The processing method of the semiconductor device according to Embodiment 1 of the present disclosure will be described. Figure 1 It is a diagram showing the semiconductor device according to Embodiment 1 of the present disclosure. The semiconductor device 100 includes a wafer 12. The wafer 12 is, for example, a single crystal SiC wafer having a first main surface and an opposing second main surface. Here, the first main surface is the back surface of the wafer, and the second main surface is the front surface of the wafer.

[0040] The wafer 12 can be formed of Si or a wide bandgap semiconductor having a larger bandgap than Si. The wide bandgap semiconductor is, for example, SiC, a GaN-based material, a gallium oxide-based material, or diamond. By forming a switching element or a diode element from a wide bandgap semiconductor, the breakdown voltage and the allowable current density can be increased, and thus miniaturization can be achieved.

[0041] The method of the present disclosure is particularly effective in semiconductor devices using wafers that are cost-effective and difficult to obtain. As a particularly effective example, the case where the wafer 12 is formed of SiC is cited. SiC wafers are more difficult to make large-diameter than Si wafers, are costly, and have a poor yield due to crystal defects. That is, SiC wafers have the problem of poor cost performance.

[0042] In addition, single crystals of SiC are generally made by the sublimation method. In this sublimation method, as the diameter of the wafer increases, the temperature difference in the crystal becomes larger and the crystal defects increase. That is, SiC wafers have the problem that it becomes difficult to obtain a substrate with few crystal defects as the diameter of the wafer increases.

[0043] The problems of the above-described SiC wafers can be solved simultaneously by reusing SiC wafers with fewer crystal defects.

[0044] An epitaxial film is formed on the second main surface of the wafer 12. A semiconductor element structure 14 is formed on the epitaxial film. The semiconductor element structure 14 is, for example, a power device structure such as a MOSFET, a diode, or an IGBT. The formation of the semiconductor element structure 14 includes ion implantation and the formation of a surface electrode. Among them, the semiconductor element structure 14 is formed at a position on the wafer 12 that is closer to the inside than the conical outermost peripheral portion.

[0045] In addition, when the wafer 12 is formed of GaN, the semiconductor element structure 14 is, for example, a GaN high-frequency device structure. Alternatively, a GaN high-frequency device structure may be formed on the wafer 12 formed of SiC.

[0046] Figure 2 FIG. is a diagram showing a grinding process according to Embodiment 1 of the present disclosure. In the grinding process of the present embodiment, by grinding the outer peripheral portion of the second main surface of the wafer 12 until the middle in the thickness direction from the second main surface toward the first main surface, a wafer 16 having a convex cross-section is formed. As a result, a semiconductor device 102 in which the semiconductor element structure 14 protrudes more than the outer peripheral portion is formed.

[0047] This grinding process can be implemented, for example, by a device that mounts a grinding wheel on a rotary edge processing machine. The grinding wheel is used as a grinding wheel adjusted to be able to form the wafer into an arbitrary shape by grinding the outer periphery of the wafer. In addition, this grinding process can also be formed by semi-cutting the outer periphery in a cutting device.

[0048] Figure 23 FIG. is a diagram showing a grinding process implemented by a device that mounts a grinding wheel on a rotary edge processing machine. Figure 23 The left figure of FIG. shows the wafer after grinding when a newly replaced grinding wheel is used. Figure 23 The right figure of FIG. shows the wafer after grinding when a worn grinding wheel is used. If multiple wafers are processed using the same grinding wheel, due to the wear of the grinding wheel, it becomes impossible to perform the grinding as expected, so the shape of the processed wafer becomes Figure 23 the right figure of FIG. In this case, due to the grinding process, the corners 50 and 51 in the wafer become rounded corners 50a and 51a.

[0049] In the corner 50a, if R = 500 μm or less, dust and debris caused by the blade described later can be reduced. If it is further reduced to R = 300 μm or less, dust or debris can be further reduced. If R = 100 μm or less, dust or debris caused by the edge shape can be almost suppressed.

[0050] Figure 24 It represents the kerf loss of the grinding process accompanied by Figure 23 the figure of the kerf loss. Figure 24 The left figure of Figure 24 represents the wafer before dicing, Figure 24 shows Figure 23 the kerf loss generated when the corner 51 in the left figure of

[0051] becomes the corner 51b with a large R due to the grinding process. Among them, the kerf loss refers to the so-called material loss, which represents the part removed as chips along with the cutting of the wafer. Specifically, Figure 24 the part corresponding to the boundary of the diced wafer in the right figure of

[0052] In Figure 24 the case where the R of the corner 51b is large as in the left figure of Figure 24 the right figure of

[0053] the end shape becomes sharp. Hereinafter, this shape is called a blade. Due to this blade, chips and dust are generated. The larger the kerf loss during dicing, the more the chips and dust caused by the blade can be suppressed. That is, even in the case where the R of the corner 51b is large, the concern about chips and dust becomes less. For example, when the kerf loss during dicing is greater than 100 μm, R = 200 μm or less is allowed. In addition, when the kerf loss is further reduced to 100 μm to 80 μm, R = 150 μm or less is allowed. In addition, when the kerf loss is further reduced to 60 μm or less, R = 100 μm or less is allowed. However, when one of the diced wafers is processed and reused to form a device again, it is preferable that the kerf loss and the R of the corner 51b are small.

[0054] And if the angle of the terrace is 45 degrees to 135 degrees, the dust or chips caused by the blade can be reduced. If it is 60 degrees to less than 120 degrees, the dust or chips can be further reduced. If it is 75 degrees to less than 105 degrees, the dust or chips caused by the edge shape can be almost suppressed.

[0055] In addition, this grinding process is preferably small in the processing width. This is because when the grinding width is large, in the outer peripheral part of the wafer 16, the area where the substrate thickness is thin becomes large, so it becomes easy to generate chips and cracks. It is known that a large amount of chips and cracks will be generated when the grinding width is 10 mm or more. Therefore, the grinding width is preferably less than 10 mm, and it is more preferable if it is further reduced to, for example, less than 5 mm, less than 3 mm, or less than 1 mm.

[0056] In addition, the grinding process is preferably carried out to a depth that leaves a substrate thickness of more than 100 μm. Thereby, it is possible to suppress cracking and chipping generated at the ends of the wafers reused after the subsequent dicing process.

[0057] Moreover, the grinding process can be carried out before the deposition of the epitaxial film that is carried out before forming the semiconductor element structure 14, or it can be carried out after that. In addition, the grinding process is carried out at a position outside the semiconductor element structure 14 so as not to damage the semiconductor element structure 14.

[0058] Figure 3 FIG. is a diagram showing the dicing process according to Embodiment 1 of the present disclosure. In the dicing process of the present embodiment, the wafer 16 is diced in a direction perpendicular to the thickness direction at a position where the depth from the second main surface is shallower than the depth at which the outer peripheral portion of the wafer 12 is ground. As a result, the semiconductor device 102 is diced into a diced wafer 18 including the semiconductor element structure 14 and a diced wafer 20 not including the semiconductor element structure 14. That is, the diced wafer 20 not including the semiconductor element structure 14 is diced from the wafer 16.

[0059] At this time, the outer peripheral portion of the diced wafer 18 will not become a blade edge. This is because, by performing the Figure 2 shown grinding process, the outermost peripheral portion that may become a blade edge is removed in advance. As a result, in the diced wafer 18, the manufacturing process of the semiconductor device can be advanced without generating dust or debris.

[0060] Moreover, the wafer diameter of the diced wafer 20 is the same as the wafer diameter of the original wafer 12. This is because the grinding process of the present embodiment is different from the beveling process to be described in Figure 10 and does not remove the outermost peripheral portion. That is, by suppressing the reduction of the wafer diameter, it is possible to carry and process using the same device as the wafer before processing.

[0061] In addition, the dicing method can be a contact-based method using a dicing machine or the like, or a non-contact-based method using a laser or the like. For example, a laser scribing technique that uses a laser to form a modified layer and dices in a direction perpendicular to the direction from the first main surface toward the second main surface can also be used.

[0062] In addition, the substrate thickness of the diced wafer 20 is preferably 100 μm or more. This is because, if the substrate thickness of the diced wafer 20 is thin, there will be problems such as cracking during subsequent Figures 4 to 7 processes, or it will be difficult to carry and process due to large bending.

[0063] Figure 4FIG. 0 is a view showing the bonding process according to Embodiment 1 of the present disclosure. In the bonding process of the present embodiment, another divided wafer 20 is bonded to the first main surface of the divided wafer 20. As a result, a bonded wafer 21 having the same wafer diameter as the original wafer 12 is formed. In this way, by bonding a plurality of divided wafers 20, the substrate thickness is increased, so that the bending of the wafer can be suppressed more than in the case of using only the divided wafer 20 alone.

[0064] Figure 5 FIG. 4 is an enlarged view showing the bonding process according to Embodiment 1 of the present disclosure. The bonding process of the present embodiment can also be implemented, for example, using a technique based on room temperature bonding. At this time, an amorphous layer 24 is formed at the bonding interface of the bonded wafer 21.

[0065] Room temperature bonding is a bonding method that can obtain a clean interface because it does not include a metal layer or the like at the bonding interface. In addition, by performing a planarization process of grinding and planarizing at least one of the bonding interfaces before the bonding process, the close contact force during bonding can be improved. Among them, instead of grinding, planarization can also be performed by CMP or the like.

[0066] Figure 6 FIG. 11 is a view showing the beveling process according to Embodiment 1 of the present disclosure. In the beveling process of the present embodiment, the outer peripheral portion on the second main surface side of the bonded wafer 21 is ground into a conical shape. That is, the outer peripheral portion of the dividing surface of the divided wafer 20 on the second main surface side is ground into a conical shape. As a result, a bonded wafer 23 is formed in which the outer peripheral portion on the second main surface side is processed into a conical shape and is bonded to the unprocessed divided wafer 20. Through this process, the shape of the bonded wafer 21 can be made close to the shape of the original wafer 12, so that fine adjustment for wafer alignment is not required.

[0067] The fine adjustment for wafer alignment will be described in detail. In wafer alignment, when scanning a laser on the wafer, a portion where the light transmittance is below the threshold is recognized as the wafer edge. When the edge of the wafer is processed into a conical shape, since the surface of the conical portion is rough and light is difficult to pass through, the wafer edge becomes easy to be recognized.

[0068] On the other hand, for example, when the cross section of the wafer is ground into a convex structure, the wafer edge becomes thinner than the central portion of the wafer. In this case, sometimes the light transmittance at the wafer edge does not become below the threshold, and the wafer edge cannot be recognized.

[0069] Therefore, when processing such a wafer using the same apparatus as that for a normal wafer, it is necessary to adjust the threshold value of the light transmittance each time, or to set a new threshold value capable of recognizing the ends of both wafers. That is, in either case, fine adjustment for wafer alignment is required. In the beveling process of the present embodiment, since the outer peripheral portion on the second main surface side of the bonding wafer 21 is ground into a conical shape, there is an advantage that such fine adjustment is not required.

[0070] In addition, the bonding wafer 23 can also be processed, for example, by grinding, polishing, or CMP so that the whole becomes a desired substrate thickness. The desired substrate thickness can also be, for example, the same substrate thickness as that of the wafer 12. Thus, when the bonding wafer 23 is reused as a wafer, it is possible to carry and process it using the same apparatus as that before processing without making adjustments due to the difference in substrate thickness.

[0071] Figure 7 It is a diagram showing an element formation process according to Embodiment 1 of the present disclosure. In the element formation process of the present embodiment, an epitaxial film is formed on the second main surface side of the bonding wafer 23, and a semiconductor element structure 14 is formed on the epitaxial film. That is, the semiconductor element structure 14 is formed on the dividing surface of the dividing wafer 30. Among them, the semiconductor element structure 14 is formed at a position inside the outermost peripheral portion of the conical shape of the dividing wafer 30.

[0072] The semiconductor device 108 obtained thereby has the same function as the semiconductor device 100. Therefore, the semiconductor device 108 can also sequentially perform Figures 2 to 7 the processes shown.

[0073] As described above, by Figures 2 to 7 the processes shown, the reduction in the wafer diameter of the semiconductor device is suppressed, so that it is possible to carry and process it using the same apparatus as that before processing.

[0074] [Processing method of semiconductor device according to comparative example]

[0075] In order to explain the effects of the semiconductor device according to the present disclosure, the processing method of the semiconductor device according to the comparative example will be described. Figure 8 It is a diagram showing a semiconductor device according to the first comparative example. The semiconductor device 500 includes a wafer 502 and a semiconductor element structure 504, and has the same structure as the semiconductor device 100.

[0076] Figure 9This is a diagram showing the dicing process for the first comparative example. In the dicing process for the first comparative example, the wafer 502 is diced in a direction perpendicular to the thickness direction. As a result, the semiconductor device 500 is diced into a diced wafer 506 including the semiconductor element structure 504 and a diced wafer 508 not including the semiconductor element structure 504.

[0077] At this time, the outer peripheral portion of the diced wafer 506 becomes a thin and sharp blade. If a wafer with a blade on its outer peripheral portion is used to advance the manufacturing process of the semiconductor device, there will be problems such as dust generation or chip generation due to cutting the carrier that houses the wafer. Therefore, when performing the dicing process of the wafer, it is necessary to perform processing such that the outer peripheral portion does not become a blade.

[0078] Figure 10 This is a diagram showing the beveling process for the second comparative example. In the second comparative example, before the dicing process, a beveling process is performed on the semiconductor device 500 having the same structure as the first comparative example.

[0079] In the beveling process for the second comparative example, the outer peripheral portion of the wafer 502 is ground so as to penetrate in the thickness direction. That is, the outermost peripheral portion of the wafer 502 is removed. As a result, a diced wafer 510 including the semiconductor element structure 504 and a wafer outer peripheral portion 512 not including the semiconductor element structure 504 are generated.

[0080] Figure 11 This is a diagram showing the dicing process for the second comparative example. In the dicing process for the second comparative example, the diced wafer 510 is diced in a direction perpendicular to the thickness direction. As a result, the diced wafer 510 is diced into a diced wafer 514 including the semiconductor element structure 504 and a diced wafer 516 not including the semiconductor element structure 504.

[0081] At this time, the outer peripheral portion of the diced wafer 514 does not become a blade. This is because, by performing the beveling process shown in Figure 10 , the outermost peripheral portion that could become a blade is removed in advance. As a result, for the diced wafer 514, the manufacturing process of the semiconductor device can be advanced without generating dust or chips.

[0082] On the other hand, the wafer diameter of the diced wafer 516 becomes smaller than the wafer diameter of the original wafer 502. This is because, by performing the beveling process shown in Figure 10 , the outermost peripheral portion is removed. As a result, when the diced wafer 516 is reused, there will be problems such as being unable to use the same device as before the processing for handling and processes, or needing to adjust the device to be able to cope with the change in the wafer diameter. The present disclosure can solve this problem.

[0083] [Method for Processing a Semiconductor Device According to a Modified Example of Embodiment 1 of the Present Disclosure]

[0084] Hereinafter, a processing method according to a modified example of the present embodiment will be described. Figure 12 FIG. is a diagram showing a modified example of the grinding process according to Embodiment 1 of the present disclosure. The grinding process of the modified example is different from the Figure 6 grinding process in that it further includes a process of grinding the entire outer peripheral portion of the wafer.

[0085] Figure 12 The upper figure of FIG. is a diagram showing the semiconductor device 100 before the grinding process. Figure 12 The lower figure of FIG. is a diagram showing the semiconductor device 102a after the grinding process. The grinding process of the modified example further includes a process of grinding the entire outermost peripheral portion of the wafer in addition to the grinding process of Embodiment 1. Therefore, the wafer diameter of the wafer 16a after the grinding process becomes smaller than the wafer diameter of the wafer 12.

[0086] Since the end portion on the back side of the wafer 16 has a conical shape, the closer to the end portion, the thinner the substrate thickness. As a result, cracking and chipping may occur at the end portion on the back side of the wafer 16. The grinding process of the modified example has an effect of suppressing cracking and chipping at the end portion by also grinding the outer peripheral portion on the back side of the wafer 16a.

[0087] In addition, in the grinding process of the modified example, the width of grinding the entire outermost peripheral portion of the wafer, that is, the reduction amount of the wafer diameter, is preferably small. This is because, when the processing width is large, the wafer diameter of the wafer to be reused in the future becomes small, and there is a problem that handling and processing during device structure formation cannot be performed.

[0088] If the reduction amount of the wafer diameter is less than 1 mm, it can be handled by adjusting the device or changing the jig. In addition, if the reduction amount of the wafer diameter is less than 0.8 mm, the number of devices that can be handled without adjusting the device or changing the jig increases. Furthermore, if the reduction amount of the wafer diameter is less than 0.5 mm, the number of devices that can be handled without adjusting the device or changing the jig further increases. Therefore, the width of grinding the entire outer peripheral portion of the wafer is preferably less than 1 mm, more preferably less than 0.8 mm, and further preferably less than 0.5 mm.

[0089] In addition, the width of grinding the entire outermost peripheral portion of the wafer in the grinding process of the modified example is much smaller than the width of processing the outer peripheral portion in the beveling process according to the second comparative example. This is because the purpose of the beveling process according to the second comparative example can be achieved by forming a convex structure in the grinding process of the modified example. Therefore, the grinding process of the modified example has an effect of suppressing the reduction of the wafer diameter compared to the comparative example.

[0090] Figure 13 This is a diagram showing a first modification example of the bonding process according to Embodiment 1 of the present disclosure. In the bonding process of the first modification example, a divided wafer 20 and a divided wafer 22 having a wafer diameter smaller than that of the divided wafer 20 are bonded. As a result, a bonded wafer 21a having a convex cross-section is formed. In this way, by forming the bonded wafer with a convex structure, it is possible to suppress the bending of the wafer and also omit the beveling process performed subsequently.

[0091] Figure 14 This is a diagram showing a second modification example of the bonding process according to Embodiment 1 of the present disclosure. In the bonding process of the second modification example, the planarization process performed before bonding is different from that in Embodiment 1. Specifically, the amount of polishing performed on the outer peripheral portion of the bonding interface is made larger than the amount of polishing performed on the central portion of the bonding interface. As a result, the outer peripheral portion of the wafer becomes thinner than the central portion, and thus an unbonded region 26 is formed in the outer peripheral portion of the bonding interface of the bonded wafer 21b.

[0092] For example, by measuring this unbonded region 26 with an optical interference type wafer thickness measuring device, it is possible to measure the substrate thickness of each divided wafer to be bonded. That is, it is possible to detect in advance the depth of the bonding interface of the bonded wafer 21b.

[0093] For example, in the case of a wafer in which the dividing process and the bonding process are repeated multiple times, there may be a bonding interface near the semiconductor element structure 14 of the completed semiconductor device. In this case, problems such as poor characteristics and deteriorated reliability of the completed semiconductor device occur. Here, this modification example can detect in advance the bonding interface existing near the semiconductor element structure 14. Therefore, by grinding and removing this bonding interface, the above problems can be avoided.

[0094] In addition, in the subsequent wet etching process, moisture will penetrate into this unbonded region. This moisture cannot be removed by spin drying, which is a post-treatment of the wet etching process, and may cause problems in subsequent manufacturing processes. On the other hand, if the distance of the unbonded region from the outer periphery is 1 mm or less, the amount of infiltrated moisture can be ignored. Therefore, the distance of the unbonded region from the outer periphery of the bonded wafer 21b is preferably 1 mm or less.

[0095] Figure 15FIG. is a diagram showing a modified example of the beveling process according to Embodiment 1 of the present disclosure. In the beveling process of the modified example, the outer peripheral portion on the second main surface side of the bonding wafer 21 is processed so that the cross section becomes a convex structure. As a result, a bonded wafer 23a is formed by bonding a divided wafer 30a whose inner diameter is reduced by similarly grinding the outer peripheral portion and a divided wafer 20a whose outer peripheral portion is similarly ground to a certain depth so that the cross section becomes a convex structure. That is, the inner diameter of the upper surface of the divided wafer 20a is the same as the inner diameter of the divided wafer 30a.

[0096] The beveling process of this modified example can also be performed on the bonding wafer 21b according to the second modified example of the bonding process, for example. In this case, the unbonded region 26 can be removed by the beveling process.

[0097] Embodiment 2

[0098] [Processing method of semiconductor device according to Embodiment 2 of the present disclosure]

[0099] Figure 16 FIG. is a diagram showing the thick film process according to Embodiment 2 of the present disclosure. In Embodiment 1, in order to suppress the bending of the divided wafer 20, a bonding process of bonding a plurality of divided wafers 20 was performed. On the other hand, in the thick film process of the present embodiment, an epitaxial film 32 is formed on the divided wafer 20. As a result, a thick film wafer 41 having the same wafer diameter as the original wafer 12 is formed. By thickening the substrate thickness in this way, the bending of the wafer can be suppressed more than in the case of using only the divided wafer 20. Here, the epitaxial film 32 and the divided wafer 20 preferably have a small difference in resistivity. If the difference in resistivity between the epitaxial film 32 and the divided wafer 20 becomes large, the electrical characteristics change. This is because, as a result, there is a problem that the electrical characteristics of the entire semiconductor device change when forming the semiconductor element structure 14 in subsequent processes.

[0100] Here, the epitaxial film 32 and the divided wafer 20 preferably have a small difference in resistivity. If the difference in resistivity between the epitaxial film 32 and the divided wafer 20 becomes large, the electrical characteristics change. This is because, as a result, there is a problem that the electrical characteristics of the entire semiconductor device change when forming the semiconductor element structure 14 in subsequent processes.

[0101] If the above resistivity difference is within 30 mΩ·m, the change in the electrical characteristics of the entire semiconductor device converges to a level that can be used equivalently to the original semiconductor device. In addition, if the above resistivity difference is within 15 mΩ·m, the change in the electrical characteristics of the entire semiconductor device converges within the error range. Furthermore, if the above resistivity difference is within 6 mΩ·m, the change in the electrical characteristics of the entire semiconductor device is almost zero.

[0102] Therefore, the resistivity difference between the epitaxial film 32 and the divided wafer 20 is preferably within 30 mΩ·m, more preferably within 15 mΩ·m, and further preferably within 6 mΩ·m.

[0103] In addition, the epitaxial film 32 is preferably thick. This is because, when the epitaxial film 32 is thin, there is a problem that the effect of sufficiently suppressing the bending of the divided wafer 20 cannot be obtained.

[0104] If the thickness of the epitaxial film 32 is 50 μm or more, the bending can be sufficiently suppressed, but errors may occur during the transfer or adsorption of the manufacturing apparatus used. In addition, if the thickness of the epitaxial film 32 is 100 μm or more, the bending can be sufficiently suppressed, and almost no errors occur during the transfer or adsorption of the manufacturing apparatus used. Further, if the thickness of the epitaxial film 32 is 150 μm, the semiconductor device 114 becomes the same thickness as the wafer before division, so no errors occur during the transfer or adsorption of the manufacturing apparatus used.

[0105] Therefore, the thickness of the epitaxial film 32 is preferably 50 μm or more, more preferably 100 μm or more, and further preferably 150 μm.

[0106] Figure 17 FIG. is a view showing a chamfering process according to Embodiment 2 of the present disclosure. In the chamfering process of the present embodiment, the outer peripheral portion on the second main surface side of the thick film wafer is processed into a conical shape. As a result, a thick film wafer 43 having an epitaxial film 34 in which the outer peripheral portion on the second main surface side is processed into a conical shape formed on the unprocessed divided wafer 20 can be obtained.

[0107] In addition, the thick film wafer 43 can be processed into a desired substrate thickness by, for example, grinding, polishing, or CMP. The desired substrate thickness can be, for example, the same substrate thickness as the wafer 12. Thus, when the thick film wafer 43 is reused as a wafer, it is possible to carry and process using the same apparatus as the wafer before processing without performing adjustment due to the difference in substrate thickness.

[0108] Figure 18 FIG. is a view showing an element formation process according to Embodiment 2 of the present disclosure. In the element formation process of the present embodiment, an epitaxial film is formed on the second main surface side of the thick film wafer 43, and a semiconductor element structure 14 is formed on the epitaxial film. Among them, the semiconductor element structure 14 is formed at a position inside the conical outermost peripheral portion of the epitaxial film 34.

[0109] The semiconductor device 118 obtained thereby has the same function as the semiconductor device 100. Therefore, the semiconductor device 118 can also sequentially perform, like the semiconductor device 100, Figures 2 to 7 or Figures 2 to 3 and Figures 16 to 18 the processes shown.

[0110] As described above, through Figures 16 to 18The process shown suppresses the reduction of the wafer diameter of the semiconductor device, enabling handling and processing using the same equipment as before processing.

[0111] [Method for processing a semiconductor device according to a modified example of Embodiment 2 of the present disclosure]

[0112] Figure 19 It is a diagram showing a modified example of the beveling process according to Embodiment 2 of the present disclosure. In the beveling process of the modified example, the outer peripheral portion on the second main surface side of the thick film wafer 41 is processed so that the cross section becomes a convex structure. As a result, a thick film wafer 43a can be obtained in which an epitaxial film 34a ground to the same depth is formed on the divided wafer 20b whose outer peripheral portion is similarly ground.

[0113] For example, the beveling process of this modified example can also be applied to a semiconductor device having an unbonded region 26 such as the semiconductor device 104b. In this case, the unbonded region 26 can be removed by the beveling process.

[0114] Embodiment 3

[0115] Figure 20 It is a diagram showing the beveling process according to Embodiment 3 of the present disclosure. In Embodiments 1 and 2, in order to suppress the bending of the wafer 16, the beveling process was performed after thickening the entire wafer. On the other hand, the substrate thickness of the divided wafer according to this embodiment converges to a range where its bending does not interfere with the manufacturing process. Therefore, the divided wafer can be reused without being thickened. As a result, the man-hours required for reusing the wafer can be reduced.

[0116] In the beveling process of this embodiment, the outer peripheral portion on the second main surface side of the divided wafer is processed into a conical shape. As a result, a divided wafer 30b with the outer peripheral portion on the second main surface side processed into a conical shape can be obtained.

[0117] Figure 21 It is a diagram showing the element formation process according to Embodiment 3 of the present disclosure. In the element formation process of this embodiment, an epitaxial film is formed on the second main surface side of the divided wafer 30b, and a semiconductor element structure 14 is formed on the epitaxial film. Among them, the semiconductor element structure 14 is formed at a position on the divided wafer 30b inside the outermost peripheral portion of the conical shape.

[0118] The semiconductor device 128 thus obtained has the same function as the semiconductor device 100. Therefore, like the semiconductor device 100, the semiconductor device 128 can also sequentially perform Figures 2 to 7 the processes shown.

[0119] As described above, through Figures 20 to 21The process shown suppresses the reduction of the wafer diameter of the semiconductor device, enabling handling and processing using the same device as the wafer before processing.

[0120] Figure 22 It is a diagram showing a modification example of the beveling process according to Embodiment 3 of the present disclosure. In the beveling process of the modification example, the outer peripheral portion on the second main surface side of the divided wafer may also be processed in such a way that the cross section becomes a convex structure. As a result, a divided wafer 30c with the outer peripheral portion ground in the same manner can be obtained.

[0121] In addition, in the present disclosure, a method of bonding two divided wafers is described, but any method of bonding multiple divided wafers is acceptable. That is, the content of the present disclosure can also be applied to a method of bonding three or more divided wafers.

[0122] Hereinafter, each aspect of the present disclosure is collectively described as an appended note.

[0123] (Appended Note 1)

[0124] A method for manufacturing a semiconductor device, comprising:

[0125] Comprising:

[0126] A process of forming a semiconductor element structure on the second main surface of a wafer having a first main surface and a second main surface facing each other;

[0127] A process of grinding the outer peripheral portion of the second main surface of the wafer on which the semiconductor element structure is formed to the middle in the thickness direction from the second main surface toward the first main surface;

[0128] A process of dividing the wafer in a direction perpendicular to the thickness direction at a position shallower in depth from the second main surface than the depth at which the outer peripheral portion of the wafer is ground, and dividing a first divided wafer that does not include the semiconductor element structure from the wafer;

[0129] A process of grinding the outer peripheral portion of the dividing surface of the first divided wafer; and

[0130] A process of forming a semiconductor element structure on the dividing surface of the first divided wafer after grinding the outer peripheral portion of the dividing surface.

[0131] (Appended Note 2)

[0132] According to the method for manufacturing a semiconductor device described in Appended Note 1, wherein:

[0133] It further includes a process of bonding a second divided wafer to the first main surface of the first divided wafer.

[0134] (Appended Note 3)

[0135] The manufacturing method of the semiconductor device according to Note 2, wherein,

[0136] An amorphous layer is formed at the bonding interface between the first divided wafer and the second divided wafer.

[0137] (Note 4)

[0138] The manufacturing method of the semiconductor device according to Note 2 or 3, wherein,

[0139] It further includes a process of grinding and planarizing the bonding interface of the first divided wafer or the second divided wafer before bonding,

[0140] The grinding amount applied to the outer peripheral portion of the bonding interface is made larger than the grinding amount applied to the central portion of the bonding interface.

[0141] (Note 5)

[0142] The manufacturing method of the semiconductor device according to any one of claims 1 to 4, wherein,

[0143] The cross-section of the wafer after grinding the outer peripheral portion of the second main surface and before dicing is a convex structure.

[0144] (Note 6)

[0145] The manufacturing method of the semiconductor device according to claim 5, wherein,

[0146] It further includes a process of grinding the entire outermost peripheral portion of the wafer before dicing the wafer.

[0147] (Note 7)

[0148] The manufacturing method of the semiconductor device according to any one of claims 1 to 6, wherein,

[0149] The outer peripheral portion of the dicing surface of the first divided wafer is ground into a conical shape.

[0150] (Note 8)

[0151] The manufacturing method of the semiconductor device according to any one of claims 1 to 6, wherein,

[0152] The cross-section of the wafer after grinding the outer peripheral portion of the dicing surface of the first divided wafer and before forming the semiconductor element structure on the dicing surface is a convex structure.

[0153] (Note 9)

[0154] The manufacturing method of the semiconductor device according to claim 1, wherein,

[0155] It also has a process of forming an epitaxial film on the first divided wafer.

[0156] (Supplementary Note 10)

[0157] The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein

[0158] the wafer is formed of a wide bandgap semiconductor.

[0159] (Supplementary Note 11)

[0160] A semiconductor device, wherein

[0161] it includes:

[0162] a first divided wafer having a first main surface and a second main surface facing each other, and having a semiconductor element structure on the second main surface; and

[0163] a second divided wafer bonded to the first main surface of the first divided wafer,

[0164] an unbonded region is formed at the outer peripheral portion of the bonding interface between the first divided wafer and the second divided wafer.

[0165] (Supplementary Note 12)

[0166] The semiconductor device according to claim 11, wherein

[0167] an amorphous layer is formed at the bonding interface.

[0168] (Supplementary Note 13)

[0169] The semiconductor device according to claim 11 or 12, wherein

[0170] the outer peripheral portion of the first divided wafer is processed into a conical shape.

[0171] (Supplementary Note 14)

[0172] The semiconductor device according to any one of claims 11 to 13, wherein

[0173] the wafer diameter of the first divided wafer is smaller than the wafer diameter of the second divided wafer.

[0174] (Supplementary Note 15)

[0175] The semiconductor device according to any one of claims 11 to 14, wherein

[0176] the cross section of the second divided wafer has a convex structure,

[0177] the inner diameter of the upper surface of the second divided wafer is the same as the inner diameter of the first divided wafer.

[0178] (Supplementary Note 16)

[0179] A semiconductor device, wherein,

[0180] comprises:

[0181] a first divided wafer having a first main surface and a second main surface opposed to each other;

[0182] an epitaxial film formed on the second main surface of the first divided wafer; and

[0183] a semiconductor element structure formed on the epitaxial film,

[0184] the cross-section of the first divided wafer has a convex structure.

[0185] (Supplementary Note 17)

[0186] The semiconductor device according to claim 16, wherein,

[0187] the epitaxial film is 50 μm or more.

[0188] (Supplementary Note 18)

[0189] A semiconductor device, wherein,

[0190] it comprises a first divided wafer having a first main surface and a second main surface opposed to each other, and having a semiconductor element structure on the second main surface,

[0191] the cross-section of the first divided wafer has a convex structure.

Claims

1. A method for manufacturing a semiconductor device, wherein: have: forming a semiconductor element structure on the second main surface of a wafer having a first main surface and a second main surface facing each other; A step of grinding the outer periphery of the second main surface of the wafer on which the semiconductor element structure is formed to a point midway in the thickness direction from the second main surface toward the first main surface; The step of dividing the wafer in a direction perpendicular to the thickness direction at a position where the depth from the second main surface is shallower than the depth of the outer periphery of the wafer ground, thereby dividing the wafer into first divided wafers that do not include the semiconductor element structure; a step of grinding an outer peripheral portion of a divided surface of the first divided wafer; and The step of forming a semiconductor element structure on the divided surface of the first divided wafer after grinding the outer periphery of the divided surface.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further includes bonding a second divided wafer to the first main surface of the first divided wafer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: An amorphous layer is formed at a bonding interface between the first divided wafer and the second divided wafer.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The method further comprises the step of polishing and flattening the bonding interface of the first divided wafer or the second divided wafer before bonding. The amount of grinding applied to the outer peripheral portion of the bonding interface is greater than the amount of grinding applied to the central portion of the bonding interface.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The cross section of the wafer after grinding the outer peripheral portion of the second main surface and before division has a convex structure.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The method further includes grinding the entire outermost peripheral portion of the wafer before dividing the wafer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The outer peripheral portion of the split surface of the first split wafer is ground into a tapered shape.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: After the outer periphery of the split surface of the first split wafer is ground and before the semiconductor element structure is formed on the split surface, the cross section of the wafer has a convex structure.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further includes forming an epitaxial film on the first divided wafer.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The wafer is formed of a wide bandgap semiconductor.

11. A semiconductor device, wherein: have: A first divided wafer having a first main surface and a second main surface facing each other, wherein the second main surface has a semiconductor element structure; and a second divided wafer bonded to the first main surface of the first divided wafer, An unbonded region is formed at an outer periphery of a bonding interface between the first divided wafer and the second divided wafer.

12. The semiconductor device according to claim 11, wherein An amorphous layer is formed at the bonding interface.

13. The semiconductor device according to claim 11, wherein The outer peripheral portion of the first divided wafer is processed into a tapered shape.

14. The semiconductor device according to claim 11, wherein A wafer diameter of the first divided wafer is smaller than a wafer diameter of the second divided wafer.

15. The semiconductor device according to claim 11, wherein The cross section of the second split wafer is a convex structure, An inner diameter of an upper surface of the second divided wafer is the same as an inner diameter of the first divided wafer.

16. A semiconductor device, wherein: have: A first split wafer having a first main surface and a second main surface facing each other; an epitaxial film formed on the second main surface of the first divided wafer; and A semiconductor element structure is formed on the epitaxial film. The cross section of the first divided wafer has a convex structure.

17. The semiconductor device according to claim 16, wherein: The epitaxial film has a thickness of 50 μm or more.

18. A semiconductor device, wherein: A first divided wafer is provided, wherein the first divided wafer has a first main surface and a second main surface facing each other, and the second main surface has a semiconductor element structure, The cross section of the first divided wafer has a convex structure.

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