Deposition apparatus

Abstract

The invention relates to a deposition apparatus. The deposition apparatus includes: a chamber; a deposition source disposed within the chamber; a mask disposed within the chamber between the first substrate and the deposition source; and a mask support disposed between the deposition source and the mask and supporting at least a portion of the mask. The mask includes a plurality of cell regions and a mask frame region other than the plurality of cell regions, the mask frame region includes a mask rib region separating the plurality of cell regions and an outer frame region provided at an outermost periphery of the mask, and the mask support includes a plurality of support ribs, the plurality of support ribs each support the mask rib region and have a cross-sectional structure having a taper angle, and the taper angles of each of the plurality of support ribs are different from each other.

Description

Technical Field

[0001] The present disclosure relates to deposition equipment. Background Art

[0002] A wearable device has been developed in the form of glasses or a helmet, which forms a focus at a short distance from the user's eyes. For example, the wearable device may be a head-mounted display (HMD) device or augmented reality (AR) glasses. Such a wearable device provides an AR screen or a virtual reality (VR) screen to the user.

[0003] Wearable devices such as HMD devices or AR glasses are required to have a display specification of at least 2,000 pixels per inch (PPI) so that a user can use it for a long time without dizziness. For this purpose, organic light-emitting diodes on silicon (OLEDoS) technology has been proposed, which is a small high-resolution organic light-emitting display device. OLEDoS is a technology in which an organic light-emitting diode (OLED) is placed on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided.

[0004] To manufacture a display panel having a resolution of 3,500 PPI or higher, a high-resolution deposition mask is required. Summary of the Invention

[0005] Aspects of the present disclosure provide a deposition equipment for easily manufacturing a display device having a resolution of 3,500 pixels per inch (PPI) or higher.

[0006] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to an embodiment of the present disclosure, a deposition equipment may include: a chamber; a deposition source disposed in the chamber; a mask disposed in the chamber between a first substrate and the deposition source; and a mask support disposed between the deposition source and the mask and supporting at least a part of the mask. The mask may include a plurality of unit regions and a mask frame region other than the plurality of unit regions, the mask frame region may include a mask rib region separating the plurality of unit regions and an outer frame region disposed at the outermost periphery of the mask, the mask support may include a plurality of support ribs, each of the plurality of support ribs supports the mask rib region and has a cross-sectional structure having a taper angle, and the taper angles of each of the plurality of support ribs may be different from each other.

[0008] The mask support may further include an electrostatic chuck supporting the outer frame region.

[0009] The electrostatic chuck of the mask support may be integrally formed with the plurality of support ribs.

[0010] The electrostatic chuck of the mask support can be separately provided from a plurality of support ribs and connected to some of the plurality of support ribs.

[0011] The material of the mask support may include invar alloy.

[0012] The material of the mask support may include stainless steel.

[0013] The taper angle of each of the plurality of support ribs may be less than or equal to the deposition incident angle formed by the deposition source and the corresponding one of the plurality of support ribs.

[0014] The plurality of support ribs may include: a first support rib that forms a first deposition incident angle with the deposition source and supports a first mask rib region spaced apart from the center of the mask by a first distance; a second support rib that forms a second deposition incident angle greater than the first deposition incident angle with the deposition source and supports a second mask rib region spaced apart from the center of the mask by a second distance; and a third support rib that forms a third deposition incident angle greater than the second deposition incident angle with the deposition source and supports a third mask rib region spaced apart from the center of the mask by a third distance.

[0015] The cross-sectional structure of the first support rib may have a first taper angle less than or equal to the first deposition incident angle, the cross-sectional structure of the second support rib may have a second taper angle less than or equal to the second deposition incident angle, and the cross-sectional structure of the third support rib may have a third taper angle less than or equal to the third deposition incident angle.

[0016] The first taper angle may be greater than or equal to the second taper angle, and the second taper angle may be greater than or equal to the third taper angle.

[0017] The first taper angle may be less than or equal to the second taper angle, and the second taper angle may be less than or equal to the third taper angle.

[0018] The first taper angle may be equal to the third taper angle, and the second taper angle may be less than the first taper angle.

[0019] The first taper angle may be equal to the third taper angle and less than the second taper angle.

[0020] Each of the first support rib to the third support rib may have a symmetric structure in a cross-sectional view.

[0021] At least one of the first support rib to the third support rib may have an asymmetric structure in a cross-sectional view.

[0022] The heights of the first support rib to the third support rib may be different from each other.

[0023] The first support rib may have a first height, the second support rib may have a second height greater than the first height, and the third support rib may have a third height greater than the second height.

[0024] The first support rib may have a first height, the second support rib may have a second height less than the first height, and the third support rib may have a third height less than the second height.

[0025] The mask may further include a mask diaphragm including an inorganic layer.

[0026] The mask may further include a mask diaphragm including a metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] These and / or other aspects will become apparent and more readily appreciated from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is an exploded perspective view of a display device according to an embodiment;

[0029] Figure 2 is a schematic block diagram of a display device according to an embodiment;

[0030] Figure 3 is a schematic diagram of an equivalent circuit of a first sub-pixel according to an embodiment;

[0031] Figure 4 is a plan view showing the layout of a display panel according to an embodiment;

[0032] Figure 5 is a plan view showing the layout of the Figure 4 display area according to an embodiment;

[0033] Figure 6 is a plan view showing the layout of the Figure 4 display area according to an embodiment;

[0034] Figure 7 is a schematic cross-sectional view of a display panel taken along line I1-I1' according to an embodiment Figure 5 ;

[0035] Figure 8 is a perspective view of a head-mounted display device according to an embodiment;

[0036] Figure 9 is a perspective view of the Figure 8 head-mounted display device according to an embodiment;

[0037] Figure 10 is a perspective view of a head-mounted display device according to an embodiment;

[0038] Figure 11 is a perspective view of a mask according to an embodiment;

[0039] Figure 12 is a schematic plan view of a mask according to an embodiment;

[0040] Figure 13 is a schematic cross-sectional view showing the configuration of a deposition apparatus according to an embodiment;

[0041] Figure 14 is a schematic cross-sectional view of a mask according to an embodiment;

[0042] Figure 15 is a perspective view of a mask support according to an embodiment;

[0043] Figure 16 schematically shows a plurality of support ribs of a mask support according to an embodiment; and

[0044] Figures 17 to 23 is a schematic cross-sectional view showing the structure of a first support rib to a third support rib according to an embodiment. Detailed Embodiments

[0045] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0046] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. For this reason, the term "connection" may refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements. Further, when an element is referred to as being "in contact" or "contacted" with another element, etc., the element may be "electrically in contact" or "physically in contact" with the other element, or "indirectly in contact" or "directly in contact" with the other element. Throughout the specification, like reference numerals denote like components.

[0047] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure. Similarly, the second element may also be referred to as the first element.

[0048] Given the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximate" includes the recited value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0049] For descriptive purposes, spatial relative terms, such as "below", "beneath", "under", "lower", "above", "upper", "on", "over", "higher", "side" (e.g., as in "sidewall"), etc., may be used herein and thereby describe the relationship of one element to another (or elements) as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation above and below. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0050] In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B". In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0051] The features of each of the various embodiments of the present disclosure can be partially or fully combined with each other, and can cooperate with each other in technically different ways, and the various embodiments can be implemented independently of each other, or can be implemented together in a related manner.

[0052] All terms used (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise defined or implied herein. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0053] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0054] Figure 1 is an exploded perspective view of a display device 10 according to an embodiment. Figure 2 is a schematic block diagram of a display device 10 according to an embodiment.

[0055] Reference Figure 1 and Figure 2 , the display device 10 according to an embodiment may be a device for displaying moving images or still images. The display device 10 according to an embodiment may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 according to an embodiment may be used as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. In another embodiment, the display device 10 according to an embodiment may be applied to a smart watch, a watch phone, and a head-mounted display for realizing virtual reality and augmented reality.

[0056] The display device 10 according to an embodiment may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing controller 400, and a power supply unit 500.

[0057] The display panel 100 may have a shape similar to a quadrilateral in a plan view. For example, the display panel 100 may have a shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1 in a plan view. In the display panel 100, each corner where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect may be a rounded corner having a curvature or may be a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the embodiments of the present disclosure are not limited thereto.

[0058] As Figure 2As shown, the display panel 100 may include a display area DAA for displaying an image and a non-display area NDA for not displaying an image.

[0059] The display area DAA may include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0060] The pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. The scan lines SL and the emission control lines EL may extend in the first direction DR1 and may be arranged in the second direction DR2. The data lines DL may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0061] The scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The emission control lines EL may include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0062] Each of the pixels PX may include a plurality of sub-pixels SP1 to SP3. Each of the sub-pixels SP1 to SP3 may include a plurality of pixel transistors as Figure 3 shown. The pixel transistors may be formed by a semiconductor process and may be provided on a semiconductor substrate SSUB (see Figure 7 ). For example, the plurality of pixel transistors of the data driver 700 may be formed as complementary metal oxide semiconductors (CMOS).

[0063] Each of the sub-pixels SP1 to SP3 may be connected to one of the write scan lines GWL, one of the control scan lines GCL, one of the bias scan lines EBL, one of the first emission control lines EL1, one of the second emission control lines EL2, and one of the data lines DL. Each of the sub-pixels SP1 to SP3 may receive the data voltage of the data line DL according to the write scan signal of the write scan line GWL, and cause the light-emitting element to emit light according to the data voltage.

[0064] The non-display area NDA may include a scan driver 610, an emission driver 620, and a data driver 700.

[0065] The scan driver 610 may include a plurality of scan transistors, and the emission driver 620 may include a plurality of emission transistors. The scan transistors and the emission transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Figure 7 ). For example, the scan transistors and the emission transistors may be formed as CMOS. Figure 2It is shown that the scan driver 610 is disposed on the left side of the display area DAA, and the emission driver 620 is disposed on the right side of the display area DAA. However, embodiments of the present disclosure are not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on both the left and right sides of the display area DAA.

[0066] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing controller 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing controller 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line EBL.

[0067] The emission driver 620 may include a first emission control driving unit 621 and a second emission control driving unit 622. Each of the first emission control driving unit 621 and the second emission control driving unit 622 may receive an emission timing control signal ECS from the timing controller 400. The first emission control driving unit 621 may generate a first emission control signal according to the emission timing control signal ECS, and sequentially output the first emission control signal to the first emission control line EL1. The second emission control driving unit 622 may generate a second emission control signal according to the emission timing control signal ECS, and sequentially output the second emission control signal to the second emission control line EL2.

[0068] The data driver 700 may include a plurality of data transistors. The data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Figure 7 ). For example, the data transistors may be formed as CMOS.

[0069] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing controller 400. The data driver 700 may convert the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and output the analog data voltage to the data lines DL. The sub-pixels SP1 to SP3 may be selected by a write scan signal of the scan driver 610, and the data voltage may be provided to the selected sub-pixels SP1 to SP3.

[0070] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on the surface (e.g., the back surface) of the display panel 100. The heat dissipation layer 200 may dissipate the heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0071] The circuit board 300 may be electrically connected to a first pad portion PDA1 (see Figure 4 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film, and a plurality of first pads PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board made of a flexible material, or may be a flexible film. Although Figure 1 the circuit board 300 is shown as not being folded, the circuit board 300 may be bent, and one end of the circuit board 300 may be placed on the back surface of the display panel 100 and / or the back surface of the heat dissipation layer 200. One end of the circuit board 300 may be an end opposite to the other end of the circuit board 300 that is connected to the first pad portion PDA1 (see Figure 4 ) of the display panel 100 by using a conductive adhesive member, and the first pads PD1 (see Figure 4 ).

[0072] The timing controller 400 may receive digital video data DATA and timing signals from the outside. The timing controller 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 according to the timing signals. The timing controller 400 may output the scan timing control signal SCS to the scan driver 610, and output the emission timing control signal ECS to the emission driver 620. The timing controller 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0073] The power supply unit 500 may generate a plurality of panel driving voltages based on a power supply voltage received from the outside. For example, the power supply unit 500 may generate a first driving voltage VSS, a second driving voltage VDD, a third driving voltage VINT, and a fourth driving voltage VREF, and supply the driving voltages to the display panel 100. Below will refer to Figure 3 describe the first driving voltage VSS, the second driving voltage VDD, the third driving voltage VINT, and the fourth driving voltage VREF.

[0074] Each of the timing controller 400 and the power supply unit 500 may be formed as an integrated circuit and attached to the surface of the circuit board 300, and the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing controller 400 may be provided to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply unit 500 may be provided to the display panel 100 through the circuit board 300.

[0075] In another embodiment, like the scan driver 610, the emission driver 620, and the data driver 700, the timing controller 400 and the power supply unit 500 may be disposed in the non-display area NDA of the display panel 100, and the timing controller 400 may include a plurality of timing transistors, and the power supply unit 500 may include a plurality of power transistors. The timing transistors and the power transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Figure 7 ). For example, the timing transistors and the power transistors may be formed as CMOS. Each of the timing controller 400 and the power supply unit 500 may be disposed between the data driver 700 and the first pad portion PDA1 (see Figure 4 ).

[0076] Figure 3 is a schematic diagram of an equivalent circuit of a first sub-pixel SP1 according to an embodiment.

[0077] Refer to Figure 3, the first sub-pixel SP1 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line EBL, a first emission control line EL1, a second emission control line EL2, and a data line DL. The first sub-pixel SP1 can also be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage line VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied. For example, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. The first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0078] The first sub-pixel SP1 can include a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0079] The light-emitting element LE can emit light according to a driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted from the light-emitting element LE can be proportional to the driving current Ids. The light-emitting element LE can be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE can be an anode, and the second electrode of the light-emitting element LE can be a cathode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode. However, the embodiments of the present disclosure are not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. The light-emitting element LE can be a micro light-emitting diode.

[0080] The first transistor T1 can be a driving transistor that controls a source-drain current Ids (also referred to as a "driving current") flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 can include a gate electrode connected to a first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0081] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by a write scan signal of the write scan line GWL and connect one electrode of the first capacitor CP1 to the data line DL. Accordingly, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 can include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0082] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 can be turned on by a control scan signal of the control scan line GCL and connect the first node N1 to the second node N2. Accordingly, since the gate electrode and the source electrode of the first transistor T1 are connected, the first transistor T1 can operate as a diode. The third transistor T3 can include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0083] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 can be turned on by a first emission control signal of the first emission control line EL1 and connect the second node N2 to the third node N3. Accordingly, the drive current Ids of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 can include a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0084] The fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 can be turned on by a bias scan signal of the bias scan line EBL and connect the third node N3 to the third drive voltage line VIL. Accordingly, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 can include a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0085] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 can be turned on by a second emission control signal of the second emission control line EL2, and connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, a second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 can include a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0086] The first capacitor CP1 can be formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 can include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0087] The second capacitor CP2 can be formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 can include one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0088] The first node N1 can be a contact point among the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, another electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 can be a contact point among the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 can be a contact point among the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0089] Each of the first transistor T1 to the sixth transistor T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET. However, embodiments of the present disclosure are not limited thereto. Each of the first transistor T1 to the sixth transistor T6 can also be an N-type MOSFET. In another embodiment, some of the first transistor T1 to the sixth transistor T6 can be P-type MOSFETs, and other transistors can be N-type MOSFETs.

[0090] Figure 3 It is shown that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 3 the circuit diagram shown in. For example, the number of transistors and capacitors of the first sub-pixel SP1 is not limited to Figure 3The embodiment shown in

[0091] The equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 may be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described with reference to Figure 3 Accordingly, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will not be described in the specification.

[0092] Figure 4 is a plan view showing the layout of the display panel 100 according to an embodiment.

[0093] Reference Figure 4 , the display area DAA of the display panel 100 according to an embodiment may include a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to an embodiment may include a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0094] The scan driver 610 may be disposed on a first side of the display area DAA, and the emission driver 620 may be disposed on a second side of the display area DAA. For example, the scan driver 610 may be disposed on one side in a first direction DR1 of the display area DAA, and the emission driver 620 may be disposed on the other side in the first direction DR1 of the display area DAA. For example, the scan driver 610 may be disposed on the left side of the display area DAA, and the emission driver 620 may be disposed on the right side of the display area DAA. However, the embodiments of the present disclosure are not limited thereto, and the scan driver 610 and the emission driver 620 may be disposed on both the first side and the second side of the display area DAA.

[0095] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through a conductive adhesive member. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side in a second direction DR2 of the display area DAA.

[0096] The first pad portion PDA1 may be disposed on one side in a second direction DR2 of the data driver 700. For example, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0097] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to test pads for testing whether the display panel 100 is operating normally. The second pads PD2 may be connected to a jig or probe pins during a test process, or may be connected to a test circuit board. The test circuit board may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0098] The first distribution circuit 710 may distribute the data voltage received through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 may distribute the data voltage received through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer greater than or equal to 2) data lines DL. Accordingly, the number of the first pads PD1 may be reduced. The first distribution circuit 710 may be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be disposed on one side in the second direction DR2 of the display area DAA. For example, the first distribution circuit 710 may be disposed on the lower side of the display area DAA.

[0099] The second distribution circuit 720 may distribute the signals received through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data lines DL. The second pad portion PDA2 and the second distribution circuit 720 may be elements for testing the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 may be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 may be disposed on the other side in the second direction DR2 of the display area DAA. For example, the second distribution circuit 720 may be disposed on the upper side of the display area DAA.

[0100] Figure 5 and Figure 6 is a plan view showing the layout of the Figure 4 display area DAA according to an embodiment.

[0101] Referring Figure 5 and Figure 6 each of the pixels PX may have a first emission area EA1 as an emission area of the first sub-pixel SP1, a second emission area EA2 as an emission area of the second sub-pixel SP2, and a third emission area EA3 as an emission area of the third sub-pixel SP3.

[0102] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal, circular, elliptical, or irregular shape in a plan view.

[0103] The maximum length in the first direction DR1 of the third emission region EA3 can be less than the maximum length in the first direction DR1 of the first emission region EA1 and the maximum length in the first direction DR1 of the second emission region EA2. The maximum length in the first direction DR1 of the first emission region EA1 and the maximum length in the first direction DR1 of the second emission region EA2 can be substantially the same.

[0104] The maximum length in the second direction DR2 of the third emission region EA3 can be greater than the maximum length in the second direction DR2 of the first emission region EA1 and the maximum length in the second direction DR2 of the second emission region EA2. The maximum length in the second direction DR2 of the first emission region EA1 can be greater than the maximum length in the second direction DR2 of the second emission region EA2.

[0105] As Figure 5 and Figure 6 shown, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can have a hexagonal shape composed of six straight lines in a plan view. However, embodiments of the present disclosure are not limited thereto. The first emission region EA1, the second emission region EA2, and the third emission region EA3 can have a polygonal planar shape other than a hexagonal shape or a circular, elliptical, or irregular planar shape.

[0106] As Figure 5 shown, in each of the pixels PX, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the second direction DR2. The first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1. The second emission region EA2 and the third emission region EA3 can be adjacent to each other in the first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be different in a plan view.

[0107] In another embodiment, as Figure 6 shown, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the first direction DR1. However, the second emission region EA2 and the third emission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be a direction between the first direction DR1 and the second direction DR2 and a direction inclined 45 degrees with respect to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 can be a direction orthogonal to the first diagonal direction DD1.

[0108] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. In an embodiment, the light of the first color can be light in a blue wavelength band, the light of the second color can be light in a green wavelength band, and the light of the third color can be light in a red wavelength band. For example, the blue wavelength band can have a main peak wavelength of light included in a wavelength band ranging from about 370 nm to about 460 nm, the green wavelength band can have a main peak wavelength of light included in a wavelength band ranging from about 480 nm to about 560 nm, and the red wavelength band can have a main peak wavelength of light included in a wavelength band ranging from about 600 nm to about 750 nm.

[0109] Although each of the pixels PX in Figure 5 and Figure 6 includes three emission regions EA1 to EA3, embodiments of the present disclosure are not limited thereto. In another embodiment, each of the pixels PX can include four emission regions.

[0110] The arrangement of the emission regions of the pixel PX is not limited to Figure 5 and Figure 6 shown therein. For example, the emission regions of the pixel PX can be arranged in a stripe structure in which the emission regions are arranged in a first direction DR1, a structure in which the emission regions are arranged in a diamond shape, or a hexagonal structure in which the emission regions having a hexagonal planar shape are arranged as Figure 6 shown therein.

[0111] Figure 7 is a schematic cross-sectional view of the display panel 100 taken along the line I1-I1' of Figure 5 according to an embodiment.

[0112] Referring to Figure 7 , the display panel 100 can include a semiconductor backplane SBP, a light-emitting element backplane EBP, a display element layer EML, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizer POL.

[0113] The semiconductor backplane SBP can include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the pixel transistors PTR. The pixel transistor PTR can be any one of the first transistor T1 to the sixth transistor T6 described with reference to Figure 3 .

[0114] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with impurities of a first type. A plurality of well regions WA can be formed on the upper surface of the semiconductor substrate SSUB. The well region WA can be a region doped with impurities of a second type. The impurities of the second type can be different from the above-mentioned impurities of the first type. For example, when the impurities of the first type are p-type impurities, the impurities of the second type can be n-type impurities. In another embodiment, when the impurities of the first type are n-type impurities, the impurities of the second type can be p-type impurities.

[0115] Each of the well regions WA can include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0116] A bottom insulating layer BINS can be disposed between the gate electrode GE and each well region WA. A side insulating layer SINS can be disposed on the side surface of the gate electrode GE.

[0117] Each of the source region SA and the drain region DA can be a region doped with impurities of the first type. The gate electrode GE of each pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0118] Each of the well regions WA can further include a first lightly doped impurity region LDD1 disposed between the channel region CH and the source region SA and a second lightly doped impurity region LDD2 disposed between the channel region CH and the drain region DA. The first lightly doped impurity region LDD1 can be a region having a lower impurity concentration than the source region SA due to the bottom insulating layer BINS. The second lightly doped impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA due to the bottom insulating layer BINS. The distance between the source region SA and the drain region DA can be increased by the first lightly doped impurity region LDD1 and the second lightly doped impurity region LDD2. Therefore, the length of the channel region CH of each pixel transistor PTR can be increased, thereby preventing punch-through and hot carrier phenomena caused by a short channel.

[0119] A first semiconductor insulating layer SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 can be an inorganic layer based on silicon carbonitride (SiCN) or silicon oxide (SiO x )), but the embodiments of the present disclosure are not limited thereto.

[0120] The second semiconductor insulating layer SINS2 may be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be an inorganic layer based on silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0121] The contact terminal CTE may be disposed on the second semiconductor insulating layer SINS2. Each of the contact terminals CTE may be connected to one of the gate electrode GE, source region SA, and drain region DA of the pixel transistor PTR through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The contact terminal CTE may be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys.

[0122] The third semiconductor insulating layer SINS3 may be disposed on the side surfaces of each of the contact terminals CTE. The upper surface of each of the contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be an inorganic layer based on silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0123] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as a polyimide substrate), and a thin film transistor may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a non-bendable rigid substrate, and the polymer resin substrate may be a flexible substrate that can be bent or curved.

[0124] The light-emitting element backplane EBP may include a plurality of conductive layers ML1 to ML8 and a plurality of through holes VA1 to VA9. The light-emitting element backplane EBP may further include a plurality of insulating layers INS1 to INS9 disposed between the first conductive layer ML1 to the eighth conductive layer ML8.

[0125] The first conductive layer ML1 to the eighth conductive layer ML8 may be implemented by connecting the contact terminals CTE exposed in the semiconductor backplane SBP Figure 3 to the circuit of the first sub-pixel SP1 shown therein. For example, only the first transistor T1 to the sixth transistor T6 may be formed in the semiconductor backplane SBP, and the connection of the first transistor T1 to the sixth transistor T6 with the first capacitor CP1 and the second capacitor CP2 may be implemented by the first conductive layer ML1 to the eighth conductive layer ML8. The connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE may be implemented by the first conductive layer ML1 to the eighth conductive layer ML8.

[0126] The first insulating layer INS1 can be disposed on the semiconductor backplane SBP. The first via holes VA1 can pass through the first insulating layer INS1 and can be respectively connected to the contact terminals CTE exposed in the semiconductor backplane SBP. The first conductive layer ML1 can be disposed on the first insulating layer INS1 and can be respectively connected to the first via holes VA1.

[0127] The second insulating layer INS2 can be disposed on the first insulating layer INS1 and the first conductive layer ML1. The second via holes VA2 can pass through the second insulating layer INS2 and can be respectively connected to the exposed first conductive layer ML1. The second conductive layer ML2 can be disposed on the second insulating layer INS2 and can be respectively connected to the second via holes VA2.

[0128] The third insulating layer INS3 can be disposed on the second insulating layer INS2 and the second conductive layer ML2. The third via holes VA3 can pass through the third insulating layer INS3 and can be respectively connected to the exposed second conductive layer ML2. The third conductive layer ML3 can be disposed on the third insulating layer INS3 and can be respectively connected to the third via holes VA3.

[0129] The fourth insulating layer INS4 can be disposed on the third insulating layer INS3 and the third conductive layer ML3. The fourth via holes VA4 can pass through the fourth insulating layer INS4 and can be respectively connected to the exposed third conductive layer ML3. The fourth conductive layer ML4 can be disposed on the fourth insulating layer INS4 and can be respectively connected to the fourth via holes VA4.

[0130] The fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. The fifth via holes VA5 can pass through the fifth insulating layer INS5 and can be respectively connected to the exposed fourth conductive layer ML4. The fifth conductive layer ML5 can be disposed on the fifth insulating layer INS5 and can be respectively connected to the fifth via holes VA5.

[0131] The sixth insulating layer INS6 can be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. The sixth via holes VA6 can pass through the sixth insulating layer INS6 and can be respectively connected to the exposed fifth conductive layer ML5. The sixth conductive layer ML6 can be disposed on the sixth insulating layer INS6 and can be respectively connected to the sixth via holes VA6.

[0132] The seventh insulating layer INS7 can be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. The seventh via holes VA7 can pass through the seventh insulating layer INS7 and can be respectively connected to the exposed sixth conductive layer ML6. The seventh conductive layer ML7 can be disposed on the seventh insulating layer INS7 and can be respectively connected to the seventh via holes VA7.

[0133] The eighth insulating layer INS8 can be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. The eighth via hole VA8 can pass through the eighth insulating layer INS8 and can be respectively connected to the exposed seventh conductive layer ML7. The eighth conductive layer ML8 can be disposed on the eighth insulating layer INS8 and can be respectively connected to the eighth via hole VA8.

[0134] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via hole VA1 to the eighth via hole VA8 can be made of substantially the same material. For example, the first conductive layer ML1 to the eighth conductive layer ML8 and the first via hole VA1 to the eighth via hole VA8 can be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys. The first via hole VA1 to the eighth via hole VA8 can be made of substantially the same material. Each of the first insulating layer INS1 to the eighth insulating layer INS8 can be an inorganic layer based on silicon oxide (SiO x )), but embodiments of the present disclosure are not limited thereto.

[0135] In the third direction DR3, the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can each be greater than the thickness of the first via hole VA1, the thickness of the second via hole VA2, the thickness of the third via hole VA3, the thickness of the fourth via hole VA4, the thickness of the fifth via hole VA5, and the thickness of the sixth via hole VA6. In the third direction DR3, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can each be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be about and the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can each be about The thickness of the first via hole VA1, the thickness of the second via hole VA2, the thickness of the third via hole VA3, the thickness of the fourth via hole VA4, the thickness of the fifth via hole VA5, and the thickness of the sixth via hole VA6 can each be about

[0136] In a third direction DR3, the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 can each be greater than the thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. In the third direction DR3, the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 can each be greater than the thicknesses of the seventh via hole VA7 and the eighth via hole VA8. The thicknesses of the seventh via hole VA7 and the eighth via hole VA8 can each be greater than the thicknesses of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6. The thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thicknesses of the seventh conductive layer ML7 and the eighth conductive layer ML8 can each be about The thicknesses of the seventh via hole VA7 and the eighth via hole VA8 can each be about

[0137] A ninth insulating layer INS9 can be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be an inorganic layer based on silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto.

[0138] A ninth via hole VA9 can pass through the ninth insulating layer INS9 and can be respectively connected to the exposed eighth conductive layer ML8. The ninth via hole VA9 can be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys. In the third direction DR3, the thickness of the ninth via hole VA9 can be about

[0139] A display element layer EML can be disposed on a light-emitting element backplane EBP. The display element layer EML can include a reflective electrode layer RL, a tenth insulating layer INS10 and an eleventh insulating layer INS11, a tenth via hole VA10, light-emitting elements LE each including a first electrode AND, a light-emitting stack IL, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0140] The reflective electrode layer RL can be disposed on the ninth insulating layer INS9. The reflective electrode layer RL can include one or more reflective electrodes RL1 to RL4. For example, as Figure 7 shown, the reflective electrode layer RL can include a first reflective electrode RL1 to a fourth reflective electrode RL4.

[0141] The first reflective electrode RL1 can be disposed on the ninth insulating layer INS9 and can be respectively connected to the ninth via hole VA9. The first reflective electrode RL1 can be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys. For example, the first reflective electrode RL1 can include titanium nitride (TiN).

[0142] The second reflective electrode RL2 can be respectively disposed on the first reflective electrode RL1. The second reflective electrode RL2 can be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys. For example, the second reflective electrode RL2 can include aluminum (Al).

[0143] The third reflective electrode RL3 can be respectively disposed on the second reflective electrode RL2. The third reflective electrode RL3 can be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys. For example, the third reflective electrode RL3 can include titanium nitride (TiN).

[0144] The fourth reflective electrode RL4 can be respectively disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 can be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys. For example, the fourth reflective electrode RL4 can include titanium (Ti).

[0145] Since the second reflective electrode RL2 is an electrode that substantially reflects the light from the light-emitting element LE, in the third direction DR3, the thickness of the second reflective electrode RL2 can be greater than the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4. For example, the thickness of the first reflective electrode RL1, the thickness of the third reflective electrode RL3, and the thickness of the fourth reflective electrode RL4 can be about And the thickness of the second reflective electrode RL2 can be about

[0146] The tenth insulating layer INS10 can be disposed on the ninth insulating layer INS9. The tenth insulating layer INS10 can be disposed between the reflective electrode layers RL adjacent to each other in the horizontal direction. The tenth insulating layer INS10 can be an inorganic layer based on silicon oxide (SiO x )), but the embodiments of the present disclosure are not limited thereto.

[0147] The eleventh insulating layer INS11 may be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 may be an inorganic layer based on silicon oxide (SiO x ), but embodiments of the present disclosure are not limited thereto. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical assist layers, and light reflected by the reflective electrode layer RL among the light emitted from the light emitting element LE passes through the optical assist layers.

[0148] The tenth insulating layer INS10 or the eleventh insulating layer INS11 may not be disposed under the first electrode AND of at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 to match the resonance distance of the light emitted from the light emitting element LE. For example, the first electrode AND of the first sub-pixel SP1 may be disposed on the reflective electrode layer RL. The eleventh insulating layer INS11 may be disposed under the first electrode AND of the second sub-pixel SP2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be disposed under the first electrode AND of the third sub-pixel SP3.

[0149] In an embodiment, the distance between the first electrode AND and the reflective electrode layer RL may be different in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, whether the tenth insulating layer INS10 and the eleventh insulating layer INS11 exist in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be set according to the main wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 to adjust the distance from the reflective electrode layer RL to the first electrode AND. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. However, embodiments of the present disclosure are not limited thereto.

[0150] Although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are described in embodiments of the present disclosure, a twelfth insulating layer disposed under the first electrode AND of the first sub-pixel SP1 may also be added. The eleventh insulating layer INS11 and the twelfth insulating layer may be disposed under the first electrode AND of the second sub-pixel SP2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer may be disposed under the first electrode AND of the third sub-pixel SP3.

[0151] The tenth through-hole VA10 can pass through the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the second sub-pixel SP2 and the third sub-pixel SP3 respectively, and can be connected to the exposed fourth reflective electrode RL4. The tenth through-hole VA10 can be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys. In the third direction DR3, the thickness of the tenth through-hole VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth through-hole VA10 in the third sub-pixel SP3.

[0152] The first electrode AND of the light-emitting element LE can be disposed on the tenth insulating layer INS10 and can be connected to the tenth through-hole VA10 respectively. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth through-hole VA10, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first through-hole VA1 to the ninth through-hole VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be made of at least one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and their alloys. For example, the first electrode AND of each of the light-emitting elements LE can include titanium nitride (TiN).

[0153] The pixel defining layer PDL can be disposed on a part of the first electrode AND of each of the light-emitting elements LE. The pixel defining layer PDL can cover the edge of the first electrode AND of each of the light-emitting elements LE. The pixel defining layer PDL can define the first emission region EA1 to the third emission region EA3.

[0154] The first emission region EA1 can be defined as the region where the first electrode AND, the light-emitting stack IL, and the second electrode CAT in the first sub-pixel SP1 are stacked in sequence to emit light. The second emission region EA2 can be defined as the region where the first electrode AND, the light-emitting stack IL, and the second electrode CAT in the second sub-pixel SP2 are stacked in sequence to emit light. The third emission region EA3 can be defined as the region where the first electrode AND, the light-emitting stack IL, and the second electrode CAT in the third sub-pixel SP3 are stacked in sequence to emit light.

[0155] The pixel defining layer PDL may include a first pixel defining layer PDL1 to a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be disposed on an edge of the first electrode AND of each of the light emitting elements LE. The second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1. The third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. Each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be an inorganic layer based on silicon oxide (SiO x )), but embodiments of the present disclosure are not limited thereto. In the third direction DR3, the thicknesses of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each be about

[0156] When the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed as a single pixel defining layer, the height of the single pixel defining layer may increase, and the first encapsulation inorganic layer TFE1 may be damaged due to step coverage. Step coverage may refer to the ratio of the degree to which a thin film is applied on an inclined portion to the degree to which the thin film is applied on a flat portion. The lower the step coverage, the higher the probability that the thin film breaks on the inclined portion.

[0157] Therefore, in order to prevent the first encapsulation inorganic layer TFE1 from breaking due to step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have a cross-sectional structure with steps. For example, the width of the first pixel defining layer PDL1 may be greater than the widths of the second pixel defining layer PDL2 and the third pixel defining layer PDL3, and the width of the second pixel defining layer PDL2 may be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 may refer to the horizontal length of the first pixel defining layer PDL1 defined by the first direction DR1 and the second direction DR2.

[0158] Each of the trenches TRC may pass through the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. Each of the trenches TRC may also pass through the eleventh insulating layer INS11. A part of the tenth insulating layer INS10 may have a concave shape in each of the trenches TRC.

[0159] At least one trench TRC may be provided between adjacent sub-pixels SP1 to SP3. Although two trenches TRC are provided between adjacent sub-pixels SP1 to SP3 in Figure 7 , embodiments of the present disclosure are not limited thereto.

[0160] The light-emitting stack IL may include a plurality of intermediate layers. Figure 7 It is shown that the light-emitting stack IL has a three-column structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3. However, embodiments of the present disclosure are not limited thereto. In another embodiment, the light-emitting stack IL may have a two-column structure including two intermediate layers.

[0161] In the three-column structure, the light-emitting stack IL may have a column structure including a plurality of stacked layers IL1 to IL3 that emit different lights. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a third color, and a third stacked layer IL3 that emits light of a second color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked in sequence.

[0162] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are stacked in sequence. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a third color, and a second electron transport layer are stacked in sequence. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a second color, and a third electron transport layer are stacked in sequence.

[0163] A first charge generation layer may be disposed between the first stacked layer IL1 and the second stacked layer IL2 to provide charge to the second stacked layer IL2 and electrons to the first stacked layer IL1. The first charge generation layer may include an N-type charge generation layer that provides electrons to the first stacked layer IL1 and a P-type charge generation layer that provides holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0164] A second charge generation layer may be disposed between the second stacked layer IL2 and the third stacked layer IL3 to provide charge to the third stacked layer IL3 and electrons to the second stacked layer IL2. The second charge generation layer may include an N-type charge generation layer that provides electrons to the second stacked layer IL2 and a P-type charge generation layer that provides holes to the third stacked layer IL3.

[0165] The first stacked layer IL1 may be disposed on the first electrode AND and the pixel defining layer PDL, and may be disposed on the bottom surface of each of the trenches TRC. Due to the trenches TRC, the first stacked layer IL1 may be disconnected between adjacent sub-pixels SP1 to SP3. The second stacked layer IL2 may be disposed on the first stacked layer IL1. Due to the trenches TRC, the second stacked layer IL2 may be disconnected between adjacent sub-pixels SP1 to SP3. A void or empty space ESS may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 may be disposed on the second stacked layer IL2. The third stacked layer IL3 may not be disconnected due to the trenches TRC, and may cover the second stacked layer IL2 in each of the trenches TRC. For example, in a three-column structure, each of the trenches TRC may be a structure for disconnecting the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1 to SP3, the first charge generation layer and the second charge generation layer. In a two-column structure, each of the trenches TRC may be a structure for disconnecting the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer and disconnecting the lower intermediate layer.

[0166] In order to stably disconnect the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1 to SP3, in the third direction DR3, the height of each of the trenches TRC may be greater than the height of the pixel defining layer PDL. The height of each of the trenches TRC may refer to the length of each of the trenches TRC in the third direction DR3. The height of the pixel defining layer PDL may refer to the length of the pixel defining layer PDL in the third direction DR3. In order to disconnect the first stacked layer IL1 to the third stacked layer IL3 of the display element layer EML between adjacent sub-pixels SP1 to SP3, there may be another structure to replace the trenches TRC. For example, instead of the trenches TRC, reverse tapered barrier ribs may be disposed on the pixel defining layer PDL.

[0167] The number of stacked layers IL1 to IL3 emitting different lights is not limited to Figure 7 the embodiment shown in. For example, the light-emitting stacked layer IL may include two intermediate layers. One of the two intermediate layers may be substantially the same as the first stacked layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. A charge generation layer may be disposed between the two intermediate layers to supply electrons to one of the two intermediate layers and supply charges to the other of the two intermediate layers.

[0168] Figure 7It shows that the first stacked layer IL1 to the third stacked layer IL3 are provided in all of the first emission region EA1, the second emission region EA2, and the third emission region EA3. However, embodiments of the present disclosure are not limited thereto. For example, the first stacked layer IL1 may be provided in the first emission region EA1 and may not be provided in the second emission region EA2 and the third emission region EA3. The second stacked layer IL2 may be provided in the second emission region EA2 and may not be provided in the first emission region EA1 and the third emission region EA3. The third stacked layer IL3 may be provided in the third emission region EA3 and may not be provided in the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1 to the third color filter CF3 of the optical layer OPL may be omitted.

[0169] The second electrode CAT may be provided on the third stacked layer IL3. The second electrode CAT may be provided on the third stacked layer IL3 in each of the trenches TRC. The second electrode CAT may be made of a transparent conductive material (TCO) (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) that can transmit light or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is made of a semi-transmissive conductive material, the light output efficiency of each of the first sub-pixel SP1 to the third sub-pixel SP3 may be increased by a microcavity.

[0170] The encapsulation layer TFE may be provided on the display element layer EML. The encapsulation layer TFE may include one or more encapsulation inorganic layers TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0171] The first encapsulation inorganic layer TFE1 may be provided on the second electrode CAT. The first encapsulation inorganic layer TFE1 may be multi-layered, in which one or more inorganic layers selected from a silicon nitride (SiN x ) layer, a silicon oxynitride (SiON) layer, and a silicon oxide (SiO x ) layer are alternately stacked with each other. The first encapsulation inorganic layer TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0172] The second encapsulation inorganic layer TFE2 may be provided on the first encapsulation inorganic layer TFE1. The second encapsulation inorganic layer TFE2 may be titanium oxide (TiO x ) or aluminum oxide (AlO x) layer, but the embodiments of the present disclosure are not limited thereto. The second encapsulation inorganic layer TFE2 can be formed by an atomic layer deposition (ALD) process. In the third direction DR3, the thickness of the second encapsulation inorganic layer TFE2 can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0173] The organic layer APL can be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL can include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0174] The optical layer OPL can include a plurality of color filters CF1 to CF3, a plurality of lenses LNS, and a filling layer FIL. The color filters CF1 to CF3 can include a first color filter CF1 to a third color filter CF3. The first color filter CF1 to the third color filter CF3 can be disposed on the organic layer APL.

[0175] The first color filter CF1 can overlap with the first emission region EA1 of the first sub-pixel SP1 in the third direction DR3. The first color filter CF1 can transmit light of a first color, for example, light in the blue wavelength band. The blue wavelength band can be in the range of about 370 nm to about 460 nm. Therefore, the first color filter CF1 can transmit light of the first color in the light emitted from the first emission region EA1.

[0176] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2 in the third direction DR3. The second color filter CF2 can transmit light of a second color, for example, light in the green wavelength band. The green wavelength band can be in the range of about 480 nm to about 560 nm. Therefore, the second color filter CF2 can transmit light of the second color in the light emitted from the second emission region EA2.

[0177] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3 in the third direction DR3. The third color filter CF3 can transmit light of a third color, for example, light in the red wavelength band. The red wavelength band can be in the range of about 600 nm to about 750 nm. Therefore, the third color filter CF3 can transmit light of the third color in the light emitted from the third emission region EA3.

[0178] The lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the lenses LNS can be a structure for increasing the proportion of light guided to the front of the display device 10. Each of the lenses LNS can have a cross-sectional shape that bulges upward.

[0179] The filling layer FIL may be disposed on the lens LNS. The filling layer FIL may have a refractive index such that light can travel in a third direction DR3 at the interface between the lens LNS and the filling layer FIL. The filling layer FIL may be a planarization layer. The filling layer FIL may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0180] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. In the case where the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL, and the filling layer FIL may be used to bond the cover layer CVL. In the case where the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. In the case where the cover layer CVL is a polymer resin, the cover layer CVL may be directly applied on the filling layer FIL.

[0181] The polarizer POL may be disposed on the surface of the cover layer CVL. The polarizer POL may be a structure for preventing a reduction in visibility due to reflection of external light. The polarizer POL may include a linear polarizer and a phase retardation film. For example, the phase retardation film may be a quarter-wave plate (λ / 4 plate), but embodiments of the present disclosure are not limited thereto. If the reduction in visibility due to reflection of external light is sufficiently improved by the first color filter CF1 to the third color filter CF3, the polarizer POL may be omitted.

[0182] Figure 8 is a perspective view of the head-mounted display device 1000 according to an embodiment. Figure 9 is according to an embodiment of Figure 8 exploded perspective view of the head-mounted display device 1000.

[0183] Refer to Figure 8 and Figure 9 According to an embodiment, the head-mounted display device 1000 may include a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0184] The first display device 10_1 may provide an image to the user's left eye, and the second display device 10_2 may provide an image to the user's right eye. Each of the first display device 10_1 and the second display device 10_2 may be substantially the same as the display device 10 described with reference to Figure 1 and Figure 2 Thus, the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0185] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0186] The intermediate frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600, and may be disposed between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 may support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0187] The control circuit board 1600 may be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through connectors. The control circuit board 1600 may convert an image source received from the outside into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connectors.

[0188] The control circuit board 1600 may transmit the digital video data DATA corresponding to the left image optimized for the user's left eye to the first display device 10_1, and transmit the digital video data DATA corresponding to the right image optimized for the user's right eye to the second display device 10_2. In another embodiment, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0189] The display device housing 1100 may accommodate the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 may cover the opening surface of the display device housing 1100. The housing cover 1200 may include the first eyepiece 1210 and the second eyepiece 1220, on which the user's left eye is located on the first eyepiece 1210 and the user's right eye is located on the second eyepiece 1220. Although Figure 8 and Figure 9 the first eyepiece 1210 and the second eyepiece 1220 are shown as being separately disposed, the embodiments of the present disclosure are not limited thereto. In another embodiment, the first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0190] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0191] The head-mounted band 1300 can fix the display device housing 1100 to the user's head such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 can be respectively held over the user's left eye and right eye. In the case where the display device housing 1100 is implemented to be lightweight and small, the head-mounted display device 1000 can include an eyeglass frame as shown in Figure 10 instead of the head-mounted band 1300.

[0192] The head-mounted display device 1000 can further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0193] Figure 10 is a perspective view of a head-mounted display device 1000_1 according to an embodiment.

[0194] Refer to Figure 10 , a head-mounted display device 1000_1 according to an embodiment can be a display device in the form of glasses, in which the display device housing 1200_1 is implemented to be lightweight and small. A head-mounted display device 1000_1 according to an embodiment can include a display device 10_3, a left lens 1010, a right lens 1020, a support frame 1030, eyeglass frame legs 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0195] The display device housing 1200_1 can accommodate the display device 10_3, the optical member 1060, and the optical path conversion member 1070. The image displayed on the display device 10_3 can be magnified by the optical member 1060, its optical path can be converted by the optical path conversion member 1070, and can be provided to the user's right eye through the right lens 1020. Accordingly, the user can view an augmented reality image, in which the virtual image displayed on the display device 10_3 and the real image viewed through the right lens 1020 are combined into the augmented reality image.

[0196] Although Figure 10 the display device housing 1200_1 is shown as being disposed at the right end of the support frame 1030, embodiments of the present disclosure are not limited thereto. In another embodiment, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and an image of the display device 10_3 may be provided to the user's left eye. In another embodiment, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and the user may view an image displayed on the display device 10_3 through both the left and right eyes.

[0197] Figure 11 is a perspective view of a mask MK according to an embodiment. Figure 12 is a schematic plan view of a mask MK according to an embodiment. Figure 11 is a perspective view showing a state in which a unit mask UM is separated from a plurality of unit masks. According to Figure 11 and Figure 12 the mask MK according to the embodiment shown in may be used in a process of depositing at least a part of the light-emitting stack IL described in Figure 7 For example, the light-emitting stack IL may be configured to emit light of different colors in the sub-pixels SP1 to SP3.

[0198] Reference Figure 11 and Figure 12 According to an embodiment, the mask MK may be a shadow mask, in which a mask diaphragm MM is disposed on a silicon substrate 1700. The mask MK according to an embodiment may be referred to as a "silicon mask".

[0199] According to an embodiment, the mask MK may include a silicon substrate 1700, and a mask diaphragm MM may be disposed on the silicon substrate 1700. The mask diaphragms MM may be respectively disposed in unit regions 1710 arranged in a matrix form, and each unit region 1710 may be surrounded by a mask rib region 1721. The mask rib region 1721 may support the mask diaphragm MM.

[0200] The mask diaphragm MM may be a part of the unit mask UM disposed in each of the unit regions 1710.

[0201] The silicon substrate 1700 may include a plurality of unit regions 1710 and a mask frame region 1720 other than the unit regions 1710. The mask frame region 1720 may include a mask rib region 1721 surrounding each unit region 1710 and an outer frame region 1722 disposed at the outermost periphery of the silicon substrate 1700. A mask frame MF may be disposed in the mask frame region 1720. The mask frame MF may include mask ribs 7211 surrounding the unit regions 1710 (seeFigure 14 )。

[0202] The mask rib region 1721 may be a region that separates the cell regions 1710. For example, the cell regions 1710 may be arranged in a matrix form, and mask ribs 7211 (see Figure 14 ) provided in the mask rib region 1721 may surround the outer sides of the mask diaphragms MM provided in each of the cell regions 1710.

[0203] A cell opening COP and a cell mask UM that masks at least a portion of the cell opening COP may be provided in each of the cell regions 1710 of the silicon substrate 1700.

[0204] A plurality of cell openings COP may pass through the mask frame MF in the thickness direction of the mask MK (e.g., the third direction DR3). The cell openings COP may be formed by etching the silicon substrate 1700 from the backside portion.

[0205] Each cell mask UM may include a mask diaphragm MM, and the mask diaphragm MM may include a mask opening OP.

[0206] The mask opening OP of each mask diaphragm MM may be referred to as a "hole" or a "mask hole". The mask opening OP may pass through the cell mask UM in the thickness direction of the mask MK (e.g., the third direction DR3).

[0207] The cell mask UM may be used in the deposition process of the display panel 100. In the present disclosure, the term "cell mask UM" may be replaced with a term such as "mask cell UM".

[0208] Figure 13 is a schematic cross-sectional view showing the configuration of a deposition apparatus according to an embodiment.

[0209] Reference Figure 13 , a deposition apparatus according to an embodiment may include a chamber 1810, a deposition source DS provided in the chamber 1810, a mask MK provided in the chamber 1810 between a first substrate 1820 and the deposition source DS, and a mask support 1840 provided between the deposition source DS and the mask MK to support at least a portion of the mask MK.

[0210] According to an embodiment, the mask MK may include a second substrate 1700, the second substrate 1700 including a plurality of cell regions 1710 and a mask frame region 1720 other than the cell regions 1710 and mask diaphragms MM provided in each of the cell regions 1710.

[0211] Figure 13 The first substrate 1820 shown in Figures 1 to 10The display panel 100 described above. Accordingly, the description of the first substrate 1820 will be replaced with the description of the display panel 100 with reference Figures 1 to 10 thereof.

[0212] Figure 13 The second substrate 1700 shown in Figure 11 and Figure 12 may be the silicon substrate 1700 described with reference Figure 11 and Figure 12 thereof. Accordingly, the description of the second substrate 1700 will be replaced with the description of the silicon substrate 1700 with reference

[0213] A mask support 1840 may be disposed under the mask MK to support and fix the mask MK. For example, the mask support 1840 may include an electrostatic chuck. According to an embodiment, the mask support 1840 may include a first support area 1841 that supports the mask rib area 1721 and a second support area 1842 that supports the outer frame area 1722.

[0214] As will be described below with reference to Figures 16 to 23 according to an embodiment, a plurality of support ribs 1841a, 1841b, and 1841c may be disposed in the first support area 1841 of the mask support 1840.

[0215] According to an embodiment, the electrostatic chuck of the mask support 1840 may be integrally formed with the support ribs 1841a, 1841b, and 1841c.

[0216] According to an embodiment, the electrostatic chuck of the mask support 1840 may be separately disposed from the support ribs 1841a, 1841b, and 1841c and may be coupled to some of the support ribs 1841a, 1841b, and 1841c.

[0217] According to an embodiment, the mask support 1840 may include invar, stainless steel, or ceramic.

[0218] Figure 13 The reference numeral 1830 in

[0219] Figure 14 may denote a fixing member for fixing the first substrate 1820 and may include, for example, an electrostatic chuck.

[0220] Reference Figure 14 shows that the silicon substrate 1700 of the mask MK may be divided into a plurality of unit areas 1710 and a mask frame area 1720 other than the unit areas 1710. The mask frame area 1720 may include a mask rib area 1721 on the outside of each of the unit areas 1710.

[0221] The mask diaphragm MM may be disposed on the silicon substrate 1700 and may be exposed in the back direction DR4 through the cell opening COP of the silicon substrate 1700. The back direction DR4 may refer to the direction facing the deposition source DS (see Figure 13 ).

[0222] The cross section of each mask diaphragm MM may have an inverted conical shape, and its width may decrease from the front direction (e.g., the third direction DR3) of the silicon substrate 1700 toward the back direction DR4 of the silicon substrate 1700.

[0223] Each of the mask diaphragms MM may include a mask shadow made of a metal layer or an inorganic layer and holes OP provided between adjacent mask shadows.

[0224] Mask ribs 7211 surrounding the outside of the mask diaphragm MM disposed in each cell region 1710 may be provided in the mask rib region 1721. The mask ribs 7211 and the mask diaphragm MM may be made of the same material. For example, the mask ribs 7211 may be made of a metal layer, but the present disclosure is not limited thereto. For example, although not shown, the mask ribs 7211 may be portions remaining after a part of the silicon substrate 1700 is patterned.

[0225] As shown in the figure, the mask support 1840 may be disposed under the mask MK and support the mask MK. The mask support 1840 may include a first support region 1841 that supports the mask rib region 1721 and a second support region 1842 that supports the outer frame region 1722.

[0226] Figure 15 is a perspective view of the mask support 1840 according to an embodiment. Figure 16 A plurality of support ribs 1841a, 1841b, and 1841c of the mask support 1840 according to the present embodiment are schematically shown.

[0227] Reference Figure 15 and Figure 16 , the mask support 1840 may include a plurality of support ribs 1841a, 1841b, and 1841c, and each of the plurality of support ribs 1841a, 1841b, and 1841c supports the mask rib region 1721 and has a cross-sectional structure with a taper angle. For example, according to the distance from the center 1901 of the mask MK, the support ribs 1841a, 1841b, and 1841c may include a first support rib 1841a, a second support rib 1841b, and a third support rib 1841c. However, the present disclosure is not limited to the embodiment in which the mask support 1840 includes the first support rib 1841a, the second support rib 1841b, and the third support rib 1841c.

[0228] According to an embodiment, the first support rib 1841a may form a first deposition incident angle with the deposition source DS and support a first mask rib region A1 that is spaced apart from the center 1901 of the mask MK by a first distance.

[0229] According to an embodiment, the second support rib 1841b may form a second deposition incident angle greater than the first deposition incident angle with the deposition source DS and support a second mask rib region A2 that is spaced apart from the center 1901 of the mask MK by a second distance. The second distance may be greater than the first distance.

[0230] According to an embodiment, the third support rib 1841c may form a third deposition incident angle greater than the second deposition incident angle with the deposition source DS and support a third mask rib region A3 that is spaced apart from the center 1901 of the mask MK by a third distance. The third distance may be greater than the second distance.

[0231] According to an embodiment, the taper angles K1, K2, or K3 of each of the support ribs 1841a, 1841b, and 1841c (see Figure 17 ) may be less than or equal to the deposition incident angle formed by the deposition source DS and the corresponding one of the support ribs 1841a, 1841b, and 1841c.

[0232] According to an embodiment, the taper angles K1, K2, and K3 of the support ribs 1841a, 1841b, and 1841c (see Figure 17 ) may be different from each other. The shapes of the support ribs 1841a, 1841b, and 1841c may be different from each other. The heights H1, H2, and H3 of the support ribs 1841a, 1841b, and 1841c (see Figure 22 ) may be different from each other. The shapes of the support ribs 1841a, 1841b, and 1841c of the present disclosure will be described in detail with reference to Figures 17 to 23 .

[0233] Figures 17 to 23 is a schematic cross-sectional view showing the structures of the first support rib 1841a, the second support rib 1841b, and the third support rib 1841c according to an embodiment.

[0234] Figure 17 An embodiment is shown in which the taper angles K1, K2, and K3 of the support ribs 1841a, 1841b, and 1841c decrease toward the periphery of the mask support 1840.

[0235] Refer to Figure 17, the cross-sectional structure of the first support rib 1841a may have a first taper angle K1 less than or equal to the first deposition incident angle, the cross-sectional structure of the second support rib 1841b may have a second taper angle K2 less than or equal to the second deposition incident angle, and the cross-sectional structure of the third support rib 1841c may have a third taper angle K3 less than or equal to the third deposition incident angle.

[0236] According to an embodiment, the first taper angle K1 may be greater than or equal to the second taper angle K2, and the second taper angle K2 may be greater than or equal to the third taper angle K3.

[0237] As described above, according to an embodiment, the taper angles K1, K2, and K3 of the support ribs 1841a, 1841b, and 1841c included in the mask support 1840 may decrease toward the periphery of the mask support 1840.

[0238] Figure 18 An embodiment is shown in which the taper angles K1, K2, and K3 of the plurality of support ribs 1841a, 1841b, and 1841c increase toward the periphery of the mask support 1840.

[0239] Figure 18 The embodiment of Figure 17 The embodiment of may be different in that the first taper angle K1 is less than or equal to the second taper angle K2, and the second taper angle K2 is less than or equal to the third taper angle K3.

[0240] As described above, according to an embodiment, the taper angles K1, K2, and K3 of the support ribs 1841a, 1841b, and 1841c included in the mask support 1840 may increase toward the periphery of the mask support 1840.

[0241] Figure 19 An embodiment is shown in which the taper angles K1, K2, and K3 of the plurality of support ribs 1841a, 1841b, and 1841c decrease and increase toward the periphery of the mask support 1840.

[0242] Figure 19 The embodiment of Figure 17 The embodiment of may be different in that the first taper angle K1 is equal to the third taper angle K3, and the second taper angle K2 is less than the first taper angle K1.

[0243] As described above, according to an embodiment, the taper angles K1, K2, and K3 of the support ribs 1841a, 1841b, and 1841c included in the mask support 1840 may decrease and increase toward the periphery of the mask support 1840.

[0244] Figure 20An embodiment is shown in which the taper angles K1, K2, and K3 of the plurality of support ribs 1841a, 1841b, and 1841c increase and decrease towards the periphery of the mask support 1840.

[0245] Figure 20 The embodiment of Figure 17 may differ from the embodiment of

[0246] in that the first taper angle K1 is equal to the third taper angle K3 and less than the second taper angle K2. As described above, according to an embodiment, the taper angles K1, K2, and K3 of the support ribs 1841a, 1841b, and 1841c included in the mask support 1840 may increase and decrease towards the periphery of the mask support 1840.

[0247] Figure 21 An embodiment is shown in which at least one of the plurality of support ribs 1841a, 1841b, and 1841c includes an asymmetric cross-sectional structure.

[0248] Figure 21 The embodiment of Figures 17 to 20 may differ from the embodiment of Figures 17 to 20 in that the cross-section of at least one of the first support rib 1841a to the third support rib 1841c has an asymmetric structure. For example, although the cross-section of each of the first support rib 1841a, the second support rib 1841b, and the third support rib 1841c has a symmetric structure in the

[0249] Figure 22 embodiment, the present disclosure is not limited thereto.

[0250] Referring to Figure 22 , the heights H1, H2, and H3 of the first support rib 1841a, the second support rib 1841b, and the third support rib 1841c may be different from each other. For example, the first support rib 1841a may have a first height H1, the second support rib 1841b may have a second height H2 greater than the first height H1, and the third support rib 1841c may have a third height H3 greater than the second height H2. As described above, according to an embodiment, the heights H1, H2, and H3 of the support ribs 1841a, 1841b, and 1841c included in the mask support 1840 may increase towards the periphery of the mask support 1840.

[0251] As described above, according to an embodiment, the heights H1, H2, and H3 of the support ribs 1841a, 1841b, and 1841c included in the mask support 1840 may increase towards the periphery of the mask support 1840.

[0252] Figure 23An embodiment is shown in which the heights H1, H2, and H3 of a plurality of support ribs 1841a, 1841b, and 1841c decrease toward the periphery of the mask support 1840.

[0253] Figure 23 The embodiment of Figure 22 may differ from the embodiment of

[0254] that the first support rib 1841a has a first height H1, the second support rib 1841b has a second height H2 less than the first height H1, and the third support rib 1841c has a third height H3 less than the second height H2.

[0255] In a deposition apparatus according to an embodiment, a mask support for supporting a mask may include a plurality of support ribs, each of the plurality of support ribs having a cone angle less than or equal to a deposition incident angle, and the cone angles of the support ribs may be designed to be different from each other. Accordingly, shadow defects may be minimized.

[0256] Since the support ribs have a specified cone angle, the thickness of the mask support may be increased, and the mask support may more stably support the mask.

[0257] With the deposition apparatus according to an embodiment, it may be possible to easily manufacture a display panel having a resolution of 3500 pixels per inch (PPI) or higher.

[0258] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and variations. Accordingly, the above embodiments of the present disclosure may be implemented individually or in combination with each other.

[0259] Accordingly, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. Deposition equipment, including: room; A deposition source is disposed in the chamber; a mask disposed in the chamber between the first substrate and the deposition source; as well as a mask support disposed between the deposition source and the mask and supporting at least a portion of the mask, wherein: The mask includes a plurality of unit regions and a mask frame region excluding the plurality of unit regions, The mask frame region includes a mask rib region separating the plurality of unit regions and an outer frame region disposed at an outermost periphery of the mask, The mask support includes a plurality of support ribs, each of the plurality of support ribs supports the mask rib region and has a cross-sectional structure having a tapered angle, and The taper angle of each of the plurality of support ribs is different from each other.

2. The deposition apparatus according to claim 1, wherein: The mask support also includes an electrostatic chuck supporting the outer frame region.

3. The deposition apparatus according to claim 2, wherein: The electrostatic chuck of the mask support is integrally formed with the plurality of support ribs.

4. The deposition apparatus according to claim 2, wherein: The electrostatic chuck of the mask support is disposed separately from the plurality of support ribs and is coupled to some of the plurality of support ribs.

5. The deposition apparatus according to claim 1, wherein: The material of the mask support includes Invar alloy.

6. The deposition apparatus according to claim 1, wherein: The material of the mask support includes stainless steel.

7. The deposition apparatus according to claim 1, wherein: The taper angle of each of the plurality of supporting ribs is less than or equal to a deposition incident angle formed by the deposition source and a corresponding one of the plurality of supporting ribs.

8. The deposition apparatus according to claim 7, wherein: The plurality of support ribs include: a first supporting rib forming a first deposition incident angle with the deposition source and supporting a first mask rib region spaced a first distance from a center of the mask; a second supporting rib that forms a second deposition incident angle with the deposition source that is greater than the first deposition incident angle and supports a second mask rib region that is spaced a second distance from the center of the mask; and A third supporting rib forms a third deposition incident angle with the deposition source that is greater than the second deposition incident angle and supports a third mask rib region spaced a third distance from the center of the mask.

9. The deposition apparatus according to claim 8, wherein: The cross-sectional structure of the first supporting rib has a first cone angle less than or equal to the first deposition incident angle, The cross-sectional structure of the second supporting rib has a second cone angle less than or equal to the second deposition incident angle, and A cross-sectional structure of the third supporting rib has a third cone angle that is less than or equal to the third deposition incident angle.

10. The deposition apparatus according to claim 9, wherein: The first cone angle is greater than or equal to the second cone angle, and The second cone angle is greater than or equal to the third cone angle.

11. The deposition apparatus according to claim 9, wherein: The first cone angle is less than or equal to the second cone angle, and The second cone angle is less than or equal to the third cone angle.

12. The deposition apparatus according to claim 9, wherein: The first cone angle is equal to the third cone angle, and The second taper angle is smaller than the first taper angle.

13. The deposition apparatus according to claim 9, wherein: The first cone angle is equal to the third cone angle and smaller than the second cone angle.

14. The deposition apparatus according to claim 8, wherein: Each of the first to third supporting ribs has a symmetrical structure in a cross-sectional view.

15. The deposition apparatus according to claim 8, wherein: At least one of the first to third supporting ribs has an asymmetric structure in a cross-sectional view.

16. The deposition apparatus according to claim 8, wherein: The heights of the first to third supporting ribs are different from each other.

17. The deposition apparatus according to claim 16, wherein: The first supporting rib has a first height, The second support rib has a second height greater than the first height, and The third supporting rib has a third height greater than the second height.

18. The deposition apparatus according to claim 16, wherein: The first supporting rib has a first height, The second support rib has a second height that is less than the first height, and The third supporting rib has a third height that is smaller than the second height.

19. The deposition apparatus according to claim 1, wherein: The mask further includes a mask membrane including an inorganic layer.

20. The deposition apparatus according to claim 1, wherein: The mask further includes a mask membrane including a metal layer.

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