Circuit for measuring resistance distribution of fuse wire
By designing the circuit of sensitive amplifier and current mirroring unit, the fuse resistance distribution is directly judged from the circuit output, which solves the problems of large fuse resistance measurement error and cumbersome testing in the prior art, and achieves efficient and accurate fuse resistance testing.
Patent Information
- Application Number
- CN202510397404.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-06-20
AI Technical Summary
The prior art has problems such as large errors, cumbersome testing procedures and long-term time-consuming when measuring fuse resistance values. Especially in large resistance fuse testing, the current is small and difficult to accurately measure, and may cause incorrect burning of the unfired unit.
A circuit including a sensitive amplifier, a sensitive amplifier reference unit and a current mirror unit is designed. The current is controlled by multiple resistor selection modules and MOS tubes to determine the fuse resistance value distribution, avoiding the application of large current and programming voltage to the unfilled unit, and directly judging the fuse resistance value from the circuit output.
It improves the efficiency and accuracy of fuse resistance value testing, simplifies the test process, is suitable for actual mass production, is not affected by machine test accuracy and voltage, and avoids the risk of incorrect burning.
Smart Images
Figure CN120177873A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of memories, and particularly to a circuit for measuring the resistance value distribution of fuses. Background Art
[0002] An eFuse (electronic fuse) is a one-time programmable memory. A commonly used eFuse storage cell is a metal fuse, which is based on the principle of electromigration or Joule heat to fuse the fuse to achieve programming. In the programming mode, a large current generated by a programming voltage fuses the fuse, causing the resistance value of the fuse to change from a small resistance to a large resistance after programming. In the read mode, a current mirror or a sense amplifier (SA) is used to identify the resistance value.
[0003] Reference Figure 1 As shown, the input signals of the memory include a programming enable signal PGNB (effective at low level), a sense amplifier enable control signal LD (effective at high level), and a first boundary read signal MR1; the programming enable signal PGNB and the sense amplifier enable control signal LD always remain in phase. If both are at low level L, the control circuit CTRL outputs a programming signal prog, and the memory enters the programming mode; if the programming enable signal PGNB and the sense amplifier enable control signal LD are both at high level H, the memory enters the read mode. The first boundary read signal MR1 generates an internal normal read signal NR_in and an internal boundary read signal MR_in through a conversion circuit. The internal normal read signal NR_in controls the memory to enter the NR (normal read) mode, and the internal boundary read signal MR_in controls the memory to enter the MR (margin read) mode.
[0004] The resistance value of the fuse after programming is usually very large. However, during the process of programming the fuse, uncontrollable factors may cause the fuse not to be fused or to re-melt, resulting in the logical value output not meeting the expectation. Even for all successfully programmed fuses, there are still differences in resistance, that is, differences in the read window. Therefore, after programming, it is necessary to know the resistance value distribution of the fuses to determine the quality of fuse programming.
[0005] When calculating the resistance value of the fuse after programming, currently, the eFuse is usually placed in the programming mode, and a test bench is used to apply different programming voltages to each fuse by selecting the word address and bit address, measure the programming current flowing through the fuse, and then estimate an approximate value through calculation and fitting. However, there are three problems with such an operation: First, when the programmed resistance value is large, the current flowing through the storage unit (bitcell) or the fuse is small, and it is impossible to exclude the error caused by the programming voltage flowing through other control circuit modules; Second, the measured programming current is often very small or even lower than the accuracy lower limit of the test bench, and it is impossible to exclude the error caused by the fluctuation of the test bench. Increasing the programming voltage may cause misprogramming of the unprogrammed bitcell, which is not conducive to testing in actual mass production projects; Third, the test process is cumbersome. Only one fuse can be tested in each test cycle, and each fuse needs to scan multiple programming voltages and programming currents. It takes a long time to traverse and scan all the fuses in the array, and the measured voltage-current curve needs to be fitted and calculated to obtain the resistance value range. Summary of the Invention
[0006] The present invention provides a circuit for measuring the resistance value distribution of a fuse to solve the technical problem that the resistance value of the fuse needs to be determined according to the fitted programming voltage and programming current.
[0007] To solve the above technical problems, the present invention provides a circuit for measuring the resistance value distribution of a fuse, including a sense amplifier, a reference unit of the sense amplifier, and a current mirror unit;
[0008] The reference unit of the sense amplifier includes a plurality of resistor selection modules, and the resistor values configured by the plurality of resistor selection modules are different from each other;
[0009] One end of the current mirror unit is connected to the reference unit of the sense amplifier, and the other end is connected to the sense amplifier. The current mirror unit is used to mirror the currents corresponding to the plurality of resistor selection modules into the sense amplifier respectively;
[0010] The sense amplifier includes MOS transistors. The sense amplifier is connected to the bit line of the fuse to be measured and uses the currents corresponding to the plurality of resistor selection modules to control the conduction or cutoff of the MOS transistors respectively.
[0011] Preferably, the reference unit of the sense amplifier includes a plurality of select NMOS transistors and a plurality of resistors connected in series; the gate of each select NMOS transistor is connected to a preset selection signal, and the drain is connected to one end of the current mirror unit; the number of resistors connected to the sources of the plurality of select NMOS transistors decreases in sequence.
[0012] Preferably, the multiple selected NMOS transistors include a first NMOS transistor to a sixth NMOS transistor, and the source electrodes of the first NMOS transistor to the sixth NMOS transistor are respectively connected to one end of a first resistor to one end of a sixth resistor.
[0013] Preferably, the resistance value range configured by the multiple resistor selection modules is 3 KΩ to 100 KΩ.
[0014] Preferably, the circuit further includes a decoding and control module, and the decoding and control module includes a first NAND gate, a first NOT gate, a second NAND gate, and a second NOT gate connected in series, a third NOT gate, a third NAND gate, and a fourth NOT gate connected in series, a fifth NOT gate and a first NOR gate connected in series, and a sixth NOT gate and a second NOR gate connected in series; the output end of the fourth NOT gate is respectively connected to the input ends of the second NAND gate, the first NOR gate, and the second NOR gate; the input end of the first NAND gate is used for inputting the bit address of the memory, and the input end of the third NOT gate is used for inputting a sense amplifier enable control signal; the output end of the second NOT gate is used for outputting the selection signal; the input end of the fifth NOT gate is used for inputting an internal boundary read signal; the input end of the sixth NOT gate is used for inputting an internal normal read signal; the input end of the first NOR gate is used for outputting a second boundary read signal, and the input end of the second NOR gate is used for outputting a second normal read signal.
[0015] Preferably, the output end of the first NOR gate is connected to two NOT gates connected in series.
[0016] Preferably, the output end of the second NOR gate is connected to two NOT gates connected in series.
[0017] Preferably, the sense amplifier includes a first PMOS transistor, a seventh NMOS transistor, a second PMOS transistor, and an eighth NMOS transistor; the source electrode of the first PMOS transistor is connected to a preset voltage source, and the drain electrode of the first PMOS transistor is connected to the drain electrode of the seventh NMOS transistor; the gate electrode of the seventh NMOS transistor is connected to a preset enable signal, and the source electrode of the seventh NMOS transistor is used for connecting the bit line of the fuse; the gate electrode of the second PMOS transistor is connected to the source electrode of the seventh NMOS transistor, the source electrode of the second PMOS transistor is connected to a preset voltage source, and the drain electrode of the second PMOS transistor, the drain electrode of the eighth NMOS transistor, and the input end of an output NOT gate are connected; the source electrode of the eighth NMOS transistor is connected to the ground terminal.
[0018] Preferably, the current mirror unit includes a third PMOS transistor, a fourth PMOS transistor, and a ninth NMOS transistor; the source of the third PMOS transistor is connected to a preset voltage source, the drain of the third PMOS transistor is connected to the reference unit of the sense amplifier, and the gates of the third PMOS transistor, the fourth PMOS transistor, and the first PMOS transistor are connected; the source of the fourth PMOS transistor is connected to a preset voltage source, the drain of the fourth PMOS transistor, the drain and gate of the ninth NMOS transistor, and the gate of the eighth NMOS transistor are connected, and the source of the ninth NMOS transistor is connected to the ground terminal.
[0019] Preferably, the memory under test includes bit lines of multiple fuses, and the sense amplifier is respectively connected to the bit lines of the multiple fuses.
[0020] The present invention provides a circuit for measuring the resistance value distribution of fuses, including a sense amplifier, a reference unit of the sense amplifier, and a current mirror unit. The sense amplifier uses current control MOS transistors corresponding to multiple resistor selection modules to conduct or turn off respectively. The conduction or turn-off of the MOS transistor can cause the output of the circuit to flip. According to the change of the circuit output, the resistance value distribution of the fuses after programming can be judged. For example, when the current corresponding to the T-th gear in multiple resistor selection modules can make the output of the circuit high level, and the current corresponding to T + 1 in multiple resistor selection modules can make the output of the circuit low level, this indicates that the resistance value of the fuses after programming is between the resistance value corresponding to the T-th gear and the resistance value corresponding to the T + 1-th gear. Using the circuit provided by the present invention, the resistance value distribution of the fuses can be judged according to the output result of the circuit, without the need to obtain and fit the programming voltage and programming current of the storage unit, improving the test efficiency; the fuse resistance test mode is similar to the read mode, without the need to apply a voltage to the storage unit with a programming voltage, not affected by the test range and accuracy of the machine, and will not apply a large current to the unwritten storage unit, and can be used for the test items of actual mass production. Description of the Drawings
[0021] Figure 1 is a signal control schematic diagram of the programming mode and the read mode in the prior art.
[0022] Figure 2 is a circuit schematic diagram of a decoding and control module provided by an embodiment of the present invention.
[0023] Figure 3 is a circuit schematic diagram of a circuit for measuring the resistance value distribution of fuses provided by an embodiment of the present invention.
[0024] Figure 4 is Figure 3 a corresponding simulation result schematic diagram.
[0025] Figure 5It is a schematic circuit diagram for measuring the resistance value distribution of fuses provided by an embodiment of the present invention.
[0026] [Explanation of the reference numerals is as follows]:
[0027] Sense amplifier - SA, reference unit of the sense amplifier - SA_REF;
[0028] First NMOS transistor - M1, second NMOS transistor - M2, third NMOS transistor - M3, fourth NMOS transistor - M4, fifth NMOS transistor - M5, sixth NMOS transistor - M6, seventh NMOS transistor - M7, eighth NMOS transistor - M8, ninth NMOS transistor - M9;
[0029] First PMOS transistor - P1, second PMOS transistor - P2, third PMOS transistor - P3, fourth PMOS transistor - P4;
[0030] First NAND gate - N1, first NOT gate - T1, second NAND gate - N2, second NOT gate - T2, third NOT gate - T3, third NAND gate - N3, fourth NOT gate - T4, fifth NOT gate - T5, first NOR gate - O1, sixth NOT gate - T6, second NOR gate - O2. Detailed implementation manners
[0031] To make the objectives, advantages and features of the present invention clearer, the following further describes in detail a circuit for measuring the resistance value distribution of fuses proposed by the present invention with reference to the accompanying drawings. It should be noted that the accompanying drawings are in very simplified forms and use non-precise scales, only for facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.
[0032] In the description of the present invention, the limiting terms such as "first", "second", etc. are added for convenience of description and reference, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features.
[0033] Refer to Figure 3 As shown, this embodiment provides a circuit for measuring the resistance value distribution of fuses, including a sense amplifier SA, a reference unit SA_REF of the sense amplifier SA, and a current mirror unit ( Figure 3the part between the two dashed boxes); the reference unit SA_REF of the sense amplifier SA includes a plurality of resistor selection modules, and the configured resistance values of the plurality of resistor selection modules are different; one end of the current mirror unit is connected to the reference unit SA_REF of the sense amplifier SA, and the other end is connected to the sense amplifier SA. The current mirror unit is configured to mirror the currents corresponding to the plurality of resistor selection modules into the sense amplifier SA respectively; the sense amplifier SA includes MOS transistors, and the sense amplifier SA is connected to the bit line of the fuse to be measured and controls the MOS transistors to turn on or off by using the currents corresponding to the plurality of resistor selection modules respectively.
[0034] This embodiment provides a circuit for measuring the resistance value distribution of fuses, including a sense amplifier SA, a reference unit SA_REF of the sense amplifier SA, and a current mirror unit. The sense amplifier SA controls the MOS transistors to turn on or off by using the currents corresponding to the plurality of resistor selection modules respectively. The on or off state of the MOS transistors can cause the output of the circuit to flip. According to the change of the circuit output, the resistance value distribution of the fuse after programming can be judged. For example, when the current corresponding to the T-th gear among the plurality of resistor selection modules can make the output of the circuit be high level, and the current corresponding to T + 1 among the plurality of resistor selection modules can make the output of the circuit be low level, this indicates that the resistance value of the fuse after programming is between the resistance value corresponding to the T-th gear and the resistance value corresponding to the T + 1-th gear. Using the circuit provided by the present invention, the resistance value distribution of the fuse can be judged according to the output result of the circuit, without obtaining and fitting the programming voltage and programming current of the memory cell, improving the test efficiency; the fuse resistance test mode is similar to the read mode, without applying a voltage to the memory cell by a programming voltage, not affected by the test range and accuracy of the machine, and will not apply a large current to the unprogrammed memory cell, and can be used for the test items of actual mass production.
[0035] Preferably, referring to Figure 3 as shown, the reference unit SA_REF of the sense amplifier SA includes a plurality of select NMOS (N-Metal-Oxide-Semiconductor) transistors and a plurality of resistors connected in series; the gate of each select NMOS transistor is connected to a preset selection signal, and the drain is connected to one end of the current mirror unit; the number of resistors connected to the sources of the plurality of select NMOS transistors decreases in sequence. The NMOS can be used as a selection switch to control resistors of different gears as the reference resistors of the reference unit SA_REF of the sense amplifier SA. The selection signal of the NMOS transistor can be generated by the high-order address of the memory, for example, using TR<0> to TR<3> as the selection signal of the NMOS transistor.
[0036] Preferably, referring to Figure 3As shown, the multiple select NMOS transistors include a first NMOS transistor M1 to a sixth NMOS transistor M6. The source electrodes of the first NMOS transistor M1 to the sixth NMOS transistor M6 are respectively connected to one end of a first resistor R1 to one end of a sixth resistor R6. Six series-connected resistors can be set to adjust the resistance values of each gear in the multiple resistor selection modules. In other embodiments, the number of resistors included in the reference unit SA_REF of the sense amplifier SA can be adjusted according to the size of the fuse resistance value. The resistors included in the reference unit SA_REF of the sense amplifier SA can also be connected in a parallel or hybrid connection manner.
[0037] Preferably, refer to Figure 3 As shown, the resistance value ranges configured by the multiple resistor selection modules are from 3 KΩ to 100 KΩ. The resistance values of the first resistor to the sixth resistor can be 25.18 KΩ, 25.18 KΩ, 10.71 KΩ, 6.43 KΩ, 2.96 KΩ, and 0.98 KΩ in sequence, so that the resistance values connected to the first NMOS transistor M1 to the sixth NMOS transistor M6 are 100 KΩ, 50 KΩ, 25 KΩ, 15 KΩ, 5 KΩ, and 3 KΩ in sequence. When specifically using a circuit for measuring the fuse resistance value distribution provided by this solution, the resistance value ranges configured by the multiple resistor selection modules can be flexibly set according to actual requirements.
[0038] Preferably, refer to Figure 2 As shown, the circuit further includes a decoding and control module. The decoding and control module includes a series-connected first NAND gate N1, first NOT gate T1, second NAND gate N2, and second NOT gate T2, a series-connected third NOT gate T3, third NAND gate N3, and fourth NOT gate T4, a series-connected fifth NOT gate T5 and first NOR gate O1, and a series-connected sixth NOT gate T6 and second NOR gate O2; the output terminal of the fourth NOT gate T4 is respectively connected to the input terminals of the second NAND gate N2, the first NOR gate O1, and the second NOR gate O2; the input terminal of the first NAND gate N1 is used to input the bit address A of the memory <bl0> 、A <bl1> …A <bln>, the input terminal of the third NOT gate T3 is used to input the sense amplifier SA enable control signal LD; the output terminal of the second NOT gate T2 is used to output the selection signal TR<2 n -1>; the input terminal of the fifth NOT gate T5 is used to input the internal boundary read signal MR_in; the input terminal of the sixth NOT gate T6 is used to input the internal normal read signal NR_in; the input terminal of the first NOR gate O1 is used to output the second boundary read signal MR2, and the input terminal of the second NOR gate O2 is used to output the second normal read signal NR2. In this embodiment, the original signals of the memory are used to implement the function of testing the resistance, and no additional input signals need to be added. Specifically, the programming enable signal PGNB and the sense amplifier SA enable control signal LD are logically combined to generate the resistance test signal TR, and the resistance test signal TR is used to enable the resistance test mode; when the programming enable signal PGNB and the sense amplifier SA enable control signal LD are in phase, the resistance test signal TR is at a low level L, and the memory enters the write or read mode. In the read mode, the resistance test signal TR does not affect the functions of the second normal read signal NR2 and the second boundary read signal MR2. The second boundary read signal MR2 controls the reference unit SA_REF of the sense amplifier SA to perform boundary reading, and the second normal read signal NR2 controls the reference unit SA_REF of the sense amplifier SA to perform normal reading; when the programming enable signal PGNB is at a high level H and the sense amplifier SA enable control signal LD is at a low level L, the resistance test signal TR is at a high level H, and the memory enables the resistance measurement mode. At this time, regardless of whether the externally input first boundary read signal MR is set high or low, the second boundary read signal MR2 and the second normal read signal NR2 are both at a low level L. The selection signal TR<2 n -1> controls the reference unit SA_REF of the sense amplifier SA to perform resistance testing. In other embodiments, other preset external signals can be input to the input terminals of the first NAND gate N1 to generate the selection signals of the first NMOS transistor M1 to the sixth NMOS transistor M6.
[0039] Preferably, referring to Figure 2 as shown, the output terminal of the first NOR gate O1 is connected to two cascaded NOT gates, which can improve the driving ability of the decoding and control module.
[0040] Preferably, referring to Figure 2 as shown, the output terminal of the second NOR gate O2 is connected to two cascaded NOT gates, which can improve the driving ability of the decoding and control module.
[0041] Preferably, referring to Figure 3 As shown, the sense amplifier SA includes a first PMOS (P-Metal-Oxide-Semiconductor) transistor P1, a seventh NMOS transistor M7, a second PMOS transistor P2, and an eighth NMOS transistor M8; the source of the first PMOS transistor P1 is connected to a preset voltage source, and the drain of the first PMOS transistor P1 is connected to the drain of the seventh NMOS transistor M7; the gate of the seventh NMOS transistor M7 is connected to a preset enable signal EN, and the source of the seventh NMOS transistor M7 is used to connect to the bit line of the fuse; the gate of the second PMOS transistor P2 is connected to the source of the seventh NMOS transistor M7, the source of the second PMOS transistor P2 is connected to a preset voltage source, and the drain of the second PMOS transistor P2, the drain of the eighth NMOS transistor M8, and the input terminal of the output NOT gate are connected; the source of the eighth NMOS transistor M8 is connected to the ground terminal. When the conduction state of the second PMOS transistor P2 changes, the output signal of the output NOT gate will flip. According to the output signal Qout of the output NOT gate, the resistance value distribution of the fuse can be deduced. The output signal Qout of the output NOT gate is also the output signal of the circuit for measuring the resistance value distribution of the fuse. As shown in Table 1 and Figure 4 as shown Figure 4 The above 4 signals in are the signals input by the memory input pins (pins). CLK is the clock signal. If a certain fuse is only valid when the second boundary read signal MR2 is valid (at this time, the sixth NMOS transistor M6 is turned on), the output signal Qout is high level H; when other selection signals are valid, the output signal Qout is low level L, indicating that the resistance value of the fuse is between the resistance levels corresponding to the fifth NMOS transistor and the sixth NMOS transistor M6, that is, between 3KΩ and 5KΩ. If the output signal Qout of a certain fuse is high level H in each gear, it means that the resistance value of the fuse is greater than 100KΩ. If the output signal Qout of a certain fuse is low level L in each gear, it means that the resistance value of the fuse is less than 3KΩ.
[0042] Table 1: Test result distribution table of different fuses
[0043]
[0044] Preferably, refer to Figure 3 As shown, the current mirror unit includes a third PMOS transistor P3, a fourth PMOS transistor P4, and a ninth NMOS transistor M9; the source of the third PMOS transistor P3 is connected to a preset voltage source, the drain of the third PMOS transistor P3 is connected to the reference unit SA_REF of the sense amplifier SA, and the gates of the third PMOS transistor P3, the fourth PMOS transistor P4, and the first PMOS transistor P1 are connected; the source of the fourth PMOS transistor P4 is connected to a preset voltage source, the drain of the fourth PMOS transistor P4, the drain and gate of the ninth NMOS transistor M9, and the gate of the eighth NMOS transistor M8 are connected, and the source of the ninth NMOS transistor M9 is connected to the ground terminal. Through the current mirror unit, the currents I corresponding to multiple resistor selection modules can be mirrored into the sense amplifier SA ref When the current I ref flows through the fuse via the bit line BL of the fuse, the current I ref is converted into a voltage, which is the gate voltage of the second PMOS transistor P2. The change in the magnitude of this voltage will change the output signal Qout of the output NOT gate. If this voltage is small, the second PMOS transistor P2 is turned on, and the output signal Qout of the output NOT gate outputs 0, i.e., the low level L; if this voltage is large, the second PMOS transistor P2 is turned off, the eighth NMOS transistor M8 weakly pulls down, and the output signal Qout of the output NOT gate outputs 1, i.e., the high level H. When the circuit for measuring the resistance value distribution of the fuse is provided with the output signals Qout of multiple output NOT gates, the multiple output NOT gates can output in parallel, so that multiple fuse resistances can be measured simultaneously.
[0045] Preferably, as shown in Figure 5 the measured memory includes bit lines of multiple fuses, and the sense amplifier SA is respectively connected to the bit lines of the multiple fuses, so that the resistance ranges of multiple fuses in the same word line can be measured respectively.
[0046] In summary, the present invention provides a circuit for measuring the resistance value distribution of fuses, which includes a sense amplifier SA, a reference unit SA_REF of the sense amplifier SA, and a current mirror unit. The sense amplifier SA controls the conduction or cutoff of MOS transistors corresponding to multiple resistor selection modules respectively by using currents. The conduction or cutoff of the MOS transistors can cause the output of the circuit to flip. According to the change of the circuit output, the resistance value distribution of the fuses after programming can be judged. For example, when the current corresponding to the T-th gear in multiple resistor selection modules can make the output of the circuit be at a high level, and the current corresponding to T+1 in multiple resistor selection modules can make the output of the circuit be at a low level, this indicates that the resistance value of the fuses after programming is between the resistance value corresponding to the T-th gear and the resistance value corresponding to the T+1-th gear. By using the circuit provided by the present invention, the resistance value distribution of the fuses can be judged according to the output result of the circuit, without the need to obtain and fit the programming voltage and programming current of the storage unit, improving the test efficiency; the fuse resistance test mode is similar to the read mode, without the need to apply a voltage to the storage unit with a programming voltage, not affected by the test range and accuracy of the machine, and will not apply a large current to the unprogrammed storage unit, and can be used for the test items of actual mass production.
[0047] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art according to the above disclosure shall fall within the protection scope of the present invention.< / bln> < / bl1> < / bl0>
Claims
1. A circuit for measuring fuse resistance distribution, characterized in that: It includes a sense amplifier, a reference unit of the sense amplifier and a current mirror unit; The reference unit of the sense amplifier includes a plurality of resistance selection modules, and the resistance values configured by the plurality of resistance selection modules are different; One end of the current mirror unit is connected to the reference unit of the sense amplifier, and the other end is connected to the sense amplifier, and the current mirror unit is used to mirror the currents corresponding to the multiple resistance selection modules to the sense amplifier; The sensitive amplifier comprises a MOS tube, which is connected to the bit line of the fuse to be tested and uses the currents respectively corresponding to a plurality of resistance selection modules to control the MOS tube to be turned on or off.
2. A circuit for measuring fuse resistance distribution as claimed in claim 1, characterized in that: The reference unit of the sensitive amplifier includes multiple selection NMOS tubes and multiple resistors connected in series; the gate of each selection NMOS tube is connected to a preset selection signal, and the drain is connected to one end of the current mirror unit; the number of resistors connected to the source of the multiple selection NMOS tubes decreases in sequence.
3. A circuit for measuring fuse resistance distribution as claimed in claim 2, characterized in that: The plurality of selection NMOS transistors include a first NMOS transistor to a sixth NMOS transistor, and sources of the first NMOS transistor to the sixth NMOS transistor are connected to one end of the first resistor to one end of the sixth resistor respectively.
4. A circuit for measuring fuse resistance distribution as claimed in claim 3, characterized in that: The resistance value range configured by the multiple resistance selection modules is 3KΩ~100KΩ.
5. A circuit for measuring fuse resistance distribution as claimed in claim 2, characterized in that: The circuit also includes a decoding and control module, which includes a first NAND gate, a first NOT gate, a second NAND gate and a second NOT gate connected in series, a third NOT gate, a third NAND gate, a fourth NOT gate connected in series, a fifth NOT gate and a first NOR gate connected in series, and a sixth NOR gate and a second NOR gate connected in series; the output end of the fourth NOT gate is respectively connected to the input end of the second NAND gate, the input end of the first NOR gate, and the input end of the second NOR gate; the input end of the first NAND gate is used to input the bit address of the memory, and the input end of the third NOT gate is used to input the sense amplifier start control signal; the output end of the second NOR gate is used to output the selection signal; the input end of the fifth NOT gate is used to input the internal boundary read signal; the input end of the sixth NOT gate is used to input the internal normal read signal; the input end of the first NOR gate is used to output the second boundary read signal, and the input end of the second NOR gate is used to output the second normal read signal.
6. A circuit for measuring fuse resistance distribution as claimed in claim 5, characterized in that: The output end of the first NOR gate is connected to two serially connected NOT gates.
7. A circuit for measuring fuse resistance distribution as claimed in claim 5, characterized in that: The output end of the second NOR gate is connected to two serially connected NOT gates.
8. A circuit for measuring fuse resistance distribution as claimed in claim 1, characterized in that: The sensitive amplifier includes a first PMOS tube, a seventh NMOS tube, a second PMOS tube and an eighth NMOS tube; the source of the first PMOS tube is connected to a preset voltage source, the drain of the first PMOS tube is connected to the drain of the seventh NMOS tube; the gate of the seventh NMOS tube is connected to a preset enable signal, and the source of the seventh NMOS tube is used to connect the bit line of the fuse; the gate of the second PMOS tube is connected to the source of the seventh NMOS tube, the source of the second PMOS tube is connected to the preset voltage source, the drain of the second PMOS tube, the drain of the eighth NMOS tube and the input end of the output NOT gate are connected; the source of the eighth NMOS tube is connected to the ground end.
9. A circuit for measuring fuse resistance distribution as claimed in claim 8, characterized in that: The current mirror unit includes a third PMOS tube, a fourth PMOS tube and a ninth NMOS tube; the source of the third PMOS tube is connected to a preset voltage source, the drain of the third PMOS tube is connected to the reference unit of the sensitive amplifier, the gate of the third PMOS tube, the gate of the fourth PMOS tube and the gate of the first PMOS tube are connected; the source of the fourth PMOS tube is connected to a preset voltage source, the drain of the fourth PMOS tube, the drain and the gate of the ninth NMOS tube are connected to the gate of the eighth NMOS tube, and the source of the ninth NMOS tube is connected to the ground terminal.
10. A circuit for measuring fuse resistance distribution as claimed in claim 1, characterized in that: The memory under test includes bit lines of a plurality of fuses, and the sense amplifiers are respectively connected to the bit lines of the plurality of fuses.