Chip aging test device and chip aging test method

Abstract

The invention provides a chip aging test device and a chip aging test method, and relates to the technical field of semiconductor test. The device comprises a plurality of test cavities and a plurality of buffer cavities, each test cavity is provided with a first temperature control assembly which is used for independently regulating and controlling the temperature in the corresponding test cavity, so that the test cavity has a constant test temperature, and the test cavity is used for carrying out an aging test on the chipset; the buffer cavities and the test cavities are alternately arranged and form a closed cavity structure, the closed cavity structure is used for accommodating at least one test core assembly, the test core assembly is configured to be capable of rotating in the closed cavity structure, and the test core assembly provides a test signal for each chip in the chip set; each buffer cavity comprises at least two partition pieces, and the partition pieces are used for blocking airflow exchange between the buffer cavity and the adjacent test cavity; the partitions are configured to be opened and closed alternately, so that the chip set can enter and exit from the buffer cavity. The chip aging test efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor testing technologies, and more particularly, to a chip aging test device and a chip aging test method. Background Art

[0002] The semiconductor chip post-packaging aging test process (Burn-in Testing) refers to a test process in which, after the chip is packaged, the chip is subjected to accelerated aging screening by applying electrical stress, temperature stress, or a combination of both that is higher than normal operating conditions. This is one of the key quality assurance links in the semiconductor manufacturing process.

[0003] Currently, aging test furnace equipment is often used to perform aging tests on semiconductor chips. However, most aging test furnace equipment can only test a single chip at a specific temperature, and it is necessary to frequently switch the equipment temperature to obtain the aging performance of the chip at different temperatures. The temperature adjustment of the equipment occupies most of the test time, resulting in low chip test efficiency.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] In view of this, a chip aging test device and a chip aging test method are provided. The device includes a plurality of alternately arranged test cavities and buffer cavities, and in cooperation with a rotatable test core assembly, can perform multi-temperature aging tests on multiple chip groups simultaneously, shortening the temperature adjustment time of the device and greatly improving the chip aging test efficiency.

[0006] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be partially learned through the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a chip aging test device is provided, the device comprising: A plurality of test cavities, each of the test cavities being equipped with a first temperature control component, the first temperature control component independently regulating the temperature in the corresponding test cavity to make the test cavity have a constant test temperature, and the test cavity being used for performing aging tests on a chip group; A plurality of buffer cavities, the buffer cavities and the test cavities being alternately arranged and forming a closed cavity structure, the closed cavity structure being used to accommodate at least one test core assembly, the test core assembly being configured to be able to perform rotational movement within the closed cavity structure, and the test core assembly providing test signals for each chip in the chip group; Each of the buffer cavities includes at least two partition members, and the partition members are used to block the air flow exchange between the buffer cavity and the adjacent test cavity; wherein, the plurality of partition members are configured to open and close alternately so that the chipset can enter and exit the buffer cavity.

[0008] In an exemplary embodiment of the present disclosure, the test temperatures of at least two of the test cavities are different.

[0009] In an exemplary embodiment of the present disclosure, the test temperatures of two adjacent test cavities are different, and each of the buffer cavities is equipped with a second temperature control component to adjust the temperature in the buffer cavity through the second temperature control component so that the temperature in the buffer cavity is between the test temperatures of two adjacent test cavities.

[0010] In an exemplary embodiment of the present disclosure, before the chipset enters the buffer cavity, the second temperature control component is used to control the temperature in the buffer cavity to be adjusted to the current test temperature of the chipset; the temperature of the buffer cavity is between the test temperatures of two adjacent test cavities.

[0011] In an exemplary embodiment of the present disclosure, the number of the test core components and the number of the chipset are both one, and the test core component rotates according to the test cavity where the chipset is located so that the test core component is docked with the chipset.

[0012] In an exemplary embodiment of the present disclosure, the number of the test core components and the number of the chipset are both multiple, the test core components are arranged in one-to-one correspondence with the chipset, and the test core components rotate synchronously with the corresponding chipset.

[0013] In an exemplary embodiment of the present disclosure, the device further includes a first driving mechanism disposed in the closed cavity structure, the test core component is connected to the first driving mechanism, and the first driving mechanism is used to drive the test core component to rotate along the circumferential direction of the closed cavity structure according to the position of the chipset so that the chipset is docked with the test core component.

[0014] In an exemplary embodiment of the present disclosure, the number of the test core components is multiple and the number of the chipset is one, the test core components are arranged in one-to-one correspondence with the test cavities, and when testing one chipset and the chipset moves between different test cavities, the test core components do not rotate relative to the test cavities.

[0015] In an exemplary embodiment of the present disclosure, each of the partition pieces is provided with a wind curtain isolation assembly, and the wind curtain isolation assembly is used to generate a wind curtain when the partition piece is opened to isolate the airflow exchange between the buffer cavity and the test cavity; wherein the projection of the wind curtain on the surface of the partition piece at least partially overlaps with the surface of the partition piece.

[0016] In an exemplary embodiment of the present disclosure, the time for the air curtain isolation assembly to generate the air curtain is greater than or equal to the opening time of the partition member.

[0017] In an exemplary embodiment of the present disclosure, a connector is provided on a surface of each test cavity facing the test core component, each connector is located in the closed cavity structure, one end of the connector is connected to each chip in the chipset, and the other end of the connector is connected to the test core component.

[0018] According to another aspect of the present disclosure, a chip aging test method is provided, the method comprising: In response to the test conditions, controlling the chipset to move into the test chamber; Controlling the chipset to remain in the test chamber for a preset time to obtain an aging state of each chip in the chipset under the test conditions; Wherein, the test conditions include a test temperature, different test temperatures correspond to different test cavities, each test cavity has a constant test temperature, a buffer cavity is arranged between two adjacent test cavities, and the buffer cavity and the test cavity enclose a closed cavity structure; Before controlling the chipset to move to the test cavity, the method includes: controlling the chipset to move to the buffer cavity for pre-processing to reduce the temperature difference between each chip in the chipset and the test temperature of the test cavity.

[0019] In an exemplary embodiment of the present disclosure, controlling the chipset to move into the buffer chamber for preprocessing includes: The temperature in the buffer cavity is adjusted so that the temperature in the buffer cavity is between the test temperatures of two adjacent test cavities.

[0020] The chip aging test device provided by the present disclosure includes a plurality of test cavities and a plurality of buffer cavities that are alternately arranged and form a closed cavity structure. Each test cavity is independently regulated in temperature by a first temperature control component equipped, ensuring that the test temperature in each test cavity is constant and the test temperatures between the test cavities do not affect each other, so that each test cavity can independently perform chip aging tests, and multiple different chip groups can be aged tested simultaneously to improve the test efficiency. A buffer cavity is provided between two adjacent test cavities in this device. The chip group can move between different test cavities to perform aging tests on the same chip group at different test temperatures. When the same chip group moves between different test cavities, the buffer cavity can preprocess the chip group to shorten the temperature conversion time of the chip group and further improve the test efficiency. In addition, since the buffer cavity includes at least two partition members that alternately open and close to block the air flow exchange between the buffer cavity and the test cavity, when the chip group moves between different test cavities, the constancy of the test temperature in each test cavity can be ensured, guaranteeing the reliability of the chip aging test.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings here are incorporated into the specification and form a part of this specification, showing the embodiments in line with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic structural diagram of a chip aging test device in an exemplary embodiment of the present disclosure.

[0024] Figure 2 It is a schematic position diagram of the air curtain isolation component in the chip aging test device in an exemplary embodiment of the present disclosure.

[0025] Figure 3 It is a schematic position relationship diagram between the air curtain and the surface of the partition member in an exemplary embodiment of the present disclosure.

[0026] Figure 4 It is a schematic position relationship diagram between the test core component, the connector and the chip group in an exemplary embodiment of the present disclosure.

[0027] Figure 5 It is a schematic corresponding connection relationship diagram between the test core component, the connector and the chip group in an exemplary embodiment of the present disclosure.

[0028] Figure 6 This is a corresponding relationship diagram between a test core component and a chipset in an exemplary embodiment of the present disclosure.

[0029] Figure 7 This is another corresponding relationship diagram between a test core component and a chipset in an exemplary embodiment of the present disclosure.

[0030] Figure 8 This is another corresponding relationship diagram between a test core component and a chipset in an exemplary embodiment of the present disclosure.

[0031] Figure 9 This is another corresponding relationship diagram between a test core component and a chipset in an exemplary embodiment of the present disclosure.

[0032] Figure 10 This is a flowchart of a chip aging test method in an exemplary embodiment of the present disclosure.

[0033] Among them, the reference numerals are explained as follows: 100, test cavity; 200, buffer cavity; 300, chipset; 301, test core component; 302, connector; 400, closed cavity structure; 500, partition; 501, air curtain isolation component; 502, air curtain; 503, surface of the partition; 601, first driving mechanism; 700, control center. Detailed implementation manners

[0034] Now, the exemplary embodiments will be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0035] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0036] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and refer to the possibility of the existence of additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0037] In the related art, the semiconductor back-end aging test is one of the key quality assurance links in the semiconductor manufacturing process. The aging test enables the semiconductor chip to pass through the early failure stage of the bathtub curve and enter the performance stable period through high and low temperature and high voltage tests.

[0038] Since the aging test items need to be completed at multiple different temperatures, common test temperatures include -10°C, 25°C, 88°C, 125°C, etc. Currently, the commonly used chip aging test device is a high-temperature aging furnace, which mostly has a single furnace cavity structure. It is necessary to frequently switch the temperature in the furnace cavity to complete the entire aging test cycle with different test temperatures. Among them, the temperature rise and fall time in the cavity accounts for a relatively large proportion of the entire test time, affecting the aging test efficiency. In addition, the high-temperature aging furnace can only perform the aging test of a single chip or a single chip group at the same temperature each time, resulting in low test efficiency and high test cost.

[0039] Based on this, the embodiments of the present disclosure provide a chip aging test device, as Figure 1 shown, the device includes: a plurality of test cavities 100 and a plurality of buffer cavities 200.

[0040] Wherein, each test cavity 100 is equipped with a first temperature control component, and the first temperature control component independently controls the temperature in the corresponding test cavity 100 to make the test cavity 100 have a constant test temperature. The test cavity 100 is used for aging test of the chip group 300. Each test cavity 100 provided by the present disclosure has a constant test temperature, and the test temperatures between the test cavities 100 do not affect each other, so that each test cavity 100 can independently perform the chip aging test, and multiple different chip groups 300 can be aged tested simultaneously to improve the test efficiency.

[0041] The buffer cavity 200 and the test cavity 100 are alternately arranged and form a closed cavity structure 400. The closed cavity structure 400 is used to accommodate at least one test core component 301. The test core component 301 is configured to be able to perform rotational movement within the closed cavity structure 400. The test core component 301 provides test signals for the chips within the chipset 300. Through the position cooperation between the test core component 301 and the buffer cavity 200 and the test cavity 100, the chipset 300 can be moved between different test cavities 100 to perform aging tests on the same chipset 300 at different test temperatures. And when the same chipset 300 moves between different test cavities 100, the buffer cavity 200 can preprocess the chipset 300 to shorten the temperature conversion time of the chipset 300 and further improve the test efficiency.

[0042] Each buffer cavity 200 includes at least two partition members 500. The partition members 500 are used to block the air flow exchange between the buffer cavity 200 and the adjacent test cavity 100. Among them, a plurality of partition members 500 are configured to alternately open and close, so that the test chipset 300 can enter and exit the buffer cavity 200. When the chipset 300 moves between different test cavities 100, the partition members 500 provided on the buffer cavity 200 can ensure the constancy of the test temperature in each test cavity 100 and ensure the reliability of the chip aging test.

[0043] Next, each part of the chip aging test device provided by the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings: In the embodiments provided by the present disclosure, as Figure 1 shown, in combination with Figures 5 to 9 , the chip aging test device includes a plurality of test cavities 100. Each test cavity 100 is used to perform aging tests on the chipset 300.

[0044] Among them, the number of test cavities 100 is at least two. For example, the number of test cavities 100 can be two, three, four or more. The number of test cavities 100 can be selected according to different test temperatures and the number of chipsets 300. For example, for 4 groups of chipsets 300 to be aged tested at the same temperature, the test device can be adaptively provided with 4 test cavities 100, and each test cavity 100 corresponds to one group of chipset 300; or for four different test temperatures including -10°C, 25°C, 88°C, and 125°C, the test device can be adaptively provided with 4 test cavities 100, and each test cavity 100 corresponds to one test temperature; of course, the number of test cavities 100 can also be combined with different test temperatures and different numbers of chipsets 300, and no specific examples will be given here.

[0045] Each test chamber 100 is equipped with a first temperature control component, which independently regulates the temperature inside the corresponding test chamber 100 to enable the test chamber 100 to have a constant test temperature. Taking four common test temperatures of -10°C, 25°C, 88°C, and 125°C as an example, the device has four test chambers 100 with test temperatures of -10°C, 25°C, 88°C, and 125°C respectively, and each test chamber 100 maintains its respective test temperature constant. Of course, the test temperature of each test chamber can be a constant temperature value within the range of -20°C to 200°C, and the specific test temperature of each test chamber can be determined according to actual test requirements.

[0046] In some embodiments, the first temperature control component may include a temperature sensor and a refrigeration and heating system disposed inside the test chamber 100. The device can monitor the temperature inside the test chamber 100 in real time through the temperature sensor, and according to the temperature information obtained by the temperature sensor, adjust the test temperature inside the test chamber 100 in real time through the refrigeration and heating system, and keep the test temperature inside the test chamber 100 constant.

[0047] Taking the test temperature inside the test chamber 100 as 25°C as an example, when the chipset 300 enters and exits the test chamber 100, due to the flow of air, the temperature of the test chamber 100 changes. The temperature sensor in the first temperature control component senses the change range of the temperature of the test chamber 100, and controls the refrigeration and heating system to heat or cool the test chamber 100 according to the change range of the temperature of the test chamber 100, so that the test chamber 100 maintains a test temperature of 25°C. The above embodiments are described by taking the test temperature of the test chamber 100 as 25°C as an example. When the test chamber 100 has different test temperatures, the first temperature control component can be adaptively adjusted according to the test temperature inside the test chamber 100 to keep each test chamber 100 having a constant test temperature.

[0048] It should be noted that the test temperature inside the test chamber 100 being constant is not strictly limited. The test temperature can have a deviation of ±1°C, and within this deviation range, the test temperature can be considered constant.

[0049] In some embodiments, when multiple test chambers 100 have the same test temperature and aging tests on multiple groups of chipsets 300 are carried out at the same temperature through the multiple test chambers 100, a first temperature control component can be equipped in each test chamber 100 to ensure precise regulation of the test temperature of each test chamber 100; or multiple test chambers 100 with the same temperature can be equipped with a first temperature control component, and multiple test chambers 100 are simultaneously regulated by one first temperature control component to make the multiple test chambers 100 at the same test temperature, so as to further simplify the structure of the device and improve the compactness of the device.

[0050] Among them, the adjustment time of the first temperature control component for the test temperature can be 5 s to 30 s. For example, it can be 5 s, 10 s, 15 s, 20 s, 25 s or 30 s, etc. In addition, the adjustment time of the first temperature control component for the test temperature needs to be less than or equal to the residence time of the chipset 300 in the buffer cavity 200, so as to ensure that the chipset 300 can perform the aging test at an accurate and constant test temperature, and improve the test reliability. It should be noted that the adjustment time of the first temperature control component for the test temperature includes the response time of the first temperature control component to the test temperature, so as to improve the detection efficiency and adjustment efficiency of the first temperature control component for the test temperature, thereby shortening the entire aging test time and improving the aging test efficiency.

[0051] In some specific embodiments, the refrigeration and heating system in the first temperature control component may include a circulation air duct, and the circulation air duct is arranged on the bottom wall and / or side walls and / or top wall of the test cavity 100. When the test cavity 100 needs to be heated, hot air is input into the test cavity 100 through the circulation air duct to achieve the purpose of heating; when the test cavity 100 needs to be cooled, cold air can be input into the test cavity 100 through the circulation air duct to achieve the purpose of cooling.

[0052] In some specific embodiments, the temperature sensors in the first temperature control component may include a first temperature sensor and a second temperature sensor. Among them, the first temperature sensor can be arranged on the side wall and / or bottom wall of the test cavity 100 and / or suspended in the cavity of the test cavity 100, and is used to obtain the test temperature in the test cavity 100 in real time. At the same time, the first temperature sensor transmits the real-time test temperature obtained in the test cavity 100 to the control center. By comparing the preset constant test temperature of the test cavity 100 with the real-time test temperature, the refrigeration and heating system is used to adjust the temperature in the test cavity 100 to always maintain the preset constant test temperature.

[0053] The second temperature sensor can be arranged in the chipset 300. For example, it can be arranged on a certain chip in the chipset 300, or can be arranged on the connection board for carrying the chips. The actual test temperature of the chipset 300 can be obtained through the second temperature sensor. Since there may be a phenomenon of uneven temperature distribution in the space of the test cavity 100, resulting in a difference between the actual test temperature of the chipset 300 and the preset constant test temperature in the test cavity 100, and further resulting in an aging test error. Therefore, the second temperature sensor can transmit the actual test temperature of the chipset 300 to the control center. By comparing the actual test temperature with the preset constant test temperature, the actual test temperature of the chipset 300 is adjusted to the preset constant test temperature to improve the test accuracy.

[0054] Among them, the adjustment of the actual test temperature of the chipset 300 can be adjusted through a refrigeration and heating system, or a temperature control system can be separately set on the chipset 300 to achieve separate, rapid, and precise control of the temperature of the chipset 300. Specifically, the temperature control system can be a heater and a cooler set on the chipset 300 or in the area near the chipset 300 to achieve rapid heating or cooling of the chipset 300. At the same time, the heater cooperates with the cooler to achieve two-way precise temperature control. Among them, the heater can be a resistance wire heater or an oil bath heater, etc.; the cooler can be a compressor, a radiator, or a cooling pipe, etc. When using a separate temperature control system to adjust the actual temperature of the chipset 300, the temperature control system needs to cooperate with the refrigeration and heating system to avoid large fluctuations in the temperature and air flow near the chipset 300, which may affect the accuracy of the aging test.

[0055] In order to further improve the applicable scenarios and applicability of the device, in some embodiments, multiple test cavities 100 in the device can have the same test temperature, so that the device can be used for aging tests of multiple groups of chipsets 300 at the same test temperature; in some embodiments, multiple test cavities 100 of the device can partially have the same test temperature, and the other part can have different test temperatures, so that the device can perform aging tests of multiple groups of chipsets 300 at the same test temperature, and can also perform aging tests of the same chipset 300 at multiple different test temperatures; in some embodiments, the test temperatures of multiple test cavities 100 of the device can all be different, so that the device can perform aging tests of the same chipset 300 at different test temperatures.

[0056] In some specific embodiments, the test temperatures of at least two test cavities 100 are different. When performing aging tests of the same group of chipset 300 at different test temperatures, among the multiple test cavities 100 in the device provided by the present disclosure, at least two test cavities 100 have different test temperatures, so as to perform aging tests of the same group of chipset 300 at multiple different test temperatures in this device.

[0057] In the embodiments provided by the present disclosure, as Figure 1 shown, in combination with Figures 5 to 9 , the chip aging test device includes multiple buffer cavities 200, and the buffer cavities 200 and the test cavities 100 are alternately arranged and form a closed cavity structure 400.

[0058] Among them, the number of buffer cavities 200 is at least two. For example, the number of buffer cavities 200 can be two, three, four or more. The number of buffer cavities 200 can be set according to the number of different test cavities 100. In order to ensure that the buffer cavity 200 can provide temperature pre-treatment for each test cavity 100, and the test cavity 100 and the buffer cavity 200 can enclose a closed cavity structure 400, usually the number of buffer cavities 200 is kept the same as the number of test cavities 100. For example, when the number of test cavities 100 is four, the number of buffer cavities 200 can also be four, and the four buffer cavities 200 and the four test cavities 100 are arranged alternately, and one buffer cavity 200 is arranged between two adjacent test cavities 100.

[0059] As Figure 1 shown, in order to enable the chipset 300 to move into the test cavity 100 via the buffer cavity 200, each buffer cavity 200 includes at least two partition members 500, and the plurality of partition members 500 can be opened and closed to enable the test chipset 300 to enter and exit the buffer cavity 200. In the present disclosure, the partition member 500 is used to isolate the test cavity 100 and the buffer cavity 200 to ensure that the test temperature in the test cavity 100 is not affected by the temperature in the buffer cavity 200 or the external temperature, and to ensure the constancy of the test temperature in each test cavity 100. Further, in order to prevent the influence of the air flow exchange generated by the opening and closing of the partition member 500 on the test temperature in the test cavity 100, the plurality of partition members 500 are configured to be opened and closed alternately. When the chipset 300 is about to move into or out of the buffer cavity 200, the partition member 500 is opened, and after the chipset 300 moves to a position where there is no intersection with the partition member 500, the partition member 500 is immediately closed to minimize the air flow exchange.

[0060] The opening and closing time of each partition member 500 can be adjusted according to the moving time of the chipset 300 at the corresponding position. In order to ensure that the chipset 300 can move smoothly between the buffer cavity 200 and the test cavity 100 and reduce the air flow exchange between the buffer cavity 200 and the test cavity 100, usually the opening and closing time of the partition member 500 can be less than or equal to 1.5 s. For example, it can be 1.5 s, 1.0 s, 0.5 s, 0.3 s, 0.1 s, etc. The shorter the opening and closing time of each partition member 500, the better the air flow isolation effect. Among them, the opening and closing times of the plurality of partition members 500 can be the same or different, and the opening and closing time of each partition member 500 can also be determined according to the specific moving time of the chipset 300 to ensure the smooth movement of the chipset 300.

[0061] In the present disclosure, each partition member 500 can be arranged in a double-layer structure or a multi-layer structure to further improve the thermal insulation performance of the partition member 500. When the partition member 500 is arranged in a double-layer structure, the inner structure of the partition member 500 can be a vacuum insulation layer, and the pressure leakage rate of this inner structure is less than 1×10 -5 Pa·m³ / s, so as to maintain the pressure in the buffer cavity 200 through the inner structure, thereby ensuring that the influence of the buffer cavity 200 on the test temperature in the adjacent test cavity 100 is minimized; the outer structure of the partition member 500 can adopt a high-temperature alloy honeycomb seal structure, and the temperature resistance range of this outer structure is -50°C to 300°C, so as to ensure the temperature resistance strength of the partition member 500, reduce the heat transfer of the partition member 500, and prevent the phenomenon of non-constant temperature in the test cavity 100 caused by the transfer of temperature by the partition member 500.

[0062] Among them, the inner structure of the partition member 500 refers to the side of the partition member 500 close to the cavity structure of the buffer cavity 200, and the outer structure of the partition member 500 refers to the side of the partition member 500 far from the cavity structure of the buffer cavity 200. Of course, the partition member 500 can also adopt a three-layer structure, a four-layer structure or even more layer structures, and the specific structure of each layer in the partition member 500 can be selected and adaptively adjusted according to the actual structural design requirements of the device, which will not be elaborated here.

[0063] As Figure 2 shown, combined with Figure 1 , since when the partition member 500 is opened, air flow exchange will occur between the buffer cavity 200 and the test cavity 100, thereby affecting the constancy of the test temperature in the test cavity 100. In order to further reduce the influence of the air flow exchange on the test temperature in the test cavity 100, each partition member 500 is configured with an air curtain isolation component 501, and the air curtain isolation component 501 is used to generate an air curtain 502 when the partition member 500 is opened, so as to isolate the air flow exchange between the buffer cavity 200 and the test cavity 100.

[0064] The air curtain isolation component 501 can be arranged at the junction of the buffer cavity 200 and the test cavity 100. When the partition member 500 is opened, the air curtain isolation component 501 can generate a gradient air curtain 502 with an air curtain structure, and the buffer cavity 200 and the test cavity 100 are isolated through the air flow isolation effect of this air curtain 502.

[0065] Among them, as Figure 3 shown, combined with Figure 2, To ensure the isolation effect of the air curtain 502, at least part of the projection of the air curtain 502 on the surface 503 of the partition overlaps with the surface 503 of the partition. Further, to improve the isolation effect of the air curtain 502, the projection of the air curtain 502 on the surface 503 of the partition covers the surface 503 of the partition.

[0066] To improve the isolation effect of the air curtain 502, the time for the air curtain isolation assembly 501 to generate the air curtain 502 is greater than or equal to the opening time of the partition 500. Before the partition 500 is opened, the air curtain isolation assembly 501 generates the air curtain 502 to prevent the air flow exchange generated at the moment when the partition 500 is opened. After the partition 500 is closed, the air curtain isolation assembly 501 stops generating the air curtain 502. By forming a partition with the air curtain 502 during the closing process of the partition 500, the air flow exchange between the buffer cavity 200 and the test cavity 100 is further prevented. Among them, the time for the air curtain isolation assembly 501 to generate the air curtain 502 can be greater than 1.5 s. For example, it can be 1.5 s, 1.8 s, 2.0 s, 2.5 s, etc. The generation time of the air curtain 502 should not be too long to prevent excessive power consumption of the device and reduce the aging test cost while ensuring the isolation effect of the air curtain 502.

[0067] Among them, each buffer cavity 200 is also equipped with a second temperature control component. By adjusting the temperature in the buffer cavity 200 through the second temperature control component, before the chipset 300 enters the test cavity 100, pre-heating or pre-cooling treatment is performed on the chipset 300, thereby shortening the test time of the chipset 300 and improving the test efficiency.

[0068] The second temperature control component can include a temperature sensor and a temperature regulation system. Among them, the temperature sensor detects the temperature in the buffer cavity 200, and according to the temperature information obtained by the temperature sensor, the temperature in the buffer cavity 200 is adjusted to be between the test temperatures of two adjacent test cavities 100 through the temperature regulation system, so as to perform pre-heating or pre-cooling treatment on the chipset 300, reduce the temperature difference generated by the chipset 300 after entering the test cavity 100, so that the chipset 300 can be quickly adjusted to the test temperature for aging test, thereby shortening the aging test time and improving the aging test efficiency.

[0069] In addition, before the chipset 300 enters the buffer cavity 200, the second temperature control component is used to control the temperature in the buffer cavity 200 to be adjusted to the current test temperature of the chipset 300, avoiding damage to the chipset 300 due to excessive temperature difference between the test temperature and the temperature in the buffer cavity 200, and improving the overall test reliability of the device.

[0070] Among them, the temperature control system in the second temperature control component can be arranged on the side wall and / or the bottom wall and / or the top wall of the buffer cavity 200, or can be suspended in the cavity of the buffer cavity 200. The temperature control system can be a heating device, a cooling device or a heating and cooling combined device. For example, it can be a PTC heater, a heat pump heater, a heat sink, a heat pipe cooler, etc. The specific type of the temperature control system can be selected according to the actual design requirements of the buffer cavity 200, and the present disclosure does not make specific limitations.

[0071] In the embodiment provided by the present disclosure, the chip aging test device includes at least one test core component 301, and the test core component 301 is configured to be able to perform rotational motion in the closed cavity structure 400, and the test core component 301 provides test signals for the chips in the chip group 300.

[0072] Among them, the closed cavity structure 400 is in a room temperature environment. For example, the test core component 301 can be in a temperature environment of 20°C to 30°C to prevent the test core component 301 from being damaged in a high temperature environment, improve the service life of the test core component 301, and thus improve the overall service life and test reliability of the device.

[0073] Each test core component 301 may include a test core board, and the test core board can integrate a power module, a signal input / output module, etc., and integrate functions such as test algorithms, data analysis and timing control logic, and is responsible for generating test patterns and controlling test processes, such as power sequences, signal timings, etc. The test core board in the test core component 301 provided by the present disclosure has the functions and hardware structures required for aging tests, and the specific structure and functions of the test core board here will not be elaborated.

[0074] Such as Figure 4 and Figure 5 shown, in combination with Figure 1 , in order to realize the connection between the test core component 301 and the chip group 300, a connector 302 is provided between each test core component 301 and the chip group 300. Since the chip group 300 moves inside the test cavity 100 and the buffer cavity 200, and the test core component 301 rotates in the closed cavity structure 400, there is cavity isolation between the chip group 300 and the test core component 301, and there is also a phenomenon of asynchronous movement between the chip group 300 and the test core component 301. In order to enable effective connection between the test core component 301 and the chip group 300, a connector 302 is provided on each surface of the test cavity 100 facing the test core component 301. Each connector 302 is located in the closed cavity structure 400. One end of the connector 302 is docked with each test chip in the test chip group 300, and the other end of the connector 302 is docked with the test core component 301.

[0075] The connector 302 can be a site board. The connector 302 can provide an adapted physical interface, and it can also perform functions such as power distribution and signal conditioning. It is the connection bridge between the chipset 300 and the test core component 301. Of course, the connector 302 can also be a connection structure other than the site board. With the development of the chip aging test device, the structure of the connector 302 can also be updated accordingly.

[0076] As Figure 1 shown, in combination with Figures 5 to 9 , in order to realize the rotation of the test core component 301 within the closed cavity structure 400, the device further includes a first driving mechanism 601 disposed within the closed cavity structure 400. The test core component 301 is connected to the first driving mechanism 601. The first driving mechanism 601 is configured to drive the test core component 301 to rotate along the circumferential direction of the closed cavity structure 400 according to the position of the chipset 300, so as to dock the chipset 300 with the test core component 301.

[0077] The first driving mechanism 601 can include a driving motor and a stage connected to the driving motor. The test core component 301 is disposed on the stage. The driving motor within the first driving mechanism 601 can be integrated at the bottom of the device. The driving motor can drive the stage to rotate, thereby driving the test core component 301 to rotate to a position corresponding to the chipset 300. In addition, the driving motor within the first driving mechanism 601 can also drive the stage to perform a swinging motion. After the test core component 301 rotates to a position corresponding to the chipset 300, the driving motor drives the test core component 301 to swing, so as to realize the plugging and unplugging between the test core component 301 and the connector 302, thereby realizing the connection and disconnection between the test core component 301 and the connector 302.

[0078] To enable the chipset 300 to move within the buffer cavity 200 and the test cavity 100, the device further includes a second driving mechanism (not shown in the figure). The second driving mechanism may include tracks provided at the bottoms of the buffer cavity 200 and the test cavity 100 and a driving motor. The driving motor can drive the chipset 300 located on the tracks to move, so as to realize the movement of the chipset 300 within the buffer cavity 200 and the test cavity 100. It should be noted that the setting of the tracks in the second driving mechanism does not affect the sealing performance of the test cavity 100 and the buffer cavity 200. Additionally, the tracks may not be provided, and the chipset 300 can be directly driven by the driving motor to move. Moreover, the driving motor in the second driving mechanism can also drive the chipset 300 to perform a swinging motion. After the test core component 301 rotates to a position corresponding to the chipset 300, the driving motor drives the chipset 300 to swing, so as to realize the plugging and unplugging between the chipset 300 and the connector 302, thereby realizing the connection and disconnection between the chipset 300 and the connector 302.

[0079] It should be understood that both the first driving mechanism 601 and the second driving mechanism can be designed and adjusted according to the actual structural requirements of the device. For example, the first driving mechanism 601 and the second driving mechanism can be related, and both can use the same driving motor to provide driving force to improve the integration of the device. Of course, the first driving mechanism 601 and the second driving mechanism can also be two independent and different mechanisms.

[0080] Among them, as Figure 4 shown, the device may further include a control center 700. The control center 700 has general control functions such as controlling the movement trajectories of each mechanism and collecting and processing data. The control center 700 can be a central processing unit (CPU), a microcontroller (MCU), a programmable logic controller (PLC), a system-on-chip (SoC), etc. that are signal-connected to the test device, and is used to coordinate, manage, and schedule each component within the device to complete the entire process of the device aging test. Of course, the device also includes other auxiliary components or conventional connection components that can be obtained in the art and are not listed here, which will not be elaborated further.

[0081] Based on the above-mentioned aging test device structure provided by the present disclosure, the device can be used for the aging test of at least one chipset 300 at at least one test temperature. The relationship between the test core component 301 and the chipset 300 within the chip aging test device provided by the present disclosure will be described below in combination with specific embodiments.

[0082] In some embodiments, as Figure 6As shown, the number of test core components 301 and the number of chip groups 300 are both one. The test core component 301 rotates according to the test cavity 100 where the chip group 300 is located, so that the test core component 301 is docked with the chips in the chip group 300. In this embodiment, the test core component 301 and the chip group 300 can perform synchronous rotational motion. After the chip group 300 determines the position of the test cavity 100 where it is located, the test core component 301 is docked with the chip group 300, so as to shorten the docking time between the test core component 301 and the chip group 300, further shorten the test time, and improve the test efficiency. In this embodiment, one chip group 300 can move between multiple test cavities 100, and the multiple test cavities 100 can have different test temperatures, so as to perform aging tests on the same chip group 300 at different test temperatures.

[0083] In some embodiments, as Figure 7 As shown, the number of test core components 301 and the number of chip groups 300 are both multiple. The test core components 301 and the chip groups 300 are arranged in one-to-one correspondence, and the test core components 301 and the corresponding chip groups 300 rotate synchronously. In this embodiment, the test core components 301 and the corresponding chip groups 300 can perform synchronous rotational motion. After the corresponding chip group 300 determines the position of the test cavity 100 where it is located, the test core component 301 is docked with the corresponding chip group 300, so as to shorten the docking time between the test core component 301 and the corresponding chip group 300, further shorten the test time, and improve the test efficiency. In this embodiment, multiple chip groups 300 can move between multiple test cavities 100, and the multiple test cavities 100 can have different test temperatures, so as to perform aging tests on multiple different chip groups 300 at different test temperatures simultaneously. Of course, in this embodiment, the test temperatures of the multiple test cavities 100 can also be the same or partially the same, so as to perform aging tests on multiple chip groups 300 or some chip groups 300 at the same test temperature.

[0084] In some embodiments, as Figure 8As shown in the figure, the number of test core components 301 is multiple, and the number of chip sets 300 is one. The test core components 301 are arranged in one-to-one correspondence with the test cavities 100. When testing a chip set 300 and the chip set 300 moves between different test cavities 100, the test core components 301 do not rotate relative to the test cavities 100. In this embodiment, the test core components 301 are relatively stationary with respect to the corresponding test cavities 100. After the chip set 300 determines the position of the test cavity 100 where it is located, the test core components 301 are docked with the chip set 300, avoiding the power consumption caused by the first driving mechanism 601 driving the test core components 301 to perform rotational motion, thereby achieving the purpose of reducing the overall power consumption of the device. In this embodiment, a chip set 300 can move between multiple test cavities 100, and the multiple test cavities 100 can have different test temperatures to perform aging tests on the same chip set 300 at different test temperatures.

[0085] In some embodiments, as Figure 9 shown in the figure, the number of test core components 301 is one, and the number of chip sets 300 is multiple. The number of chip sets 300 is less than the number of test cavities 100. The test core components 301 can be used to correspondingly connect one of the multiple chip sets 300. The test core components 301 rotate according to the test cavity 100 where the chip set 300 to be docked is located, so that the test core components 301 are docked with the chips in the corresponding chip set 300. In this embodiment, there is no specific corresponding relationship between the test core components 301 and the chip sets 300, and they can rotate according to the actual chip set 300 for aging tests. After the test core components 301 rotate to the preset position, they are docked with the chip set 300, and targeted aging tests can be performed on the chip set 300. In this embodiment, multiple chip sets 300 can move between multiple test cavities 100, and the multiple test cavities 100 can have different test temperatures to perform aging tests on a chip set 300 at different test temperatures. Of course, in this embodiment, the test temperatures of the multiple test cavities 100 can also be the same or partially the same, and the test core components 301 can be adjusted in position according to actual test requirements.

[0086] According to the test, compared with a single-test-cavity aging furnace, the chip aging test device provided by the present disclosure shortens the test time by at least 2 hours each time. For multiple chip sets 300, the cumulative reduction in the shortened test time is relatively large, which can improve the utilization rate of the device itself, shorten the test time, and improve the test efficiency.

[0087] The buffer cavity 200 provided by the present disclosure can also be used as a standby cavity for the test cavity 100. When the test cavity 100 fails or the number of the chip groups 300 to be tested changes, the temperature of the buffer cavity 200 can be adjusted to a preset test temperature, so as to meet various test requirements of the aging test device and improve the reuse rate of the device. When the buffer cavity 200 is used as a standby cavity, components such as a standby connector can be adaptively arranged on the buffer cavity 200 to meet the test conditions.

[0088] In the present disclosure, the chip group 300 includes at least one chip, and the chip can be one of DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), NAND Flash (NOT AND Flash Memory), NOR Flash (NOT OR Flash Memory), MRAM (Magnetoresistive RAM), ReRAM (Resistive RAM), PCRAM (Phase Change RAM), etc. The chips in each chip group 300 can be of the same type or different types, and the specific setting of the chip group 300 can be selected or adaptively adjusted according to specific test requirements. In addition, the structure and configuration of the test core component 301 can also be adaptively adjusted according to the number of the chip groups 300 and the types of the chips in the chip groups 300 to meet the chip test requirements.

[0089] An embodiment of the present disclosure provides a chip aging test method, as Figure 10 shown, in combination with Figure 1 , the method includes: step S10 to step S20.

[0090] Among them, step S10: in response to the test conditions, control the chip group to move into the test cavity; Step S20: control the chip group to stay in the test cavity for a preset duration to obtain the aging states of the chips in the chip group under the test conditions.

[0091] Among them, the test conditions include the test temperature, different test temperatures correspond to different test cavities 100, each test cavity 100 has a constant test temperature, a buffer cavity 200 is arranged between two adjacent test cavities 100, and the buffer cavity 200 and the test cavity 100 enclose a closed cavity structure 400; Before the control chipset 300 is moved to the test cavity 100, it includes: moving the control chipset 300 into the buffer cavity 200 for pre-treatment to reduce the temperature difference between each chip in the chipset 300 and the test temperature of the test cavity 100, thereby shortening the temperature conversion time of the chipset 300 at different test temperatures, thus shortening the test time and improving the test efficiency.

[0092] Among them, moving the control chipset 300 into the buffer cavity 200 for pre-treatment includes: adjusting the temperature in the buffer cavity 200 so that the temperature in the buffer cavity 200 is between the test temperatures of two adjacent test cavities 100. Specifically, before the chipset 300 enters the buffer cavity 200, the buffer cavity 200 can be controlled to adjust the temperature to the test temperature of the test cavity 100 where the chipset 300 is currently located, so as to avoid damage to the chips in the chipset 300 due to excessive temperature difference between the buffer cavity 200 and the test cavity 100. Before the chipset 300 is about to move from the buffer cavity 200 to the test cavity 100, the buffer cavity 200 can be controlled to adjust the temperature to the test temperature of the test cavity 100 to which the chipset 300 is about to move, pre-heating or pre-cooling the chipset 300, thereby shortening the test time of the chipset 300 and further improving the test efficiency.

[0093] The chip aging test method provided by the present disclosure can use the chip aging test device provided in the above embodiment to perform aging test on the chipset 300, and the specific test method can be adaptively adjusted according to the change of the specific structure of the device.

[0094] The following takes the device to perform aging test on a group of chipsets at four different test temperatures as an example to illustrate the test method provided by the present disclosure. Refer to Figure 1 , the chip aging test device has 4 test cavities 100 and 4 buffer cavities 200 arranged alternately, and the test temperatures of the 4 test cavities 100 are -10°C (low temperature stress test), 25°C (room temperature reference), 88°C (accelerated aging), 125°C (high temperature limit test) respectively, and the test cavities 100 corresponding to the above four test temperatures are arranged in sequence and enclosed, each test cavity 100 maintains a constant test temperature, and there is a test core component 301 in the closed cavity structure 400 formed by the buffer cavity 200 and the test cavity 100.

[0095] At the beginning of the test, according to the initial test temperature required by the chipset 300, the chipset 300 can be directly placed in the test cavity 100 corresponding to the initial test temperature. For example, before the test starts, the chipset 300 can be placed in the test cavity 100 at 25°C first.

[0096] When starting the test, the device controls the chipset 300 to move into the corresponding test cavity 100 in response to the test conditions. For example, when the test condition is the test temperature of chip accelerated aging at 88°C, the device includes: controlling the disconnection of the chipset 300 from the test core component 301 in the 25°C test cavity 100; controlling the chipset 300 to enter the 88°C test cavity 100 from the 25°C test cavity 100 via the buffer cavity 200. Meanwhile, controlling the synchronous rotation of the test core component 301 from the 25°C test cavity 100 to the 88°C test cavity 100; connecting the chipset 300 and the test core component 301 through the connector 302 provided on the 88°C test cavity 100, so as to keep the chipset 300 static for a preset duration under the test temperature condition of 88°C to obtain the accelerated aging test curve of the chip at 88°C.

[0097] Among them, before the chipset 300 enters the buffer cavity 200, the buffer cavity 200 is controlled to adjust the temperature to 25°C; during the movement of the chipset 300 from the 25°C test cavity 100 to the buffer cavity 200, the temperature inside the buffer cavity 200 is continuously adjusted so that the temperature inside the buffer cavity 200 is between 25°C and 88°C, to reduce the influence of temperature difference on the chip aging test, and at the same time preheat the chip before entering the 88°C test cavity 100 to shorten the chip heating time.

[0098] Among them, during the transfer process of the chipset 300 from the 25°C test cavity 100 to the 88°C test cavity 100, when the chipset 300 moves to the position adjacent to the buffer cavity 200 in the 25°C test cavity 100, the air curtain isolation component of the buffer cavity 200 is opened to form an air curtain. After the air flow between the 25°C test cavity 100 and the buffer cavity 200 is isolated, the corresponding partition 500 at this adjacent position is opened, and the chipset 300 moves from the 25°C test cavity 100 into the buffer cavity 200, and the isolation member is turned off; when the chip moves to the position adjacent to the 88°C test cavity 100 in the buffer cavity 200, the air curtain isolation component of the buffer cavity 200 is opened to form an air curtain. After the air flow between the 88°C test cavity 100 and the buffer cavity 200 is isolated, the corresponding partition 500 at this adjacent position is opened, and the chipset 300 moves from the buffer cavity 200 into the 88°C test cavity 100, and the isolation member is turned off.

[0099] The above embodiments are described by taking the example that the chipset 300 is moved from the 25°C test chamber 100 to the 88°C test chamber 100. When the chipset 300 is moved from the 88°C test chamber 100 to the 125°C test chamber 100 for high-temperature limit testing, the moving process, temperature control process, and component control process of the chipset 300 are the same as or substantially the same as those in the above embodiments, and will not be repeated here. After the chipset 300 undergoes low-temperature stress testing at -10°C, normal-temperature testing at 25°C, accelerated aging testing at 88°C, and high-temperature limit testing at 125°C, the chip can pass through the early failure stage of the bathtub curve and enter the performance stable period, completing the entire test cycle of the aging test. The above method can shorten the time of the entire test cycle and greatly improve the test efficiency.

[0100] It should be noted that although the steps of the chip aging test method in the present disclosure are described in a specific order in the drawings, this does not require or imply that these steps must be executed in that specific order, or that all the steps shown must be executed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0101] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include well-known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A chip aging test device, characterized in that: include: A plurality of test cavities, each of which is equipped with a first temperature control component, which independently regulates the temperature in the corresponding test cavity so that the test cavity has a constant test temperature, and the test cavity is used to perform an aging test on a chipset; A plurality of buffer cavities, wherein the buffer cavities and the test cavities are alternately arranged and form a closed cavity structure, wherein the closed cavity structure is used to accommodate at least one test core component, wherein the test core component is configured to be able to perform rotational motion within the closed cavity structure, and wherein the test core component provides a test signal for each chip in the chipset; Each of the buffer cavities comprises at least two partitions, which are used to block the airflow exchange between the buffer cavity and the adjacent test cavity; wherein the plurality of partitions are configured to open and close alternately so that the chipset can enter and exit the buffer cavity.

2. The chip aging test device according to claim 1, characterized in that: The test temperatures of at least two of the test cavities are different.

3. The chip aging test device according to claim 2, characterized in that: The test temperatures of two adjacent test cavities are different. Each buffer cavity is equipped with a second temperature control component. The temperature inside the buffer cavity is adjusted by the second temperature control component so that the temperature inside the buffer cavity is between the test temperatures of the two adjacent test cavities.

4. The chip aging test device according to claim 3, characterized in that: Before the chipset enters the buffer cavity, the second temperature control component is used to control the temperature in the buffer cavity to be adjusted to the current test temperature of the chipset; The temperature of the buffer cavity is between the test temperatures of two adjacent test cavities.

5. The chip aging test device according to claim 1, characterized in that: The number of the test core components and the number of the chipset are both one, and the test core component rotates according to the test cavity where the chipset is located so that the test core component is docked with the chipset.

6. The chip aging test device according to claim 1, characterized in that: The number of the test core components and the number of the chipsets are both plural, the test core components and the chipsets are arranged in a one-to-one correspondence, and the test core components rotate synchronously with the corresponding chipsets.

7. The chip aging test device according to claim 5 or 6, characterized in that: The device also includes a first driving mechanism arranged in the closed cavity structure, and the test core assembly is connected to the first driving mechanism. The first driving mechanism is used to drive the test core assembly to rotate along the circumferential direction of the closed cavity structure according to the position of the chipset, so that the chipset can be docked with the test core assembly.

8. The chip aging test device according to claim 1, characterized in that: There are multiple test core components and one chipset. The test core components are arranged in a one-to-one correspondence with the test cavities. When one chipset is tested and the chipset moves between different test cavities, the test core component does not rotate relative to the test cavity.

9. The chip aging test device according to claim 1, characterized in that: Each of the partition pieces is provided with a wind curtain isolation assembly, which is used to generate a wind curtain when the partition piece is opened to isolate the airflow exchange between the buffer cavity and the test cavity; wherein the projection of the wind curtain on the surface of the partition piece at least partially overlaps with the surface of the partition piece.

10. The chip aging test device according to claim 9, characterized in that: The time for the air curtain isolation component to generate the air curtain is greater than or equal to the opening time of the partition member.

11. The chip aging test device according to any one of claims 1-6 and 8-10, characterized in that: A connector is provided on a surface of each test cavity facing the test core component. Each connector is located in the closed cavity structure. One end of the connector is connected to each chip in the chipset, and the other end of the connector is connected to the test core component.

12. A chip aging test method, characterized in that: include: In response to the test conditions, controlling the chipset to move into the test chamber; Controlling the chipset to remain in the test chamber for a preset time to obtain an aging state of each chip in the chipset under the test conditions; Wherein, the test conditions include a test temperature, different test temperatures correspond to different test cavities, each test cavity has a constant test temperature, a buffer cavity is arranged between two adjacent test cavities, and the buffer cavity and the test cavity enclose a closed cavity structure; Before controlling the chipset to move to the test cavity, the method includes: controlling the chipset to move to the buffer cavity for pre-processing to reduce the temperature difference between each chip in the chipset and the test temperature of the test cavity.

13. The chip aging test method according to claim 12, characterized in that: The controlling the chipset to move into the buffer chamber for pre-processing includes: The temperature in the buffer cavity is adjusted so that the temperature in the buffer cavity is between the test temperatures of two adjacent test cavities.

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