Data processing method based on ARM instruction set, processor and computing equipment

Abstract

The embodiment of the invention provides a data processing method based on an ARM (Advanced RISC Machines) instruction set, which comprises the following steps of: generating an index sequence corresponding to to-be-shifted data in response to a shifting instruction carrying a shifting parameter, and then realizing shifting operation on the to-be-shifted data by using the index sequence to be matched with a TBL (Tunnel Bit Language) instruction. According to the method, the shift operation of the to-be-shifted data with different lengths can be realized by adjusting the total number of the data indexes and the invalid indexes in the index sequence, and the shift operation is not limited by the length of the to-be-shifted data, for example, when 16-bit indexes (including the data indexes and the invalid indexes) exist in the index sequence, the shift operation is not limited by the length of the to-be-shifted data; according to the data processing method, the displacement operation of the 128 (16 * 8)-bit data to be displaced can be realized by matching with the TBL instruction, the limitation that the displacement instruction in the traditional ARM instruction set can only realize the displacement operation of the 64-bit or less-length data to be displaced is broken through, and the purposes of improving the adaptability of the data processing method and meeting the multi-scene data displacement requirement are realized.

Description

Technical Field

[0001] This specification relates to the field of computer application technologies. Specifically, it relates to instruction set technologies in the field of computer application technologies. More specifically, it relates to a data processing method, apparatus, processor, computing device, and computer-readable storage medium based on the ARM instruction set. Background Art

[0002] A data shift operation refers to moving the binary values in a register along a specified direction. Shift operations can be divided into two forms: logical shift and arithmetic shift. Logical shift can include logical left shift and logical right shift, and arithmetic shift can include arithmetic left shift and arithmetic right shift. By reasonably using shift operations, the efficiency and accuracy of data processing can be improved.

[0003] Currently, in devices based on the ARM (Advanced RISC Machines) architecture, the applicability of shift instructions is poor and cannot meet the data shift requirements in multiple scenarios. Summary of the Invention

[0004] Embodiments of this specification provide a data processing method, apparatus, processor, computing device, and computer-readable storage medium based on the ARM instruction set, achieving the purpose of improving the adaptability of the data processing method and meeting the data shift requirements in multiple scenarios.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, an embodiment of this specification provides a data processing method based on the ARM instruction set, including:

[0007] Responding to a shift instruction carrying shift parameters, generating an index sequence corresponding to the data to be shifted; the shift parameters are used to represent the shift length of the data to be shifted, the index sequence includes multiple data indexes and at least one invalid index, the number of invalid indexes corresponds to the shift parameters, the data to be shifted includes multiple data segments, the data indexes correspond to the data segments, and the invalid indexes are used to indicate that the table branch lookup TBL instruction fills zeros at the target position, and the target position corresponds to the position of the invalid index in the index sequence;

[0008] According to the index sequence, using the TBL instruction to perform a shift operation on the data to be shifted.

[0009] In an embodiment, the shift instruction also carries a first shift direction, and the shift parameters include the number of invalid indexes;

[0010] The generation of the index sequence corresponding to the data to be shifted includes:

[0011] Parse the shift instruction to obtain the shift parameter and the first shift direction;

[0012] According to the first shift direction, shift multiple data indexes in the initial index sequence by N bits towards the lower bit direction to remove the data indexes stored in the lower N bits of the initial index sequence, where N is equal to the number of invalid indexes; the multiple data indexes in the initial index sequence correspond one-to-one with multiple data segments in the data to be shifted;

[0013] Fill the higher N bits in the shifted initial index sequence with the invalid indexes to obtain the first index sequence.

[0014] In one embodiment, the shift operation on the data to be shifted using the TBL instruction according to the index sequence includes:

[0015] Use the TBL instruction to store the data segments corresponding to the data indexes in the first index sequence in the target register, and fill 0 in the higher X bits in the target register according to the number of invalid indexes in the first index sequence to implement a logical right shift operation on the data to be shifted, where X is equal to the product of the number of bits of the data segment and the number of invalid indexes.

[0016] In one embodiment, the shift instruction also carries a second shift direction, and the shift parameter includes the number of invalid indexes;

[0017] The generation of the index sequence corresponding to the data to be shifted includes:

[0018] Parse the shift instruction to obtain the shift parameter and the second shift direction;

[0019] According to the second shift direction, shift multiple data indexes in the initial index sequence by N bits towards the higher bit direction to remove the data indexes stored in the higher N bits of the initial index sequence, where N is equal to the number of invalid indexes; the multiple data indexes in the initial index sequence correspond one-to-one with multiple data segments in the data to be shifted;

[0020] Fill the lower N bits in the shifted initial index sequence with the invalid indexes to obtain the second index sequence.

[0021] In one embodiment, the shift operation on the data to be shifted using the TBL instruction according to the index sequence includes:

[0022] Using the TBL instruction, store the data segment corresponding to the data index in the second index sequence in the target register, and fill 0 in the low X bits of the target register according to the number of invalid indexes in the second index sequence, so as to implement a logical left shift operation on the data to be shifted, where X is equal to the product of the number of bits of the data segment and the number of invalid indexes.

[0023] In one embodiment, the number of data indexes in the initial index sequence is greater than 8 bits, and the number of bits of the data segment is 8 bits.

[0024] In one embodiment, the shift parameter is an immediate value of the shift instruction, the immediate value represents the number of invalid indexes, or the shift parameter represents a register storing the number of invalid indexes.

[0025] Second, an embodiment of this specification provides a data processing device based on the ARM instruction set. The data processing device based on the ARM instruction set includes:

[0026] An index module, configured to generate an index sequence corresponding to the data to be shifted in response to a shift instruction carrying a shift parameter; the shift parameter is used to represent the shift length of the data to be shifted, the index sequence includes a plurality of data indexes and at least one invalid index, the number of invalid indexes corresponds to the shift parameter, the data to be shifted includes a plurality of data segments, the data indexes correspond to the data segments, and the invalid indexes are used to indicate that the table branch lookup TBL instruction fills zeros at the target position, and the target position corresponds to the position of the invalid index in the index sequence;

[0027] A shift module, configured to perform a shift operation on the data to be shifted according to the index sequence by using the TBL instruction.

[0028] Third, an embodiment of this specification also provides a processor, including:

[0029] A decoder, configured to decode a computation instruction into a decoded instruction;

[0030] An execution unit, configured to execute the decoded instruction to implement the data processing method based on the ARM instruction set described in any one of the above.

[0031] Fourth, an embodiment of this specification also provides a computing device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the data processing method based on the ARM instruction set described above is implemented.

[0032] Fifth aspect, an embodiment of this specification also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the data processing method based on the ARM instruction set as described above.

[0033] Sixth aspect, an embodiment of this specification provides a computer program product or a computer program. The computer program product includes a computer program, and the computer program is stored in a computer-readable storage medium; a processor of the computer device reads the computer program from the computer-readable storage medium, and when the processor executes the computer program, it implements the steps of the above-mentioned data processing method based on the ARM instruction set.

[0034] As can be seen from the above technical solutions, the data processing method based on the ARM instruction set provided by the embodiments of this specification first responds to a shift instruction carrying a shift parameter to generate an index sequence corresponding to the data to be shifted, and then uses this index sequence in cooperation with the TBL instruction to implement the shift operation on the data to be shifted. This data processing method based on the ARM instruction set can adjust to implement the shift operation on data to be shifted with different lengths according to the data indexes in the index sequence and the total number of invalid indexes, and is not limited by the length of the data to be shifted. For example, when there are 16-bit indexes (including data indexes and invalid indexes) in the index sequence, in cooperation with the TBL instruction, a shift operation on 128 (16×8)-bit data to be shifted can be implemented, breaking through the limitation that the shift instruction in the traditional ARM instruction set can only implement the shift operation on data to be shifted with a length of 64 bits or less, achieving the purpose of improving the adaptability of the data processing method and meeting the data shift requirements in multiple scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this specification, and for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0036] Figure 1 A schematic diagram of the correspondence relationship between index values, data to be shifted, and zero-filled data segments provided by an embodiment of this specification;

[0037] Figure 2 A schematic diagram of the process of logical right shift provided by an embodiment of this specification;

[0038] Figure 3 A schematic diagram of the process of logical right shift provided by another embodiment of this specification;

[0039] Figure 4 Schematic diagram of a logical left shift process provided for one embodiment of this specification;

[0040] Figure 5 Schematic diagram of a logical left shift process provided for another embodiment of this specification;

[0041] Figure 6 Schematic diagram of the process of a data processing method based on the ARM instruction set provided for one embodiment of this specification;

[0042] Figure 7 Schematic diagram of the structure of a shift instruction provided for one embodiment of this specification;

[0043] Figure 8 Schematic diagram of the structure of a shift instruction provided for another embodiment of this specification;

[0044] Figure 9 Schematic diagram of the structure of a data processing device based on the ARM instruction set provided for one embodiment of this specification;

[0045] Figure 10 Schematic diagram of the structure of a processor provided for one embodiment of this specification;

[0046] Figure 11 Schematic diagram of the structure of a computing device provided for one embodiment of this specification. Specific embodiments

[0047] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification should have the ordinary meaning as understood by those of ordinary skill in the field to which this specification belongs. The "first", "second" and similar terms used in the embodiments of this specification do not denote any order, quantity or importance, but are only used to avoid confusion of components.

[0048] Unless otherwise required by the context, throughout this specification, "a plurality" means "at least two", and "including" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0049] Next, the technical solutions in the embodiments of this specification will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification.

[0050] Overview

[0051] In the related art, traditional shift instructions in the ARM instruction set may include instructions such as LSL (Logical Shift Left), LSR (Logical Shift Right), ASR (Arithmetic Shift Right), and ROR (Rotate Right). These instructions can perform shift operations on data of 64 bits and below. However, in some scenarios, it may be necessary to perform shift operations on data exceeding 64 bits. At this time, these shift instructions cannot meet the shift operations of, for example, 128-bit or higher-bit data, revealing the problem of poor applicability and inability to meet the data shift requirements of multiple scenarios.

[0052] The inventor found through research that the characteristics of the TBL (Table Branch Lookup) instruction can be utilized to implement shift operations on data to be shifted with different bit widths by generating a specific index sequence for the TBL instruction. Specifically, first, by studying the characteristics of the TBL instruction, it is found that the main function of the TBL instruction is to perform a table lookup operation, retrieve data from the lookup table in the source register according to the index value, and place the retrieved data in the appropriate position in the destination register. In this way, a set of predefined data can be associated with the index, and the corresponding data can be obtained at runtime according to the index value. For example, assume there is a set of 16 index values: 0x0, 0x1, 0x2, 0x3, 0x4, 0x5... 0xd, 0xe, and 0xf. This set of index values respectively correspond to 16 data segments: data segment 0, data segment 1, data segment 2, data segment 3, data segment 4, data segment 5... data segment d, data segment e, and data segment f. Then, the corresponding relationship between the index value and the data segment is stored in the lookup table. Assume there is an index sequence including data segment 0, data segment 1, data segment d, and data segment e arranged in sequence. Then, according to this index sequence, the TBL instruction can place data segment 0, data segment 1, data segment d, and data segment e into the target register in sequence.

[0053] Through research, it is found that if an invalid index is set such that the TBL instruction fills 0 at the corresponding position according to this invalid index, then with a specific index sequence, a logical shift operation on data exceeding 64 bits can be achieved. Specifically, referring to Figure 1 , assuming that 0x10 is set as the invalid index and other index values are data indices, the original data to be shifted includes data segments 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, and f arranged in sequence. These data segments correspond one-to-one with the index values 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, and 0xf respectively, and the corresponding relationship is stored in the lookup table. At the same time, the index value 0x10 is defined as the invalid index, and the TBL instruction will fill 0 in the target register at the position of the invalid index in the index sequence (i.e., the zero-filled data segment "00" in Figure 1 ). Then, referring to Figure 2 , if the index sequence is: 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, and 0x1, after the TBL instruction fills data into the target register according to this index sequence, the following can be obtained: the zero-filled data segment (represented by "00" for the zero-filled data segment in Figure 2 ), data segment f, data segment e, data segment d, data segment c, data segment b, data segment a, data segment 9, data segment 8, data segment 7, data segment 6, data segment 5, data segment 4, data segment 3, data segment 2, and data segment 1 after shifting, achieving a right shift effect of removing data segment 0 from the data to be shifted.

[0054] Similarly, referring to Figure 3 , if the index sequence is: 0x10, 0x10, 0xf, 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, and 0x2, after the TBL instruction fills data into the target register according to this index sequence, the following can be obtained: the zero-filled data segment (represented by "00" for the zero-filled data segment in Figure 3 ), the zero-filled data segment, data segment f, data segment e, data segment d, data segment c, data segment b, data segment a, data segment 9, data segment 8, data segment 7, data segment 6, data segment 5, data segment 4, data segment 3, and data segment 2 after shifting, achieving a right shift effect of removing data segment 0 and data segment 1 from the data to be shifted.

[0055] Similarly, referring to Figure 4, if the index sequence is: 0xe, 0xd, 0xc, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, 0x0, and 0x10, after the TBL instruction fills data into the target register according to this index sequence, the following can be obtained: data segment e, data segment d, data segment c, data segment b, data segment a, data segment 9, data segment 8, data segment 7, data segment 6, data segment 5, data segment 4, data segment 3, data segment 2, data segment 1, data segment 0, and the shifted data of the zero-filled data segment (in Appendix Figure 4 which is represented by "00" for the zero-filled data segment), achieving the left-shift effect of removing data segment f from the data to be shifted.

[0056] Reference Figure 5 , if the index sequence is: 0xc, 0xb, 0xa, 0x9, 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, 0x0, 0x10, 0x10, and 0x10, after the TBL instruction fills data into the target register according to this index sequence, the following can be obtained: data segment c, data segment b, data segment a, data segment 9, data segment 8, data segment 7, data segment 6, data segment 5, data segment 4, data segment 3, data segment 2, data segment 1, data segment 0, the zero-filled data segment (in Appendix Figure 3 which is represented by "00" for the zero-filled data segment), the zero-filled data segment, and the shifted data of the zero-filled data segment, achieving the left-shift effect of removing data segment f and data segment e from the data to be shifted.

[0057] When each data segment includes 8-bit data, by generating the above index sequence including 16 index values and cooperating with the TBL instruction, the shift operation of 128-bit data can be realized. When it is necessary to perform a shift operation on 64-bit data, an index sequence including 8 index values can be generated and cooperate with the TBL instruction to realize the shift operation on 64-bit data; when it is necessary to perform a shift operation on 256-bit data, an index sequence including 32 index values can be generated and cooperate with the TBL instruction to realize the shift operation on 256-bit data. In this way, the above method first generates an index sequence corresponding to the data to be shifted, and then uses this index sequence to cooperate with the TBL instruction to realize the shift operation on the data to be shifted. In this method, the shift operation on data to be shifted with different lengths can be adjusted according to the data index in the index sequence and the total number of invalid indexes, without being limited by the length of the data to be shifted. For example, when there are 16-bit indexes (including data indexes and invalid indexes) in the index sequence, cooperating with the TBL instruction can realize the shift operation on 128 (16×8)-bit data to be shifted, breaking through the limitation that the shift instructions in the traditional ARM instruction set can only realize the shift operation on data to be shifted with a length of 64 bits and below, achieving the purpose of improving the adaptability of the data processing method and meeting the data shift requirements in multiple scenarios.

[0058] Based on the above concept, an embodiment of this specification provides a data processing method based on the ARM instruction set, aiming to solve the problem that data with a length greater than 64 bits cannot be shifted in a computing device based on the ARM architecture. Next, an exemplary description of the data processing method based on the ARM instruction set provided by the embodiment of this specification will be given with reference to the accompanying drawings.

[0059] Exemplary Method

[0060] Referring to Figure 6 , taking the processor 11 in the computing device 10 as an example, an embodiment of this specification provides a data processing method based on the ARM instruction set, including:

[0061] S601: In response to a shift instruction carrying a shift parameter, generate an index sequence corresponding to the data to be shifted; the shift parameter is used to represent the shift length of the data to be shifted, the index sequence includes a plurality of data indexes and at least one invalid index, the number of invalid indexes corresponds to the shift parameter, the data to be shifted includes a plurality of data segments, the data indexes correspond to the data segments, and the invalid indexes are used to indicate that the table branch lookup TBL instruction fills zeros at the target position, and the target position corresponds to the position of the invalid index in the index sequence;

[0062] S602: According to the index sequence, use the TBL instruction to perform a shift operation on the data to be shifted.

[0063] In Figure 6 , the shown application scenario is the scenario where the processor 11 shifts the data to be shifted to obtain the shifted data. Although Figure 6 the data to be shifted and the shifted data are represented outside the processor 11, it can be understood that in an actual processing scenario, the data to be shifted and the shifted data can also be located inside the processor 11. This specification does not limit this. The processor 11 can perform shift operations on data of various lengths through the data processing method based on the ARM instruction set provided by the embodiment of this specification when performing tasks such as bit operations, encryption algorithms, and compression algorithms.

[0064] As described above, the index sequence can be a sequence including a plurality of index values and their storage order, where the index values can be data indexes or invalid indexes. A data index refers to an index value corresponding to a data segment in the data to be shifted, and an invalid index can refer to an index value that does not correspond to a data segment in the shifted data.

[0065] The TBL instruction will find the data segment corresponding to the data index according to the data index and place it at the position corresponding to the position of the data index in the index sequence. Similarly, the TBL instruction will fill zeros at the target position according to the invalid index. For example, if a data index 1 corresponds to data segment A and the position of the data index 1 in the index sequence is the first position, the TBL instruction will find data segment A according to the data index 1 and place data segment A at the first data segment position from the low bit in the target register. Also, for example, if the position of the invalid index in the index sequence is the third position, the TBL instruction can fill 0 at the third data segment position from the low bit in the target register according to the position of the invalid index in the index sequence.

[0066] The shift parameter characterizing the shift length of the data to be shifted may refer to the shift parameter characterizing how many data segments the data to be shifted needs to be shifted, that is, the shift length may be equal to a multiple of the number of bits of the data segment.

[0067] In this embodiment, as can be seen from the previous description, by responding to the shift instruction to generate an index sequence, the index sequence can cooperate with the TBL instruction to implement the shift operation on the data to be shifted.

[0068] Specifically, the shift operation may include a logical right shift operation and a logical left shift operation.

[0069] For the logical right shift operation, optionally, in combination with Figure 2 and Figure 3 , the shift instruction also carries a first shift direction, and the shift parameter includes the number of invalid indexes;

[0070] The generation of the index sequence corresponding to the data to be shifted includes:

[0071] Parse the shift instruction to obtain the shift parameter and the first shift direction;

[0072] According to the first shift direction, move multiple data indexes in the initial index sequence N bits towards the low bit direction to remove the data indexes stored in the low N bits in the initial index sequence, where N is equal to the number of invalid indexes; the multiple data indexes in the initial index sequence correspond one by one to the multiple data segments in the data to be shifted;

[0073] Fill the high N bits in the shifted initial index sequence with the invalid indexes to obtain the first index sequence.

[0074] The first shift direction may be an immediate number in the shift instruction, and specifically, the binary value of one bit of data can be used to characterize the first shift direction. For example, in one embodiment, the value of a specific data bit in the shift instruction being 1 can be used to represent the first shift direction.

[0075] Specific reference Figure 7 , Figure 7 In it, Vn represents the source register, Vd represents the destination register, and size represents the assembly symbol. In the shift instruction, the value of size can be 16b, where b represents 8 bits and 16b represents 128 bits; imm8[7:3] and imm8[2:0] respectively represent two parts that make up the shift parameter. In Figure 7 , the shift parameter is stored in the shift instruction in the form of an immediate number. In this way, during the execution of the instruction, the shift parameter can be directly obtained from the instruction without occupying additional registers for storing the shift parameter, which helps to reduce the operating burden of the computing device and improve the execution efficiency of the algorithm. The "1" on the right side of size indicates that this shift instruction is an instruction indicating a logical right shift operation. The other "0" and "Q" are parameters filled in accordance with the format of this type of instruction in the ARM instruction.

[0076] Correspondingly, the performing a shift operation on the data to be shifted according to the index sequence by using the TBL instruction includes:

[0077] Using the TBL instruction, storing the data segment corresponding to the data index in the first index sequence in the destination register, and filling 0 in the high X bits in the destination register according to the number of invalid indexes in the first index sequence to implement a logical right shift operation on the data to be shifted, where X is equal to the product of the number of bits of the data segment and the number of invalid indexes.

[0078] For the logical left shift operation, optionally, the shift instruction also carries a second shift direction, and the shift parameter includes the number of invalid indexes;

[0079] The generating an index sequence corresponding to the data to be shifted includes:

[0080] Parsing the shift instruction to obtain the shift parameter and the second shift direction;

[0081] According to the second shift direction, shifting a plurality of data indexes in the initial index sequence N bits in the high-order direction to remove the data indexes stored in the high N bits in the initial index sequence, where N is equal to the number of invalid indexes; the plurality of data indexes in the initial index sequence correspond one by one to the plurality of data segments in the data to be shifted;

[0082] Filling the invalid indexes in the low N bits in the shifted initial index sequence to obtain a second index sequence.

[0083] The performing a shift operation on the data to be shifted according to the index sequence by using the TBL instruction includes:

[0084] Using the TBL instruction, store the data segment corresponding to the data index in the second index sequence in the target register. According to the number of invalid indexes in the second index sequence, fill 0 in the low X bits of the target register to implement a logical left shift operation on the data to be shifted, where X is the product of the number of bits of the data segment and the number of invalid indexes.

[0085] Similarly, the second shift direction can be an immediate number in the shift instruction. Specifically, the first shift direction can be represented by the binary value of a single-bit data. For example, in one embodiment, a value of 0 for a specific data bit in the shift instruction can represent the second shift direction.

[0086] Specifically refer to Figure 8 , Figure 8 where Vn represents the source register, Vd represents the target register, and size represents an assembly symbol. In the shift instruction, the value of size can be 16b, where b represents 8 bits and 16b represents 128 bits; imm8[7:3] and imm8[2:0] respectively represent the two parts that make up the shift parameter. In Figure 8 , the shift parameter is stored in the shift instruction in the form of an immediate number. In this way, during the execution of the instruction, the shift parameter can be directly obtained from the instruction without occupying additional registers for storing the shift parameter, which helps to reduce the operating burden of the computing device and improve the execution efficiency of the algorithm. The "0" on the right side of size indicates that this shift instruction is an instruction indicating a logical right shift operation. The other "0"s and "Q"s are parameters filled in accordance with the format of this type of instruction in the ARM instruction.

[0087] Optionally, in other embodiments, the shift parameter can also represent a register storing the number of invalid indexes. In this way, by storing different numbers of invalid indexes in the register, the purpose of generating index sequences with different numbers of invalid indexes through the same shift instruction can be achieved.

[0088] Optionally, in one embodiment, the number of data indexes in the initial index sequence is greater than 8 bits, and the number of bits of the data segment is 8 bits. For example, the number of data indexes in the initial index sequence can be 16 bits, 32 bits, etc., which can be used to achieve the purpose of generating index sequences with 16 and 32 index values respectively. In this way, logical shift operations on data to be shifted greater than 64 bits, such as 128 bits and 256 bits, can be achieved.

[0089] Exemplary Apparatus

[0090] In an exemplary embodiment of the present specification, a data processing device based on the ARM instruction set is further provided, which is characterized in that it is applied to a computing device, such as Figure 9 As shown, the data processing device based on the ARM instruction set includes:

[0091] An index module 901, configured to generate an index sequence corresponding to the data to be shifted in response to a shift instruction carrying a shift parameter; the shift parameter is used to characterize the shift length of the data to be shifted, the index sequence includes a plurality of data indexes and at least one invalid index, the number of invalid indexes corresponds to the shift parameter, the data to be shifted includes a plurality of data segments, the data indexes correspond to the data segments, and the invalid indexes are used to indicate that the table branch lookup TBL instruction fills zeros at the target position, and the target position corresponds to the position of the invalid index in the index sequence;

[0092] A shift module 902, configured to perform a shift operation on the data to be shifted according to the index sequence by using the TBL instruction.

[0093] In one embodiment, the shift instruction further carries a first shift direction, and the shift parameter includes the number of invalid indexes;

[0094] The index module generating an index sequence corresponding to the data to be shifted is specifically configured to:

[0095] Parse the shift instruction to obtain the shift parameter and the first shift direction;

[0096] According to the first shift direction, shift a plurality of data indexes in the initial index sequence N bits towards the lower bit direction to remove the data indexes stored in the lower N bits in the initial index sequence, where N is equal to the number of invalid indexes; the plurality of data indexes in the initial index sequence correspond one-to-one with the plurality of data segments in the data to be shifted;

[0097] Fill the invalid indexes in the higher N bits of the shifted initial index sequence to obtain a first index sequence.

[0098] In one embodiment, the shift module performing a shift operation on the data to be shifted according to the index sequence by using the TBL instruction is specifically configured to:

[0099] Use the TBL instruction to store the data segment corresponding to the data index in the first index sequence in a target register, and fill 0 in the higher X bits in the target register according to the number of invalid indexes in the first index sequence to implement a logical right shift operation on the data to be shifted, where X is equal to the product of the number of bits of the data segment and the number of invalid indexes.

[0100] In one embodiment, the shift instruction also carries a second shift direction, and the shift parameter includes the number of invalid indexes;

[0101] Specifically, the index module generates an index sequence corresponding to the data to be shifted for:

[0102] Parsing the shift instruction to obtain the shift parameter and the second shift direction;

[0103] According to the second shift direction, shifting multiple data indexes in the initial index sequence N bits towards the high-order direction to remove the data indexes stored in the high N bits in the initial index sequence, where N is equal to the number of invalid indexes; the multiple data indexes in the initial index sequence correspond one by one to the multiple data segments in the data to be shifted;

[0104] Filling the low N bits in the shifted initial index sequence with the invalid indexes to obtain a second index sequence.

[0105] In one embodiment, the shift module performs a shift operation on the data to be shifted according to the index sequence by using the TBL instruction, specifically for:

[0106] Using the TBL instruction to store the data segments corresponding to the data indexes in the second index sequence in a target register, and filling 0 in the low X bits in the target register according to the number of invalid indexes in the second index sequence to implement a logical left shift operation on the data to be shifted, where X is equal to the product of the number of bits of the data segment and the number of invalid indexes.

[0107] In one embodiment, the number of data indexes in the initial index sequence is greater than 8 bits, and the number of bits of the data segment is 8 bits.

[0108] In one embodiment, the shift parameter is an immediate value of the shift instruction, and the immediate value represents the number of invalid indexes, or the shift parameter represents a register storing the number of invalid indexes.

[0109] For the specific limitations of the data processing device based on the ARM instruction set, reference can be made to the limitations of the data processing method based on the ARM instruction set in the foregoing text, which will not be elaborated here. Each module in the above data processing device based on the ARM instruction set can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or independent of it, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0110] Exemplary Processor and Computing Device

[0111] One embodiment of this specification provides a processor, such as Figure 10 As shown, the processor 1001 includes:

[0112] A decoder 1002 for decoding computation instructions into decoded instructions;

[0113] An execution unit 1003 for executing the decoded instructions to implement the data processing method described in any of the above embodiments or the data processing method based on the ARM instruction set described in any of the above embodiments.

[0114] In addition to the above structure, the processor 1001 may further include a plurality of registers 1004 to cooperate with the execution unit 1003 to execute tasks. Both the register 1004 and the decoder 1002 are connected to the execution unit 1003.

[0115] Another embodiment of this application also proposes a computing device. Refer to Figure 11 As shown, an exemplary embodiment of this specification also provides a computing device, including: a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it executes the steps in the data processing method based on the ARM instruction set according to various embodiments of this specification described in the above embodiments of this specification.

[0116] The internal structure of this computing device may be as Figure 11 As shown, this computing device includes a processor, a memory, a network interface, and an input device connected through a system bus. Among them, the processor of this computing device is used to provide computing and control capabilities. The memory of this computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of this computing device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it performs the steps in the data processing method based on the ARM instruction set described in the above embodiments of this specification according to various embodiments of this specification.

[0117] The processor may include a main processor, and may also include a baseband chip, a modem, etc.

[0118] The memory stores a program for implementing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, and so on.

[0119] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or may be an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0120] The input device may include a device for receiving user input data and information, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer or a gravity sensor, etc.

[0121] The output device may include a device for allowing output of information to the user, such as a display screen, a printer, a speaker, etc.

[0122] The communication interface may include a device of any transceiver type for communicating with other devices or communication networks, such as Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0123] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any one of the data processing methods based on the ARM instruction set provided in the above embodiments of the present application.

[0124] The computing device may further include a display component and a voice component. The display component may be a liquid crystal display screen or an electronic ink display screen. The input device of the computing device may be a touch layer covered on the display component, or a button, a trackball or a touchpad provided on the housing of the computing device, or an external keyboard, a touchpad or a mouse, etc.

[0125] Those skilled in the art can understand, Figure 11The structure shown is only a block diagram of some structures related to the solution of this specification, and does not constitute a limitation on the computing device to which the solution of this specification is applied. The specific computing device may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0126] Exemplary Computer Program Product and Storage Medium

[0127] In addition to the above methods and devices, the data processing method based on the ARM instruction set provided in the embodiments of this specification may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor executes the steps in the data processing method based on the ARM instruction set according to various embodiments of this specification described in the "Exemplary Method" section above of this specification.

[0128] The computer program product can be written in any combination of one or more programming languages to write program code for performing the operations of the embodiments of this specification. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed completely on the user's computing device, partially on the user's device, executed as an independent software package, partially on the user's computing device and partially on a remote computing device, or completely on a remote computing device or server.

[0129] In addition, the embodiments of this specification also provide a computer-readable storage medium, on which a computer program is stored. The computer program is executed by a processor to perform the steps in the data processing method based on the ARM instruction set according to various embodiments of this specification described in the "Exemplary Method" section above of this specification.

[0130] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this specification can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0131] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0132] The above-described embodiments merely represent several implementation manners of this specification. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the solutions provided by the embodiments of this specification. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. A data processing method based on the ARM instruction set, characterized in that, Including: Generating an index sequence corresponding to data to be shifted in response to a shift instruction carrying a shift parameter; The shift parameter is used to characterize the shift length of the data to be shifted. The index sequence includes a plurality of data indexes and at least one invalid index. The number of invalid indexes corresponds to the shift parameter. The data to be shifted includes a plurality of data segments. The data indexes correspond to the data segments. The invalid index is used to indicate that the table branch look-up TBL instruction fills zeros at the target position, and the target position corresponds to the position of the invalid index in the index sequence; Performing a shift operation on the data to be shifted according to the index sequence by using the TBL instruction.

2. The method according to claim 1, characterized in that, The shift instruction also carries a first shift direction, and the shift parameter includes the number of invalid indexes; The generating the index sequence corresponding to the data to be shifted includes: Parsing the shift instruction to obtain the shift parameter and the first shift direction; According to the first shift direction, shifting a plurality of data indexes in the initial index sequence by N bits towards the lower bit direction to remove the data indexes stored in the lower N bits in the initial index sequence, where N is equal to the number of invalid indexes; the plurality of data indexes in the initial index sequence correspond one-to-one to the plurality of data segments in the data to be shifted; Filling the higher N bits in the shifted initial index sequence with the invalid indexes to obtain a first index sequence.

3. The method according to claim 2, characterized in that, The performing the shift operation on the data to be shifted according to the index sequence by using the TBL instruction includes: Using the TBL instruction to store the data segments corresponding to the data indexes in the first index sequence in a target register, and filling 0 in the higher X bits in the target register according to the number of invalid indexes in the first index sequence to implement a logical right shift operation on the data to be shifted, where X is equal to the product of the number of bits of the data segment and the number of invalid indexes.

4. The method according to claim 1, characterized in that, The shift instruction also carries a second shift direction, and the shift parameter includes the number of invalid indexes; The generating the index sequence corresponding to the data to be shifted includes: Parsing the shift instruction to obtain the shift parameter and the second shift direction; According to the second shift direction, shifting a plurality of data indexes in the initial index sequence by N bits towards the higher bit direction to remove the data indexes stored in the higher N bits in the initial index sequence, where N is equal to the number of invalid indexes; the plurality of data indexes in the initial index sequence correspond one-to-one to the plurality of data segments in the data to be shifted; Filling the lower N bits in the shifted initial index sequence with the invalid indexes to obtain a second index sequence.

5. The method according to any one of claim 4, characterized in that, The performing the shift operation on the data to be shifted according to the index sequence by using the TBL instruction includes: Using the TBL instruction to store the data segments corresponding to the data indexes in the second index sequence in a target register, and filling 0 in the lower X bits in the target register according to the number of invalid indexes in the second index sequence to implement a logical left shift operation on the data to be shifted, where X is equal to the product of the number of bits of the data segment and the number of invalid indexes.

6. The method according to any one of claims 2 to 5, characterized in that, The number of data indexes in the initial index sequence is greater than 8 bits, and the number of bits of the data segment is 8 bits.

7. The method according to any one of claims 1 to 5, characterized in that, The shift parameter is an immediate value of the shift instruction, and the immediate value represents the number of invalid indexes. Alternatively, the shift parameter represents a register storing the number of invalid indexes.

8. A data processing device based on the ARM instruction set, characterized in that, The data processing device based on the ARM instruction set includes: An index module, configured to generate an index sequence corresponding to the data to be shifted in response to a shift instruction carrying a shift parameter; the shift parameter is used to represent the shift length of the data to be shifted, the index sequence includes a plurality of data indexes and at least one invalid index, the number of invalid indexes corresponds to the shift parameter, the data to be shifted includes a plurality of data segments, the data indexes correspond to the data segments, and the invalid index is used to indicate that the table branch lookup TBL instruction fills zeros at the target position, and the target position corresponds to the position of the invalid index in the index sequence; A shift module, configured to perform a shift operation on the data to be shifted by using the TBL instruction according to the index sequence.

9. A processor, characterized in that, including: A decoder, configured to decode a calculation instruction into a decoded instruction; An execution unit, configured to execute the decoded instruction to implement the data processing method based on the ARM instruction set according to any one of claims 1 to 7.

10. A computing device, characterized in that, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the data processing method based on the ARM instruction set according to any one of claims 1 to 7 when executing the computer program.

11. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the data processing method based on the ARM instruction set according to any one of claims 1 to 7 is implemented.

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