Pseudo out-of-order instruction scheduling method based on branch jump

Abstract

The present invention provides a pseudo-out-of-order instruction scheduling method based on branch jumps, which belongs to the field of processor technology and is applied to a dispatch and emission unit in a superscalar processor. The method comprises: if the currently received instruction is a branch instruction, dispatching the current branch instruction to a branch instruction emission queue; determining whether the current branch instruction needs to be speculatively awakened; if it is determined that the current branch instruction needs to be speculatively awakened, determining whether the oldest branch instruction in the branch instruction emission queue can be awakened within two clock cycles; if it is determined that the oldest branch instruction in the branch instruction emission queue cannot be awakened within two clock cycles, pausing the operation of transmitting other instructions in the branch instruction emission queue and the non-branch instruction emission queue that follow the oldest branch instruction to the execution unit. By conditionally pausing branch instructions, the present invention avoids the cost of branch prediction errors caused by out-of-order execution and significantly reduces the power consumption of the processor.

Description

Technical Field

[0001] The present invention belongs to the technical field of hardware processors, and in particular relates to a pseudo-out-of-order instruction scheduling method based on branch jumps. Background Art

[0002] Power consumption optimization in high-performance processors has always been a hot topic in processor technology research and a major factor limiting processor performance stability. To adapt to the increasing number of processor back-end execution components and complex data path networks without compromising computing performance, power consumption optimization is becoming increasingly important.

[0003] like Figure 1 As shown, the general structure of a superscalar processor can execute multiple instructions simultaneously. The central processing unit (CPU) includes an instruction fetch unit, a level 1 instruction cache (L1 Instruction Cache), a pre-decode unit, an instruction fetch buffer (Fetch Buffer), a decode unit, a register rename unit, a dispatch and issue unit, an execution unit (EU), a reorder buffer (ROB), and a commit unit. The execution unit can execute multiple instructions in a single clock cycle, surpassing the ability of a typical processor to process only one instruction at a time. The main feature of a superscalar architecture is that it has multiple execution units that can handle different types of operations in parallel, such as integer operations, floating-point operations, load operations, and store operations.

[0004] Branch instructions are a special type of instruction that disrupts the entire execution order. Therefore, in out-of-order units, branch instructions cause these units to perform ineffective work. Scheduling branch instructions is an effective method for reducing system power consumption. Currently, many branch instructions are scheduled completely out of order, with predictions made based on the results. However, this scheduling method introduces two problems: First, when a branch instruction is executed, many subsequent instructions may have already completed execution. If the branch instruction prediction fails, the previously executed instructions are effectively wasted. Second, out-of-order execution of branch instructions requires bulk storage of branch instruction results, increasing storage resources and power consumption. Therefore, how to properly schedule branch instructions is a key factor affecting processor performance.

[0005] In summary, the unreasonable existing branch instruction scheduling method leads to high processor power consumption and seriously affects the performance of the processor. Summary of the Invention

[0006] In view of this, the present invention proposes a pseudo-out-of-order instruction scheduling method based on branch jumps. By conditionally pausing branch instructions, the cost of branch prediction errors caused by out-of-order execution is avoided, and the power consumption of the processor is significantly reduced, so as to solve the technical defects of the existing branch instruction scheduling method that is unreasonable and leads to poor processor performance.

[0007] In a first aspect, the present invention provides a pseudo-out-of-order instruction scheduling method based on branch jumps, which is applied to a dispatch and issue unit in a superscalar processor, the method comprising:

[0008] If the currently received instruction is a branch instruction, the current branch instruction is dispatched to the branch instruction issuance queue;

[0009] Based on instruction prediction analysis, determine whether the current branch instruction needs to be speculated and woken up in advance;

[0010] If it is determined that the current branch instruction needs to be speculatively awakened, determining whether the oldest branch instruction in the branch instruction issue queue can be awakened within two clock cycles;

[0011] If it is determined that the oldest branch instruction in the branch instruction issuance queue cannot be awakened within two clock cycles, the operation of issuing other instructions in the branch instruction issuance queue and the non-branch instruction issuance queue that follow the oldest branch instruction to the execution unit is suspended, so that other instructions in the branch instruction issuance queue and the non-branch instruction issuance queue that follow the oldest branch instruction cannot be issued to the execution unit.

[0012] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jumps, after suspending the operation of issuing other instructions in the branch instruction issue queue and the non-branch instruction issue queue that follow the oldest branch instruction to the execution unit, the method further includes:

[0013] After the oldest branch instruction is awakened, the oldest branch instruction is transmitted to the execution unit, and other instructions in the branch instruction transmission queue and the non-branch instruction transmission queue that are arranged after the oldest branch instruction can be scheduled and transmitted to the execution unit after being awakened.

[0014] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jump, after determining whether the oldest branch instruction in the branch instruction issue queue can be awakened within two clock cycles, the method further includes:

[0015] If it is determined that the oldest branch instruction can be awakened within two clock cycles, the oldest branch instruction is transmitted to the execution unit, and instructions in other queues in the awakened state can be scheduled and transmitted to the execution unit.

[0016] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jump, after determining whether the current branch instruction needs to be speculated and awakened based on instruction prediction analysis, thereby awakening the current branch instruction in advance, the method further includes:

[0017] If it is determined that there is no need to speculate and wake up the current branch instruction, the current branch instruction continues to be stored in the branch instruction issue queue waiting to be woken up.

[0018] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jump, the method further includes:

[0019] If the currently received instruction is not a branch instruction, dispatch the current non-branch instruction to the non-branch instruction issue queue corresponding to the instruction type;

[0020] Based on the instruction type and dependency, determine whether the current non-branch instruction needs to be speculatively awakened, thereby waking up the current non-branch instruction in advance;

[0021] If it is determined that there is no instruction in the non-branch issue instruction queue that needs to wait for wake-up for more than two clock cycles, other non-branch instructions in the non-branch issue instruction queue are issued to the execution unit.

[0022] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jump, the method further includes:

[0023] When the oldest branch instruction in the branch instruction issuance queue needs to access the operands provided by the memory instruction but has not been awakened after waiting for two clock cycles, or when other dependent instructions in the branch instruction issuance queue need to provide operands to the oldest branch instruction and have not been awakened after waiting for two clock cycles, the operation of issuing other instructions in the branch instruction issuance queue and the non-branch instruction issuance queue that follow the oldest branch instruction to the execution unit is suspended.

[0024] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jump, the method further includes:

[0025] After the branch instruction is executed, if the branch prediction result is incorrect, the states of all registers awakened by the branch instruction are set to non-awakening, and the instructions awakened by the branch instruction are rewritten into the branch instruction issuance queue to achieve on-site recovery.

[0026] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jump, the method for determining whether the current branch instruction needs to be speculatively awakened based on instruction prediction analysis includes:

[0027] If the operands that the current branch instruction depends on can be prepared and completed within the speculative clock period, it is determined that the current branch instruction needs to be speculatively awakened.

[0028] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jump, the oldest branch instruction refers to the branch instruction in the branch instruction issuance queue that has its operands waiting to be prepared the earliest.

[0029] Furthermore, in the above-mentioned pseudo-out-of-order instruction scheduling method based on branch jump, when the oldest branch instruction in the branch instruction issuance queue that needs to access the memory instruction to provide operands has not been awakened after waiting for two clock cycles, the operation of sending the instructions in the branch instruction issuance queue and the non-branch instruction issuance queue that are subsequent to the oldest branch instruction to the execution unit is suspended.

[0030] The pseudo-out-of-order instruction scheduling method based on branch jump provided by the present invention has the following beneficial effects:

[0031] The method for processing branch instructions of the present invention is to suspend the issuance of other instructions in the branch instruction issuance queue and other instruction issuance queues that are arranged after the current oldest branch instruction when it can be speculated that the current branch instruction can be awakened and the current oldest branch instruction cannot be awakened within two clock cycles, so as to avoid executing uncertain branches in advance, thereby converting the complete out-of-order execution of branch instructions into pseudo-out-of-order execution, and avoiding the cost of branch prediction errors caused by out-of-order execution by conditionally pausing branch instructions.

[0032] The present invention provides a branch-based pseudo-out-of-order instruction scheduling method that can reduce power consumption. By dynamically scheduling instructions following a branch instruction based on the readiness of the branch instruction, this method effectively avoids wasted execution by the execution unit, thereby reducing processor power consumption. By analyzing the order-preserving function of instruction execution in current processors, the present invention proposes a special scheduling mode for branch instructions. Based on this, the fully out-of-order execution of branch instructions is replaced with a pseudo-out-of-order execution mode for branch instructions. This ensures that subsequent execution units do not waste work in the event of prediction errors, saving power and improving stability.

[0033] The pseudo-out-of-order instruction scheduling method based on branch jump provided by the present invention reduces unnecessary register read and write access operations and operation unit flip operations, reduces the power consumption of the processor, and also reduces the logical complexity of branch prediction failure recovery, thereby improving the timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are only used to further understand the embodiments of the present invention and constitute part of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0035] Figure 1 It is a common structure of existing superscalar processors;

[0036] Figure 2 A schematic diagram of the internal structure of a dispatch and issue unit in a superscalar processor provided by an embodiment of the present invention, which also shows a rename register and an execution unit;

[0037] Figure 3 A flow chart of a pseudo-out-of-order instruction scheduling method based on branch jumps provided by an embodiment of the present invention;

[0038] Figure 4 A flow chart of another pseudo-out-of-order instruction scheduling method based on branch jumps provided by an embodiment of the present invention;

[0039] Figure 5 A scheduling flow chart when a TLB Miss causes a branch instruction to fail to wake up according to an embodiment of the present invention;

[0040] Figure 6 A flowchart of the pipeline processing when branch prediction fails provided by an embodiment of the present invention;

[0041] Figure 7 A schematic diagram of the structure of a superscalar processor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The technical solution provided by the present invention is further described below with reference to the accompanying drawings and examples. It should be understood that the system structure and business scenarios provided in the embodiments of the present invention are mainly for illustrating possible implementation methods of the technical solution of the present invention and should not be interpreted as the sole limitation of the technical solution of the present invention. It is known to those skilled in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by the present invention is also applicable to similar technical problems.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. In the event of any inconsistency, the meanings herein described or derived from the contents described herein shall prevail. In addition, the terms used herein are for the purpose of describing the embodiments of the present invention only and are not intended to limit the present invention.

[0044] The embodiment of the present invention provides a pseudo-out-of-order instruction scheduling method based on branch jump, which is applied to the dispatch and emission unit in a superscalar processor. Figure 2 As shown, an embodiment of the present invention provides a schematic diagram of the internal structure of a dispatch and emission unit in a superscalar processor. Figure 2 As shown, the dispatch and issue unit obtains instructions from the rename register (Rename) and then distributes them to the corresponding issue queue (IQ) based on the instruction type. This queue stores instructions to be issued to the execution units (EUs) for execution. These instructions need to wait for their source operands before issuing. The issue queues include the Branch Issue Queue (Br IQ) for handling branches, the Load / Store Issue Queue (LS IQ) for handling branches, the Arithmetic Instruction Issue Queue (ALU IQ) for handling integer operations such as addition, subtraction, shifts, and logical operations, and the Specialized Instruction Issue Queue (SPEC IQ) for handling floating-point operations such as division and multiplication. In a pipelined processor, instructions are executed in multiple stages, such as instruction fetch, decode, execute, memory access, and writeback. Branch instructions determine the program's control flow during the execution phase, potentially changing the order of program execution.

[0045] like Figure 3 As shown, an embodiment of the present invention provides a pseudo-out-of-order instruction scheduling method based on branch jump, including:

[0046] Step 11: If the currently received instruction is a branch instruction, dispatch the current branch instruction to a branch instruction issue queue.

[0047] Step 12: Based on instruction prediction analysis, determine whether the current branch instruction needs to be speculatively awakened, thereby waking up the current branch instruction in advance. If speculative awakening is required, execute step 131; if speculative awakening is not required, execute step 132.

[0048] In order to increase the chances of concurrent execution of instructions, reduce stalls caused by waiting for data, and keep the pipeline running at full load as much as possible, thereby improving processor performance, before the branch instruction is executed, it can be assumed that the branch instructions that meet the conditions get operands, and these branch instructions can be awakened in advance, that is, the status of these branch instructions is set to ready.

[0049] Determine whether the current branch instruction can be speculatively awakened. This involves speculating whether the operands on which the branch instruction depends can be ready within the speculation cycle, such as within two clock cycles. The operands are the results of other instructions. For example, consider two instructions: the addition instruction add(x1, x2, x3) and the conditional jump instruction bne(x1, x2, label). The conditional jump instruction is a branch instruction that uses the result of the addition instruction. It is predicted that the result of the addition instruction can be calculated within a single clock cycle, so the branch of the conditional jump instruction can be speculatively awakened. If the current branch instruction can be ready within the speculation cycle, it is awakened in advance and can be issued to the execution unit for execution. If it cannot be completed within the speculation cycle, the current branch instruction waits in the branch instruction issue queue until it is ready before being awakened.

[0050] Specifically, in an embodiment of the present invention, a method for determining whether a branch instruction can be speculatively awakened is to determine whether an operand on which the branch instruction depends can be prepared within a speculative clock period, such as within two clock cycles.

[0051] Step 131: If it is determined that the current branch instruction needs to be speculatively awakened, determine whether the oldest branch instruction in the branch instruction issue queue can be awakened within two clock cycles. If the oldest branch instruction cannot be awakened within two clock cycles, execute step 141; if the oldest branch instruction can be awakened within two clock cycles, execute step 142.

[0052] In an embodiment of the present invention, the oldest branch instruction generally refers to the branch instruction that is waiting for the execution results of other instructions in the branch instruction issue queue and has a dependency relationship with other instructions, and such dependent instructions have a long execution time. In other words, it is the branch instruction in the branch instruction issue queue that is waiting for its operand to be ready the earliest. The oldest branch instruction is ready after waiting for two clock cycles in the issue queue, that is, the oldest branch instruction is awakened. The oldest branch instruction is still not ready after waiting for two clock cycles in the issue queue, that is, the oldest branch instruction has not been awakened.

[0053] Step 132: If it is determined that the current branch instruction does not need to be speculatively awakened, the current branch instruction waits in the branch instruction issue queue to be awakened.

[0054] Step 141: If it is determined that the oldest branch instruction cannot be awakened within two clock cycles, suspend the operation of transmitting other instructions in the branch instruction transmission queue and the non-branch instruction transmission queue that follow the oldest branch instruction to the execution unit, so that other instructions in the branch instruction transmission queue and the non-branch instruction transmission queue that follow the oldest branch instruction cannot be transmitted to the execution unit.

[0055] The instructions suspended from being issued to the execution unit include not only branch instructions in the branch instruction issuance queue, but also instructions in the non-branch instruction issuance queue, that is, instructions in other instruction issuance queues, such as load and store instruction issuance queue, operation instruction issuance queue or special instruction issuance queue.

[0056] Step 142: If it is determined that the oldest branch instruction can be awakened within two clock cycles, the oldest branch instruction is sent to the execution unit, and all instructions in the awakened state can be normally scheduled and sent to the execution unit.

[0057] The oldest branch instruction is the earliest branch instruction in the current branch instruction issuance queue that is waiting for its operand to be ready. The oldest branch instruction is waiting for two clock cycles in the current branch instruction issuance queue and is still waiting for the calculation result of its dependent instruction, indicating that the dependent instruction is still in an uncertain state during its execution phase, which will also affect the prediction of the branch result. It is uncertain whether it is correct. If its subsequent instructions are sent to the execution unit for early execution, it may be possible to execute invalid instructions. Therefore, the issuance of other instructions that follow the oldest branch instruction in the branch instruction issuance queue and the non-branch instruction issuance queue to the execution unit is suspended, thereby avoiding the execution of potentially invalid instructions and reducing the possibility of useless execution. All instructions after the oldest branch instruction are subsequent instructions related to the branch result of the oldest branch instruction, and these instructions have been speculated and awakened in advance.

[0058] If the oldest branch instruction is ready to be awakened within two clock cycles, it indicates that the operands it depends on have been obtained, and the scheduling and execution of the subsequent instructions of the oldest branch instruction are certain, and executing the subsequent instructions of the oldest branch instruction will not cause invalid execution.

[0059] After pausing the issuance of all instructions following the oldest branch instruction in the branch instruction issuance queue and the non-branch instruction issuance queue to the execution unit, it is discovered that the oldest branch instruction is ready and in a wake-up state. This indicates that the oldest branch instruction has obtained its dependent operands, and the scheduling and execution of subsequent instructions of the oldest branch instruction are certain (will not jump to special situations such as exceptions). Executing subsequent instructions of the oldest branch instruction will not cause invalid execution. Therefore, after pausing the issuance of all instructions following the oldest branch instruction in the branch instruction issuance queue and the non-branch instruction issuance queue to the execution unit, after the oldest branch instruction is awakened, the oldest branch instruction is issued to the execution unit, and all instructions following the oldest branch instruction in the branch instruction issuance queue and the non-branch instruction issuance queue can be scheduled and issued to the execution unit after being awakened, thereby allowing all instructions following the oldest branch instruction to be executed in the execution unit.

[0060] In the prior art, due to the complete out-of-order execution of instructions, multiple computing components experience invalid operations. Furthermore, as the number of execution components increases, the number of various instruction channels grows, leading to a rapid increase in the number of components in the processor back-end design. This waste of power becomes even more pronounced. The embodiments of the present invention utilize the characteristics of branch instructions to conditionally pause branch instructions, avoiding the cost of branch prediction errors caused by out-of-order execution. This significantly reduces processor power consumption, addresses the technical defect of existing branch instruction scheduling methods that lead to poor processor performance due to irrational scheduling, and effectively schedules the operations of the entire execution component, resulting in significant results in overall power consumption optimization.

[0061] Figure 4 The present invention provides another flow chart of a pseudo out-of-order instruction scheduling method based on branch jump. Figure 4 As shown, the instruction goes from the start stage to the dispatch stage, and determines whether the instruction is a branch instruction. If it is, it is sent to the branch instruction issuance queue. Otherwise, the current instruction is distributed to other instruction issuance queues corresponding to the instruction type, such as the load and store instruction issuance queue, the operation instruction issuance queue or the special instruction issuance queue.

[0062] If the currently received instruction is not a branch instruction, the current non-branch instruction is dispatched to the non-branch instruction issuance queue corresponding to the instruction type. Then, based on the instruction type and dependency relationship, it is determined whether the non-branch instruction needs to be speculatively awakened, thereby waking up the non-branch instruction in advance. If it is determined that there are no instructions in the non-branch instruction issuance queue that need to wait for more than two clock cycles to be awakened, that is, the instructions in the non-branch instruction issuance queue can be awakened within two clock cycles, then the other non-branch instructions in the non-branch instruction issuance queue are issued to the execution unit.

[0063] Non-branch instructions are handled as follows: Based on the instruction's ready state, they are directly sent to the corresponding execution unit. If they are not ready, a predictive analysis is performed on the instruction based on its type and dependencies to determine whether it needs to be speculatively woken up. Specifically, if the instruction's execution cycle is known, or if the non-branch instruction is a memory access instruction, it is determined that the instruction needs to be woken up in advance.

[0064] If it is determined that the instructions in the non-branch instruction issue queue can be awakened within two clock cycles, all other non-branch instructions in the non-branch instruction issue queue are issued to the execution unit for execution. If it is determined that the instruction cannot be speculated and awakened, the instruction continues to wait in the instruction issue queue to be awakened.

[0065] The branch instructions in the branch instruction issue queue are processed as follows:

[0066] Determine whether the current branch instruction requires speculative wakeup. If not, the branch instruction remains in the instruction issue queue awaiting wakeup. Speculative wakeup occurs when an operand required by the instruction is the result of another instruction being executed. Determine whether the execution time of the other instruction exceeds two clock cycles (common integer operations are one clock cycle). If so, the instruction is considered speculatively awakenable. If speculative wakeup is required, determine whether the oldest branch instruction in the current instruction issue queue can be awakened within two clock cycles. If the oldest branch instruction is not ready after two clock cycles, halt the issuance of all instructions in the branch issue queue and other instruction issue queues that follow the oldest branch instruction until the oldest branch instruction is ready and awakened. At this point, the oldest branch instruction is issued to the execution unit. Simultaneously, the issuance of other instructions in the branch issue queue and other instruction issue queues that follow the oldest branch instruction is released, allowing the remaining instructions in the branch issue queue and other instruction issue queues that follow the oldest branch instruction to be scheduled for issuance to the execution unit after awakening.

[0067] If the oldest branch instruction can be awakened within two beats, the oldest branch instruction will be sent to the execution unit without affecting the issuance of all instructions after the current branch instruction. That is, the instructions in the branch instruction issuance queue and other instruction issuance queues that are in the awakened state can all be scheduled and sent to the execution unit.

[0068] The method for processing branch instructions in an embodiment of the present invention is to suspend the issuance of all instructions in the branch instruction issuance queue and other instruction issuance queues that are arranged after the current oldest branch instruction when the current branch instruction can be presumably awakened but the current oldest branch instruction cannot be awakened within two beats, so as to avoid executing uncertain branches in advance, thereby converting the complete out-of-order execution of branch instructions into pseudo-out-of-order execution, and reducing the cost of branch prediction errors caused by out-of-order execution by conditionally pausing branch instructions.

[0069] The scheduling method provided by the embodiment of the present invention can be applied to various scenarios, such as Figure 5 The TLB Miss scenario shown and Figure 6 The scenario shown occurs when a branch prediction fails.

[0070] Figure 5The scenario shown involves memory access. When the processor attempts to access memory, it first checks the Translation Lookaside Buffer (TLB) to determine whether the virtual address has been translated into a physical address. If a matching mapping is found in the TLB, a TLB hit occurs, and the memory access can be performed directly using that physical address. If no match is found, a TLB miss occurs, and the page table entry must be read from memory into the TLB to complete the address translation.

[0071] When a branch instruction is dispatched to the branch instruction issuance queue and enters the awake state in advance after a speculative awakening judgment, if the instruction before the oldest branch instruction in the branch instruction issuance queue is a memory access instruction, that is, the instruction that feeds back the operand for the oldest branch instruction, a TLB Miss occurs during memory access, which will cause the operand of the oldest branch instruction to be not ready within more than two clock cycles. This is because when a TLB Miss occurs, the page table entry needs to be read from the memory into the translation lookaside buffer, and reading memory is a relatively time-consuming process. Therefore, in order to avoid useless work on the pipeline when a TLB Miss occurs, the oldest branch instruction in the branch instruction issuance queue that requires the memory access instruction to provide the operand is not ready after waiting for two clock cycles. The embodiment of the present invention suspends sending instructions in the branch instruction issuance queue and other instruction issuance queues that are arranged after the oldest branch instruction to the execution unit, thereby avoiding the execution of uncertain branch prediction instructions on the pipeline due to TLB miss, thereby generating useless work on the pipeline, reducing unnecessary register read and write access operations and operation unit flip operations, and reducing the power consumption of the processor. After pausing the sending of instructions in the branch instruction issuance queue and other instruction issuance queues that are arranged after the current oldest branch instruction to the execution unit, when it is found that a TLB Miss occurs when the instruction before the current oldest branch instruction accesses the memory, the states of all registers awakened by the instruction before the current oldest branch instruction, i.e., the memory access instruction, are set to non-awakening, and the instruction awakened by the memory access instruction is rewritten into the branch instruction issuance queue to achieve on-site recovery, and then it will be re-entered into the branch instruction issuance queue to wait for its operand to be ready.

[0072] Figure 6 The scenario shown is the processing flow when branch prediction fails. Figure 6As shown, after a branch instruction completes execution, if the branch prediction result is incorrect (i.e., a non-jump is predicted but a jump is actually required, or a jump is predicted but not actually jumped), all registers awakened by the branch instruction must be reset to the non-awakened state, and the instructions awakened by the branch instruction must be rewritten to the branch instruction issue queue to achieve on-site recovery in the event of a branch prediction failure. If the instruction preceding the oldest branch instruction in the branch instruction issue queue is a branch instruction, meaning multiple branch instructions are awakened simultaneously, the validity of the entire instruction can be quickly controlled because the final branch result can be calculated within three clock cycles. However, if the oldest branch instruction waits two clock cycles without being ready to be awakened, the branch result of the instructions preceding the oldest branch instruction is still undetermined and these instructions may be invalid. However, the instructions following the oldest branch instruction have been awakened in advance and, if issued to the execution unit for execution, may be ineffective. In this case, an embodiment of the present invention suspends sending instructions that are arranged after the oldest branch instruction in the branch instruction issuance queue and other instruction issuance queues to the execution unit, avoiding the execution of instructions after the branch instruction, that is, executing invalid instructions, thereby reducing the power consumption of the processor and reducing the logical complexity of branch prediction failure recovery, thereby improving the timing.

[0073] like Figure 7 As shown, the present invention further provides a superscalar processor, which includes a dispatch unit 701 and an emission unit 702 .

[0074] The dispatch unit 701 is used to dispatch the current branch instruction to the branch instruction issuance queue when the current instruction to be distributed is a branch instruction; based on instruction prediction analysis, determine whether the current branch instruction needs to be speculated and awakened, thereby waking up the current branch instruction in advance; if it is determined that the current branch instruction needs to be speculated and awakened, determine whether the oldest branch instruction in the branch instruction issuance queue can be awakened within two clock cycles.

[0075] The emission unit 702 is used to suspend the operation of transmitting other instructions that follow the oldest branch instruction in the branch instruction emission queue and the non-branch instruction emission queue to the execution unit when the dispatch unit 701 determines that the oldest branch instruction cannot be awakened within two clock cycles, so that all instructions that follow the oldest branch instruction in the branch instruction emission queue and the non-branch instruction emission queue cannot be transmitted to the execution unit.

[0076] Furthermore, the emission unit 702 is used to emit the oldest branch instruction to the execution unit after the oldest branch instruction is awakened, and to enable all instructions in the branch instruction emission queue and the non-branch instruction emission queue that follow the oldest branch instruction to be scheduled and emitted to the execution unit after being awakened.

[0077] Furthermore, the emission unit 702 is configured to emit the oldest branch instruction to the execution unit when the dispatch unit 701 determines that the oldest branch instruction can be awakened within two clock cycles, and instructions in the awakened state can be scheduled to be emitted to the execution unit at the same time.

[0078] Furthermore, the dispatch unit 701 is configured to, when determining that the current branch instruction does not need to be speculatively awakened, continue to store the current branch instruction in the branch instruction issue queue to wait for awakening.

[0079] Furthermore, the dispatch unit 701 is used to dispatch the current non-branch instruction to the non-branch instruction emission queue corresponding to the instruction type when the currently received instruction is not a branch instruction; based on the instruction type and dependency relationship, it is determined whether the non-branch instruction needs to be speculated and awakened in advance.

[0080] Furthermore, the issuing unit 702 is configured to issue the non-branch instruction to the execution unit if it is determined that there is no instruction in the non-branch instruction issue queue that needs to wait for wake-up for more than two clock cycles.

[0081] Furthermore, the dispatch unit 701 is used to suspend the operation of issuing other instructions that follow the oldest branch instruction in the branch instruction issuance queue and the non-branch instruction issuance queue to the execution unit when the oldest branch instruction in the branch instruction issuance queue needs to access the operands provided by the memory instruction but has not been awakened after waiting for two clock cycles, or when other dependent instructions in the branch instruction issuance queue need to provide operands to the oldest branch instruction and have also not been awakened after waiting for two clock cycles.

[0082] Furthermore, the superscalar processor also includes a recovery unit, which is used to set the status of all registers awakened by the branch instruction to non-awakening when it is determined that the branch prediction result is incorrect after the branch instruction is executed, and rewrite the instructions awakened by the branch instruction into the branch instruction issuance queue to achieve on-site recovery.

[0083] Furthermore, the dispatch unit 701 is configured to determine that the current branch instruction needs to be speculatively awakened when it is determined that operands of the current branch instruction that are dependent on the current branch instruction can be prepared within the speculative clock period.

[0084] Furthermore, the emission unit 702 is used to suspend the operation of sending instructions in the branch instruction emission queue and other instruction emission queues that are subsequent to the current oldest branch instruction to the execution unit when the current oldest branch instruction in the branch instruction emission queue that needs to access the memory instruction to provide operands has not been awakened after waiting for two clock cycles.

[0085] It should be noted that the embodiments described in the present invention are only some of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention generally described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of the present invention.

[0086] The words "first, second, third, etc." or module A, module B, module C and the like in the specification and claims are used only to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that the specific order or sequence can be interchanged where permitted so that the embodiments of the invention described herein can be implemented in an order other than that illustrated or described herein.

[0087] In the above description, the numbers representing the steps involved do not necessarily mean that the steps must be executed. Intermediate steps may also be included or replaced by other steps. If permitted, the order of the previous and next steps may be interchanged or executed simultaneously.

[0088] The term "comprising" as used in the specification and claims should not be construed as limiting to what is listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the features, integers, steps, or components mentioned, but not excluding the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the expression "a device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0089] The reference to "one embodiment" or "an embodiment" in this specification means that the specific features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in the various embodiments of the present invention, unless otherwise specified or there is a logical conflict, the terms and / or descriptions of different embodiments are consistent and can be referenced to each other. The technical features of different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0090] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A pseudo-out-of-order instruction scheduling method based on branch jump, characterized in that: Applied to a dispatch and issue unit in a superscalar processor, the method comprises: If the currently received instruction is a branch instruction, the current branch instruction is dispatched to the branch instruction issuance queue; Based on instruction prediction analysis, determine whether the current branch instruction needs to be speculated and woken up in advance; If it is determined that the current branch instruction needs to be speculatively awakened, determining whether the oldest branch instruction in the branch instruction issue queue can be awakened within two clock cycles; If it is determined that the oldest branch instruction in the branch instruction issue queue cannot be awakened within two clock cycles, suspending the operation of issuing other instructions in the branch instruction issue queue and the non-branch instruction issue queue that follow the oldest branch instruction to the execution unit, so that other instructions in the branch instruction issue queue and the non-branch instruction issue queue that follow the oldest branch instruction cannot be issued to the execution unit; Based on instruction prediction analysis, the method for determining whether the current branch instruction needs to be speculated and woken up includes: If the operands that the current branch instruction depends on can be prepared and completed within the speculation clock period, it is determined that the current branch instruction needs to be speculated and woken up; The oldest branch instruction refers to the branch instruction in the branch instruction issuance queue that has its operands ready the earliest; All instructions following the oldest branch instruction are subsequent instructions related to the branch result of the oldest branch instruction, and these instructions have been speculated to wake up in advance; After suspending the operation of issuing other instructions in the branch instruction issue queue and the non-branch instruction issue queue that follow the oldest branch instruction to the execution unit, the method further includes: After the oldest branch instruction is awakened, the oldest branch instruction is emitted to the execution unit, and other instructions in the branch instruction emission queue and the non-branch instruction emission queue that are arranged after the oldest branch instruction can be scheduled and emitted to the execution unit after being awakened; The method further comprises: After the branch instruction is executed, if the branch prediction result is incorrect, the states of all registers awakened by the branch instruction are set to non-awakening, and the instructions awakened by the branch instruction are rewritten into the branch instruction issuance queue to achieve on-site recovery.

2. The pseudo-out-of-order instruction scheduling method based on branch jump according to claim 1, characterized in that: After determining whether the oldest branch instruction in the branch instruction issue queue can be awakened within two clock cycles, the method further includes: If it is determined that the oldest branch instruction can be awakened within two clock cycles, the oldest branch instruction is transmitted to the execution unit, and instructions in other queues in the awakened state can be scheduled and transmitted to the execution unit.

3. The pseudo-out-of-order instruction scheduling method based on branch jump according to claim 1, characterized in that: Based on instruction prediction analysis, it is determined whether the current branch instruction needs to be speculated and woken up in advance, and the following steps are also included: If it is determined that there is no need to speculate and wake up the current branch instruction, the current branch instruction continues to be stored in the branch instruction issue queue waiting to be woken up.

4. The pseudo-out-of-order instruction scheduling method based on branch jump according to claim 1, characterized in that: The method further comprises: If the currently received instruction is not a branch instruction, dispatch the current non-branch instruction to the non-branch instruction issue queue corresponding to the instruction type; Based on the instruction type and dependency, determine whether the current non-branch instruction needs to be speculatively awakened, thereby waking up the current non-branch instruction in advance; If it is determined that there is no instruction in the non-branch issue instruction queue that needs to wait for wake-up for more than two clock cycles, other non-branch instructions in the non-branch issue instruction queue are issued to the execution unit.

5. The pseudo-out-of-order instruction scheduling method based on branch jump according to claim 1, characterized in that: The method further comprises: When the oldest branch instruction in the branch instruction issuance queue needs to access the operands provided by the memory instruction but has not been awakened after waiting for two clock cycles, or when other dependent instructions in the branch instruction issuance queue need to provide operands to the oldest branch instruction and have not been awakened after waiting for two clock cycles, the operation of issuing other instructions in the branch instruction issuance queue and the non-branch instruction issuance queue that follow the oldest branch instruction to the execution unit is suspended.

6. The pseudo-out-of-order instruction scheduling method based on branch jump according to any one of claims 1 to 5, characterized in that: When the oldest branch instruction in the branch instruction issuance queue that needs to access the memory instruction to provide operands has not been awakened after waiting for two clock cycles, the operation of sending the instructions in the branch instruction issuance queue and the non-branch instruction issuance queue that are subsequent to the oldest branch instruction to the execution unit is suspended.

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