Chip starting method and device, equipment, storage medium and computer program product

Abstract

The invention relates to a chip starting method and device, equipment, a storage medium and a computer program product. The method comprises the following steps: in response to detecting that the data receiving module receives serial data sent by an upper computer, the data receiving module preprocesses the serial data to obtain processed data; the data receiving module stores the processed data into the static random access memory unit and executes cyclic redundancy check at the same time; and in response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip starting signal to the micro-processing unit, so that the micro-processing unit starts a chip according to the chip starting signal. By adopting the method, the transmission efficiency can be improved, and the chip starting time is shortened.

Description

Technical Field

[0001] This application relates to the technical field of chip data communication, and in particular, to a chip startup method, device, equipment, storage medium, and computer program product. Background Art

[0002] Currently, some chips are based on SRAM (Static Random-Access Memory) programming technology. After power-off, the program information is lost. When the chip is powered on each time, the external circuit needs to download the configuration data to the SRAM inside the chip again. After completing the corresponding configuration process, the chip can work properly according to the user's design.

[0003] Currently, in the configuration mode, some chips burn the program (such as the startup code of the logic block and the microprocessor) into the EPCS (Erasable programmable configurable serial). The microprocessor in the chip cannot directly execute the program from the EPCS. It actually executes the program stored in the internal memory of the EPCS controller and transfers the program stored in the internal memory of the EPCS to the SRAM for execution.

[0004] However, the current chip startup method depends on the EPCS as the data transmission medium, which is not applicable in the case of chip volume and application scenario limitations; in addition, as the data transmission medium, the EPCS has a larger area, higher cost, and slower read and write speed, resulting in a longer chip startup time. Summary of the Invention

[0005] Based on this, it is necessary to provide a chip startup method, device, equipment, storage medium, and computer program product that can improve the transmission efficiency, shorten the chip startup time, and have strong compatibility for the above technical problems.

[0006] In a first aspect, this application provides a chip startup method, which is applied to a chip to be started. The chip to be started includes a data receiving module, a static random access storage unit, and a microprocessing unit. The method includes:

[0007] In response to detecting that the data receiving module receives serial data sent by the host computer, the data receiving module preprocesses the serial data to obtain processed data;

[0008] The data receiving module stores the processed data in the static random access storage unit and simultaneously performs cyclic redundancy check;

[0009] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit, so that the microprocessing unit starts the chip according to the chip startup signal.

[0010] In one embodiment, the host computer is a field programmable gate array, and the serial data includes a serial timing pre-agreed with the field programmable gate array in a preset configuration mode.

[0011] In one embodiment, the preset configuration mode includes a passive serial mode.

[0012] In one embodiment, the serial data includes at least one data segment, the data segment includes a frame header, and the frame header includes the agreed data volume of the current data segment.

[0013] In response to detecting that the data receiving module receives the serial data sent by the host computer, the data receiving module performs preprocessing on the serial data to obtain processed data, including:

[0014] After detecting that the serial data received by the data receiving module from the host computer meets the agreed data volume, the data receiving module performs splicing and restoration processing on the serial data to obtain processed data in a specified data format, and the specified data format includes a data format preset for recognition by the microprocessing unit.

[0015] The data receiving module stores the processed data in the static random access memory unit and simultaneously performs cyclic redundancy check, including:

[0016] The data receiving module stores the processed data in the static random access memory unit and simultaneously receives a cyclic redundancy check code, and the data receiving module performs a cyclic redundancy check comparison according to the cyclic redundancy check code.

[0017] In one embodiment, the chip to be started further includes a state machine, and the method further includes:

[0018] The data receiving module sets the state machine to an initial state;

[0019] In response to the state machine receiving the handshake signal sent by the host computer, the state machine performs a handshake interaction with the host computer.

[0020] In response to detecting that the handshake interaction is successful, the data receiving module starts to receive the serial data sent by the host computer and sets the state machine to a data receiving state.

[0021] In one embodiment, the method further includes:

[0022] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit and resets the state machine to its initial state;

[0023] In response to detecting that the cyclic redundancy check comparison fails, the data receiving module returns an error signal to the host computer and resets the state machine to its initial state.

[0024] In a second aspect, the present application also provides a chip startup device, and the device includes:

[0025] A transmission module, configured to, in response to detecting that the data receiving module receives serial data sent by a host computer, the data receiving module performs preprocessing on the serial data to obtain processed data;

[0026] A verification module, configured to the data receiving module stores the processed data in a static random access memory unit and simultaneously performs a cyclic redundancy check;

[0027] A startup module, configured to, in response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit, so that the microprocessing unit starts the chip according to the chip startup signal.

[0028] In a third aspect, the present application also provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0029] In response to detecting that the data receiving module receives serial data sent by a host computer, the data receiving module performs preprocessing on the serial data to obtain processed data;

[0030] The data receiving module stores the processed data in the static random access memory unit and simultaneously performs a cyclic redundancy check;

[0031] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit, so that the microprocessing unit starts the chip according to the chip startup signal.

[0032] In a fourth aspect, the present application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, and when the computer program is executed by a processor, the following steps are implemented:

[0033] In response to detecting that the data receiving module receives serial data sent by a host computer, the data receiving module performs preprocessing on the serial data to obtain processed data;

[0034] The data receiving module stores the processed data into the static random access memory unit and simultaneously performs cyclic redundancy check;

[0035] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit, so that the microprocessing unit starts the chip according to the chip startup signal.

[0036] In a fifth aspect, the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0037] In response to detecting that the data receiving module receives the serial data sent by the host computer, the data receiving module preprocesses the serial data to obtain processed data;

[0038] The data receiving module stores the processed data into the static random access memory unit and simultaneously performs cyclic redundancy check;

[0039] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit, so that the microprocessing unit starts the chip according to the chip startup signal.

[0040] The embodiments of the present application have the following beneficial effects:

[0041] The chip startup method, device, equipment, storage medium and computer program product provided by the embodiments of the present application can eliminate the need for a serial memory as a data transmission medium, the transmission method is simpler, and at the same time, the chip design area is reduced, thereby reducing the chip design cost; in addition, when receiving serial data, performing splicing and restoration on the data and writing it into SRAM while performing cyclic redundancy check can improve the data transmission efficiency, thereby shortening the chip startup time. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic flowchart of a chip startup method in an embodiment;

[0043] Figure 2 It is a schematic diagram of data interaction between a field programmable gate array and a chip to be started in an embodiment;

[0044] Figure 3 It is a schematic flowchart of a chip startup method in another embodiment;

[0045] Figure 4 It is a structural block diagram of a chip startup device in an embodiment. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] Embodiment 1

[0048] The present application provides a method for starting a chip, which is applied to a chip to be started. The chip to be started includes a data receiving module, a static random access memory unit, and a microprocessing unit. Referring to Figure 1 , the method includes:

[0049] S1. In response to detecting that the data receiving module receives serial data sent by the host computer, the data receiving module performs preprocessing on the serial data to obtain processed data;

[0050] S2. The data receiving module stores the processed data in the static random access memory unit and simultaneously performs a cyclic redundancy check;

[0051] S3. In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip start signal to the microprocessing unit so that the microprocessing unit starts the chip according to the chip start signal.

[0052] Specifically, the configuration modes of the chip to be started include the following: AS (Active serial), AP (Active parallel), PS (Passive serial), and JTAG (Joint Test Action Group). The host computer may include chips such as CPLD (Complex Programmable Logic Device) or FPGA (Field-Programmable Gate Array). A data sending module is provided in the host computer. The host computer converts the startup code of the RISC (Reduced Instruction Set Computer), that is, the above-mentioned microprocessing unit, and the CRC (Cyclic Redundancy Check) code into serial data agreed with the data receiving module of the chip to be started by calling the data sending module. The data receiving module of the chip to be started receives the serial data, performs preprocessing on the serial data, restores the data to a data format recognizable by the RISC microprocessing unit and stores it in the SRAM (Static Random Access Memory) unit, and at the same time performs cyclic redundancy check. When the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to notify the RISC microprocessing unit to read instructions from the SRAM to start the chip to be started. By adopting such a method, there is no need for a serial memory as a data transmission medium, the transmission method is simpler, and at the same time, the chip design area is reduced, thereby reducing the chip design cost; in addition, when receiving serial data, performing splicing and restoration of the data and writing it into the SRAM while performing cyclic redundancy check can improve the data transmission efficiency, thereby shortening the chip startup time.

[0053] In some embodiments, the host computer is a field-programmable gate array, and the serial data includes a serial timing pre-agreed with the field-programmable gate array in a preset configuration mode.

[0054] Specifically, refer to Figure 2, when the host computer is an FPGA, since the FPGA chip requires an EPCS as a data transmission medium during the traditional configuration process, the chip design area is large and the chip design cost is higher. Moreover, the internal of the EPCS uses a serial flash memory as the storage medium, and the read and write speed is slow. When the host computer is an FPGA, a data sending module is set in the host computer FPGA. The FPGA converts the startup code and CRC check code of the microprocessing unit into a serial timing pre-agreed with the chip to be started in the preset configuration mode by calling the data sending module. The data receiving module of the chip to be started receives the serial data, performs preprocessing on the serial data, restores the data to a data format recognizable by the RISC microprocessing unit and stores it in the SRAM static random access memory unit, and at the same time performs cyclic redundancy check. When the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to notify the RISC microprocessing unit to read the instruction from the SRAM to start the chip to be started. The data sending module of the FPGA chip and the data receiving module of the chip to be started can be used as the external interfaces of the corresponding chips respectively. In this embodiment, the configured data stream is transmitted from the external interface to the SRAM and then to the microprocessing unit. Compared with the traditional configuration data stream transmitted from the external interface to the flash memory in the EPCS and then to the RISC microprocessing unit and then to the SRAM, the data transmission process is simplified and the data transmission efficiency is improved. Moreover, by using the data sending module of the FPGA chip and the data receiving module of the chip to be started as the external interfaces of the corresponding chips respectively, it has strong compatibility and can be compatible with most FPGA chips, solving the problem that different FPGA products use private transmission protocols and the interfaces are incompatible with each other. By adopting such a method, for the FPGA application scenario, there is no need to use a serial memory as the data transmission medium, the transmission method is simpler, the chip design area is reduced, and thus the chip design cost is reduced; and because the flash memory is not used as the storage medium, but the data is spliced and restored and written into the SRAM while performing cyclic redundancy check, the data transmission efficiency can be greatly improved, and thus the chip startup time is shortened.

[0055] In some embodiments, the preset configuration mode includes a passive serial mode.

[0056] Specifically, take the passive serial mode, i.e., the PS mode, in the preset configuration mode of the FPGA chip as an example. In the traditional FPGA in the passive serial mode, the logic block and the RISC startup code are burned into the EPCS through tools. Since the RISC microprocessing unit in the FPGA cannot directly execute the program from the EPCS, the chip actually executes the program in the EPCS controller, and transfers the program stored in the on-chip flash of the EPCS to the SRAM for execution. In the passive serial mode, the configuration data stream is transmitted from the external interface to the flash memory in the EPCS, then to the RISC microprocessing unit, and then to the SRAM. In this embodiment, the configuration data stream is transmitted from the external interface to the SRAM and then to the microprocessing unit. By adopting this method, the data transmission process in the passive serial mode can be simplified, thereby improving the data transmission efficiency of the FPGA chip in the passive serial mode and shortening the startup time of the chip to be started.

[0057] In some embodiments, the serial data includes at least one data segment, and the data segment includes a frame header, and the frame header includes the agreed data volume of the current data segment. Based on this, S1 includes:

[0058] S11. After detecting that the serial data received by the data receiving module from the host computer meets the agreed data volume, the data receiving module performs splicing and restoration processing on the serial data to obtain processed data in a specified data format, and the specified data format includes the data format preset for recognition by the microprocessing unit;

[0059] S2 includes:

[0060] S21. The data receiving module stores the processed data in the static random access storage unit and simultaneously receives the cyclic redundancy check code, and the data receiving module performs cyclic redundancy check comparison according to the cyclic redundancy check code.

[0061] Specifically, the serial data includes one or more data segments. Each data segment includes a frame header, valid data, and a frame tail. Among them, the frame header includes the agreed data volume of the current data segment. The received data volume to be satisfied is determined by the agreed data volume of the current data segment in the frame header. After the serial data sent by the host computer received by the data receiving module meets the agreed data volume, the data receiving module performs splicing and restoration processing on the serial data to obtain processed data in a specified data format. The data receiving module stores the processed data in a static random access memory unit and simultaneously receives a cyclic redundancy check code. The data receiving module performs a cyclic redundancy check comparison according to the cyclic redundancy check code. Exemplarily, the data receiving module can generate a CRC check code for each frame of received data, and the CRC check code can be located between the valid data and the frame tail in each frame of data to perform the CRC check comparison. Different subsequent processes are executed according to different check comparison results. By adopting such a method, it is possible to splice and restore the data and write it into the SRAM while receiving the serial data and perform the CRC check, which can improve the chip data transmission efficiency and shorten the chip startup time. In addition, when the data receiving module is working, the priority of occupying the SRAM can be set to the highest. Only after the data transmission is confirmed can the RISC read and execute the startup program in the SRAM. By adopting such a method, transmission conflicts can be avoided, and there is no need to exclusively occupy the memory, saving chip design resources while optimizing data transmission.

[0062] In some embodiments, the chip to be started further includes a state machine, and the method further includes:

[0063] 101. The data receiving module sets the state machine to the initial state;

[0064] 102. In response to the state machine receiving the handshake signal sent by the host computer, the state machine performs a handshake interaction with the host computer;

[0065] 103. In response to detecting that the handshake interaction is successful, the data receiving module starts to receive the serial data sent by the host computer and sets the state machine to the data receiving state.

[0066] Specifically, referring to Figure 3, at the beginning, the state machine is in the initial state waiting for the handshake signal sent by the data sending module of the host computer. When the handshake is successful, the data receiving module starts to receive the serial data sent by the host computer and sets the state machine to the data receiving state. At this time, the data receiving module receives the serial data, performs splicing and restoration processing on the serial data to obtain the processed data in the specified data format. The data receiving module stores the processed data in the static random access memory unit and simultaneously receives the cyclic redundancy check code. The data receiving module performs cyclic redundancy check comparison according to the cyclic redundancy check code. By adopting such a method, the current data transmission situation of the chip to be started can be identified through the state of the state machine, and then the chip startup situation can be accurately identified.

[0067] In some embodiments, the method further includes:

[0068] 201. In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit and resets the state machine to the initial state;

[0069] 202. In response to detecting that the cyclic redundancy check comparison fails, the data receiving module returns an error signal to the host computer and resets the state machine to the initial state.

[0070] Specifically, when the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the RSIC and returns to the initial state; when the cyclic redundancy check comparison fails, the data receiving module returns an error signal to the host computer and returns to the initial state to wait for the next transmission. By adopting such a method, when an error occurs in chip data transmission, the error signal can be transmitted to the host computer through the external interface, so that an error can be reported in time, the error handling time can be reduced, and then the data transmission interval can be shortened, and the overall chip startup time can be reduced.

[0071] In this embodiment, it is possible to dispense with the serial memory as the data transmission medium, the transmission method is simpler, and at the same time, the chip design area is reduced, thereby reducing the chip design cost; in addition, when receiving serial data, performing splicing and restoration on the data and writing it into the SRAM while performing cyclic redundancy check can improve the data transmission efficiency and then shorten the chip startup time.

[0072] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown in the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0073] Embodiment 2

[0074] Based on the same inventive concept, an embodiment of the present application also provides a chip startup device for implementing the above-mentioned chip startup method. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the chip startup device provided below can refer to the limitations on the chip startup method in the above text, and will not be repeated here.

[0075] In one embodiment, as Figure 4 shown, a chip startup device is provided, and the device includes:

[0076] A transmission module, configured to respond to detecting that the data receiving module receives serial data sent by the host computer, and the data receiving module preprocesses the serial data to obtain processed data;

[0077] A verification module, configured to store the processed data into a static random access storage unit by the data receiving module and simultaneously perform a cyclic redundancy check;

[0078] A startup module, configured to respond to detecting that the cyclic redundancy check comparison is successful, and the data receiving module sends a chip startup signal to the microprocessing unit, so that the microprocessing unit starts the chip according to the chip startup signal.

[0079] Further, the host computer is a field programmable gate array, and the serial data includes a serial timing pre-agreed with the field programmable gate array in a preset configuration mode.

[0080] Further, the preset configuration mode includes a passive serial mode.

[0081] Further, the serial data includes at least one data segment, and the data segment includes a frame header, and the frame header includes the agreed data volume of the current data segment. Based on this, the transmission module is further configured to, after detecting that the data receiving module receives the serial data sent by the host computer and meets the agreed data volume, the data receiving module performs splicing and restoration processing on the serial data to obtain processed data in a specified data format, and the specified data format includes the data format preset and recognized by the microprocessing unit; the verification module is further configured to the data receiving module stores the processed data in the static random access storage unit and simultaneously receives a cyclic redundancy check code, and the data receiving module performs a cyclic redundancy check comparison according to the cyclic redundancy check code.

[0082] Further, the to-be-started chip further includes a state machine, and the device further includes a state setting module for setting the state machine to an initial state by the data receiving module; the transmission module is further configured to, in response to the state machine receiving a handshake signal sent by the host computer, the state machine performs a handshake interaction with the host computer; the transmission module is further configured to, in response to detecting that the handshake interaction is successful, the data receiving module starts to receive the serial data sent by the host computer, and the state setting module is further configured to set the state machine to a data receiving state.

[0083] Further, the startup module is further configured to, in response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit, and the state setting module is further configured to reset the state machine to the initial state; the startup module is further configured to, in response to detecting that the cyclic redundancy check comparison fails, the data receiving module returns an error signal to the host computer, and the state setting module is further configured to reset the state machine to the initial state.

[0084] Each module in the above chip startup device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or independent of the processor, or can be stored in the memory in the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to the above respective modules.

[0085] Embodiment III

[0086] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0087] In response to detecting that the data receiving module receives the serial data sent by the host computer, the data receiving module performs preprocessing on the serial data to obtain processed data;

[0088] The data receiving module stores the processed data into the static random access memory unit and simultaneously performs cyclic redundancy check;

[0089] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit, so that the microprocessing unit starts the chip according to the chip startup signal.

[0090] In one embodiment, the host computer is a field programmable gate array, and the serial data includes a serial timing pre-agreed with the field programmable gate array in a preset configuration mode.

[0091] In one embodiment, the preset configuration mode includes a passive serial mode.

[0092] In one embodiment, the serial data includes at least one data segment, the data segment includes a frame header, and the frame header includes a pre-agreed data volume of the current data segment. When the processor executes the computer program, the following steps are further implemented:

[0093] In response to detecting that the serial data received by the data receiving module from the host computer meets the pre-agreed data volume, the data receiving module performs splicing and restoration processing on the serial data to obtain processed data in a specified data format, and the specified data format includes a data format preset for recognition by the microprocessing unit;

[0094] The data receiving module stores the processed data into the static random access memory unit and simultaneously receives a cyclic redundancy check code, and the data receiving module performs a cyclic redundancy check comparison according to the cyclic redundancy check code.

[0095] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0096] The data receiving module sets the state machine to the initial state;

[0097] In response to the state machine receiving the handshake signal sent by the host computer, the state machine performs a handshake interaction with the host computer;

[0098] In response to detecting that the handshake interaction is successful, the data receiving module starts to receive the serial data sent by the host computer and sets the state machine to the data receiving state.

[0099] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0100] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit and resets the state machine to the initial state;

[0101] In response to detecting that the cyclic redundancy check comparison fails, the data receiving module returns an error signal to the host computer and resets the state machine to the initial state.

[0102] Embodiment 4

[0103] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0104] In response to detecting that the data receiving module receives serial data sent by the host computer, the data receiving module performs preprocessing on the serial data to obtain processed data;

[0105] The data receiving module stores the processed data in the static random access storage unit and simultaneously performs cyclic redundancy check;

[0106] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip start signal to the microprocessing unit so that the microprocessing unit starts the chip according to the chip start signal.

[0107] In one embodiment, the host computer is a field programmable gate array, and the serial data includes a serial timing pre-agreed with the field programmable gate array in a preset configuration mode.

[0108] In one embodiment, the preset configuration mode includes a passive serial mode.

[0109] In one embodiment, the serial data includes at least one data segment, the data segment includes a frame header, and the frame header includes the agreed data volume of the current data segment. When the computer program is executed by a processor, the following steps are further implemented:

[0110] In response to detecting that the serial data received by the data receiving module from the host computer meets the agreed data volume, the data receiving module performs splicing and restoration processing on the serial data to obtain processed data in a specified data format, and the specified data format includes a data format preset for recognition by the microprocessing unit;

[0111] The data receiving module stores the processed data in the static random access storage unit and simultaneously receives a cyclic redundancy check code, and the data receiving module performs a cyclic redundancy check comparison according to the cyclic redundancy check code.

[0112] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0113] The data receiving module sets the state machine to the initial state;

[0114] In response to the state machine receiving the handshake signal sent by the host computer, the state machine performs a handshake interaction with the host computer;

[0115] In response to detecting that the handshake interaction is successful, the data receiving module starts to receive the serial data sent by the host computer and sets the state machine to the data receiving state.

[0116] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0117] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit and resets the state machine to the initial state;

[0118] In response to detecting that the cyclic redundancy check comparison fails, the data receiving module returns an error signal to the host computer and resets the state machine to the initial state.

[0119] Embodiment Five

[0120] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0121] In response to detecting that the data receiving module receives the serial data sent by the host computer, the data receiving module performs preprocessing on the serial data to obtain processed data;

[0122] The data receiving module stores the processed data in the static random access memory unit and simultaneously performs a cyclic redundancy check;

[0123] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit so that the microprocessing unit starts the chip according to the chip startup signal.

[0124] In one embodiment, the host computer is a field programmable gate array, and the serial data includes a serial timing that is pre-agreed with the field programmable gate array in a preset configuration mode.

[0125] In one embodiment, the preset configuration mode includes a passive serial mode.

[0126] In one embodiment, the serial data includes at least one data segment, the data segment includes a frame header, and the frame header includes the agreed data volume of the current data segment. When the computer program is executed by a processor, the following steps are further implemented:

[0127] After detecting that the serial data sent by the host computer received by the data receiving module meets the agreed data volume, the data receiving module performs splicing and restoration processing on the serial data to obtain processed data in a specified data format, and the specified data format includes the data format preset and recognized by the microprocessing unit;

[0128] The data receiving module stores the processed data in the static random access storage unit and simultaneously receives a cyclic redundancy check code, and the data receiving module performs a cyclic redundancy check comparison according to the cyclic redundancy check code.

[0129] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0130] The data receiving module sets the state machine to the initial state;

[0131] In response to the state machine receiving the handshake signal sent by the host computer, the state machine performs a handshake interaction with the host computer;

[0132] In response to detecting that the handshake interaction is successful, the data receiving module starts to receive the serial data sent by the host computer and sets the state machine to the data receiving state.

[0133] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0134] In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit and resets the state machine to the initial state;

[0135] In response to detecting that the cyclic redundancy check comparison fails, the data receiving module returns an error signal to the host computer and resets the state machine to the initial state.

[0136] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0137] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0138] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0139] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A chip startup method, applied to a chip to be started, characterized in that: The chip to be started includes a data receiving module, a static random access storage unit and a microprocessing unit, and the method includes: In response to detecting that the data receiving module receives the serial data sent by the host computer, the data receiving module performs preprocessing on the serial data to obtain processed data; The data receiving module stores the processed data into the static random access memory unit and performs a cyclic redundancy check at the same time; In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip start signal to the micro-processing unit, so that the micro-processing unit starts the chip according to the chip start signal.

2. The chip startup method according to claim 1, characterized in that: The host computer is a field programmable logic gate array, and the serial data includes a serial timing pre-agreed with the field programmable logic gate array in a preset configuration mode.

3. The chip startup method according to claim 2, characterized in that: The preset configuration mode includes a passive serial mode.

4. The chip startup method according to claim 1, characterized in that: The serial data includes at least one data segment, the data segment includes a frame header, and the frame header includes the agreed data amount of the current data segment. In response to detecting that the data receiving module receives the serial data sent by the host computer, the data receiving module performs preprocessing on the serial data to obtain processed data, including: In response to detecting that the serial data sent by the host computer received by the data receiving module meets the agreed data amount, the data receiving module performs splicing and restoration processing on the serial data to obtain processed data in a specified data format, wherein the specified data format includes a data format preset and recognized by the microprocessing unit; The data receiving module stores the processed data into the static random access storage unit and performs a cyclic redundancy check at the same time, including: The data receiving module stores the processed data into the static random access memory unit and receives a cyclic redundancy check code at the same time, and the data receiving module performs a cyclic redundancy check comparison according to the cyclic redundancy check code.

5. The chip startup method according to any one of claims 1 to 4, characterized in that: The chip to be started also includes a state machine, and the method further includes: The data receiving module sets the state machine to an initial state; In response to the state machine receiving a handshake signal sent by the host computer, the state machine performs a handshake interaction with the host computer; In response to detecting that the handshake interaction is successful, the data receiving module starts to receive serial data sent by the host computer and sets the state machine to a data receiving state.

6. The chip startup method according to claim 5, characterized in that: The method further comprises: In response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip start signal to the microprocessing unit and resets the state machine to an initial state; In response to detecting that the cyclic redundancy check comparison fails, the data receiving module returns an error signal to the host computer and resets the state machine to an initial state.

7. A chip startup device, characterized in that: The device comprises: The transmission module is used for, in response to detecting that the data receiving module receives the serial data sent by the host computer, the data receiving module performs preprocessing on the serial data to obtain processed data; A verification module, used for the data receiving module to store the processed data into a static random access storage unit and perform a cyclic redundancy check at the same time; The startup module is used for, in response to detecting that the cyclic redundancy check comparison is successful, the data receiving module sends a chip startup signal to the microprocessing unit, so that the microprocessing unit starts the chip according to the chip startup signal.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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