Kernel control method, device and electronic equipment

Abstract

The application provides a kernel control method and device and electronic equipment; and relates to the technical field of kernels. The method comprises the following steps: obtaining kernel state information of a kernel in the case of processing a current thread; in response to the kernel state information satisfying a set control condition or receiving a running control instruction for the kernel, determining a target running state of the kernel; the target running state comprises a target running state of a power domain and / or a target running state of a clock domain of the kernel; the power consumption corresponding to the target running state is less than the power consumption of the kernel in a normal running state; determining an adjustment signal corresponding to the kernel based on the target running state, and sending the adjustment signal to the power domain and / or the clock domain of the kernel to control the running state of the kernel. Through the application, the precision of power consumption management can be improved, and the flexibility of kernel control in a low-power mode can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of kernels, and in particular to a kernel control method and device and electronic equipment. BACKGROUND

[0002] In the current kernel control method, fixed power state switching is usually used, and there is a lack of dynamic monitoring and adjustment of the real-time state of the kernel. In terms of clock control, although the existing method can adjust the clock frequency according to the task demand, power waste may still occur in a low-load scenario. The existing kernel control method has the problems of insufficient fine power management and poor flexibility of kernel control in a low-power mode. SUMMARY

[0003] Embodiments of the present application provide a kernel control method, device and electronic equipment.

[0004] According to a first aspect of the present application, a kernel control method is provided, which includes: obtaining kernel state information of a kernel in the case of processing a current thread; in response to the kernel state information meeting a set control condition or receiving a running control instruction for the kernel, determining a target running state of the kernel; the target running state includes a target running state of a power domain and / or a target running state of a clock domain of the kernel; the power consumption corresponding to the target running state is less than the power consumption of the kernel in a normal running state; determining an adjustment signal corresponding to the kernel based on the target running state, and sending the adjustment signal to the power domain and / or the clock domain of the kernel to control the running state of the kernel.

[0005] According to an embodiment of the present application, the obtaining of the kernel state information of the kernel in the case of processing the current thread includes: obtaining the usage frequency and cache hit condition of the kernel in the case of processing the current thread; in the case of processing the current thread, obtaining instruction type information of an executed instruction from a decoding stage corresponding to the kernel; and determining the kernel state information based on the usage frequency, cache hit condition and instruction type information.

[0006] According to an embodiment of the present application, the determination of the target running state of the kernel includes at least one of the following: determining a target running state of a power domain of the kernel based on the kernel state information or the running control instruction; the power domain at least includes a main domain, a security domain, a storage domain and a always-on domain; determining a target running state of a clock domain of the kernel based on the kernel state information or the running control instruction; the clock domain at least includes a main clock domain, a data transmission clock domain, a calculation clock domain, a debugging domain and a always-on clock domain.

[0007] According to one embodiment of the present application, the determining the target running state of the power domain of the core comprises at least one of the following: determining the power switch state of each domain included in the power domain based on the power switch signal included in the running control instruction; determining the voltage state of each domain included in the power domain based on the voltage control signal included in the running control instruction; and determining the power switch state of each domain included in the power domain based on the register information included in the core state information.

[0008] According to one embodiment of the present application, the determining the target running state of the clock domain of the core comprises at least one of the following: determining the clock switch state of each domain included in the clock domain based on the clock switch signal included in the running control instruction; determining the clock frequency state of each domain included in the clock domain based on the clock frequency control signal included in the running control instruction; and determining the clock frequency state of each domain included in the clock domain based on the core state information obtained according to the set running period.

[0009] According to one embodiment of the present application, the core state information comprises the usage frequency, cache hit condition and instruction type information of the core, and the determining the clock frequency state of each domain included in the clock domain based on the core state information obtained according to the set running period comprises at least one of the following: adjusting the clock frequency of each domain included in the clock domain to obtain the corresponding clock frequency state in response to the usage frequency of the core obtained according to the set first running period satisfying the set frequency threshold; adjusting the clock frequency of each domain included in the clock domain to obtain the corresponding clock frequency state in response to the cache hit condition obtained according to the set second running period satisfying the set hit rate threshold; determining the first instruction quantity of the vector type calculation instruction included in the instruction type information obtained according to the set third running period, and adjusting the clock frequency of each domain included in the clock domain based on the first instruction quantity to obtain the corresponding clock frequency state; and determining the second instruction quantity of the floating point type calculation instruction included in the instruction type information obtained according to the set fourth running period, and adjusting the clock frequency of each domain included in the clock domain based on the second instruction quantity to obtain the corresponding clock frequency state.

[0010] According to an embodiment of the present application, the method further comprises: in response to completion of execution of the current thread, storing the target address information corresponding to the current thread and the target running state into a history information table; adjusting the core from the target running state to a normal running state; in response to address information corresponding to a next thread matching the target address information, determining the target running state corresponding to the next thread from the history information table; based on the determined target running state, determining an adjustment signal corresponding to the core, and sending the adjustment signal to a power domain and / or a clock domain of the core to control the running state of the core.

[0011] According to a second aspect of the present application, a core control apparatus is provided, comprising: an acquisition module configured to acquire core state information of a core in a case of processing a current thread; a determination module configured to determine a target running state of the core in response to the core state information satisfying a set control condition or receiving a running control instruction for the core; the target running state comprising a target running state of a power domain of the core and / or a target running state of a clock domain of the core; power consumption corresponding to the target running state being less than power consumption of the core in a normal running state; and a control module configured to determine an adjustment signal corresponding to the core based on the target running state, and send the adjustment signal to the power domain and / or the clock domain of the core to control the running state of the core.

[0012] According to an embodiment of the present application, the acquisition module is configured to: acquire usage frequency and cache hit condition of the core in a case of processing the current thread; acquire instruction type information of executed instructions from a decoding stage corresponding to the core in a case of processing the current thread; and determine the core state information based on the usage frequency, the cache hit condition and the instruction type information.

[0013] According to an embodiment of the present application, the determination module is configured to at least one of: determine a target running state of a power domain of the core based on the core state information or the running control instruction; the power domain comprising at least a main domain, a security domain, a storage domain and a normal-on domain; and determine a target running state of a clock domain of the core based on the core state information or the running control instruction; the clock domain comprising at least a main clock domain, a data transmission clock domain, a calculation clock domain, a debugging domain and a normal-on clock domain.

[0014] According to an embodiment of the present application, the determination module is configured to at least one of: determine power switch states of respective domains included in the power domain based on a power switch signal included in the running control instruction; determine voltage states of respective domains included in the power domain based on a voltage control signal included in the running control instruction; and determine power switch states of respective domains included in the power domain based on register information included in the core state information.

[0015] According to one embodiment of the present application, the determining module is configured to determine at least one of: a clock switch state of each domain included in the clock domain based on a clock switch signal included in the running control instruction; a clock frequency state of each domain included in the clock domain based on a clock frequency control signal included in the running control instruction; and the clock frequency state of each domain included in the clock domain based on the kernel state information obtained according to the set running period.

[0016] According to one embodiment of the present application, the kernel state information includes usage frequency, cache hit condition and instruction type information of the kernel, and the determining module is configured to perform at least one of: adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency state in response to the usage frequency of the kernel obtained according to a set first running period satisfying a set frequency threshold; adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency state in response to the cache hit condition obtained according to a set second running period satisfying a set hit rate threshold; determining a first instruction quantity of vector type calculation instructions included in the instruction type information obtained according to a set third running period, and adjusting the clock frequency of each domain included in the clock domain based on the first instruction quantity to obtain a corresponding clock frequency state; and determining a second instruction quantity of floating point type calculation instructions included in the instruction type information obtained according to a set fourth running period, and adjusting the clock frequency of each domain included in the clock domain based on the second instruction quantity to obtain a corresponding clock frequency state.

[0017] According to one embodiment of the present application, the apparatus further includes a storage module configured to: store the target address information corresponding to the current thread and the target running state to a history information table in response to the current thread being executed; adjust the kernel from the target running state to a normal running state; determine the corresponding target running state from the history information table in response to the address information corresponding to a next thread matching the target address information; determine the adjustment signal corresponding to the kernel based on the determined target running state, and send the adjustment signal to the power domain and / or the clock domain of the kernel to control the running state of the kernel.

[0018] According to a third aspect of the present application, an electronic device is provided, comprising:

[0019] at least one processor;

[0020] and a memory in communication connection with the at least one processor; wherein

[0021] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present application.

[0022] The method provided by the embodiment of the present application comprises: obtaining kernel state information of a kernel in a case of processing a current thread; determining a target running state of the kernel in response to the kernel state information satisfying a set control condition or receiving a running control instruction for the kernel; the target running state comprises a target running state of a power domain and / or a target running state of a clock domain of the kernel; power consumption corresponding to the target running state is less than power consumption of the kernel in a normal running state; determining an adjustment signal corresponding to the kernel based on the target running state, and sending the adjustment signal to the power domain and / or the clock domain of the kernel to control the running state of the kernel. In this way, the fineness of power consumption management and the flexibility of kernel control in a low-power mode can be improved.

[0023] It should be understood that the teachings of the present application do not require all the beneficial effects described above to be achieved, but a specific technical solution can achieve a specific technical effect, and other embodiments of the present application can also achieve beneficial effects not mentioned above. BRIEF DESCRIPTION OF DRAWINGS

[0024] The above and other objects, features and advantages of the exemplary embodiments of the present application will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0025] In the drawings, identical or corresponding reference numerals indicate identical or corresponding parts.

[0026] Figure 1 A processing flow of a kernel control method provided by an embodiment of the present application is shown Figure 1 ;

[0027] Figure 2 A processing flow of a kernel control method provided by an embodiment of the present application is shown Figure 2 ;

[0028] Figure 3 A processing flow of a kernel control method provided by an embodiment of the present application is shown Figure 3 ;

[0029] Figure 4 A processing flow of a kernel control method provided by an embodiment of the present application is shown Figure 4 ;

[0030] Figure 5 A processing flow of a kernel control method provided by an embodiment of the present application is shownFigure 1 ;

[0031] Figure 6 An application scenario of the kernel control method provided by the embodiments of the present application is shown Figure 2 ;

[0032] Figure 7 An application scenario of the kernel control method provided by the embodiments of the present application is shown Figure 3 ;

[0033] Figure 8 An application scenario of the kernel control method provided by the embodiments of the present application is shown Figure 4 ;

[0034] Figure 9 An optional schematic diagram of the kernel control apparatus provided by the embodiments of the present application is shown

[0035] Figure 10 An optional schematic diagram of the electronic device provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0036] In order to make the objectives, characteristics and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0037] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0038] In the following description, the term "first\second" is only to distinguish similar objects, and does not represent the specific order of the objects. It can be understood that "first\second" can be interchanged with specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0040] Before the embodiments of the present application are further described in detail, the terms and phrases involved in the embodiments of the present application are explained, and the terms and phrases involved in the embodiments of the present application are applicable to the following explanations.

[0041] CSR (Control and Status Registers, control and status registers): CSR in RISC-V architecture is a register used to configure and record the running state of the processor. CSR registers are located inside the processor core, using independent address coding space, which is independent of the address interval of memory addressing. There are many types of CSR registers, which can be divided into different categories, including but not limited to: processor information related registers, interrupt configuration related registers, exception handling related registers, memory protection related registers, performance statistics related registers, debugging interface related registers, etc.

[0042] WFI (Wait For Interrupt, wait for interrupt) instruction: WFI instruction in RISC-V architecture is an instruction used to implement low-power state. When the processor executes the WFI instruction, it will pause the current instruction execution flow and enter a low-power waiting state until the next interrupt or trigger event occurs. This state is often referred to as "sleep" state, and the power consumption of the CPU in this state is minimized. WFI instruction is often used as a standby instruction for energy saving and power optimization, allowing the processor to reduce energy consumption when waiting for tasks.

[0043] PC (Program Counter, program counter): In computer architecture, the kernel uses the program counter to track the address of the next instruction to be executed. PC is a special register that holds the address of instructions in memory that will be fetched and executed by the processor's execution unit. In RISC-V architecture, the PC register is used to retrieve instructions from the instruction cache (I-Cache).

[0044] Offset (address offset value): The address space provided by the operating system for each process is called virtual address, which is divided into fixed size units by paging. The high bits of the virtual addresses in the same page are the same, and the low bits can be used to represent the offset value in the industry, which is called Offset here.

[0045] Decode phase: In computer architecture, the instruction decode phase is a critical step in the execution cycle of a processor. This phase occurs after the fetch phase and before the execute phase. The main task of the decode phase is to convert the instructions fetched from memory into control signals that the processor can understand and execute.

[0046] PLL (Phase-Locked Loop): It is an electronic circuit whose core function is to generate an output signal that maintains a constant phase relationship with the input signal (reference signal). PLL is widely used in clock synchronization, frequency synthesis, signal recovery, and modulation and demodulation.

[0047] Cache: It is a component in computer systems used to reduce the average time required for the processor to access memory. Cache is located in the memory hierarchy, between the processor and the main memory. The main purpose of cache is to alleviate the difference between the speed of the processor and the speed of the memory, as the processor is usually much faster than the memory.

[0048] The processing flow in the kernel control method provided by the embodiments of the present application is described. Referring to Figure 1 , Figure 1 is the processing flow of the kernel control method provided by the embodiments of the present application Figure 1 , the steps S101-S103 shown in Figure 1 will be described.

[0049] Step S101, obtaining kernel state information of the kernel in the case of processing the current thread.

[0050] In some embodiments, the kernel can include the kernel of a processor under the RISC-V architecture. The current thread can include the instruction sequence that the kernel is processing or will process. Specifically, when the kernel executes a program, the kernel processes multiple threads according to a certain scheduling strategy, and the current thread refers to the thread that is currently being executed by the kernel or occupies kernel resources for processing. The kernel can process the instructions in the current thread through pipelining. The kernel state information can include information reflecting the current running condition of the kernel when processing the current thread. The kernel state information can specifically include the usage frequency of the kernel, the instruction type information of the executed instructions, and the cache hit situation and other information. Among them, the usage frequency of the kernel and the cache hit situation can be obtained from the CSR register, and the instruction type information of the executed instructions can be obtained from the decode module.

[0051] In step S102, in response to the kernel state information satisfying a set control condition or receiving a running control instruction for the kernel, a target running state of the kernel is determined; the target running state includes a target running state of a power domain and / or a target running state of a clock domain of the kernel; and power consumption corresponding to the target running state is less than power consumption of the kernel in a normal running state.

[0052] In some embodiments, the control condition can include a pre-set condition for judging whether the running state of the kernel needs to be adjusted. The running control instruction can include an instruction received from outside for controlling the running state of the kernel. The specific running control instruction can include a RISC-V WFI instruction and a SoC low-power regulation instruction and the like. The target running state can include a running state expected to be reached by the kernel according to the kernel state information or the running control instruction. The power consumption of the kernel in the target running state is lower than the power consumption of the kernel in the normal running state. The target running state can specifically include a target running state of a power domain and / or a target running state of a clock domain of the kernel. The embodiments of the present application do not limit the specific target running state. The power domain can include different power regions divided in the kernel architecture. The specific power domain can be divided into a main domain, a security domain, a storage domain and a always-on domain and the like, and each domain in the power domain can be independently controlled by a power switch and a voltage. The clock domain can include different clock regions divided in the kernel architecture. The specific clock domain can be divided into a main clock domain, a data transmission clock domain, a calculation clock domain, a debugging domain and a always-on clock domain and the like, and each domain in the clock domain can be independently controlled by a clock frequency and a clock switch.

[0053] In step S103, an adjustment signal corresponding to the target running state is determined based on the target running state, and the adjustment signal is sent to the power domain and / or the clock domain of the kernel to control the running state of the kernel.

[0054] In some embodiments, the adjustment signal can include a signal for adjusting the running state of the power domain and / or the clock domain of the kernel according to the target running state. The adjustment signal can be generated by a power domain state table and / or a clock domain state table maintained inside the monitoring and regulation unit. The power domain state table and the clock domain state table record information such as the current state and the target state of each power domain and clock domain. When the running state of the kernel needs to be adjusted, the monitoring and regulation unit determines the target running state according to the kernel state information or the running control instruction, and then generates the adjustment signal from the corresponding information in the power domain state table and / or the clock domain state table. The power domain state table can include information such as a power domain identifier, a state and a valid bit. The clock domain state table can include information such as a clock domain identifier, a state and a valid bit. Sending these adjustment signals to the corresponding power domain and / or clock domain can achieve the control of the running state of the kernel.

[0055] The method of the embodiment of the application effectively implements the RISC-V WFI low-power consumption instruction by reasonably dividing the clock domain and the power domain, enables the core to retain necessary states when in a shallow low-power consumption state, and dynamically adjusts the power-off range, clock-off area and reduces the clock frequency according to actual needs, thereby realizing fine power consumption control and improving system energy efficiency. Meanwhile, the monitoring and control unit can perform fine-grained internal clock frequency control on the calculation unit, the L2 Cache and the bus, automatically reduces the frequency of the hardware layer using fewer logic units, effectively shares the control pressure of the overall PMU (Power Management Unit, power management unit), and makes the power consumption management more efficient and flexible. In addition, the core control method supports software shutdown of the security unit, can flexibly adjust the running state of the security unit according to different application scenario needs, balances power consumption optimization while ensuring system safety. Moreover, the low-power consumption mode control mechanism based on thread conditions can record the low-power consumption state in time after the current thread ends, and can quickly recover to the corresponding low-power consumption state when encountering a similar scenario next time, significantly reducing the delay of power consumption control and improving the response speed and energy efficiency performance of the system.

[0056] In some embodiments, the processing flow of the core control method is shown in Figure 2 As shown in Figure 2 The obtaining of the core state information of the core in the case of processing the current thread in step S101 can include:

[0057] In step S201, the usage frequency and cache hit condition of the core in the case of processing the current thread are obtained.

[0058] In this embodiment, the usage frequency can include: the number of cycles and instruction numbers that have been run since the CPU reset is obtained from the CSR register (cycle and instret counters) every fixed clock period. The usage frequency can be used to determine the current load condition of the core. The cache hit condition can include: the ratio of the number of times of successfully obtaining the required data or instructions from the cache to the total access times when the core accesses data or instructions. Specifically, the cache hit condition can be obtained and counted from the LSU (Load / Store Unit, load / store unit) and D-Cache. The cache hit condition can be used to evaluate the usage efficiency of the cache.

[0059] In step S202, the instruction type information of the executed instruction is obtained from the decoding stage corresponding to the core in the case of processing the current thread.

[0060] In the embodiment, the instruction type information can include the type of the instruction executed by the core when processing the current thread. The instruction type information can specifically include the type of vector calculation instruction, floating point calculation instruction, etc. The instruction type information can be obtained from a vector counter and a floating point counter. The vector counter can be used to count the number of times of execution of the vector calculation instruction. The floating point counter can be used to count the number of times of execution of the floating point calculation instruction. The instruction type of the executed instruction is obtained from the decoding stage of the core pipeline, and the vector counter is incremented by 1 when the instruction is a vector calculation instruction, and the floating point counter is incremented by 1 when the instruction is a floating point calculation instruction.

[0061] In step S203, the core state information is determined based on the usage frequency, the cache hit condition and the instruction type information.

[0062] As an example, a fixed clock cycle is set as a working period, and at the beginning of each working period, the counters used to count the core state information are cleared. The counters include the cycle and instret counters used to count the core usage frequency, the cache access counter and the cache hit counter used to count the cache hit condition, and the vector counter and the floating point counter used to count the instruction type, etc. In the decoding stage of the core pipeline, the type of the instruction executed in each working period is monitored, and the corresponding counter is updated. For each decoded instruction, if it is a vector calculation instruction, the vector counter is incremented by 1; if it is a floating point calculation instruction, the floating point counter is incremented by 1. At the same time, in each working period, the access request and the hit condition of the core to the cache are monitored. Each time the core accesses the cache, the cache access counter is incremented by 1; if the access is hit, the cache hit counter is also incremented by 1. The number of cycles and the number of instructions run since the CPU is reset are obtained from the cycle and instret counters, and the core usage frequency is counted accordingly. At the end of the working period, the core state information is calculated according to the collected counter data.

[0063] In some embodiments, the processing flow of the core control method is shown in Figure 3 As shown in Figure 3 The core control method can include the following steps:

[0064] In step S301a, the target running state of the power domain of the core is determined based on the core state information or the running control instruction.

[0065] In some embodiments, step S301a can include at least one of the following: determining the power switch state of each domain included in the power domain based on the power switch signal included in the running control instruction; determining the voltage state of each domain included in the power domain based on the voltage control signal included in the running control instruction; determining the power switch state of each domain included in the power domain based on the register information included in the core state information.

[0066] In some embodiments, monitoring the power domain state table inside the monitoring and control unit can determine the power switch state and voltage state of the power domain. The target running state of the power domain of the core can include: stop mode (Stop), unsafe mode (unsafe), wait mode (Wait), unsafe wait mode (unsafe_wait), unsafe stop mode (unsafe_stop), and the like. The normal running state of the power domain can include: running mode (Run). The whole kernel architecture can be divided into four power domains: main domain, security domain, storage domain and always-on domain. The main domain can include the main functional units of the core and the debug interface module. The security domain can include security and encryption units. The storage domain can include cache and memory management units. The always-on domain can include Timer, management module and interrupt related units.

[0067] As an example, based on the power switch signal included in the running control instruction, the power switch state of each domain included in the power domain is determined; based on the voltage control signal included in the running control instruction, the voltage state of each domain included in the power domain can include: switching the power switch state of each domain through RISC-V WFI instruction, interrupt request and software security control. Normally, the kernel of the processor is in Run, which is the normal running state, and all domains in the power domain are in power supply state. When the monitoring and control unit receives the RISC-V WFI instruction, the power switch signal and the voltage control signal included in the RISC-V WFI instruction are adjusted, the power domain state table inside the monitoring and control unit is adjusted, and the running state of the power domain is converted to Wait. In the Wait state, the core can return to Run after receiving an interrupt request. In the Wait state, the power of the main domain is turned off, the voltage of the storage domain and the security domain is reduced, and the voltage of the always-on domain is maintained. The reduced voltage can be determined by the voltage control signal. When the kernel of the processor is in the Wait state, if the monitoring and control unit receives the WFI instruction again, the power switch signal and the voltage control signal included in the RISC-V WFI instruction are adjusted, the power domain state table inside the monitoring and control unit is adjusted, and the running state of the power domain is converted to the Stop state. In the Stop state, the power of the main domain, the storage domain and the security encryption domain is turned off, the voltage of the always-on domain is reduced, and the state of the kernel of the processor at this time is reported to the bus PMU.

[0068] As an example, determining the power switch state of each domain included in the power domain based on the register information included in the core state information can include: monitoring the monitoring and control unit to determine whether the register information included in the core state information represents that the safety domain in the power domain is closed. In response to the register information representing that the safety domain in the power domain is closed, adjusting the power domain state table inside the monitoring and control unit based on the register information, and converting the running state of the power domain to unsafe. In the unsafe state, the power supply of the safety domain is in the closed state, and the other domains remain normally powered.

[0069] In some embodiments, in the unsafe state, when the monitoring and control unit receives the RISC-V WFI instruction, the running state of the power domain is converted to the Unsafe Wait state or the Unsafe_stop state according to the power switch signal and the voltage control signal included in the RISC-V WFI instruction. Unsafe_wait is similar to the Wait state, except that the power supply of the safety domain is closed, and Unsafe_stop is also similar to the stop state, except that the power supply of the safety domain is closed. How to convert the running state of the power domain to the Unsafe_wait state and the Unsafe_stop state will not be described here.

[0070] Step S301b, determining the target running state of the clock domain of the core based on the core state information or the running control instruction.

[0071] In some embodiments, step S301b can include at least one of the following: determining the clock switch state of each domain included in the clock domain based on the clock switch signal included in the running control instruction; determining the clock frequency state of each domain included in the clock domain based on the clock frequency control signal included in the running control instruction; and determining the clock frequency state of each domain included in the clock domain based on the core state information obtained according to the set running period.

[0072] In some embodiments, monitoring the clock domain state table inside the monitoring and regulating unit can determine the clock switch state and clock frequency state of the clock domain. The target running state of the clock domain of the core can include: stop mode (Stop), wait mode (Wait), and the like. The normal running state of the clock domain can include: running mode (Run). The clock domain does not need to set a separate unsafe state, because in the case that the core is in an unsafe state, the safe domain in the power domain is in an off state, and the clock signal cannot be normally generated. The whole kernel architecture can be divided into five clock domains: main clock domain, data transmission clock domain, calculation clock domain, debugging domain, and always-on clock domain. The main clock domain can include the main functional unit of the core, the safe calculation part of the secure encryption unit, and the first level cache and the memory management unit. The data transmission clock domain can include the encryption transmission unit, the second level cache, and the system bus. The calculation clock domain can include the vector calculation unit and the floating point calculation unit. The debugging domain can include JTAG debugging. The always-on clock domain can include management modules, timers, interrupt modules, and the like.

[0073] As an example, based on the clock switch signal included in the running control instruction, the clock switch state of each domain included in the clock domain is determined; based on the clock frequency control signal included in the running control instruction, the clock frequency state of each domain included in the clock domain can include: switching the clock switch state of each domain through the RISC-V WFI instruction, interrupt request, and software security regulation. Normally, the core of the processor is in Run, which is the normal running state, and all domains in the clock domain are in the power supply state. When the monitoring and regulating unit receives the RISC-V WFI instruction, according to the clock switch signal and the clock frequency control signal included in the RISC-V WFI instruction, the clock domain state table inside the monitoring and regulating unit is adjusted, and the running state of the clock domain is converted to Wait. In the Wait state, the core can return to Run after receiving an interrupt request. In the Wait state, the main clock domain and the calculation clock domain are turned off, and the clock frequency of the data transmission clock domain is reduced. The clock frequency of the always-on domain is kept unchanged. The reduced clock frequency can be determined by the clock frequency control signal. When the core of the processor is in the Wait state, if the monitoring and regulating unit receives the WFI instruction again, according to the clock switch signal and the clock frequency control signal included in the RISC-V WFI instruction, the clock domain state table inside the monitoring and regulating unit is adjusted, and the running state of the clock domain is converted to the Stop state. In the Stop state, the main clock domain, the data transmission clock domain, and the calculation clock domain are all turned off, and the clock frequency of the always-on domain is reduced.

[0074] In some embodiments, determining the clock frequency state of each domain included in the clock domain based on the core state information obtained according to the set running period can include at least one of the following: in response to the usage frequency of the core obtained according to the set first running period satisfying a set frequency threshold, adjusting the clock frequency of each domain included in the clock domain to obtain the corresponding clock frequency state; in response to the cache hit condition obtained according to the set second running period satisfying a set hit rate threshold, adjusting the clock frequency of each domain included in the clock domain to obtain the corresponding clock frequency state; determining a first instruction quantity of vector type computing instructions included in the instruction type information obtained according to the set third running period, and adjusting the clock frequency of each domain included in the clock domain based on the first instruction quantity to obtain the corresponding clock frequency state; determining a second instruction quantity of floating point type computing instructions included in the instruction type information obtained according to the set fourth running period, and adjusting the clock frequency of each domain included in the clock domain based on the second instruction quantity to obtain the corresponding clock frequency state.

[0075] In some embodiments, the first running period can be a fixed clock period for counting the usage frequency of the core. The second running period can be a fixed clock period for counting the cache hit condition. The third running period can be a fixed clock period for counting the quantity of vector type computing instructions. The fourth running period can be a fixed clock period for counting the quantity of floating point type computing instructions. The first running period, the second running period, the third running period and the fourth running period can be the same fixed clock period, or can be different fixed clock periods.

[0076] As an example, the core state register in the monitoring and control unit counts the usage frequency of the core itself, and when the usage frequency changes, the clock domain of the whole core is dynamically adjusted. Specifically, every fixed clock period, the usage frequency of the core is obtained from the core state register, and the usage frequency is compared with a preset frequency threshold. When the usage frequency is lower than 30%, it is considered as low load, and when the usage frequency is higher than 70%, it is considered as high load. In a fixed clock period, the statistical result shows that the usage frequency of the core reaches 80%, which exceeds the high load threshold. The monitoring and control unit adjusts the clock frequency of the main clock domain and the computing clock domain, and raises the clock frequency from the normal mode to the high performance mode to enhance the computing capability. If the usage frequency in a subsequent fixed clock period drops to 25%, which is lower than the low load threshold, the clock frequency of the main clock domain and the computing clock domain is adjusted back to the low power consumption mode to reduce the power consumption.

[0077] As an example, the monitoring and control unit monitors a kernel state register to count cache hits of the kernel, and dynamically adjusts a clock domain of the overall kernel when the cache hits change. Specifically, every fixed clock period, the monitoring and control unit obtains the cache hits of an L1 D-Cache of the kernel from the kernel state register to determine the cache hits of an L2 Cache, and compares the cache hits of the L1 D-Cache with a preset hit rate threshold. The preset hit rate threshold is that below 40% is considered low cache efficiency, and above 70% is considered high cache efficiency. In a fixed clock period, the statistics show that the cache hits of the L1 D-Cache reach 80%, which exceeds the high cache efficiency threshold. The monitoring and control unit adjusts a clock frequency of a data transfer clock domain to increase the clock frequency from a normal mode to a high performance mode to increase the data transfer rate. If the cache hits in a subsequent fixed clock period drop to 25%, which is below the low cache efficiency threshold, the monitoring and control unit adjusts the clock frequency of the data transfer clock domain back to the low power consumption mode to reduce power consumption.

[0078] As an example, the monitoring and control unit monitors a vector counter to count a first instruction number of vector type computing instructions executed by the kernel, and dynamically adjusts a clock domain of the overall kernel when the first instruction number changes. Specifically, every fixed clock period, the monitoring and control unit obtains the first instruction number from the vector counter, and compares the first instruction number with a preset number threshold. The preset number threshold is that below 20 instructions per period is considered light load, and above 50 instructions per period is considered heavy load. In a fixed clock period, the statistics show that the first instruction number reaches 60, which exceeds the high load threshold. The monitoring and control unit adjusts a clock frequency of a vector computing unit in a computing clock domain to increase the clock frequency from a normal mode to a high performance mode to enhance the computing capability. If the first instruction number in a subsequent fixed clock period reaches 10, which is below the low load threshold, the monitoring and control unit adjusts the clock frequency of the vector computing unit in the computing clock domain to the low power consumption mode to reduce power consumption, and clears the vector counter.

[0079] As an example, the monitoring and regulation unit monitors a floating point counter to count a second number of floating point type computing instructions executed by the kernel, and dynamically adjusts the clock domain of the whole kernel when the second number of instructions changes. Specifically, every fixed clock cycle, the second number of instructions is obtained from the floating point counter, and the second number of instructions is compared with a preset number threshold, where the second number of instructions less than 20 per cycle is considered as light load, and the second number of instructions greater than 50 per cycle is considered as heavy load. In a fixed clock cycle, the statistics show that the second number of instructions reaches 60, which exceeds the high load threshold. The monitoring and regulation unit adjusts the clock frequency of the floating point computing unit in the computing clock domain, and increases the clock frequency from the normal mode to the high performance mode to enhance the computing capability. If the first number of instructions in a subsequent fixed clock cycle reaches 10, which is less than the low load threshold, the clock frequency of the floating point computing unit in the computing clock domain is adjusted to the low power consumption mode to reduce the power consumption, and the floating point counter is cleared.

[0080] In step S302, an adjustment signal corresponding to the kernel is determined based on the target running state, and the adjustment signal is sent to the power domain and / or the clock domain of the kernel to control the running state of the kernel.

[0081] In this embodiment, the description of step S302 is similar to that of step S103, which will not be repeated here.

[0082] In some embodiments, the adjustment of the voltage of the power domain can be achieved by sending an instruction to the bus PMU unit, controlling the voltage transmitted to the module by feedback information, and the PMU unit is a unit for switching control and voltage regulation of the LDO inside the SoC.

[0083] In some embodiments, the adjustment of the clock frequency of the clock domain can be achieved by using a frequency hopping technology. In the embodiment of the application, a simple circuit of a counter and a multiplexer is used to implement the frequency hopping technology. The counter takes the clock signal output by the PLL as the counting clock, and the output two-divided and four-divided clock signals and other required divided clock signals enter the multiplexer together with the original clock, and are selected by the control signal as the actual clock signal used in the clock domain. The adjustment signal is given by the clock management unit of the monitoring and regulation unit according to the actual working condition of the kernel. The embodiment of the application can reduce the working frequency to 1 / 2, 1 / 4 or even lower when the chip enters the low power consumption mode, effectively reducing the overall power consumption of the circuit. The clock frequencies in different low power consumption modes can be different, for example, the clock frequency in the low_power_0 mode is two-divided, the clock frequency in the low_power_1 mode is four-divided, the clock frequency in the low_power_2 mode is eight-divided, and the clock frequency in the low_power_3 mode is sixteen-divided.

[0084] In some embodiments, the processing flow of the kernel control method is shown in Figure 4 As shown in Figure 4 The kernel control method can further include:

[0085] In step S401, in response to the completion of the current thread execution, the target address information and the target running state corresponding to the current thread are stored in the history information table.

[0086] In step S402, the kernel is adjusted from the target running state to the normal running state.

[0087] In step S403, in response to the matching of the address information corresponding to the next thread and the target address information, the corresponding target running state is determined from the history information table.

[0088] In step S404, based on the determined target running state, the adjustment signal corresponding to the kernel is determined, and the adjustment signal is sent to the power domain and / or the clock domain of the kernel to control the running state of the kernel.

[0089] In the embodiment, the target address information can include the first-occurred PC and the Offset, and the Offset is from the low bit of the first-occurred virtual address. The history information table can be used to find and determine the target running state of the kernel when the subsequent thread is started, so as to reduce the delay of power consumption control.

[0090] As an example, when the thread is first run in the kernel, the first-occurred PC and the Offset are recorded in the register, and the Offset is from the low bit of the first-occurred virtual address. When the current thread ends, the corresponding PC and Offset information and the low-power mode state in the power domain state table and the clock domain state table at this time are recorded in the history information table, and the power and clock states are restored to the normal working mode. In response to the matching of the address information corresponding to the next thread and the PC and Offset information included in the target address information, the corresponding low-power mode state is sent to the corresponding power domain state table and clock domain state table, so as to quickly restore the previous low-power mode state.

[0091] Figure 5 The application scenario of the kernel control method provided by the embodiment of the application is shown Figure 1 .

[0092] Referring to Figure 5 The application scenario one of the kernel control method provided by the embodiment of the application is applied to the low-power module of the kernel control system.

[0093] The overall architecture of the low-power module is shown in Figure 5As shown, the architecture includes three sub-modules of monitoring and control unit, power management unit, clock management unit, and a history information table is also set to record historical information and quickly enter appropriate low-power mode. The monitoring and control unit obtains the core state information in the CSR register group and the decoder module, wherein the CSR register group includes an interrupt register and a performance counter. According to the core state information, signals are sent to the power management unit and the clock management unit, and the power domain of the core is adjusted in the power management unit. The clock frequency and switch of the specified clock domain are adjusted in the clock management unit. The monitoring and control unit can also receive external low-power signals (RISC-V WFI instruction or SoC low-power control). For SoC low-power control, the values of corresponding bits in the power management unit and the clock management unit are directly changed.

[0094] Figure 6 The application scenario of the core control method provided by the embodiment of the application is shown Figure 2 .

[0095] Referring to Figure 6 , the application scenario two of the core control method provided by the embodiment of the application is applied to the monitoring and control unit in the low-power module. The monitoring and control unit includes a vector counter, a floating point counter, a core state register, a power domain state table, a clock domain state table and a TIMER. The monitoring and control unit adjusts the core running state by obtaining the information of the CSR register and recording the vector and floating point instruction execution in the decoder in a fixed working period.

[0096] Figure 7 The application scenario of the core control method provided by the embodiment of the application is shown Figure 3 .

[0097] Referring to Figure 7 , the application scenario three of the core control method provided by the embodiment of the application is applied to the power domain division in the core. The main domain includes the main functional unit of the core and the debug interface module (JTAG), the always-on domain includes the Timer, the management module and the interrupt related unit (ECLIC), the storage domain includes the cache and the memory management unit. The security domain includes the security and encryption unit.

[0098] Figure 8 The application scenario of the core control method provided by the embodiment of the application is shown Figure 4 .

[0099] Referring to Figure 8The application scenario four of the kernel control method provided by the embodiments of the present application is applied to clock domain division in the kernel. The kernel module is divided into five clock domains, and an independent gated clock signal is set for each clock domain, so that the unused module can be turned off or frequency-reduced. The main clock domain includes the main functional unit in the kernel, the security calculation in the security encryption unit, the first level cache, and the bypass translation buffer. The data transmission clock domain includes the encryption transmission unit, the second level cache, and the system bus. When it is monitored that the first level cache hit rate is extremely high so that data almost does not need to be obtained from the second level cache, frequency reduction processing is performed. The calculation clock domain includes the vector calculation unit and the floating point calculation unit. The JTAG debugging sets up a separate JTAG debugging domain. The always-on clock domain includes the power management module, the Timer, the ECLIC, the DEBUG, and the clock management module.

[0100] It can be understood that Figures 5-8 The application scenario of the kernel control method is only a part of the exemplary embodiments in the embodiments of the present application, and the application scenario of the kernel control method in the embodiments of the present application includes but is not limited to Figures 5-8 The application scenario of the kernel control method is only a part of the exemplary embodiments in the embodiments of the present application, and the application scenario of the kernel control method in the embodiments of the present application includes but is not limited to

[0101] The exemplary structure of the software module included in the kernel control device 90 provided by the embodiments of the present application will be described below. In some embodiments, as shown in Figure 9 The kernel control device 90 can include: an acquisition module 901 configured to acquire kernel state information of a kernel in a case of processing a current thread; a determination module 902 configured to determine a target running state of the kernel in response to the kernel state information satisfying a set control condition or receiving a running control instruction for the kernel; the target running state includes a target running state of a power domain and / or a target running state of a clock domain of the kernel; the power consumption corresponding to the target running state is less than the power consumption of the kernel in a normal running state; and a control module 903 configured to determine an adjustment signal corresponding to the kernel based on the target running state, and send the adjustment signal to the power domain and / or the clock domain of the kernel to control the running state of the kernel.

[0102] In some embodiments, the acquisition module 901 is configured to: acquire a usage frequency and a cache hit condition of the kernel in a case of processing a current thread; acquire instruction type information of an executed instruction from a decoding stage corresponding to the kernel in a case of processing the current thread; and determine the kernel state information based on the usage frequency, the cache hit condition, and the instruction type information.

[0103] In some embodiments, the determining module 902 is configured to determine at least one of: a target running state of a power domain of the core based on the core state information or the running control instruction; the power domain comprising at least a main domain, a security domain, a storage domain and an always-on domain; a target running state of a clock domain of the core based on the core state information or the running control instruction; the clock domain comprising at least a main clock domain, a data transfer clock domain, a calculation clock domain, a debug domain and an always-on clock domain.

[0104] In some embodiments, the determining module 902 is configured to determine at least one of: a power switch state of each domain included in the power domain based on a power switch signal included in the running control instruction; a voltage state of each domain included in the power domain based on a voltage control signal included in the running control instruction; the power switch state of each domain included in the power domain based on register information included in the core state information.

[0105] In some embodiments, the determining module 902 is configured to determine at least one of: a clock switch state of each domain included in the clock domain based on a clock switch signal included in the running control instruction; a clock frequency state of each domain included in the clock domain based on a clock frequency control signal included in the running control instruction; the clock frequency state of each domain included in the clock domain based on the core state information obtained according to a set running period.

[0106] In some embodiments, the core state information comprises usage frequency, cache hit condition and instruction type information of the core, and the determining module 902 is configured to determine at least one of: in response to the usage frequency of the core obtained according to a set first running period satisfying a set frequency threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency state; in response to the cache hit condition obtained according to a set second running period satisfying a set hit rate threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency state; determining a first instruction quantity of vector type calculation instructions included in the instruction type information obtained according to a set third running period, and adjusting the clock frequency of each domain included in the clock domain based on the first instruction quantity to obtain a corresponding clock frequency state; determining a second instruction quantity of floating point type calculation instructions included in the instruction type information obtained according to a set fourth running period, and adjusting the clock frequency of each domain included in the clock domain based on the second instruction quantity to obtain a corresponding clock frequency state.

[0107] In some embodiments, the kernel control apparatus 90 further comprises a storage module, configured to: in response to completion of execution of the current thread, store the target address information corresponding to the current thread and the target running state into a history information table; adjust the kernel from the target running state to a normal running state; in response to address information corresponding to a next thread matching the target address information, determine the corresponding target running state from the history information table; based on the determined target running state, determine an adjustment signal corresponding to the kernel, and send the adjustment signal to a power domain and / or a clock domain of the kernel to control the running state of the kernel.

[0108] It should be noted that the description of the apparatuses of the embodiments of the present application is similar to the description of the method embodiments described above, and has similar beneficial effects as the method embodiments, and thus will not be described again. For technical details of the kernel control apparatuses not described in the embodiments of the present application, they can be understood according to the description of any one of the accompanying drawings. Figures 1 to 10

[0109] According to the embodiments of the present application, the present application further provides an electronic device and a non-transitory computer readable storage medium.

[0110] Figure 10 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application described and / or claimed in this document.

[0111] As shown in Figure 10 The electronic device 800 includes a computing unit 801 that can perform various appropriate actions and processes in accordance with a computer program stored in a ROM 802 or a computer program loaded from a storage unit 808 into a RAM 803. Various programs and data required for operation of the electronic device 800 can also be stored in the RAM 803. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other through a bus 804. An I / O interface 805 is also connected to the bus 804.

[0112] ​A plurality of components in the electronic device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0113] The computing unit 801 can be various general and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 801 performs various methods and processes described above, such as the kernel control method. For example, in some embodiments, the kernel control method can be implemented as a computer software program, which is tangibly embodied in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded onto the RAM 803 and executed by the computing unit 801, one or more steps of the kernel control method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the kernel control method by any other appropriate means, such as by means of firmware.

[0114] Various implementations of the systems and techniques described above herein can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0115] Program code for carrying out methods of the present application can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces a means for implementing the functions / acts specified in the flowcharts and / or block diagrams. The program code can be retrieved from a machine-readable medium or device and executed by a processor to produce a machine for implementing the functions / acts specified in the flowcharts and / or block diagrams. The program code can be executed as a stand-alone program, or in combination with other program codes, on the machine to produce a machine that implements the functions / acts specified in the flowcharts and / or block diagrams.

[0116] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable storage media can include, without limitation, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media can include, but are not limited to, an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0117] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0118] The systems and techniques described herein can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described herein), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0119] The computer system can include clients and servers. The clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server can arise by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The servers can be cloud servers, servers of a distributed system, or servers combined with a blockchain.

[0120] It should be understood that the steps as shown above can be reordered, added, or deleted, using various forms of flow. For example, the steps described in the present application can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in the present application can be achieved, and the present application does not limit herein.

[0121] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0122] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A kernel control method, characterized in that: The method comprises: Get kernel status information of the kernel in processing the current thread; In response to the core state information satisfying a set control condition or receiving an operation control instruction for the core, determining a target operating state of the core; the target operating state includes a target operating state of a power domain and / or a target operating state of a clock domain of the core; and the power consumption corresponding to the target operating state is less than the power consumption of the core in a normal operating state; The determining of the target operating state of the kernel includes: determining the target operating state of the power domain of the kernel based on the kernel state information or the operation control instruction; the power domain includes at least a main domain, a security domain, a storage domain, and a normally-on domain; determining the target operating state of the clock domain of the kernel based on the kernel state information or the operation control instruction; the clock domain includes at least a main clock domain, a data transmission clock domain, a computing clock domain, a debugging domain, and a normally-on clock domain; Determining the target operating state of the clock domain of the core at least includes: determining the clock frequency state of each domain included in the clock domain based on the core state information obtained according to the set operating cycle; The kernel status information includes kernel usage frequency, cache hit status, and instruction type information. The determining the clock frequency status of each domain included in the clock domain based on the kernel status information obtained according to a set operating cycle includes: in response to the kernel usage frequency obtained according to a set first operating cycle satisfying a set frequency threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency status; in response to the cache hit status obtained according to a set second operating cycle satisfying a set hit rate threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency status; determining a first instruction quantity of vector type calculation instructions included in the instruction type information obtained according to a set third operating cycle, and adjusting the clock frequency of each domain included in the clock domain based on the first instruction quantity to obtain a corresponding clock frequency status; determining a second instruction quantity of floating-point type calculation instructions included in the instruction type information obtained according to a set fourth operating cycle, and adjusting the clock frequency of each domain included in the clock domain based on the second instruction quantity to obtain a corresponding clock frequency status; An adjustment signal corresponding to the core is determined based on the target operating state, and the adjustment signal is sent to a power domain and / or a clock domain of the core to control the operating state of the core.

2. The method according to claim 1, characterized in that The obtaining of kernel state information of the kernel when processing the current thread includes: Obtaining the usage frequency and cache hit status of the core when processing the current thread; In the case of processing the current thread, obtaining instruction type information of the executed instruction from the decoding stage corresponding to the kernel; The kernel status information is determined based on the usage frequency, cache hit status, and instruction type information.

3. The method according to claim 1, characterized in that Determining the target operating state of the power domain of the core includes at least one of the following: Determining a power switch state of each domain included in the power domain based on a power switch signal included in the operation control instruction; Determining a voltage state of each domain included in the power domain based on a voltage control signal included in the operation control instruction; Based on the register information included in the core state information, the power switch state of each domain included in the power domain is determined.

4. The method according to claim 1, wherein Determining the target operating state of the clock domain of the core includes at least one of the following: Determining a clock switch state of each domain included in the clock domain based on a clock switch signal included in the operation control instruction; Based on the clock frequency control signal included in the operation control instruction, the clock frequency status of each domain included in the clock domain is determined.

5. The method according to claim 1, wherein The method further comprises: In response to the current thread completing execution, storing the target address information and the target running state corresponding to the current thread in a history information table; Adjusting the kernel from a target operating state to a normal operating state; In response to the address information corresponding to the next thread matching the target address information, determining the corresponding target running state from the history information table; Based on the determined target operating state, an adjustment signal corresponding to the core is determined, and the adjustment signal is sent to a power domain and / or a clock domain of the core to control the operating state of the core.

6. A kernel control device, characterized in that: The device comprises: An acquisition module is used to obtain kernel state information of the kernel when processing the current thread; a determination module, configured to determine a target operating state of the core in response to the core state information satisfying a set control condition or receiving an operation control instruction for the core; the target operating state includes a target operating state of a power domain and / or a target operating state of a clock domain of the core; and power consumption corresponding to the target operating state is less than power consumption of the core in a normal operating state; The determining of the target operating state of the kernel includes: determining the target operating state of the power domain of the kernel based on the kernel state information or the operation control instruction; the power domain includes at least a main domain, a security domain, a storage domain, and a normally-on domain; determining the target operating state of the clock domain of the kernel based on the kernel state information or the operation control instruction; the clock domain includes at least a main clock domain, a data transmission clock domain, a computing clock domain, a debugging domain, and a normally-on clock domain; Determining the target operating state of the clock domain of the core at least includes: determining the clock frequency state of each domain included in the clock domain based on the core state information obtained according to the set operating cycle; The kernel status information includes kernel usage frequency, cache hit status, and instruction type information. The determining the clock frequency status of each domain included in the clock domain based on the kernel status information obtained according to a set operating cycle includes: in response to the kernel usage frequency obtained according to a set first operating cycle satisfying a set frequency threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency status; in response to the cache hit status obtained according to a set second operating cycle satisfying a set hit rate threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency status; determining a first instruction quantity of vector type calculation instructions included in the instruction type information obtained according to a set third operating cycle, and adjusting the clock frequency of each domain included in the clock domain based on the first instruction quantity to obtain a corresponding clock frequency status; determining a second instruction quantity of floating-point type calculation instructions included in the instruction type information obtained according to a set fourth operating cycle, and adjusting the clock frequency of each domain included in the clock domain based on the second instruction quantity to obtain a corresponding clock frequency status; A control module is used to determine an adjustment signal corresponding to the core based on the target operating state, and send the adjustment signal to the power domain and / or clock domain of the core to control the operating state of the core.

7. The device according to claim 6, characterized in that The acquisition module is used to: Obtaining the usage frequency and cache hit status of the core when processing the current thread; In the case of processing the current thread, obtaining instruction type information of the executed instruction from the decoding stage corresponding to the kernel; The kernel status information is determined based on the usage frequency, cache hit status, and instruction type information.

8. The device according to claim 6, characterized in that The determining module is used for at least one of the following: Determining a power switch state of each domain included in the power domain based on a power switch signal included in the operation control instruction; Determining a voltage state of each domain included in the power domain based on a voltage control signal included in the operation control instruction; Based on the register information included in the core state information, the power switch state of each domain included in the power domain is determined.

9. The device according to claim 6, characterized in that The determining module is used for at least one of the following: Determining a clock switch state of each domain included in the clock domain based on a clock switch signal included in the operation control instruction; Based on the clock frequency control signal included in the operation control instruction, the clock frequency status of each domain included in the clock domain is determined.

10. The device according to claim 6, characterized in that The device further includes a storage module, wherein the storage module is configured to: In response to the current thread completing execution, storing the target address information and the target running state corresponding to the current thread in a history information table; Adjusting the kernel from a target operating state to a normal operating state; In response to the address information corresponding to the next thread matching the target address information, determining the corresponding target running state from the history information table; Based on the determined target operating state, an adjustment signal corresponding to the core is determined, and the adjustment signal is sent to a power domain and / or a clock domain of the core to control the operating state of the core.

11. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

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