Sequence generation device, chip testing device, chip testing equipment and sequence generation method

Abstract

The invention discloses a sequence generation device, a chip testing device, chip testing equipment and a sequence generation method, and relates to the technical field of computers. The sequence generation device comprises a first SR module, a second SR module and a configuration module, the first SR module is used for executing a first shift operation to generate a first output sequence; sending the first output sequence to a configuration module; the configuration module is used for determining a sequence generation rule of the second SR module based on the first output sequence; and the second SR module is used for executing a second shift operation to generate a second output sequence based on the sequence generation rule. The first SR module can randomly generate different output sequences, and the corresponding configuration module can determine various sequence generation rules, so that the second SR module can switch different rules to generate the output sequences, the diversity of the sequences is increased, the diversity of the test vectors generated based on the sequences is improved, and the test efficiency is improved. The test coverage rate of the chip is improved, and the test reliability is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of computer technologies, and in particular, to a sequence generation device, a chip test device, a device, and a sequence generation method. Background Art

[0002] Chip testing is an important step in the chip preparation process. In chip testing, it is necessary to input test vectors to the prepared chips and determine the operation accuracy rate of the chips based on the operation results of the test vectors output by the chips.

[0003] In related technologies, in order to quickly generate test vectors, test vectors are usually automatically generated by a Linear Feedback Shift Register (LFSR). In the LFSR, the values in the register are shifted one bit to the right as a whole in each clock cycle. The value of the rightmost register is output, and the leftmost register is filled with a new value according to a preset operation rule; by continuously repeating this process, the LFSR can continuously generate a sequence, and this sequence can be used as the test vector of the chip.

[0004] However, under the influence of the preset operation rule, after a certain number of clock cycles, the sequence generated by the LFSR will gradually evolve into a regular sequence, resulting in strong regularity of the test vectors, limitations in the coverage of chip testing, and thus reducing the credibility of the testing. Summary of the Invention

[0005] Embodiments of the present application provide a sequence generation device, a chip test device, a device, and a sequence generation method, and the technical solutions are as follows:

[0006] On the one hand, a sequence generation device is provided. The sequence generation device includes: a first shift register SR module, a second SR module, and a configuration module;

[0007] The first SR module is configured to perform a first shift operation to generate a first output sequence; and send the first output sequence to the configuration module;

[0008] The configuration module is configured to determine a sequence generation rule of the second SR module based on the first output sequence, where the sequence generation rule is used to indicate a rule for performing a shift operation to generate an output sequence; and indicate the sequence generation rule to the second SR module;

[0009] The second SR module is configured to perform a second shift operation to generate a second output sequence based on the sequence generation rule.

[0010] On the other hand, a chip test device is provided. The chip test device includes the sequence generation device as described above.

[0011] In some embodiments, the chip test device further includes: a chip to be tested; the sequence generation device for sending the second output sequence to the chip to be tested; the chip to be tested for generating a test vector based on the second output sequence and performing a chip test operation according to the test vector.

[0012] On the other hand, a computer device is provided, which includes the sequence generation device as described above, or the computer device includes the chip test device as described above.

[0013] On the other hand, a sequence generation method is provided, which is executed by a sequence generation device. The sequence generation device includes: a first shift register SR module, a second SR module, and a configuration module. The method includes:

[0014] The first SR module performs a first shift operation to generate a first output sequence and sends the first output sequence to the configuration module.

[0015] The configuration module determines a sequence generation rule for the second SR module based on the first output sequence. The sequence generation rule is used to indicate a rule for performing a shift operation to generate an output sequence, and the configuration module indicates the sequence generation rule to the second SR module.

[0016] The second SR module performs a second shift operation based on the sequence generation rule to generate a second output sequence.

[0017] On the other hand, a sequence generation method is provided, which is executed by a configuration module. The method includes:

[0018] Obtaining a first output sequence, where the first output sequence is a sequence generated by the first SR module performing a first shift operation.

[0019] Determining a sequence generation rule for the second SR module based on the first output sequence. The sequence generation rule is used to indicate a rule for performing a shift operation to generate an output sequence.

[0020] Indicating the sequence generation rule to the second SR module. The second SR module is used to perform a second shift operation based on the sequence generation rule to generate a second output sequence.

[0021] On the other hand, a computer device is provided, which includes a processor and a memory. At least one instruction, at least one program, a code set, or an instruction set is stored in the memory. The at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement any one of the above sequence generation methods.

[0022] On the other hand, a computer-readable storage medium is provided, in which at least one instruction, at least one program, a code set or an instruction set is stored, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the sequence generation method described in any one of the above.

[0023] On the other hand, a computer program product or a computer program is provided. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the sequence generation method described in any one of the above.

[0024] The beneficial effects brought by the technical solutions provided in the embodiments of the present application at least include:

[0025] A sequence generation device including a dual SR module is provided. In the sequence generation device, an output sequence generated by a first SR module is analyzed by a configuration module to dynamically determine a sequence generation rule, and a second SR module generates an output sequence based on the sequence generation rule dynamically determined by the configuration module. Since the first SR module randomly generates different output sequences, the corresponding configuration module determines multiple sequence generation rules, enabling the second SR module to switch different rules to generate output sequences, increasing the diversity of the sequences, thereby improving the diversity of test vectors generated based on the sequences, facilitating improving the test coverage rate of the chip, and enhancing the test credibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 is a schematic diagram of a sequence generation device provided by an exemplary embodiment of the present application;

[0028] Figure 2 is a structural block diagram of a sequence generation device provided by an exemplary embodiment of the present application;

[0029] Figure 3 is a structural block diagram of a sequence generation device provided by another exemplary embodiment of the present application;

[0030] Figure 4 is a structural block diagram of a sequence generation device provided by yet another exemplary embodiment of the present application;

[0031] Figure 5 It is a schematic structural diagram of an LFSR provided by an exemplary embodiment of the present application;

[0032] Figure 6 It is a schematic structural diagram of an LFSR provided by another exemplary embodiment of the present application;

[0033] Figure 7 It is a schematic structural diagram of an LFSR provided by yet another exemplary embodiment of the present application;

[0034] Figure 8 It is a schematic structural diagram of an LFSR provided by still another exemplary embodiment of the present application;

[0035] Figure 9 It is a schematic diagram of a switching circuit structure provided by an exemplary embodiment of the present application;

[0036] Figure 10 It is a schematic diagram of a switching circuit structure provided by another exemplary embodiment of the present application;

[0037] Figure 11 It is a schematic diagram of a finite state machine provided by an exemplary embodiment of the present application;

[0038] Figure 12 It is a flowchart of a sequence generation logic provided by an exemplary embodiment of the present application;

[0039] Figure 13 It is a flowchart of a sequence generation method provided by an exemplary embodiment of the present application;

[0040] Figure 14 It is a block diagram of a computer device provided by an exemplary embodiment of the present application. Detailed implementation manners

[0041] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0042] In the present application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects. It should be understood that there is no logical or temporal dependency between "first" and "second", nor are the quantity and execution order limited.

[0043] First, introduce the nouns involved in the embodiments of the present application.

[0044] Shift Register (SR): A digital circuit element composed of multiple register units (e.g., flip-flops). Each register unit can store one bit of binary number (0 or 1). For example, a 4-bit SR is composed of 4 flip-flops and can store a 4-bit binary sequence, such as 0101. The SR can perform shift operations on the stored data under the control of a clock signal. For example, in a 4-bit SR, if the currently stored data is 0101, after performing a right shift operation, the "1" stored in the rightmost register unit is output, and the leftmost register unit becomes empty. Assuming the binary number filled in the leftmost register unit is "0", then after the right shift operation, the sequence stored in the SR is updated to 0010.

[0045] Feedback Shift Register (FSR): A special type of SR, composed of multiple register units and a feedback unit. The feedback unit can receive data from the register units and then perform logical operations (such as exclusive OR operation, AND operation, OR operation, etc.) on these data to generate a feedback value. This feedback value can be used as the data filled in the register unit after the FSR performs a shift operation. For example, in a 4-bit FSR, if the currently stored sequence is 0101, assuming the feedback logic of the feedback unit is to perform an exclusive OR operation on the data of the 1st and 3rd bits to obtain the feedback value, after performing a right shift operation, the "1" stored in the rightmost register unit is output, and the leftmost register unit becomes empty. Performing an exclusive OR operation on the 1st and 3rd bits of the original stored data "0101" gives the binary number "0", and "0" is filled in the leftmost register unit. Then, after the right shift operation, the sequence stored in the FSR is updated to 0010.

[0046] Linear Feedback Shift Register (LFSR): A special type of FSR. When the feedback logic corresponding to the feedback unit in the FSR is linear, it can be called an LFSR. When the feedback logic is linear, it means that the feedback value is obtained through a linear combination operation on the data stored in the register units. This linear combination operation is mainly exclusive OR operation.

[0047] The LFSR can generate a random number sequence, which can be applied in multiple fields. For example:

[0048] (1) In the field of communication, the random number sequence generated by the LFSR is sent as a test signal into the communication channel. At the receiving end, the received signal is compared with the original sequence, and the bit error rate is calculated by counting the number of error bits, thereby evaluating the quality of the communication channel.

[0049] (2) In the field of information security, a random key stream with good randomness and unpredictability is generated using the random number sequence generated by the LFSR. This key stream is XORed bit by bit with the plaintext to achieve encryption. At the receiving end, the same key stream is generated using the same LFSR for decryption to recover the plaintext and ensure the confidentiality of communication.

[0050] (3) In the field of chips, a test vector is generated using the random number sequence generated by the LFSR. This test vector can be used for chip testing. The embodiments of this application mainly take the application of the LFSR in chip testing as an example for illustration.

[0051] Chip testing is an important step in the chip preparation process. In chip testing, a test vector needs to be input to the prepared chip, and the operation accuracy rate of the chip is judged based on the operation result of the test vector output by the chip. In the related art, in order to quickly generate test vectors, test vectors are usually automatically generated by the LFSR. In the LFSR, the values in the registers are shifted one bit to the right as a whole in each clock cycle. The value of the rightmost register is output, and the leftmost register is filled with a new value according to a preset operation rule; by continuously repeating this process, the LFSR can continuously generate a sequence, and this sequence can be used as the test vector of the chip. However, under the influence of the preset operation rule, after a certain number of clock cycles, the sequence generated by the LFSR will gradually evolve into a regular sequence, resulting in a strong regularity of the test vector and limitations in the coverage of chip testing, thereby reducing the credibility of the test.

[0052] Based on this, this application provides a sequence generation device including a dual SR module. Figure 1 The figure shows a schematic diagram of a sequence generation device provided by the embodiments of this application. Figure 1 In the shown sequence generation device 100, the first SR module is implemented as a first LFSR (4-bit LFSR), and the second SR module is implemented as a second LFSR (4-bit LFSR). As Figure 1 shown, the sequence generation device 100 includes: a first LFSR, a second LFSR, a configuration module, and a control module.

[0053] Schematically, the control module can be implemented as a Finite-State Machine (FSM). The following introduces the process of the control module controlling the sequence generation device 100 to generate an output sequence.

[0054] 1. Initialize the first LFSR.

[0055] The control module sends an initialization control signal to the first LFSR. After receiving the initialization control signal, the first LFSR performs an initialization operation. For example: (1) Initialize the content of the register unit by loading a pre-determined binary sequence (initial sequence) into each register unit of the LFSR; (2) Initialize the input of the feedback unit to determine which register unit values need to be input to the feedback unit for XOR operation.

[0056] After the first LFSR finishes initialization, the first LFSR starts to generate an output sequence. The initial sequence of the first LFSR can be "1001". Assume that the values of the register units in the 1st and 3rd positions need to be input to the feedback unit for XOR operation. At the 1st clock cycle, the first LFSR performs a right shift operation and outputs 1. The currently stored initial sequence is updated to "1100" (XOR 1 and 0 to get 1, and move 1 to the leftmost empty position). Take "1100" as the newly generated sequence and iterate this operation to continuously generate the output sequence of the first LFSR. The output sequence of the first LFSR will be sent to the configuration module.

[0057] 2. Configure the rules of the second LFSR.

[0058] The control module sends a rule configuration signal (update_select_en) to the configuration module. After receiving the rule configuration signal, if the rule configuration signal is at a high level, the sequence generation device 100 enters the rule configuration mode. In the rule configuration mode, the configuration module determines the feedback logic (i.e., the sequence generation rule) corresponding to the feedback unit of the second LFSR according to the received output sequence of the first LFSR. For example: if the output sequence of the first LFSR is "1100", then determine that the feedback logic corresponding to the feedback unit of the second LFSR is: perform XOR operation on the data in the 1st and 2nd positions to obtain the feedback value. After the configuration module determines the feedback logic, it sends a rule indication signal to the second LFSR. After receiving the rule indication signal, the second LFSR configures the feedback unit according to the rule indication signal, so that the stored data in the 1st and 2nd register units are input to the feedback unit for XOR operation.

[0059] After the feedback logic of the second LFSR is configured, the control module controls the rule configuration signal to be at a low level, so that the sequence generation device 100 exits the rule configuration mode.

[0060] 3. Update the initial sequence of the first LFSR.

[0061] The control module sends an initial sequence update signal (update_seed_en) to the first LFSR. After receiving the initial sequence update signal, if the initial sequence update signal is at a high level, the sequence generation device 100 enters the initial sequence update mode. In the initial sequence update mode, the first LFSR will perform an initial sequence update. For example, the sequence stored in each register unit of the current first LFSR is updated from "1001" to "0011", and "0011" is used as the initial sequence.

[0062] 4. Control the second LFSR to generate an output sequence.

[0063] After the initial sequence update of the first LFSR is completed, the control module controls the initial sequence update signal to be at a low level, so that the sequence generation device 100 enters the sequence generation mode. In the sequence generation mode, the first LFSR will generate an output sequence with "0011" as the initial sequence and send the generated output sequence to the configuration module. The configuration module will configure the initial sequence of the second LFSR according to the received output sequence of the first LFSR. For example, the output sequence of the first LFSR is also the initial sequence "0011" of the first LFSR, and "0011" is loaded into each register unit of the second LFSR as the initial sequence of the second LFSR.

[0064] After the initial sequence configuration of the second LFSR is completed, the second LFSR will perform a shift operation starting from this initial sequence and generate an output sequence according to the previously configured feedback logic (performing an exclusive OR operation on the data of the first and second bits to obtain the feedback value).

[0065] Optionally, the above first LFSR and second LFSR can be implemented as a hybrid ring LFSR.

[0066] In summary, the embodiment of the present application provides a sequence generation device including a dual LFSR. In the sequence generation device, on the one hand, through the control module and the configuration module, the sequence generation rule of the second LFSR can be dynamically determined according to the output sequence generated by the first LFSR, increasing the variability of the sequence generation rule in the second LFSR, so that the second LFSR is no longer limited to a fixed preset rule, thereby generating diverse output sequences; on the other hand, through the control module and the configuration module, the first LFSR can generate a new output sequence according to the updated initial sequence, and thus the initial sequence of the second LFSR can be dynamically determined according to the newly generated output sequence of the first LFSR, further improving the diversity of the output sequence generated by the second LFSR, thereby improving the diversity of test vectors, being beneficial to improving the test coverage rate of the chip, and improving the test credibility.

[0067] Next, describe the sequence generation device provided by the embodiments of the present application.

[0068] Please refer to Figure 2 , which shows a structural block diagram of a sequence generation device 200 provided by an exemplary embodiment. The sequence generation device 200 includes: a first shift register SR module 210, a second shift register SR module 220, and a configuration module 230. Among them, the first SR module 210 is connected to the configuration module 230, and the second SR module 220 is connected to the configuration module 230.

[0069] Optionally, the sequence generation device is a hardware device for performing sequence generation operations. Schematically, the sequence generation device can be implemented as at least one of an FPGA (Field-Programmable Gate Array), a CPLD (Complex Programmable Logic Device), a test circuit designed inside a chip (Design For Test, DFT), etc. The sequence generated by the sequence generation device can be binary data, decimal data, hexadecimal data, etc. In the embodiments of the present application, the case where the sequence generation device generates a binary sequence is mainly used as an example for illustration.

[0070] In some embodiments, the above sequence generation device can be used to generate test vectors. Schematically, a sequence generation device is set in a chip test device, and test vectors are generated according to the output sequence generated by the sequence generation device, and then the test vectors are used for chip testing. The number of sequence generation devices set in the chip test device can be one or more.

[0071] Next, introduce each execution module in the sequence generation device.

[0072] ● The first SR module 210

[0073] Optionally, the first SR module is a hardware module in the sequence generation device for generating a first output sequence, and the first output sequence is used to configure the second SR module. Schematically, the first SR module can be implemented as at least one of a shift register, a feedback shift register, a linear feedback shift register, etc. Schematically, the first SR module can be implemented as a hybrid ring linear feedback shift register.

[0074] ● The second SR module 220

[0075] Optionally, the second SR module is a hardware module in the sequence generation device for generating a second output sequence to be used (such as an output sequence for generating test vectors). Schematically, the second SR module can be implemented as at least one of a shift register, a feedback shift register, a linear feedback shift register, etc. Schematically, the second SR module can be implemented as a hybrid ring linear feedback shift register.

[0076] In some embodiments, the first SR module includes at least two register units and a feedback unit; the second SR module includes at least two register units and a feedback unit.

[0077] Regarding the register unit and feedback unit involved in the present application:

[0078] The register unit is the basic storage unit in the SR module, and each register unit can store one bit of binary data. For example, in a 4-bit SR module, there are 4 register units, which can store a 4-bit binary number, such as 0101. The feedback unit is used to perform a feedback operation on the output data of the specified memory unit in at least two register units according to the feedback logic to obtain a feedback value. For example, in an SR module, the feedback unit performs a logical operation (such as exclusive OR operation or equivalence operation, etc.) on the stored data of certain register units to obtain a feedback value a.

[0079] Triggered by the clock signal, the register unit will perform a data shift operation. Taking the serial shift mode as an example, in an SR module including 3 register units r1, r2, and r3, in the current clock cycle, the data stored in r1 is 1, and the data stored in r2 and r3 is 0. In the next clock cycle, the feedback unit performs a logical operation on the stored data of register units r1 and r2 to obtain a feedback value, and then the SR module performs a right shift operation; after the SR module performs a right shift operation, the data in r1 will move to r2, r1 becomes empty, the data in r2 will move to r3, the data in r3 will be output, and the feedback value will be filled in r1. Optionally, the feedback unit is composed of logic gate circuits. Taking LFSR as an example, the feedback unit can use exclusive OR gates to implement the feedback logic, and the feedback logic is the sequence generation rule described below, which is usually represented in the form of a characteristic polynomial in LFSR.

[0080] In some embodiments, the second SR module is implemented as a reconfigurable hardware module. Schematically, a reconfigurable hardware module refers to a hardware module whose internal structure or function can be changed during operation. That is to say, the second SR module is not a module for implementing a fixed function, and the second SR module can dynamically adjust its circuit connection mode and data processing flow according to external control signals.

[0081] ● Configuration module 230

[0082] Optionally, the configuration module is a hardware module in the sequence generation device for configuring the second SR model. Schematically, the configuration module can be implemented as a hardware module formed by connecting multiple registers in series. These multiple registers are used to: determine the sequence generation rule for the second SR module according to the output sequence of the first SR module, determine the initial sequence of the second SR module according to the output sequence of the first SR module, etc.

[0083] Optionally, the configuration module is used to dynamically configure the second SR module, and the content that can be dynamically configured in the second SR module includes at least one of the following:

[0084] (1) Sequence generation rule.

[0085] The sequence generation rule is used to indicate the rule for performing a shift operation to generate an output sequence. Optionally, the sequence generation rule includes at least one of the following rules:

[0086] (1) The feedback logic corresponding to the feedback unit.

[0087] The feedback logic can be represented by a logic function, such as the characteristic polynomial in an LFSR.

[0088] In some embodiments, the feedback logic indicates the operation rule of the feedback operation.

[0089] Optionally, the operation rule of the feedback operation can be implemented as basic logic operations such as exclusive OR, AND, OR, equivalence, etc., and can also be implemented as a more complex logic combination. For example, the operation rule of the feedback operation can be to first perform an AND operation on the outputs of several register units, and then perform an exclusive OR operation on the result and the output of another register unit to generate a feedback value.

[0090] In some embodiments, the feedback logic indicates the register units participating in the feedback.

[0091] Schematically, different register units are selected from multiple register units to participate in the feedback operation. For example, in the second SR module (including register units r1, r2, and r3), initially it can be indicated that the stored data of r2 and r3 participate in the feedback operation, and after configuration, it can be switched to the stored data of r1 and r3 participating in the feedback operation.

[0092] (2) Shift operation execution rule.

[0093] The execution rule of the shift operation includes at least one of sequential shift, skip shift, etc. Sequential shift means sequentially shifting data from one register unit to the next in the order of r1, r2, r3. Skip shift can be set to shift every other register unit, that is, shift from r1 to r3, from r2 to r1, etc.

[0094] (3) The number of bits of the second SR module.

[0095] The number of bits of the second SR module can be implemented as the number of activated register units in the second SR module. For example, if 5 register units are activated, then the number of bits of the second SR module is 5 bits, and a 5-bit second SR module can be used to store and process a 5-bit data sequence.

[0096] It should be noted that the above examples of sequence generation rules are only illustrative. In the embodiments of the present application, other sequence generation rules can also be dynamically configured according to user requirements and hardware environments. For example: configuring sequence output rules, and the output rules include serial output, parallel output, etc.; when outputting serially, the sequence data is output bit by bit from the register unit, and when outputting in parallel, the data of multiple register units is output simultaneously. The output format of the sequence can also be configured. For example: according to the radix requirement of the chip test vector required (such as: the test vector requirement is hexadecimal), the data output from the register unit is converted into a sequence that meets the radix requirement for output.

[0097] (2) Initial sequence.

[0098] The initial sequence refers to a set of data pre-loaded into the register unit before the second SR module starts sequence generation operations (such as shift, feedback, etc.). In the LFSR, the initial sequence can be called a "seed", and the "seed" is the starting point of the output sequence generated by the LFSR.

[0099] In some embodiments, the configuration module can also configure the first SR module. Optionally, the sequence generation device further includes a third SR module, and the third SR module is a hardware module in the sequence generation device for generating a fourth output sequence, and the fourth output sequence is used to configure the first SR module. Similarly, in some embodiments, the sequence generation device can also include a module for configuring the third SR module. That is to say, in the embodiments of the present application, the sequence generation device can be a multi-level generation device composed of multiple SR modules and a configuration module, including a multi-level configuration structure. For example: the third SR module configures the first SR module, and the first SR module configures the second SR module. Optionally, the configuration modules for configuring different SR modules can be the same or different. For example: the third SR module configures the first SR module through the first configuration module, and the first SR module configures the second SR module through the second configuration module, and the first configuration module and the second configuration module are different.

[0100] In the embodiments of the present application, the configuration of the second SR module by the first SR module is taken as an example for illustration.

[0101] The following will introduce the sequence generation process processed by each execution module in the Figure 2 sequence generation device shown. Introduction.

[0102] The first SR module 210 is used to perform a first shift operation to generate a first output sequence; and send the first output sequence to the configuration module 230.

[0103] Optionally, the first SR module includes at least two register units and a feedback unit.

[0104] Among them, the first shift operation refers to shifting the data stored in at least two register units in the first SR module in a preset shift direction. Optionally, the preset shift direction can be left or right.

[0105] In some embodiments, the feedback unit in the first SR module corresponds to first feedback logic; the first feedback logic is used to indicate the rule for the feedback unit in the first SR module to generate a feedback value.

[0106] Optionally, the feedback unit in the first SR module is used to process the data stored in at least two register units in the first SR module based on the first feedback logic to generate a second feedback value. At least two register units in the first SR module are used to perform the first shift operation, and there are idle storage units in at least two register units in the first SR module after performing the first shift operation; the feedback unit is further used to store the second feedback value into the idle register units in at least two register units in the first SR module; at least two register units in the first SR module are further used to output a second sequence value, and the second sequence value belongs to the first output sequence.

[0107] Schematically, the first feedback logic can be used to indicate that the register units at the specified logical positions in the first SR module generate feedback values. For example, the first feedback logic indicates that the data stored in the register units at the 1st and 3rd positions in the first SR module perform an exclusive OR operation to obtain the second feedback value. After performing the first shift operation, the second feedback value is stored into the idle register units in at least two register units in the first SR module. Schematically, if the first SR module performs a right shift operation and the leftmost register unit becomes empty, the second feedback value can be stored in the leftmost register unit.

[0108] Among them, the second sequence value is the stored data shifted out of the first SR module after performing the first shift operation. Schematically, the value shifted out of at least two register units in the first SR module after performing the first shift operation is a sequence value, and this sequence value is a part of the first output sequence; for example, the first SR module includes 4 register units, and one data bit is shifted out each time a shift operation is performed. After 4 shift operations, 4 sequence values will be shifted out, and combining these 4 sequence values in order will obtain the first output sequence. Or, the second sequence value is the data stored in at least two register units in the current first SR module after performing the first shift operation. Schematically, after performing the first shift operation, the data stored in at least two register units in the current first SR module is output, and the output stored data is the second sequence value, which is also the first output sequence.

[0109] Optionally, a first SR module is configured to perform a first shift operation when receiving a clock signal. Illustratively, when triggered by the rising edge (the instant when the signal changes from low level to high level) or the falling edge (the instant when the signal changes from high level to low level) of the clock signal, the first SR module performs the first shift operation.

[0110] Optionally, after generating the first output sequence, the first SR module outputs the first output sequence to the configuration module.

[0111] The configuration module 230 is configured to receive the first output sequence, determine the sequence generation rule of the second SR module 220 based on the first output sequence, and indicate the sequence generation rule to the second SR module 220.

[0112] The second SR module 220 is configured to perform a second shift operation based on the sequence generation rule to generate a second output sequence.

[0113] Wherein, the sequence generation rule is used to indicate the rule for performing a shift operation to generate an output sequence. Optionally, the sequence generation rule includes at least one of the feedback logic corresponding to the feedback unit, the shift operation execution rule, the number of bits of the second SR module, etc. Hereinafter, an example in which the sequence generation rule is implemented as the feedback logic corresponding to the feedback unit will be described.

[0114] In some embodiments, the second SR module includes a feedback unit and at least two register units. The sequence generation rule is used to indicate the rule for the feedback unit to generate a feedback value, and the feedback value is used to be written into at least two register units after performing the second shift operation.

[0115] Illustratively, the rule for the feedback unit to generate a feedback value, that is, the feedback logic corresponding to the feedback unit, can be referred to as the second feedback logic; the feedback value can be understood as the new input value in the second SR module. That is to say, the sequence generation rule indicates how to generate a new input value in the second SR module.

[0116] In some embodiments, the feedback unit is configured to process the data stored in at least two register units according to the sequence generation rule to generate a first feedback value; at least two register units in the second SR module are configured to perform a second shift operation, and there are idle storage units in at least two register units in the second SR module after performing the second shift operation; the feedback unit is further configured to store the first feedback value into the idle register unit among at least two register units in the second SR module; at least two register units are further configured to output a first sequence value, and the first sequence value belongs to the second output sequence.

[0117] Schematically, if the sequence generation rule indicates that an exclusive OR operation is performed on the data stored in the register cells at the 1st and 3rd positions in the second SR module to obtain the first feedback value. After performing the second shift operation, the first feedback value is stored in the idle register cell among at least two register cells in the second SR module. Schematically, if the leftmost register cell becomes empty after the second SR module performs a right shift operation, the first feedback value can be stored in the leftmost register cell.

[0118] Wherein, the first sequence value is the stored data shifted out of the second SR module after performing the second shift operation. Schematically, the values shifted out of at least two register cells in the second SR module after performing the second shift operation are sequence values, and this sequence value is a part of the second output sequence. For example, if the first SR module includes 4 register cells, and one bit of data is shifted out each time a shift operation is performed, after 4 shift operations, 4 sequence values will be shifted out, and combining these 4 sequence values in order will obtain the second output sequence. Alternatively, the first sequence value is the data stored in at least two register cells in the current second SR module after performing the second shift operation. Schematically, after performing the second shift operation, the stored data in at least two register cells in the current second SR module is output, and the output stored data is the first sequence value, which is also the second output sequence.

[0119] In the above embodiments, the sequence generation rule can be implemented as the feedback rule corresponding to the feedback unit. By dynamically configuring the sequence generation rule, diverse feedback value generation methods can be generated, thereby improving the diversity of the final second output sequence.

[0120] Optionally, the second SR module is configured to perform a second shift operation upon receiving a clock signal.

[0121] In some embodiments, the sequence generation rule is used to indicate that a feedback value is generated by the register cells at the specified logical positions in the second SR module. The feedback unit is connected to the register cells at the specified logical positions.

[0122] Optionally, the configuration module is configured to determine the specified logical positions based on the first output sequence; generate a sequence generation rule based on the specified logical positions; indicate the sequence generation rule to the feedback unit of the second SR module; wherein, the feedback unit is configured to obtain the first data stored in the register cells at the specified logical positions in the current second SR module based on the sequence generation rule; and generate a first feedback value according to the first data.

[0123] Schematically, assuming there are register cells A, B, and C, and the sequence generation rule is: perform an exclusive OR operation on the values of A and C, and the result is the first feedback value. In an LFSR, the specified logical positions can be referred to as "taps", and the taps determine which register bits will participate in the feedback logic to generate the feedback value.

[0124] Optionally, the method for determining a specified logical bit based on the first output sequence includes at least one of the following methods:

[0125] (1) Determine logical bit indication information based on the first output sequence, and determine the bits with values of a preset value in the logical bit indication information as the specified logical bits.

[0126] Schematically, the number of bits of the logical bit indication information is the same as the number of bits of the second SR module. For example, if the number of bits of the second SR module is 4 bits (including 4 register units), and the logical bit indication information is 0101, assuming the preset value is 1, then the second bit and the fourth bit of the second SR module are used as the specified logical bits.

[0127] Optionally, use the first output sequence as the logical bit indication information. Schematically, the first output sequence includes at least two sequence values, and the at least two sequence values correspond one-to-one to at least two register units in the second SR module. Determine the logical bits of the register units corresponding to the target sequence value as the specified logical bits, where the target sequence value refers to the sequence value in the first output sequence with a value of the preset value. For example, if the first output sequence is 0101, then the first and fourth bits are used as the specified logical bits. Optionally, the number of bits of the first SR module and the second SR module is the same, denoted as n. After triggering a clock signal once, the first SR module performs a first shift operation, and uses the n-bit data stored in the first SR module after performing the first shift operation as the first output sequence, outputs the first output sequence to the configuration module, the configuration module reads the first output sequence, determines the bits with sequence values of the preset value in the first output sequence as the specified logical bits, and the configuration module indicates the specified logical bits to the second SR module.

[0128] Alternatively, perform a sequence update operation on the first output sequence, and determine the updated first output sequence as the logical bit indication information. Optionally, when the number of bits of the first output sequence is equal to the number of bits of the second SR module, perform an update operation on the first output sequence, and use the result of the operation as the logical bit indication information. For example, if the first output sequence is 0101, perform an exclusive OR operation on the 2nd and 3rd bits, update the exclusive OR result to the 1st bit, and obtain the updated first output sequence "1101", then use the 1st, 2nd, and 4th bits as the specified logical bits. Optionally, when the number of bits of the first output sequence is greater than the number of bits of the second SR module, perform a merging operation on the first output sequence, and use the result of the operation as the logical bit indication information. For example, if the first output sequence is 01010, perform an exclusive OR operation on the 4th and 5th bits, update the exclusive OR result to the 4th bit, and delete the 5th bit, obtaining the updated first output sequence "0101", then use the 2nd and 4th bits as the specified logical bits. When the number of bits of the first output sequence is less than the number of bits of the second SR module, perform a padding operation on the first output sequence, and use the result of the operation as the logical bit indication information. For example, if the first output sequence is 001, perform an exclusive OR operation on the 1st and 2nd bits, supplement the exclusive OR result to the 4th bit, and obtain the updated first output sequence "0010", then use the 3rd bit as the specified logical bit.

[0129] (2) The specified logical bits include at least two logical bits; at least two logical bit combinations corresponding to the second SR module are stored in the configuration module; determine a first selection signal based on the first output sequence; select a target logical bit combination from the at least two logical bit combinations as the specified logical bits according to the first selection signal.

[0130] Schematically, assume that the first output sequence is the binary sequence 10, and the decimal number of this binary sequence is 2. Then, the 2nd logical bit combination can be selected from multiple logical bit combinations, and the logical bits included in the 2nd logical bit combination are the specified logical bits.

[0131] In the above solution, at least two logical bit combinations corresponding to the second SR module are pre-stored in the configuration module, and the specified logical bits are determined through a simple selection signal mechanism, which simplifies the process of determining the specified logical bits and improves the sequence generation efficiency.

[0132] The above examples of the method for determining the specified logical bits based on the first output sequence are only for illustrative purposes and will not be elaborated here.

[0133] In the above embodiments, the sequence generation rule indicates that the register unit of the specified logical bits in the second SR module generates a feedback value. Different first output sequences may cause different specified logical bits to be selected, thereby generating different sequence generation rules and increasing the diversity of the finally generated output sequences.

[0134] In some other embodiments, a configuration module is configured to determine a first identifier based on a first output sequence; determine a first rule identifier that matches the first identifier from rule identifiers respectively corresponding to multiple candidate generation rules; and indicate the first rule identifier to a second SR module, where the candidate generation rule corresponding to the first rule identifier is used as a sequence generation rule.

[0135] Schematically, there are multiple candidate generation rules, and each candidate generation rule has its corresponding rule identifier. These candidate generation rules are pre-set rule schemes for generating sequences, and the rule identifiers are marks used to uniquely distinguish each candidate generation rule. For example, the rule identifier of candidate generation rule 1 is p1; the rule identifier of candidate generation rule 2 is p2.

[0136] The configuration module analyzes the first output sequence to extract information that can represent some key features of the sequence, and then determines the first identifier. For example, the first identifier is determined based on the frequency distribution feature of the first output sequence. Suppose the first output sequence is a binary sequence, and through analysis, it is found that a specific subsequence 101 appears every 5 elements in the sequence. Then the configuration module takes 101 as the first identifier.

[0137] The configuration module matches the previously determined first identifier with the rule identifiers corresponding to multiple candidate generation rules. For example, if 101 in binary represents the number 5 in decimal, then the candidate generation rule with the rule identifier p5 is selected as the sequence generation rule.

[0138] In the above embodiments, selecting from a pre-set finite number of candidate generation rules to determine the sequence generation rule reduces the complexity of the sequence generation device.

[0139] After determining the sequence generation rule, the configuration module indicates the sequence generation rule to the second SR module. Schematically, after determining the sequence generation rule, the configuration module configures the sequence generation rule in the second SR module.

[0140] Optionally, the method for the configuration module to configure the sequence generation rule in the second SR module is described below:

[0141] (1) Implement the configuration of the sequence generation rule through a field-programmable gate array (FPGA).

[0142] Among them, FPGA is a highly flexible programmable hardware platform, and its internal hardware circuit can be customized and programmed according to specific requirements.

[0143] Optionally, the second SR module is implemented as an FPGA. In a hardware description language, the sequence generation rule corresponds to a rule variable, where the hardware description language is used to program the hardware circuit of the second SR module. After the configuration module determines the sequence generation rule, it updates the variable value of the rule variable according to the sequence generation rule, and then reprograms the hardware circuit of the second SR module based on the updated variable value to obtain the second SR module that conforms to the sequence generation rule.

[0144] (2) The configuration of the sequence generation rule is implemented through a selector.

[0145] Optionally, the second SR module includes circuit structures and selectors respectively corresponding to at least two candidate generation rules, and the selectors are respectively connected to the at least two circuit structures.

[0146] In some embodiments, the configuration module is used to determine a selection signal according to the first output sequence, and the selection signal is used to select a first candidate generation rule from at least two candidate generation rules; send the selection signal to the selector, and the selector will select and activate the circuit structure corresponding to the first candidate generation rule. The circuit structure in the current first SR module conforms to the first candidate generation rule, that is, the currently used sequence generation rule.

[0147] It should be noted that the method for the configuration module to configure the sequence generation rule in the second SR module is only for illustrative purposes, and the embodiments of the present application do not limit this.

[0148] Optionally, the configuration module is used to receive the first output sequence when receiving a rule configuration signal; determine the sequence generation rule of the second SR module based on the first output sequence; and indicate the sequence generation rule to the second SR module. Or, the configuration module is used to automatically obtain the first output sequence based on a preset time interval, and determine the sequence generation rule in the second SR module based on the first output sequence; and indicate the sequence generation rule to the second SR module. For example, every 3 minutes, the configuration module automatically obtains the latest output sequence from the first SR module, determines the sequence generation rule in the second SR module based on the first output sequence, and then indicates the latest determined sequence generation rule to the second SR module. The second SR module will generate a sequence according to the latest determined sequence generation rule.

[0149] Optionally, the second SR module is used to perform a second shift operation based on the sequence generation rule and the initial sequence to generate a second output sequence.

[0150] For the initial sequence, in some embodiments, the configuration module is further used to configure the initial sequence of the second SR module, where the initial sequence is used to indicate the initial stored data loaded in the second SR module.

[0151] Schematically, the initial sequence refers to a set of data pre-loaded into the register unit before the second SR module starts sequence generation operations (such as shifting, feedback, etc.). In an LFSR, the initial sequence can be referred to as the "seed".

[0152] Optionally, a configuration module is used to determine the initial sequence of the second SR module based on the third output sequence, where the third output sequence is the output sequence generated by the first SR module; and to indicate the initial sequence to the second SR module. The second SR module is used to perform a second shift operation based on the sequence generation rule and the initial sequence to generate a second output sequence.

[0153] Among them, the third output sequence can be the above-mentioned first output sequence.

[0154] Alternatively, the third output sequence is a newly generated output sequence of the first SR module. Optionally, the first SR module is used to perform an initial sequence update operation, which is used to update the stored data of the current first SR module; and to perform a third shift operation based on the updated stored data to generate a third output sequence. Schematically, when the first SR module receives an initial sequence update signal, it performs the initial sequence update operation: the first SR module obtains a new initial sequence and then loads the initial sequence into at least two corresponding register units. Based on the new initial sequence, the first SR module performs a third shift operation according to its corresponding feedback logic (for example: the first feedback logic) to generate a third output sequence.

[0155] In the above embodiments, since the third output sequence can change with factors such as the input data of the first SR module, the initial sequence of the second SR module can be dynamically adjusted accordingly. When the initial sequence changes, the output sequence of the second SR module will also change, thereby improving the diversity of the output sequence generated by the second SR module.

[0156] Among them, the solution for determining the initial sequence of the second SR module based on the third output sequence further includes at least one of the following solutions:

[0157] (1) The number of bits of the stored data in the second SR module is n, where n is an integer greater than 1. The configuration module is used to determine the first n sequence values in the third output sequence as the initial sequence; or to determine a sampling interval T, where T is a positive integer greater than 1, and select one element from the third output sequence every T elements until n elements are selected to form the initial sequence; or other methods can also be used to obtain the initial sequence from the third output sequence, which is not limited here.

[0158] (2) The number of bits of the first SR module and the second SR module is the same. The third output sequence is also the initial sequence of the first SR module when performing the initial sequence update operation. The third output sequence is used as the initial sequence of the second SR module.

[0159] In some embodiments, after triggering a clock signal once, the first SR module obtains a new initial sequence and outputs the initial sequence to the configuration module. The configuration module reads the initial sequence and loads the initial sequence into the second SR module.

[0160] (3) Feature extraction is performed on the third output sequence, such as counting the ratio of the number of 0s and 1s in the sequence, the maximum length of consecutive identical elements, the frequency distribution of elements, etc. Then, a feature vector is constructed based on these features, and the feature vector is converted into a binary number. The first n bits are taken as the initial sequence.

[0161] The above solution for determining the initial sequence of the second SR module based on the third output sequence is only for illustrative purposes and is not limited here.

[0162] In summary, the embodiments of the present application provide a sequence generation device including a dual SR module. In the sequence generation device, the configuration module analyzes the output sequence generated by the first SR module to dynamically determine the sequence generation rule, and the second SR module generates an output sequence based on the sequence generation rule dynamically determined by the configuration module. Since the first SR module randomly generates different output sequences, the corresponding configuration module determines multiple sequence generation rules, enabling the second SR module to switch different rules to generate output sequences, increasing the diversity of the sequences, thereby improving the diversity of the test vectors generated based on the sequences, facilitating improving the test coverage rate of the chip, and improving the test credibility.

[0163] In some embodiments, please refer to Figure 3 , the sequence generation device 200 further includes: a control module 240. The control module is respectively connected to the first SR module 210, the second SR module 220, and the configuration module 230.

[0164] ● Control module 240

[0165] The control module is a module in the sequence generation device for sending control signals, and the control signals are used to control the configuration operations of the first SR module and the configuration module on the second SR module.

[0166] Schematically, the control module can be implemented as a finite state machine (FSM). The FSM mainly configures the second LFSR by managing the states in the sequence generation device. The FSM includes five ports: TMS (Test Mode Select), TCK (Test Clock), TRST (Test Reset), TDI (Test Data Input), and TDO (Test Data Output). The FSM generates control signals to configure the second LFSR.

[0167] The following will introduce the sequence generation process processed by each execution module in the Figure 3 sequence generation device shown. Introduction.

[0168] The control module 240 sends a first control signal to the configuration module 230.

[0169] Among them, the first control signal is used to control the configuration module to enter the rule configuration mode, and the rule configuration mode is used to configure the sequence generation rule of the second SR module.

[0170] The configuration module 230 is configured to enter the rule configuration mode when receiving the first control signal.

[0171] Schematically, after receiving the first control signal, if the first control signal is at a high level, the configuration module enters the rule configuration mode.

[0172] The first SR module 210 is configured to perform a first shift operation to generate a first output sequence and send the first output sequence to the configuration module 230.

[0173] Optionally, the first SR module includes at least two register units and a feedback unit.

[0174] In some embodiments, the feedback unit in the first SR module corresponds to a first feedback logic, and the first feedback logic is used to indicate the rule for the feedback unit in the first SR module to generate a feedback value.

[0175] Optionally, a feedback unit in the first SR module is configured to generate a second feedback value based on first feedback logic for processing data stored in at least two register units in the first SR module. At least two register units in the first SR module are configured to perform a first shift operation. After performing the first shift operation, there are idle storage units in at least two register units in the first SR module. The feedback unit is further configured to store the second feedback value into an idle register unit among at least two register units in the first SR module. At least two register units in the first SR module are further configured to output a second sequence value, and the second sequence value belongs to a first output sequence. After the first SR module generates the first output sequence, the first output sequence is output to the configuration module.

[0176] The configuration module 230 is configured to, when in the regular configuration mode, determine a sequence generation rule for the second SR module 220 based on the first output sequence; and indicate the sequence generation rule to the second SR module 220.

[0177] Optionally, when the configuration module is in the regular configuration mode, the configuration module determines the sequence generation rule according to the first output sequence. For the specific method of determining the sequence generation rule, reference can be made to the above text and will not be elaborated here.

[0178] In some embodiments, when the first control signal is at a low level, the configuration module exits the regular configuration mode and indicates the sequence generation rule to the second SR module.

[0179] The control module 240 is configured to send a second control signal to the first SR module 210.

[0180] Wherein, the second control signal is used to control the first SR module to perform an initial sequence update operation, and the initial sequence update operation is used to update the stored data of the current first SR module.

[0181] The first SR module 210 is configured to perform the initial sequence update operation when receiving the second control signal.

[0182] Illustratively, after the first SR module receives the second control signal, if the second control signal is at a high level, the first SR module performs the initial sequence update operation. For example: obtaining a new initial sequence; and using this new initial sequence as the initial sequence of the first SR module.

[0183] The configuration module 230 is configured to enter the sequence generation mode when the first SR module 210 successfully performs the initial sequence update operation.

[0184] Wherein, the sequence generation mode is used to configure the initial sequence of the second SR module.

[0185] Schematically, when the first SR module successfully executes the initial sequence update operation, the second control signal is at a low level. At this time, the configuration module enters the sequence generation mode.

[0186] The configuration module 230, when in the sequence generation mode, determines the initial sequence of the second SR module 220 based on the third output sequence generated by the first SR module 210; and indicates the initial sequence to the second SR module 220.

[0187] Optionally, when the configuration module is in the sequence generation mode, the configuration module determines the initial sequence of the second SR module according to the obtained third output sequence. The specific method for determining the initial sequence can refer to the above text and will not be elaborated here. After the configuration module determines the initial sequence, it indicates the initial sequence to the second SR module.

[0188] The second SR module 220 is used to perform a second shift operation based on the sequence generation rule and the initial sequence to generate a second output sequence.

[0189] Schematically, after receiving the sequence generation rule and the initial sequence, the second SR module stores the initial sequence in at least two corresponding register units thereof, and then performs the second shift operation when receiving a clock signal.

[0190] In some embodiments, optionally, the second SR module includes at least two register units and a feedback unit.

[0191] Optionally, the feedback unit is used to process the data stored in at least two register units according to the sequence generation rule to generate a first feedback value; the at least two register units are used to perform the second shift operation, and there are idle storage units in at least two register units in the second SR module after performing the second shift operation; the feedback unit is further used to store the first feedback value in the idle register units of at least two register units in the second SR module; the at least two register units are further used to output a first sequence value, and the first sequence value belongs to the second output sequence.

[0192] In summary, for the sequence generation device provided in the embodiments of the present application, the control module sends a first control signal to the configuration module, so that the configuration module determines the sequence generation rule of the second SR module based on the output sequence of the first SR module. This makes the sequence generation rule of the second SR module not fixed, but can be dynamically adjusted according to the output sequence generated by the first SR module in real time. Thus, the sequence generation rule of the second SR module is correspondingly changed through the change of the output sequence of the first SR module to generate a sequence that meets the requirements.

[0193] On the other hand, after the first SR module successfully executes the initial sequence update operation, the control module will control the configuration module to enter the sequence generation mode, and then determine the initial sequence of the second SR module based on the third output sequence generated by the first SR module. That is to say, the initial sequence of the second SR module is not pre-fixed either, but can be flexibly set according to the update situation of the first SR module, which helps to meet the diverse sequence generation requirements.

[0194] In addition, by sending control signals of different levels, the control module can accurately make each module enter or exit the corresponding working mode. For example, when the first control signal is at a high level, the configuration module can accurately enter the rule configuration mode, ensuring the accuracy of the sequence generation process.

[0195] In some embodiments, the above-mentioned first SR module 210 can be implemented as a first LFSR, the second SR module 220 can be implemented as a second LFSR, and the control module 240 can be implemented as an FSM. Schematically, please refer to Figure 4 which shows a structural block diagram of a sequence generation device provided by an embodiment of the present application. The sequence generation device 400 includes: a first LFSR, a second LFSR, a configuration module, and an FSM.

[0196] Next, the sequence generation device provided by the present application will be introduced from three aspects: the circuit structure of the LFSR, the working process of the FSM, and the sequence generation process.

[0197] (1) Circuit structure of the LFSR

[0198] First, introduce the terms involved in the LFSR:

[0199] (1) Characteristic polynomial.

[0200] For an n-stage LFSR, its characteristic polynomial is generally expressed as:

[0201] C(x) = c0 + c1x + c2x 2 + … + c n x n , where the coefficient c i takes values of 0 or 1, and c0 = c n = 1, n is an integer greater than 1, i ≤ n and i is a positive integer.

[0202] Among them, the coefficient c i corresponds to the feedback logic of the LFSR. When c i = 1, it means that there is a connection from the i-th register unit (the i-th bit register unit) to the feedback unit; when c iWhen it is 0, it means that there is no connection from the i-th stage register unit to the feedback unit, and this characteristic polynomial is the feedback logic described above.

[0203] (2) Feedback bit.

[0204] The feedback bit refers to the position of the register unit in each register unit of the LFSR that participates in the feedback logic.

[0205] Among them, the feedback bit corresponds to the characteristic polynomial. Taking the implementation of the characteristic polynomial as C(x) = 1 + x 2 + x 3 + x 4 + x 5 as an example, the feedback bits refer to the 2nd, 3rd, 4th, and 5th register units. It should be noted that in the LFSR, the power in the characteristic polynomial represents the bit number of the register unit. For example, x 3 represents the 3rd register unit.

[0206] (3) State.

[0207] In the LFSR, the state refers to the combination of the values stored in each register unit of the LFSR. For example: The combination of the values stored in each register unit of the LFSR in the j-th clock cycle can be called the j-th state of the LFSR, where j is a positive integer.

[0208] (4) Maximum period.

[0209] In an n-stage LFSR, the maximum period is 2 n - 1. Each stage register in the n-stage LFSR has two states, 1 and 0. For n stages, there are 2 n different combined states. However, the all-0 state is a special case. When the LFSR enters the all-0 state, it will always remain in the all-0 state and cannot generate a new sequence. Therefore, when calculating the maximum period, this state needs to be excluded. Thus, the maximum period is 2 n - 1.

[0210] (5) m-sequence.

[0211] When the period of the sequence generated by the LFSR reaches the maximum period 2 n - 1, the sequence output by the LFSR is called the longest LFSR sequence, simply referred to as the m-sequence. Schematically, taking the implementation of the characteristic polynomial as C(x) = 1 + x + x 3For example, the maximum period of the LFSR is 7. Assuming the initial sequence is 110, the states of the LFSR in the first 7 cycles are as follows: 110 → 111 → 011 → 101 → 010 → 001 → 100. The m-sequence can be a combination of the values output by the LFSR in these 7 cycles, that is, the m-sequence is 110111011101010001100. In some embodiments, this m-sequence is also the output sequence involved in the present application, such as the second output sequence.

[0212] Regarding the LFSR involved in the present application, the LFSR can be implemented as at least one of a standard external LFSR (or called Fibonacci LFSR), a standard internal LFSR (or called Galois LFSR), a hybrid LFSR, a hybrid ring LFSR, etc. The circuit structures for generating the m-sequence of various LFSRs will be described below.

[0213] Regarding the standard external LFSR (or called Fibonacci LFSR), when the polynomial corresponding to the standard external LFSR is a primitive polynomial, this LFSR has the ability to generate an m-sequence. Schematically, please refer to Figure 5 , which shows a schematic diagram of a standard external LFSR. The circuit structure 500 shows a 5-stage standard external LFSR. In the circuit structure 500, it includes 5 register units: 1, 2, 3, 4, 5, and 3 exclusive-OR gates; among them, the 5 register units are connected in series, and the exclusive-OR gates are arranged outside the series circuit of the 5 register units. The characteristic polynomial corresponding to this circuit structure 500 is C(x) = 1 + x 2 +x 3 +x 4 +x 5 , and this polynomial is a primitive polynomial, that is to say, the circuit structure 500 can generate an m-sequence.

[0214] Regarding the standard internal LFSR (or called Galois LFSR), when the polynomial corresponding to the standard internal LFSR is a primitive polynomial, this LFSR has the ability to generate an m-sequence. Schematically, please refer to Figure 6 , which shows a schematic diagram of a standard internal LFSR. The circuit structure 600 shows a 5-stage standard internal LFSR. In the circuit structure 600, it includes 5-bit register units: 1, 2, 3, 4, 5, and 3 exclusive-OR gates; among them, the 5 register units are connected in series, and the exclusive-OR gates are arranged on the series circuit between adjacent two register units. The characteristic polynomial corresponding to this circuit structure 600 is C(x) = 1 + x 2 +x 3 +x 4 +x 5 , and this polynomial is a primitive polynomial, that is to say, the circuit structure 500 can generate an m-sequence.

[0215] For a hybrid LFSR, it means that when the characteristic polynomial meets the preset conditions, a special - structured LFSR can be constructed, which can reduce the number of exclusive - OR gates required. The following explains the preset conditions:

[0216] If a primitive polynomial can be rewritten in the form of C(x)=1 + b(x)+x s ×b(x), where b(x) and x s ×b(x) have no common terms (that is, in the polynomials b(x) and x s ×b(x), there are no non - zero terms with the same power), and b(x) has no common terms, s≥1 and s is an integer, then S(x)=1+^x s +x s ×b(x) can be used to implement C(x) with the corresponding hybrid LFSR. For example: the characteristic polynomial C(x)=1 + x 2 +x 3 +x 4 +x 5 , C(x)=1+(x 2 +x 3 )+x 2 ×(x 2 +x 3 ), then the hybrid LFSR of S(x)=1+^x 2 +x 4 +x 5 can be used to implement C(x). This preset condition can be called the completely decomposable condition.

[0217] Schematically, please refer to Figure 7 , which shows a schematic diagram of a hybrid LFSR corresponding to S(x)=1+^x s +x s ×b(x). In the circuit structure 700, it includes 5 register units: 1, 2, 3, 4, 5, and 2 exclusive - OR gates; among them, the 5 register units are in series, and "^x 2 " means that there is an exclusive - OR gate, which is set outside the series circuit of the 5 register units and receives the output value of register unit 2; "x 4 +x 5 " means that there is an exclusive - OR gate, which is set on the series circuit between register unit 4 and register unit 5. The characteristic polynomial corresponding to this circuit structure 700 is S(x)=1+^x 2 +x 4 +x 5 , and can be used to implement C(x)=1 + x 2 +x 3 +x 4 +x 5, that is to say, the circuit structure 700 has the ability to generate an m-sequence.

[0218] The above-mentioned Figure 5 and Figure 6 The LFSRs shown can all generate m-sequences. Assuming that the maximum-length LFSR uses k (in the LFSRs shown in Figure 5 and Figure 6 , k = 3) exclusive-OR gates to generate an m-sequence, then Figure 7 the hybrid LFSR shown only needs (k + 1)÷2 exclusive-OR gates to generate an m-sequence. That is to say, using a hybrid LFSR can generate an m-sequence with fewer exclusive-OR gates.

[0219] Regarding the hybrid ring LFSR, the hybrid ring LFSR is an LFSR obtained by constructing a ring structure on the basis of the hybrid LFSR. In the hybrid ring LFSR, there is at most one exclusive-OR gate between any two adjacent register units, and the output of each register unit drives at most 2 fan-out nodes (that is, the signal output from any one register unit can be connected to at most two other circuit nodes), thus eliminating the long feedback path and improving the operating speed of the circuit.

[0220] Please refer to Figure 8 , which shows a schematic diagram of the hybrid ring LFSR corresponding to a Figure 7 hybrid LFSR. The circuit structure 800 shows a 5-stage hybrid ring LFSR. In the circuit structure 800, there are 5 register units: 1, 2, 3, 4, 5, and 2 exclusive-OR gates. The characteristic polynomial corresponding to the circuit structure 800 is the same as the characteristic polynomial corresponding to the circuit structure 700, that is, the circuit structure 800 can also be used to implement C(x) = 1 + x 2 + x 3 + x 4 + x 5 , and has the ability to generate an m-sequence.

[0221] Assume that X = {x1, x2, x3, x4, x5} and Z = {z1, z2, z3, z4, z5} represent the current state and the next state of the circuit structure 800 respectively, then:

[0222] z1 = x5 (indicating that the state of z1 is determined by x5);

[0223] z2 = x1 (indicating that the state of z2 is determined by x1);

[0224] z3 = x2 + x3 (indicating that the state of z3 is determined by x2 and x3);

[0225] z4 = x3 (indicating that the state of z4 is determined by x3);

[0226] z5 = x1 + x4 (indicating that the state of z5 is determined by x1 and x4).

[0227] Schematically, when the shift operation is implemented as a right shift, in the circuit structure 800, the output value of register unit 1 will move to register unit 2. The output value of register unit 2 will perform an exclusive - OR operation with the output value of register unit 3 to obtain a first feedback value, and this first feedback value will move to register unit 3. The output value of register unit 3 will also move to register unit 4. The output value of register unit 4 will perform an exclusive - OR operation with the output value of register unit 1 to obtain a second feedback value, and this second feedback value will move to register unit 5. The output value of register unit 5 will also move to register unit 1. If the state of the circuit structure 800 before the shift operation is "10010", the state of the circuit structure 800 after the shift operation is "01000".

[0228] In some embodiments, the second SR module includes a cyclic linear feedback shift register (LFSR), and at least two register units in the cyclic LFSR form at least one cyclic circuit.

[0229] Schematically, a cyclic circuit is a closed loop formed by connecting at least two register units. For example, assume there are three register units A, B, and C. The output of A is connected to the input of B, the output of B is connected to the input of C, and the output of C is connected back to the input of A, thus forming a cyclic circuit. Driven by a clock signal, data circulates in the cyclic circuit. In each clock cycle, the data in the register units is shifted in the direction of the cyclic connection. For example, in the cyclic circuit formed by the above - mentioned three register units A, B, and C, in one clock cycle, the data in register unit A will move to register unit B, the data in register unit B will move to register unit C, and the data in register unit C will move to register unit A. Among them, the cyclic circuit combined with dynamically adjustable feedback logic can make the generated sequence have better randomness and complexity.

[0230] In some embodiments, the second SR module can be implemented as a hybrid cyclic LFSR. In the hybrid cyclic LFSR, there is at most one exclusive - OR gate between each register unit, and the output of each register unit drives at most two fan - out nodes. Optionally, the first SR module can also be implemented as a hybrid cyclic LFSR.

[0231] Taking the case where the first LFSR is implemented as a hybrid cyclic LFSR and the second LFSR is implemented as a hybrid cyclic LFSR as an example for illustration. The hybrid cyclic LFSR requires fewer exclusive - OR gates than the standard LFSR and can drive fewer fan - out nodes. In addition, the circuit using a cyclic structure does not have a long feedback path, so the hybrid cyclic LFSR has better circuit timing than the standard LFSR.

[0232] In the embodiments of the present application, the first LFSR is a reconfigurable LFSR, and the second LFSR is a reconfigurable LFSR. Reconfigurable means allowing the structure of the LFSR circuit to be reconfigured during runtime.

[0233] Optionally, the sequence generation rule of the second LFSR can be configured through the output sequence of the first LFSR, for example: at least one of the number of bits of the LFSR, feedback logic, ring structure parameters, etc.

[0234] (1) The number of bits of the LFSR.

[0235] If the hybrid ring LFSR includes n register units, the number of bits of the hybrid ring LFSR is e, where e is greater than or equal to n, and e is an integer greater than 1.

[0236] In hardware design, the methods for implementing the configuration of the number of bits of the LFSR include at least one of the following methods:

[0237] ● Use an extensible register array to implement the configuration of the number of bits of the LFSR.

[0238] The second LFSR is implemented as a register array. The register array can dynamically add or reduce the number of register units as needed. For example, the register array consists of several basic register units. The basic register unit includes an input, an output, and a control interface. If the configuration module receives a control signal for configuring the number of bits of the LFSR, it can obtain the output sequence of the current first LFSR, and determine the number of bits of the second LFSR according to this output sequence. For example, if the output sequence is 1001 (4 bits), the configuration module can configure the number of bits of the first LFSR to 4 bits.

[0239] ● Use a selector to implement the configuration of the number of bits of the LFSR.

[0240] Suppose two LFSR circuits with 8 bits and 16 bits are designed and connected to the selector. If the configuration module receives a control signal for configuring the number of bits of the LFSR, it can obtain the output sequence of the current first LFSR, and determine the selection signal according to this output sequence. For example: if the output sequence is 00, the selection signal is 00. When the selection signal is 00, select the 8-bit LFSR circuit; if the output sequence is 01, the selection signal is 01. When the selection signal is 01, select the 16-bit LFSR circuit.

[0241] ● Implement the configuration of the number of bits of the LFSR through a field programmable gate array (FPGA).

[0242] Optionally, the second LFSR is implemented as an FPGA, and a hardware description language is used to describe the function of the LFSR. In the hardware description language, the number of bits of the LFSR can be defined in a parameterized manner. When the number of bits of the LFSR needs to be configured, only the value of this parameter needs to be modified, and then the FPGA is recompiled and configured. Optionally, if the configuration module receives a control signal for configuring the number of bits of the LFSR, it can obtain the output sequence of the current first LFSR, determine the number of bits of the second LFSR according to this output sequence, and the configuration module will reallocate the logic units and wiring resources inside the second LFSR according to this bit parameter to construct an LFSR circuit with the corresponding number of bits.

[0243] (2) Feedback logic.

[0244] The feedback logic can be implemented as the characteristic polynomial of the LFSR. For example, for a 5-bit LFSR, if the characteristic polynomial is implemented as C(x) = 1 + x 2 + x 3 + x 4 + x 5 , it means that the values of the register units from the 2nd to the 5th bit need to be obtained for the exclusive OR operation.

[0245] In hardware design, the configuration methods for implementing the feedback logic include at least one of the following methods:

[0246] ● Use a selector to implement the configuration of the feedback logic.

[0247] In the second LFSR, a selector is inserted between each tap position and the exclusive OR gate. If the configuration module receives a control signal for configuring the feedback logic, it can obtain the output sequence of the current first LFSR, determine the selection signal according to this output sequence. For example, if the output sequence is 1001, the selection signal is 1001; the configuration module sends the selection signal to the corresponding multiplexer to implement the configuration of the feedback logic.

[0248] For example, for a 4-bit LFSR, a 2-1 selector is connected between each register unit and the exclusive OR gate. Among them, when the selection signal received by the selector is 0, the corresponding register unit does not participate in the feedback operation, and when the selection signal received by the selector is 1, the corresponding register unit participates in the feedback operation, that is, it is called the feedback bit.

[0249] ● Implement the configuration of the feedback logic through a field programmable gate array (FPGA).

[0250] Optionally, the second LFSR is implemented as an FPGA, and a hardware description language is used to describe the functions of the LFSR. In the hardware description language, the feedback logic can be defined in a parameterized manner. Optionally, if the configuration module receives a control signal for configuring the feedback logic, it can obtain the output sequence of the current first LFSR, determine the feedback logic parameters based on this output sequence, and the configuration module will reallocate the logic units and wiring resources inside the second LFSR according to these feedback logic parameters to construct the corresponding LFSR circuit.

[0251] (3) Ring structure parameters.

[0252] The ring structure parameters include the number of register units constituting the ring structure, the positions of the register units constituting the ring structure, etc. For example, in a hybrid ring LFSR with 8 register units, it can be selected to form a ring structure with the 2nd, 3rd, and 4th register units.

[0253] In hardware design, the configuration methods for implementing the ring structure parameters include at least one of the following methods:

[0254] ● Implement the configuration of the ring structure parameters through a field-programmable gate array (FPGA).

[0255] Optionally, the second LFSR is implemented as an FPGA, and a hardware description language is used to describe the functions of the LFSR. In the hardware description language, the ring structure can be defined in a parameterized manner. Optionally, if the configuration module receives a control signal for configuring the ring structure, it can obtain the output sequence of the current first LFSR, determine the ring structure parameters based on this output sequence, and the configuration module will reallocate the logic units and wiring resources inside the second LFSR according to these ring structure parameters to construct the corresponding LFSR circuit.

[0256] ● Implement the configuration of the ring structure parameters through switches.

[0257] In some embodiments, the first ring circuit in the second SR module (i.e., the second LFSR) includes switches, and the switches are used to control the connection status of the first ring circuit; the sequence generation rule is used to indicate the on / off status of the switches. Schematically, when the switch is turned on, the ring circuit is a complete path, and data can flow along the normal ring path; when the switch is turned off, the connectivity of the ring circuit is damaged, and the data flow path will change.

[0258] Optionally, at least two register units in the second SR module are used to perform a second shift operation based on the first circuit corresponding to the second SR module to generate a second output sequence when the sequence generation rule indicates that the switch is turned on. The first ring circuit in the first circuit includes p data streams, where p is a positive integer.

[0259] Optionally, at least two register units in the second SR module are further configured to, when the sequence generation rule indicates that the switch is off, perform a second shift operation based on a second circuit corresponding to the second SR module to generate a second output sequence. The first ring circuit in the second circuit includes q data streams, where q is a positive integer and p > q.

[0260] Among them, when the switch is on, p data streams in the first ring circuit mean that in this complete ring circuit, p data paths are simultaneously performing data shifting and interaction. When the switch is off, there are q data streams in the first ring circuit, where p > q, indicating that some paths of the ring circuit are cut off and the number of data streams decreases.

[0261] Schematically, please refer to Figure 9 , which shows a schematic diagram of a circuit structure for switching a second LFSR. The ring circuit in the second LFSR includes a switch K, and the switch K is used to control the connection status of the ring circuit.

[0262] Optionally, if the configuration module receives a control signal for configuring the ring structure, it can obtain the output sequence of the current first LFSR and determine the on / off status of the switch K according to the output sequence. For example, when the first output sequence is 00, control the switch K to be on; when the first output sequence is 01, control the switch K to be off.

[0263] As Figure 9 shown, if the switch is off, in the circuit structure 901 corresponding to the second LFSR, the output value of register unit 1 will move to register unit 2, the output value of register unit 2 will move to register unit 3 through an exclusive-OR gate (when the exclusive-OR gate has only one input, the output is 1 when the input is 1 and the output is 0 when the input is 0), the output value of register unit 3 will move to register unit 4, the output value of register unit 4 will perform an exclusive-OR operation with the output value of register unit 1 to obtain a second feedback value, the second feedback value will move to register unit 5, and the output value of register unit 5 will also move to register unit 1. If the data stored in the circuit structure 901 before the shift operation is "10010", the data stored in the circuit structure 901 after the shift operation is "01000".

[0264] If the switch is connected, in the circuit structure 902 corresponding to the second LFSR, the output value of register unit 1 will move to register unit 2. The output value of register unit 2 will perform an exclusive OR operation with the output value of register unit 3 to obtain a first feedback value, and the first feedback value will be stored in register unit 3. The output value of register unit 3 will move to register unit 4. The output value of register unit 4 will perform an exclusive OR operation with the output value of register unit 1 to obtain a second feedback value, and the second feedback value will be moved to register unit 5. The output value of register unit 5 will also move to register unit 1. If the data stored in the circuit structure 902 before the shift operation is "10010", the data stored in the circuit structure 902 after the shift operation is "01000".

[0265] In the above embodiment, the same set of hardware circuits (the second LFSR) realizes the sequence generation function under different data stream configurations through the control of the switch, improving the utilization rate of the hardware and reducing the hardware cost and system complexity.

[0266] ● Use a selector to configure the parameters of the ring structure.

[0267] In some embodiments, the second SR module (i.e., the second LFSR) includes a first circuit, a second circuit, and a selector. The selector is respectively connected to the input ends of the first circuit and the second circuit, and the configuration module is connected to the selector.

[0268] The configuration module is used to determine a circuit selection signal as the sequence generation rule of the second SR module based on the first output sequence. The circuit selection signal is used to indicate selecting the first circuit; send the circuit selection signal to the selector of the second SR module; the selector is used to send a sequence generation signal to the first circuit when receiving the circuit selection signal; the first circuit is used to perform a second shift operation based on the sequence generation signal to generate a second output sequence.

[0269] Suppose two ring LFSR circuits are designed and these two ring LFSR circuits are connected to the selector.

[0270] Schematically, please refer to Figure 10 , which shows a schematic diagram of a circuit structure for switching the second LFSR. The two ring LFSR circuits are 1001 and 1002 respectively. If the configuration module receives a control signal for configuring the ring structure, it can obtain the output sequence of the current first LFSR and determine the selection signal according to this output sequence. For example: if the output sequence is 00, the selection signal is 00, and when the selection signal is 00, select the ring LFSR circuit 1001; if the output sequence is 01, the selection signal is 01, and when the selection signal is 01, select the ring LFSR circuit 1002.

[0271] In the above embodiments, the first circuit and the second circuit can be designed to have different structures (such as different ring structures), logics, or parameter settings, which provides diversified strategies for sequence generation.

[0272] For a sequence generation device for generating test vectors, optionally, the first LFSR and the second LFSR can be implemented as reconfigurable hybrid ring LFSRs. The following points need to be noted for the configuration of the second LFSR:

[0273] (1) When configuring a hybrid ring LFSR, some key parameters need to be set first, such as the number of bits of the LFSR, feedback logic (or called feedback coefficient), ring structure parameters (e.g., size), etc. The number of bits of the LFSR determines the length and complexity of the generated test vectors. An LFSR with a larger number of bits can generate more complex test vectors. The choice of feedback logic has a great impact on the randomness and coverage of the test vectors. Appropriate combinations of feedback coefficients can be determined through theoretical analysis and experimental verification to meet specific test requirements. The size of the ring structure can be adjusted according to the scale of the chip and test requirements. A smaller ring structure can improve the speed of generating test vectors, while a larger ring structure can increase the coverage.

[0274] (2) According to specific test requirements, selecting appropriate feedback logic is an important step in configuring a hybrid ring LFSR. Different feedback logics (i.e., circuits) can be switched by setting switches or selectors, etc. Schematically, a feedback logic selection module can be added to the sequence generation device to allow selection among multiple feedback logics. Different feedback logics will generate different test vectors, and the most suitable feedback logic can be selected according to the characteristics of the chip to be tested and the test objectives.

[0275] (3) Configurable interface design. To facilitate the configuration of the hybrid ring LFSR, a configurable interface can be provided. This interface can be a hardware interface, such as a register, through which the number of bits of the LFSR, feedback logic (or called feedback coefficient), ring structure parameters (e.g., size), etc. can be set.

[0276] (4) Testing and optimization. After configuration, the hybrid ring LFSR needs to be tested and optimized to ensure that the generated test vectors meet the requirements of chip testing. The effectiveness and coverage of the test vectors can be verified through simulation testing, actual chip testing, etc.

[0277] The process of testing and optimization is an iterative process that requires continuous adjustment and improvement until the test conditions are met.

[0278] (2) The working process of the FSM

[0279] In the embodiments of the present application, the configuration of the second LFSR through the first LFSR and the control module is mainly achieved by the FSM in the sequence generation device 400.

[0280] As Figure 11 shown, the sequence generation device 400 includes at least five states: initialization, configuring the second LFSR, generating an initial sequence, loading the initial sequence, and generating an output sequence. The FSM will transition between these five states, and the specific working process is as follows:

[0281] S1: From the initialization state to the state of configuring the second LFSR.

[0282] Schematically, as Figure 4 shown, after the FSM is powered on, if an initialization signal is received, the sequence generation device enters the initialization state: the first LFSR and the second LFSR will be initialized.

[0283] Among them, for the first LFSR, when the first LFSR is initialized, it will load the initial sequence into at least two corresponding register units; then the first LFSR will perform a shift operation according to its corresponding feedback logic and the initial sequence to generate sequence 1. At this time, if the FSM sends a rule configuration signal to the configuration module, and if the rule configuration signal is in the high level state, the sequence generation device enters the state of configuring the second LFSR from the initialization state.

[0284] S2: Configure the second LFSR.

[0285] In the state of configuring the second LFSR, the configuration module will obtain sequence 1 generated by the first LFSR. Then, taking the case where the number of bits of the first LFSR and the second LFSR are the same as an example, if the sequence 1 generated by the first LFSR is "0011", the sequence 1 can be used as the feedback bit information, that is, the 3rd and 4th register units of the feedback bit of the second LFSR are determined.

[0286] After the configuration is completed, if the rule configuration signal is in the high level state, it remains in the state of configuring the second LFSR; if the rule configuration signal is in the low level state, it exits the state of configuring the second LFSR.

[0287] S3: From the state of configuring the second LFSR to the state of updating the initial sequence.

[0288] As Figure 4As shown, the FSM sends an initial sequence update signal to the first LFSR. If the initial sequence update signal is in the high level state, the sequence generation device enters the initial sequence update state from the state of configuring the second LFSR: the first LFSR will obtain a new initial sequence 1 and use this new initial sequence 1 as its current stored data, and then generate sequence 2 on this new initial sequence 1 (this sequence 2 can be the initial sequence 1).

[0289] S4: Update the initial sequence state to the state of configuring the second LFSR.

[0290] After the first LFSR generates sequence 2 (or obtains a new initial sequence 1), the sequence generation device enters the state of configuring the second LFSR from the initial sequence update state. In this state of configuring the second LFSR, the configuration module will obtain sequence 2 and then generate the initial sequence 2 of the second LFSR according to sequence 2. Schematically, if sequence 2 is the initial sequence 1, it also means that the initial sequence 2 of the second LFSR is also the initial sequence 1.

[0291] S5: Update the initial sequence state to the state of loading the initial sequence.

[0292] If the initial sequence update signal is in the low level state, the sequence generation device enters the state of loading the initial sequence from the initial sequence update state: the second LFSR will load the initial sequence 2 into at least two of its corresponding register units.

[0293] S6: Update the initial sequence state to the state of generating the output sequence.

[0294] When the second LFSR loads the initial sequence 2 into at least two of its corresponding register units, the sequence generation device enters the state of generating the output sequence from the initial sequence update state: at this time, the second LFSR will perform a shift operation according to the previously configured feedback bits and the currently obtained initial sequence to generate the output sequence.

[0295] S7: Load the initial sequence.

[0296] Schematically, if no new initial sequence is obtained in the sequence generation device, the second LFSR can continuously load the same initial sequence (i.e., the initial sequence 2). Then perform a shift operation according to this initial sequence 2 and the corresponding feedback value.

[0297] S8: The state of generating the output sequence to the state of configuring the second LFSR.

[0298] The sequence generation device enters the configuration second LFSR state from the output sequence state, that is, it is necessary to reconfigure the initial sequence or feedback bits of the second LFSR state. This reconfiguration operation can be triggered according to the current user requirements. For example, if the output sequence generated by the second LFSR is used to generate test vectors, then the fault coverage analysis of the current chip can be performed based on the output sequence, such as obtaining a fault analysis table, which records the fault types of the current chip. Among them, the currently detected faults are grouped into one group, and the undetected faults are grouped into another group. For the undetected faults, change the initial sequence and feedback bits of the second LFSR to generate new test vectors to cover the undetected faults.

[0299] (3) Sequence generation process

[0300] Such as Figure 12 As shown, in the sequence generation device, the steps of the sequence generation process are as follows:

[0301] Step 1201, start.

[0302] For example, when the FSM is powered on and receives the initialization signal, the sequence generation process starts.

[0303] Step 1202, determine whether to configure the second LFSR.

[0304] For example, the FSM sends a rule configuration signal to the configuration module, and determines whether to configure the second LFSR according to this rule configuration signal.

[0305] Step 1203, if configured, update the feedback logic of the second LFSR.

[0306] For example, if the rule configuration signal is at a high level, the configuration module updates the feedback logic of the second LFSR, that is, configures the feedback bits for the second LFSR according to the output sequence of the first LFSR.

[0307] Step 1204, if not configured, determine whether to update the initial sequence.

[0308] For example, if the rule configuration signal is at a low level, the configuration module does not need to update the feedback logic of the second LFSR. At this time, the FSM sends an initial sequence update signal to the first LFSR, and determines whether to update the initial sequence according to this initial sequence update signal.

[0309] Step 1205, if updated, load a new initial sequence.

[0310] For example, if the initial sequence update signal is at a high level, the first LFSR needs to load a new initial sequence. The configuration module will obtain this new initial sequence and assign this initial sequence to the second LFSR.

[0311] Step 1206, if there is no update, generate test vectors.

[0312] Illustratively, if the initial sequence update signal is at a low level, the first LFSR does not need to load a new initial sequence, and the second LFSR will perform a shift operation according to the current stored data and feedback bits to generate an output sequence, which can be used to generate test vectors.

[0313] Illustratively, after the second LFSR generates the output sequence, the output sequence is output to the scan chain corresponding to the chip to be tested, and test vectors are generated through the scan chain. A scan chain is a structure used for testing in chip design, which connects the sequential elements such as registers inside the chip into one or more shift register chains.

[0314] Taking a scan chain with 4 registers as an example, the sequence bits output by the second LFSR enter from the input port of the scan chain in sequence, and the data flows into each register in the scan chain in a certain order. The register combination in the scan chain stores the output sequence of the second LFSR, and these sequences are combined and transformed to form test vectors.

[0315] In summary, the sequence generation device provided by the embodiments of the present application has high flexibility. By configuring information such as sequence generation rules and initial sequences, more complex and diverse output sequences are generated, thereby enhancing the randomness and complexity of test vectors, helping to more efficiently and comprehensively cover various logic situations and fault modes in the chip, improving the detection ability of chip faults, thus improving the fault coverage rate of testing and the quality of chip testing.

[0316] Among them, the LFSR involved in the present application can be implemented as a hybrid ring LFSR. The hybrid ring LFSR design uses fewer exclusive-OR gate logics, is friendly to layout and wiring, saves chip layout area, and at the same time has fewer fan-out nodes, which can reduce latency and power consumption, has better operating performance, and improves test efficiency. And the configurable design in the present application can make the hybrid ring LFSR adapt to different chip structures and test scenarios, improve its versatility and practicality, and also improve the utilization rate of hardware resources.

[0317] Next, the sequence generation method provided by the embodiments of the present application will be described.

[0318] The following is an embodiment of the method of the present application. For details not disclosed in the embodiment of the method of the present application, please refer to the embodiment on the device side of the present application. Figure 13 It is a flowchart of the sequence generation method provided by an exemplary embodiment of the present application, which is executed by the above sequence generation device. The sequence generation device includes: a first shift register SR module, a second SR module, and a configuration module.

[0319] Step 1301, the first SR module performs a first shift operation to generate a first output sequence.

[0320] Optionally, the first SR module includes at least two register units and a feedback unit.

[0321] In some embodiments, the feedback unit in the first SR module corresponds to a first feedback logic; the first feedback logic is used for the rule of the feedback unit in the first SR module to generate a feedback value.

[0322] Step 1302, the first SR module sends the first output sequence to the configuration module.

[0323] Schematically, after receiving the first control signal, the configuration module sends a sequence acquisition instruction to the first SR module, and after receiving the sequence acquisition instruction, the first SR module sends the first output sequence to the configuration module; alternatively, after generating the first output sequence, the first SR module automatically sends the first output sequence to the configuration module.

[0324] Step 1303, the configuration module determines the sequence generation rule of the second SR module based on the first output sequence.

[0325] The sequence generation rule is used to indicate the rule for performing a shift operation to generate an output sequence.

[0326] In some embodiments, the second SR module includes a feedback unit and at least two register units; the sequence generation rule is used to indicate the rule for the feedback unit to generate a feedback value, and the feedback value is used to move to at least two register units in the second SR module after the second SR module performs a second shift operation.

[0327] In some embodiments, the sequence generation rule is used to indicate that the register unit of the specified logical bit in the second SR module generates a feedback value.

[0328] Optionally, the configuration module determines the specified logical bit based on the first output sequence; generates a sequence generation rule based on the specified logical bit; indicates the sequence generation rule to the feedback unit of the second SR module; the feedback unit obtains the first data stored in the register unit of the specified logical bit in the current second SR module based on the sequence generation rule; and generates a first feedback value according to the first data.

[0329] Step 1304, the configuration module indicates the sequence generation rule to the second SR module.

[0330] In some embodiments, the configuration module determines a first identifier based on the first output sequence; determines a first rule identifier that matches the first identifier from the rule identifiers corresponding to multiple candidate generation rules; and indicates the candidate generation rule corresponding to the first rule identifier to the second SR module as the sequence generation rule.

[0331] Step 1305, the second SR module performs a second shift operation based on the sequence generation rule to generate a second output sequence.

[0332] In some embodiments, optionally, the feedback unit processes the data stored in at least two register units according to the sequence generation rule to generate a first feedback value; the at least two register units perform a second shift operation, and there are idle register units in the at least two register units after the second shift operation; the feedback unit stores the first feedback value in the idle register unit among the at least two register units; the at least two register units output a first sequence value, and the first sequence value belongs to the second output sequence; wherein, the first sequence value is the stored data shifted out of the second SR module after the second shift operation, or the first sequence value is the data stored in the at least two register units after the second shift operation.

[0333] In some embodiments, the configuration module determines the initial sequence of the second SR module based on the third output sequence, where the third output sequence is the output sequence generated by the first SR module, and the initial sequence is used to indicate the stored data in the second SR module before performing the second shift operation; the initial sequence is indicated to the second SR module; the second SR module performs a second shift operation based on the sequence generation rule and the initial sequence to generate a second output sequence.

[0334] Optionally, the number of bits of the stored data in the second SR module is n, where n is an integer greater than 1; the configuration module determines the first n sequence values in the third output sequence as the initial sequence.

[0335] In some embodiments, after the configuration module determines the sequence generation rule, the first SR module performs an initial sequence update operation, and the initial sequence update operation is used to update the stored data of the current first SR module; a third shift operation is performed based on the updated stored data to generate a third output sequence.

[0336] In some embodiments, the sequence generation device further includes: a control module.

[0337] Optionally, the control module sends a first control signal to the configuration module, and the first control signal is used to control the configuration module to enter the rule configuration mode, and the rule configuration mode is used to configure the sequence generation rule of the second SR module.

[0338] Optionally, the control module sends a second control signal to the first SR module, and the second control signal is used to control the first SR module to perform the initial sequence update operation; when the first SR module successfully performs the initial sequence update operation, the configuration module enters the sequence generation mode, and the sequence generation mode is used to configure the initial sequence of the second SR module.

[0339] In some embodiments, the second SR module includes a ring linear feedback shift register (LFSR), and at least two register units in the ring LFSR form at least one ring circuit.

[0340] Optionally, a switch is included in the first ring circuit of the second SR module, and the switch is used to control the connection state of the first ring circuit; the sequence generation rule is used to indicate the on / off state of the switch; when the sequence generation rule indicates that the switch is turned on, at least two register units perform a second shift operation based on the first circuit corresponding to the second SR module to generate a second output sequence, and the first ring circuit in the first circuit includes a closed data stream; when the sequence generation rule indicates that the switch is turned off, at least two register units perform a second shift operation based on the second circuit corresponding to the second SR module to generate a second output sequence, and the first ring circuit in the second circuit does not include a closed data stream.

[0341] In some embodiments, the second SR module includes a first circuit, a second circuit, and a selector. The selector is respectively connected to the input ends of the first circuit and the second circuit, and the configuration module is connected to the selector.

[0342] Optionally, the configuration module determines a circuit selection signal as the sequence generation rule of the second SR module based on the first output sequence. The circuit selection signal is used to indicate the selection of the first circuit; the circuit selection signal is sent to the selector of the second SR module; when the selector receives the circuit selection signal, the selector sends a sequence generation signal to the first circuit; the first circuit performs a second shift operation based on the sequence generation signal to generate a second output sequence.

[0343] In summary, for the sequence generation method provided by the embodiments of the present application, in the sequence generation device, the control module analyzes the output sequence generated by the first SR module to dynamically determine the sequence generation rule, and the second SR module generates an output sequence based on the sequence generation rule dynamically determined by the control module. Since the first SR module randomly generates different output sequences, the corresponding control module determines multiple sequence generation rules, enabling the second SR module to switch different rules to generate output sequences, increasing the diversity of the sequences, thereby improving the diversity of the test vectors generated based on the sequences, facilitating the improvement of the test coverage rate of the chip, and improving the test credibility.

[0344] The following introduces the flowchart of the sequence generation method provided by another exemplary embodiment of the present application, which is executed by the configuration module in the above sequence generation device. The method includes the following steps:

[0345] Step 1, obtain the first output sequence.

[0346] The first output sequence is the sequence generated by the first SR module performing the first shift operation.

[0347] Step 2, determine the sequence generation rule of the second SR module based on the first output sequence.

[0348] The sequence generation rule is used to indicate the rule for performing a shift operation to generate an output sequence.

[0349] In some embodiments, the second SR module includes a feedback unit and at least two register units; the sequence generation rule is used to indicate the rule for the feedback unit to generate a feedback value, and the feedback value is used to be written into at least two register units after performing the second shift operation.

[0350] Step 3, indicate the sequence generation rule to the second SR module.

[0351] The second SR module is used to perform a second shift operation based on the sequence generation rule to generate a second output sequence.

[0352] In some embodiments, the sequence generation rule is used to indicate that the register unit of the specified logical bit in the second SR module generates a feedback value.

[0353] Optionally, determine the specified logical bit based on the first output sequence; generate the sequence generation rule based on the specified logical bit; indicate the sequence generation rule to the feedback unit of the second SR module. Among them, the feedback unit is used to obtain the first data stored in the register unit of the specified logical bit in the current second SR module based on the sequence generation rule; generate a first feedback value according to the first data.

[0354] In some embodiments, determine a first identifier based on the first output sequence; determine a first rule identifier that matches the first identifier from the rule identifiers corresponding to multiple candidate generation rules; indicate the first rule identifier to the second SR module, and the candidate generation rule corresponding to the first rule identifier is used as the sequence generation rule.

[0355] In some embodiments, determine the initial sequence of the second SR module based on the third output sequence, where the third output sequence is the output sequence generated by the first SR module, and the initial sequence is used to indicate the stored data in the second SR module before performing the second shift operation; indicate the initial sequence to the second SR module. Among them, the second SR module is used to perform a second shift operation based on the sequence generation rule and the initial sequence to generate a second output sequence.

[0356] In some embodiments, the number of bits of the stored data in the second SR module is n, where n is an integer greater than 1; optionally, determine the first n sequence values in the third output sequence as the initial sequence. Among them, the first SR module is used to perform an initial sequence update operation, and the initial sequence update operation is used to update the data stored in the current first SR module; perform a third shift operation based on the updated stored data to generate a third output sequence.

[0357] In some embodiments, the sequence generation device further includes: a control module; the control module is configured to send a first control signal to the configuration module, and the first control signal is used to control the configuration module to enter a rule configuration mode, and the rule configuration mode is used to configure the sequence generation rule of the second SR module.

[0358] In some embodiments, the control module is configured to send a second control signal to the first SR module, and the second control signal is used to control the first SR module to perform an initial sequence update operation.

[0359] Optionally, in the case where the first SR module successfully performs the initial sequence update operation, enter the sequence generation mode, and the sequence generation mode is used to configure the initial sequence of the second SR module.

[0360] In some embodiments, the second SR module includes a ring linear feedback shift register (LFSR), and at least two register units in the ring LFSR form at least one ring circuit.

[0361] In some embodiments, a switch is included in the first ring circuit of the second SR module, and the switch is used to control the connection status of the first ring circuit; the sequence generation rule is used to indicate the on / off state of the switch; wherein, at least two register units are used to perform a second shift operation based on the first circuit corresponding to the second SR module to generate a second output sequence when the sequence generation rule indicates that the switch is turned on, and the first ring circuit in the first circuit includes p data streams, where p is a positive integer; at least two register units are further used to perform a second shift operation based on the second circuit corresponding to the second SR module to generate a second output sequence when the sequence generation rule indicates that the switch is turned off, and the first ring circuit in the second circuit includes q data streams, where q is a positive integer and p > q.

[0362] In some embodiments, the second SR module includes a first circuit, a second circuit, and a selector. The selector is respectively connected to the input ends of the first circuit and the second circuit, and the configuration module is connected to the selector.

[0363] Optionally, determine a circuit selection signal as the sequence generation rule of the second SR module based on the first output sequence, and the circuit selection signal is used to indicate to select the first circuit; send the circuit selection signal to the selector of the second SR module; the selector is used to send a sequence generation signal to the first circuit when receiving the circuit selection signal; the first circuit is used to perform a second shift operation based on the sequence generation signal to generate a second output sequence.

[0364] In some embodiments, the embodiments of the present application further provide a chip test device, and the chip test device includes the sequence generation device described in any one of the above.

[0365] Optionally, the chip testing device includes one or more of the sequence generating devices described above, and the sequence generating device is used to generate test vectors.

[0366] Optionally, the chip testing device may only include a sequence generating device, or the chip testing device includes a sequence generating device and a chip to be tested. If the chip testing device further includes a chip to be tested, in the chip testing device, the sequence generating device is used to send a second output sequence to the chip to be tested. The chip to be tested is used to generate test vectors based on the second output sequence; and perform chip testing operations according to the test vectors.

[0367] Illustratively, assuming that the output sequence generated by the sequence generating device is "100110111011", "100110111011" can be segmented into test vectors according to the requirements of the chip to be tested. If the chip to be tested has 3 input pins, "100110111011" can be segmented into 5 test vectors: "100", "110", "111", and "011". Then, these 5 test vectors are input into the chip for testing in sequence. For example: for the first test vector "100", apply 1 to the first input pin, 0 to the second input pin, and 0 to the third input pin, and then obtain the output result of the chip to be tested, and determine whether the output result matches the expected result. If the output result matches the expected result, then for this test vector, the chip to be tested is normal; if the output result does not match the expected result, it indicates that there is a fault in the chip to be tested.

[0368] In some embodiments, the embodiments of the present application further provide a computer device, which includes one of the sequence generating devices described above, or the computer device includes one of the chip testing devices described above.

[0369] Illustratively, an example is given where the computer device includes a chip testing device, and the chip testing device includes a sequence generating device and a chip to be tested. Figure 14 FIG. 1400 is a structural block diagram of a computer device 1400 provided by an exemplary embodiment of the present application. The computer device 1400 includes a chip testing device 1410, and the chip testing device 1410 includes a sequence generating device 1411 and a chip to be tested 1412.

[0370] Optionally, in the chip testing device 1410, the chip to be tested 1412 is detachable. Illustratively, after the chip a is tested, the chip a can be removed from the chip testing device 1410, and the next test chip b is connected to the sequence generating device 1411 in the chip testing device 1410.

[0371] Those skilled in the art can understand, Figure 14The structure shown does not constitute a limitation on the computer device 1400, and may include more or fewer components than shown, or combine certain components, or adopt a different component arrangement.

[0372] The above are only alternative embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A sequence generation device, characterized in that: The sequence generation device comprises: a first shift register SR module, a second SR module and a configuration module; the first SR module is connected to the configuration module, and the second SR module is connected to the configuration module; The first SR module is used to perform a first shift operation to generate a first output sequence; and send the first output sequence to the configuration module; The configuration module is used to determine a sequence generation rule of the second SR module based on the first output sequence, wherein the sequence generation rule is used to indicate a rule for performing a shift operation to generate an output sequence; and indicate the sequence generation rule to the second SR module; The second SR module is used to perform a second shift operation to generate a second output sequence based on the sequence generation rule.

2. The device according to claim 1, characterized in that The second SR module includes a feedback unit and at least two register units; the sequence generation rule is used to indicate a rule for the feedback unit to generate a feedback value, and the feedback value is used to write into the at least two register units after performing the second shift operation; The feedback unit is used to process the data stored in the at least two register units according to the sequence generation rule to generate a first feedback value; The at least two register units are used to perform the second shift operation, and there is an idle register unit in the two register units after performing the second shift operation; The feedback unit is further configured to store the first feedback value in the idle register unit among the at least two register units; The at least two register units are also used to output a first sequence value, which belongs to the second output sequence; wherein the first sequence value is the storage data shifted out of the second SR module after executing the second shift operation, or the first sequence value is the data stored in the at least two register units after executing the second shift operation.

3. The device according to claim 2, characterized in that The sequence generation rule is used to instruct the register unit of the specified logic bit in the second SR module to generate a feedback value; the feedback unit is connected to the register unit of the specified logic bit; The configuration module is configured to determine the designated logic bit based on the first output sequence; generate the sequence generation rule based on the designated logic bit; and indicate the sequence generation rule to the feedback unit of the second SR module; The feedback unit is used to obtain the first data stored in the register unit of the specified logic bit in the current second SR module based on the sequence generation rule; and generate the first feedback value according to the first data.

4. The device according to claim 3, characterized in that The designated logic bits include at least two logic bits; the configuration module stores at least two logic bit combinations corresponding to the second SR module; The configuration module is used to determine a first selection signal based on the first output sequence; and select a target logic bit combination from the at least two logic bit combinations as the designated logic bit according to the first selection signal.

5. The device according to claim 3, characterized in that The first output sequence includes at least two sequence values, and the at least two sequence values ​​correspond one-to-one to the at least two register units; The configuration module is used to determine the logic bit of the register unit corresponding to the target sequence value as the specified logic bit, and the target sequence value refers to the sequence value of the first output sequence whose value is a preset value.

6. The device according to claim 1, characterized in that The configuration module is used to determine a first identifier based on the first output sequence; determine a first rule identifier that matches the first identifier from the rule identifiers corresponding to the plurality of candidate generation rules; The first rule identifier is indicated to the second SR module, and the candidate generation rule corresponding to the first rule identifier is used as the sequence generation rule.

7. The device according to any one of claims 1 to 6, characterized in that: The configuration module is used to determine an initial sequence of the second SR module based on a third output sequence, the third output sequence is an output sequence generated by the first SR module, and the initial sequence is used to indicate the stored data in the second SR module before performing the second shift operation; indicating the initial sequence to the second SR module; The second SR module is used to perform the second shift operation to generate the second output sequence based on the sequence generation rule and the initial sequence.

8. The device according to claim 7, characterized in that The number of bits of stored data in the second SR module is n, where n is an integer greater than 1; The configuration module is used to determine the first n sequence values ​​in the third output sequence as the initial sequence.

9. The device according to claim 7, characterized in that The first SR module is used to perform an initial sequence update operation, where the initial sequence update operation is used to update the data currently stored in the first SR module; and to perform a third shift operation based on the updated stored data to generate the third output sequence.

10. The device according to any one of claims 1 to 6, characterized in that: The sequence generation device further comprises: a control module; the control module is respectively connected to the configuration module, the SR module, the second SR module and the configuration module; The control module is used to send a first control signal to the configuration module, where the first control signal is used to control the configuration module to enter a rule configuration mode, where the rule configuration mode is used to configure a sequence generation rule of the second SR module.

11. The device according to any one of claims 1 to 6, characterized in that: The sequence generation device further comprises: a control module; The control module is used to send a second control signal to the first SR module, where the second control signal is used to control the first SR module to perform an initial sequence update operation; The configuration module is used to enter a sequence generation mode when the first SR module successfully performs the initial sequence update operation, and the sequence generation mode is used to configure the initial sequence of the second SR module.

12. The device according to any one of claims 1 to 6, characterized in that: The second SR module includes a ring-shaped linear feedback shift register LFSR, and at least two register units in the ring-shaped LFSR form at least one ring circuit.

13. The device according to claim 12, characterized in that The first ring circuit in the second SR module includes a switch, and the switch is used to control the connectivity of the first ring circuit; the sequence generation rule is used to indicate the on / off state of the switch; The at least two register units are used to generate the second output sequence by performing the second shift operation based on the first circuit corresponding to the second SR module when the sequence generation rule indicates that the switch is turned on, wherein the first ring circuit in the first circuit includes p data streams, where p is a positive integer; The at least two register units are also used to generate the second output sequence by performing the second shift operation based on the second circuit corresponding to the second SR module when the sequence generation rule indicates that the switch is disconnected, and the first ring circuit in the second circuit includes q data streams, q is a positive integer and p>q.

14. The device according to any one of claims 1 to 6, characterized in that: The second SR module includes a first circuit, a second circuit and a selector, the selector is connected to input ends of the first circuit and the second circuit respectively, and the configuration module is connected to the selector; The configuration module is used to determine a circuit selection signal as the sequence generation rule of the second SR module based on the first output sequence, and the circuit selection signal is used to indicate the selection of the first circuit; sending the circuit selection signal to the selector of the second SR module; The selector is configured to send a sequence generation signal to the first circuit upon receiving the circuit selection signal; The first circuit is used to perform the second shift operation based on the sequence generation signal to generate the second output sequence.

15. A chip testing device, characterized in that: The chip testing device comprises the sequence generating device as described in any one of claims 1 to 14.

16. A computer device, characterized in that: The computer device includes the sequence generation apparatus as claimed in any one of claims 1 to 14, or the computer device includes the chip testing device as claimed in claim 15.

17. A sequence generation method, characterized in that: The method is performed by a sequence generation device, the sequence generation device comprising: a first shift register SR module, a second SR module and a configuration module; the method comprises: The first SR module performs a first shift operation to generate a first output sequence; and sends the first output sequence to the configuration module; The configuration module determines a sequence generation rule of the second SR module based on the first output sequence, wherein the sequence generation rule is used to indicate a rule for performing a shift operation to generate an output sequence; and indicates the sequence generation rule to the second SR module; The second SR module performs a second shift operation based on the sequence generation rule to generate a second output sequence.

18. A sequence generation method, characterized in that: Executed by a configuration module, the method includes: Acquire a first output sequence, where the first output sequence is a sequence generated by the first SR module performing a first shift operation; Determine a sequence generation rule of a second SR module based on the first output sequence, wherein the sequence generation rule is used to indicate a rule for performing a shift operation to generate an output sequence; The sequence generation rule is indicated to the second SR module, and the second SR module is used to perform a second shift operation based on the sequence generation rule to generate a second output sequence.

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