Server power-on timeout monitoring system and method, medium, equipment and program product

Abstract

The invention discloses a server power-on timeout monitoring system and method, a medium, equipment and a program product, and relates to the technical field of computers.The method comprises the steps that a first controller conducts power-on timeout monitoring on different components according to the power-on sequence of the different components in a server, and power-on timeout monitoring results of the different components are obtained; and the power-on timeout monitoring result is transmitted to the second controller, and the second controller performs exception analysis on the power-on timeout monitoring result to obtain an exception analysis result. Due to the fact that the power-on time of different assemblies is inconsistent, the specific power-on timeout conditions of the different assemblies can be accurately captured through segmented monitoring, and therefore the accuracy of power-on timeout monitoring of the server is improved. Therefore, the technical problem that the accuracy of power-on overtime monitoring of the server is low can be solved, and the technical effect of improving the accuracy of power-on overtime monitoring of the server is achieved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a server power-on timeout monitoring system, method, medium, device, and program product. Background Art

[0002] During the power-on process of a server, there may be a situation of power-on timeout, which will affect the normal operation of the server. Therefore, it is necessary to monitor the server power-on timeout.

[0003] In the related technology of server power-on timeout monitoring, usually the entire power-on time of the server is monitored for timeout. Since different components in the server are powered on in stages and the power-on times of different components are inconsistent, the accuracy of server power-on timeout monitoring is relatively low. Summary of the Invention

[0004] This application provides a server power-on timeout monitoring system, method, medium, device, and program product to at least solve the problem of relatively low accuracy in server power-on timeout monitoring in the related technology.

[0005] This application provides a server power-on timeout monitoring system, including: a first controller and a second controller; The first controller is connected to the second controller; The first controller monitors the power-on timeout of different components in segments according to the power-on sequence of different components in the server, obtains the power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to the second controller; The second controller performs abnormal analysis on the power-on timeout monitoring results to obtain the abnormal analysis results.

[0006] This application also provides a server power-on timeout monitoring method, including: Using the first controller to monitor the power-on timeout of different components in segments according to the power-on sequence of different components in the server, and obtaining the power-on timeout monitoring results of different components; Using the first controller to transmit the power-on timeout monitoring results to the second controller; Using the second controller to perform abnormal analysis on the power-on timeout monitoring results to obtain the abnormal analysis results.

[0007] This application also provides a server power-on timeout monitoring device, including: A monitoring unit, configured to use the first controller to monitor the power-on timeout of different components in segments according to the power-on sequence of different components in the server, and obtain the power-on timeout monitoring results of different components; A transmission unit, configured to use the first controller to transmit the power-on timeout monitoring results to the second controller; An analysis unit is used to perform abnormal analysis on the power-on timeout monitoring result by using the second controller to obtain an abnormal analysis result.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above server power-on timeout monitoring methods when executing the computer program.

[0009] This application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above server power-on timeout monitoring methods are implemented.

[0010] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any of the above server power-on timeout monitoring methods are implemented.

[0011] Through this application, since the first controller monitors the power-on timeout of different components in the server according to the power-on sequence of different components in the server, obtains the power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to the second controller, and the second controller then performs abnormal analysis on the power-on timeout monitoring results to obtain an abnormal analysis result. Since the power-on times of different components are inconsistent, segmented monitoring can accurately capture the specific power-on timeout situations of different components, thereby improving the accuracy of server power-on timeout monitoring. Therefore, the technical problem of low accuracy of server power-on timeout monitoring can be solved, and the technical effect of improving the accuracy of server power-on timeout monitoring can be achieved. Description of the Drawings

[0012] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 It is a schematic structural diagram of a server power-on timeout monitoring system provided by an embodiment of this application; Figure 2 It is a schematic structural diagram of another server power-on timeout monitoring system provided by an embodiment of this application; Figure 3 It is a schematic structural diagram of the connection relationship between different components provided by an embodiment of this application; Figure 4 It is a schematic flow diagram of the entire process of server power-on timeout monitoring provided by an embodiment of this application; Figure 5Schematic flowchart of a server power-on timeout monitoring method provided by an embodiment of the present application; Figure 6 Schematic structural diagram of a server power-on timeout monitoring device provided by an embodiment of the present application. Detailed implementation manners

[0014] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0015] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0017] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the server power-on timeout monitoring method depends, the specific application environment architecture or specific hardware architecture will be described herein.

[0018] An embodiment of the present application provides a server power-on timeout monitoring system. The server power-on timeout monitoring system will be described in detail in conjunction with the execution process of the server power-on timeout monitoring system.

[0019] Figure 1 Schematic structural diagram of a server power-on timeout monitoring system provided by an embodiment of the present application. As Figure 1 shown, the server power-on timeout monitoring system includes: a first controller and a second controller.

[0020] The first controller is connected to the second controller.

[0021] The first controller can be a Complex Programmable Logic Device (CPLD), and the second controller can be a Baseboard Management Controller (BMC). However, it should be clear that this statement is not intended to limit that the first controller can only be a CPLD and the second controller can only be a BMC. The first controller and the second controller can also be other components with control functions.

[0022] The first controller and the second controller can be connected through a common hardware interface. On the motherboard of the server, corresponding interface slots are reserved. The first controller and the second controller are respectively equipped with matching interfaces. After inserting them into the corresponding slots on the motherboard, a physical connection can be achieved. The interface connection method can provide a high data transmission rate to ensure that monitoring data is transmitted between the two controllers in a timely and accurate manner.

[0023] The first controller monitors the power-on timeout of different components in segments according to the power-on sequence of different components in the server, obtains the power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to the second controller.

[0024] The power-on sequence refers to the order in which different components inside the server obtain power supply in sequence during the startup process. For example, usually, the key power supply module on the motherboard is powered on first. After it works stably, subsequent components such as expansion boards are powered on. Each component completes the power-on process in this predetermined order to ensure that the entire server can start normally. Different components include but are not limited to voltage regulation modules, switch boards, and Graphics Processing Unit (GPU) boards. Among them, the voltage regulation module is used to regulate the voltage of different components in the server.

[0025] Segmented monitoring means dividing the entire power-on process into multiple stages. Each stage corresponds to a specific component, and a timer and a power-on timeout threshold are independently set for monitoring. The power-on timeout monitoring result refers to the conclusion drawn by the first controller based on the preset power-on duration threshold to judge the power-on time of the components in each monitoring stage. If the power-on time of a certain component exceeds the corresponding set power-on duration threshold, it is determined that the component has a power-on timeout; otherwise, it is determined that the power-on is normal. The power-on timeout monitoring result contains the power-on status information of each monitored component.

[0026] To facilitate a better understanding of the power-on timeout monitoring results, the detailed data of the power-on timeout monitoring results provided in the embodiments of this application are as follows in the table: Table 1

[0027] The hardware components in the server are powered on according to a preset power-on sequence. The first controller monitors the power-on process of each component one by one according to the preset power-on sequence. For each component, the first controller sets a predetermined power-on time limit (such as 5 seconds, 10 seconds, etc.). After the component starts to power on, the first controller will monitor the power-on status of the component in real time and record the start time of power-on. If the component fails to complete the power-on process within the specified time, the first controller will judge it as "power-on timeout" and generate the power-on timeout monitoring result of the component. After organizing the power-on timeout monitoring results of each component, the first controller transmits them to the second controller through the communication interface.

[0028] By accurately monitoring the power-on process of each component, problems that may occur during the power-on process, such as hardware failures and incorrect power-on sequences, can be detected and responded to in a timely manner, preventing the system from failing to start.

[0029] The second controller performs abnormal analysis on the power-on timeout monitoring results to obtain the abnormal analysis results.

[0030] Abnormal analysis means that the second controller analyzes the received power-on timeout monitoring results, identifies possible abnormal causes, and generates corresponding handling solutions or reports. Through abnormal analysis, the second controller can determine the severity of the problem and take corresponding measures, such as alarming, logging, or triggering automated processing. The abnormal analysis result refers to the data output after the second controller analyzes the power-on timeout monitoring results, usually including the judgment basis, abnormal type, abnormal location, and handling suggestions during the analysis process.

[0031] The second controller analyzes the received power-on timeout monitoring results one by one to identify the timeout cause of each component. The analysis process includes: determining whether the timeout occurs in a specific component; judging whether the power-on failure is caused by a hardware failure; judging whether the timeout is caused by unstable power supply, incorrect power-on sequence, or external environmental factors. The second controller identifies different types of abnormalities, such as hardware failures, system configuration errors, and unstable power supplies, according to the abnormal analysis results. The system will perform different processing according to each abnormal type. After abnormal analysis, the second controller generates abnormal analysis results, including: the type and cause analysis of the abnormality; the hardware components that may be affected; recommended handling measures, such as restarting, replacing hardware, and adjusting the power configuration. According to the abnormal analysis results, the second controller can trigger corresponding response operations, such as issuing an alarm, logging, notifying the administrator, or performing a fault recovery operation according to the set automated policy (such as powering on again, restoring hardware, etc.). All abnormal analysis processes and results will be recorded in the log and relevant reports will be generated for system administrators or operation and maintenance personnel to view and analyze.

[0032] By performing abnormal analysis on the power-on timeout monitoring results, the second controller can quickly identify possible faults or abnormal conditions in the system, avoiding the time and cost of manual troubleshooting and improving the fault diagnosis efficiency.

[0033] Through this application, since the first controller monitors the power-on timeout of different components according to the power-on sequence of different components in the server, obtains the power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to the second controller, and the second controller then performs abnormal analysis on the power-on timeout monitoring results to obtain the abnormal analysis results. Since the power-on times of different components are inconsistent, segmented monitoring can accurately capture the specific power-on timeout situations of different components, thereby improving the accuracy of the server power-on timeout monitoring. Therefore, the technical problem of low accuracy of the server power-on timeout monitoring can be solved, and the technical effect of improving the accuracy of the server power-on timeout monitoring can be achieved.

[0034] In some embodiments, please continue to refer to Figure 1 , the first controller includes: a first monitoring module, a second monitoring module, and a third monitoring module.

[0035] When the first controller triggers a boot, the first monitoring module monitors the power-on time of at least two first voltage regulation modules on the motherboard among different components.

[0036] The first monitoring module is specifically responsible for monitoring the power-on time of the first voltage regulation module on the motherboard. The first monitoring module integrates a timer, a signal receiving and sending unit, a logic judgment unit, etc. inside, and can accurately capture the key signals during the power-on process, and accurately measure and judge the power-on time.

[0037] Triggering a boot refers to the process of a user starting the server through a physical button (such as the power button on the front panel of the server) or a software instruction (such as a boot command sent through remote management software). Under this operation, the first controller is awakened and starts to power on and initialize each component inside the server according to a preset program and sequence, gradually transitioning the server from a power-off state to a normal working state.

[0038] The first voltage regulation module is a key power supply component installed on the server motherboard. Its main function is to convert the input power supply voltage into a stable voltage suitable for the operation of various components on the motherboard. Usually, at least two first voltage regulation modules are equipped on a motherboard to meet the power supply power and voltage value requirements of different components, ensuring that the motherboard can provide reliable and stable power support for each chip during the power-on process. The first voltage regulation module includes, but is not limited to, a 3.3-volt voltage regulator (P 3.3 Volt Voltage Regulator, P3V3 VR) and a 12-volt voltage regulator (P 12 Volt Voltage Regulator, P12V VR).

[0039] Power-on time monitoring refers to the first monitoring module using its internal timer to monitor in real time the time consumed by the first voltage regulation module from the start of power-on to the completion of stable power supply. By comparing with a preset duration threshold, it is judged whether the power-on time of the first voltage regulation module is within the normal range, so as to timely detect possible abnormal delays and other problems during the power-on process.

[0040] On the server motherboard, the first monitoring module is connected to the first controller of the motherboard through a high-speed signal line to ensure that it can receive the power-on trigger signal in real time. At the same time, the first monitoring module is also connected to the control signal line and power supply signal line of each first voltage regulation module to accurately monitor the signal changes and time information during its power-on process. For example, the signal receiving port of the first monitoring module is connected to the enable signal line of the first voltage regulation module to monitor the power-on start signal; its power supply monitoring port is connected to the output end of the voltage regulation module to detect the completion signal of stable power supply.

[0041] A dedicated monitoring program runs inside the first monitoring module. This program pre-stores the normal power-on duration threshold of the first voltage regulation module and related signal characteristic parameters. When the first controller of the motherboard triggers a power-on, the first monitoring module is immediately activated, and its internal timer starts timing. At the same time, the monitoring program monitors the enable signal and power supply output signal of the first voltage regulation module in real time. For example, when it is detected that the enable signal of the first voltage regulation module becomes high level (indicating the start of power-on), the timer starts; when the voltage at the power supply output end stabilizes within the preset working voltage range (such as 1.2V ± 0.05V), the timer stops timing to obtain the power-on time of this module. This time is compared with the preset duration threshold to judge whether it times out, and the monitoring results (including information such as power-on time and whether it times out) are recorded in the local storage unit, waiting for subsequent processing and transmission.

[0042] By using a dedicated first monitoring module to monitor the power-on times of at least two first voltage regulation modules on the main board respectively, the power-on time of each module can be accurately measured, avoiding the time measurement error caused by multiple modules powering on simultaneously in the traditional overall monitoring method.

[0043] When the first controller triggers the startup, the second monitoring module monitors the power-on time of the expansion boards in different components.

[0044] The second monitoring module is specifically responsible for monitoring the power-on time of the expansion boards in the server. It has an independent timing function and signal detection ability. When the first controller triggers the startup, it can accurately record the entire process time of the expansion board from the start of power-on to the completion of power-on, and determine whether this time is within the normal range.

[0045] The expansion board refers to a daughter board connected to the main board through an interface, providing specific function expansion for the server (such as computing acceleration, storage expansion). The expansion board includes but is not limited to a switch board, a GPU board. Power-on time monitoring means that the second monitoring module uses its internal timer to monitor in real time the time consumed by the expansion board from the start of power-on to the completion of stable power supply. By comparing with a preset duration threshold, it determines whether the power-on time of the expansion board is within the normal range, so as to timely detect possible abnormal delays and other problems during the power-on process.

[0046] Inside the server, the second monitoring module is connected to the first controller through a dedicated signal line to ensure that it can receive the startup trigger signal in real time. At the same time, the second monitoring module is also connected to the power management unit and signal interface of the expansion board to accurately monitor the signal changes and time information during the power-on process of the expansion board. For example, the signal receiving port of the second monitoring module is connected to the enable signal line of the expansion board to monitor the power-on start signal; its power monitoring port is connected to the power output end of the expansion board to detect the stable power supply completion signal. A dedicated monitoring program runs inside the second monitoring module, and this program pre-stores the normal power-on duration threshold of the expansion board and related signal characteristic parameters. When the first controller triggers the startup, the second monitoring module is immediately activated, and its internal timer starts timing. At the same time, the monitoring program monitors the enable signal and power output signal of the expansion board in real time. For example, when it detects that the enable signal of the expansion board becomes high level (indicating the start of power-on), the timer starts; when the voltage at the power output end stabilizes within the preset working voltage range (such as 5V±0.1V), the timer stops timing, and the power-on time of the expansion board is obtained. This time is compared with the preset duration threshold to determine whether it times out, and the monitoring results (including power-on time, whether it times out, etc.) are recorded in the local storage unit, waiting for subsequent processing and transmission.

[0047] By using the second monitoring module to independently monitor the power-on time of the expansion board, the power-on time of the expansion board can be accurately measured, avoiding the time measurement error caused by multiple components powering on simultaneously in the traditional overall monitoring method.

[0048] When the first controller receives the first power ready signal sent by the expansion boards in different components, the third monitoring module monitors the power-on time of at least two second voltage regulation modules on the main board; the power-on time interval between the first voltage regulation module and the second voltage regulation module is greater than a preset interval threshold.

[0049] The third monitoring module is specifically responsible for monitoring the power-on time of the second voltage regulation modules on the main board. It has an independent timing function and signal detection ability. After receiving a specific signal, it can accurately record the entire process time of the second voltage regulation module from the start of power-on to the completion of stable power supply, and determine whether this time is within the normal range.

[0050] The first power ready signal is a signal sent by the expansion board to the first controller after completing its own power-on process and stabilizing the power supply. This signal indicates that the expansion board is ready, its power supply is in a stable state, and it can provide a basis for the subsequent component power-on operation. The first power ready signal is usually a specific level signal (such as a high level) or a data signal, and is transmitted through a preset communication protocol. The first power ready signal can be a Field-Programmable Gate Array_READY (FPGA_READY) signal.

[0051] The second voltage regulation module is another key power supply component installed on the server main board. Its main function is to convert the input power voltage into a stable voltage suitable for various components on the main board to work. The power-on sequence of the second voltage regulation module is later than that of the first voltage regulation module. The second voltage regulation module includes, but is not limited to, the Central Processing Unit Voltage Regulator (CPU VR), the Dual-Inline-Memory-Modules Voltage Regulator (DIMM VR). The power-on time interval refers to the time difference between the start of power-on of the first voltage regulation module and the start of power-on of the second voltage regulation module.

[0052] Inside the server, the third monitoring module is connected to the first controller via a signal line to ensure that it can receive the first power supply ready signal in real time. At the same time, the third monitoring module is also connected to the control signal line and the power supply signal line of the second voltage regulation module on the motherboard to accurately monitor the signal changes and time information during its power-on process. For example, the signal receiving port of the third monitoring module is connected to the enable signal line of the second voltage regulation module to monitor the power-on start signal; its power supply monitoring port is connected to the output end of the voltage regulation module to detect the stable power supply completion signal.

[0053] A dedicated monitoring program runs inside the third monitoring module. This program has pre-stored the normal power-on duration threshold of the second voltage regulation module and related signal characteristic parameters. When the first controller receives the first power supply ready signal sent by the expansion board, the third monitoring module is immediately activated, and the internal timer starts timing. At the same time, the monitoring program monitors the enable signal and the power output signal of the second voltage regulation module in real time. For example, when it detects that the enable signal of the second voltage regulation module becomes high level (indicating the start of power-on), the timer starts; when the voltage at the power output end stabilizes within the preset working voltage range (such as 3.3V ± 0.1V), the timer stops timing to obtain the power-on time of this module. Compare this time with the preset duration threshold to determine whether it times out, and record the monitoring results (including information such as the power-on time and whether it times out) in the local storage unit, waiting for subsequent processing and transmission.

[0054] Performing independent power-on time monitoring on the second voltage regulation module can accurately measure its power-on time, avoiding the time measurement error caused by multiple modules powering on simultaneously in the traditional overall monitoring method.

[0055] In some embodiments, please continue to refer to Figure 1 , the first monitoring module includes: a first timer; when the first controller triggers a startup, the first controller controls the first timer to start timing; if the first controller receives a second power supply ready signal sent by the target first voltage regulation module, the first controller controls the first timer to end timing and obtains the first timing duration of the first timer from the start of timing to the end of timing; the target first voltage regulation module is the first voltage regulation module with the latest power-on time among at least two first voltage regulation modules; if the first controller determines that the first timing duration is less than the first preset duration threshold, the first controller determines that the at least two first voltage regulation modules have not timed out during power-on; the first controller determines the status of the at least two first voltage regulation modules as the first power-on not timed out status.

[0056] The first timer is a hardware counter or software clock integrated in the first monitoring module, and is used to accurately measure the power-on time of the first voltage regulation module. The target first voltage regulation module refers to the voltage regulation module that powers on last in the order of power-on time among multiple first voltage regulation modules. The second power ready signal is a signal sent by the target first voltage regulation module and is used to notify the system that the voltage regulation module has completed power-on. The second power ready signal can be a power good (PWRGD) signal.

[0057] The first timing duration refers to the time interval from when the first controller triggers the boot-up, the first timer starts timing, to when the second power ready signal sent by the target first voltage regulation module is received and the first timer stops timing. This time interval reflects the total power-on time of all first voltage regulation modules. The first preset duration threshold is a preset time threshold used to determine whether the power-on time of the first voltage regulation module is normal. If the first timing duration is less than the first preset duration threshold, it is considered that the power-on time of the first voltage regulation module is within the normal range; if it exceeds the first preset duration threshold, it is considered that the power-on has timed out.

[0058] The first power-on not timed-out state is that when the first controller determines that the first timing duration is less than the first preset duration threshold, the states of at least two first voltage regulation modules are determined to be in the first power-on not timed-out state. This indicates that the power-on time of the first voltage regulation module is within the normal range and there is no timeout problem.

[0059] On the server motherboard, the first monitoring module is connected to the first controller through signal lines to ensure that it can receive the boot-up trigger signal and the second power ready signal in real time. At the same time, the first monitoring module is also connected to the control signal line and power signal line of the first voltage regulation module to accurately monitor the signal changes and time information during its power-on process. For example, the signal receiving port of the first monitoring module is connected to the enable signal line of the first voltage regulation module to monitor the power-on start signal; its power monitoring port is connected to the output end of the first voltage regulation module to detect the stable power supply completion signal.

[0060] There is a dedicated monitoring program running inside the first monitoring module. This program has pre-stored the normal power-on duration threshold of the first voltage regulation module and related signal characteristic parameters. When the first controller triggers a startup, the first controller sends a startup signal to the first monitoring module. After receiving this signal, the first monitoring module controls the first timer to start timing. At the same time, the monitoring program continuously monitors the enable signal and the power output signal of the target first voltage regulation module. For example, when it detects that the enable signal of the target first voltage regulation module becomes high level (indicating the start of power-on), the timer starts; when the voltage at the power output terminal stabilizes within the preset operating voltage range (such as 1.2V ± 0.05V), the target first voltage regulation module sends a second power ready signal. After receiving this signal, the first monitoring module controls the first timer to stop timing, obtaining the first timing duration. This time is compared with the preset first preset duration threshold to determine whether it times out. If the first timing duration is less than the first preset duration threshold, the first controller determines that the power-on of the first voltage regulation module does not time out and determines the status as the first non-timeout power-on status.

[0061] By accurately measuring the power-on time of the target first voltage regulation module through the first timer in the first monitoring module, it is possible to accurately determine whether its power-on time is within the normal range. This precise monitoring method avoids the time measurement errors caused by multiple modules powering on simultaneously in the traditional overall monitoring method, improving the accuracy and reliability of the monitoring.

[0062] In some embodiments, the server power-on timeout monitoring system further includes: if the first controller does not receive the second power ready signal within the first target time, the first controller determines that at least one of the at least two first voltage regulation modules has a power-on timeout; the first target time is the time after the first timer starts timing and intervals the first preset duration threshold.

[0063] The first target time refers to the time point after the first timer starts timing and intervals the first preset duration threshold. This time point is used to determine whether the voltage regulation module can complete the power-on process within the predetermined time.

[0064] The first controller is connected to the first voltage regulation module through a signal line to ensure that it can receive the second power supply ready signal in real time. At the same time, a first timer is integrated inside the first controller for measuring the power-on time. When the first controller triggers a startup, the first timer is started to measure time. During the operation of the first timer, the first controller continuously monitors whether it receives the second power supply ready signal sent by the target first voltage regulation module. If the signal is not received within the first target time (i.e., the time after the first preset duration threshold has elapsed since the first timer started timing), it is determined that at least one of the at least two first voltage regulation modules has a power-on timeout. The specific process is as follows: After receiving the startup signal, the first controller controls the first timer to start and begins to record time. During the timing process, the first controller monitors the second power supply ready signal in real time. If the signal is still not detected when the first target time is reached, it is determined that there is a power-on timeout for the first voltage regulation module. The timeout determination result is recorded in the storage unit of the first controller for subsequent processing and analysis.

[0065] It is possible to quickly locate the voltage regulation module with a power-on timeout, provide clear fault information for maintenance personnel, shorten the fault troubleshooting time, and improve the maintenance efficiency.

[0066] In some embodiments, the server power-on timeout monitoring system further includes: when the first controller determines that there is at least one first voltage regulation module with a power-on timeout among at least two first voltage regulation modules, the first controller obtains the first state value of the enable signal corresponding to each of the at least two first voltage regulation modules, and obtains the second state value of the second power supply ready signal corresponding to each of the at least two first voltage regulation modules; the first controller determines the state of the first voltage regulation module corresponding to the first state value being the first preset state value and the second state value being the second preset state value as the first power-on timeout state; the power-on timeout monitoring result includes the first power-on timeout state or the first power-on not timeout state.

[0067] The enable (ENABLE) signal is a control signal sent by the first controller to the first voltage regulation module (usually active high) for starting the power supply function of the first voltage regulation module. The first state value represents the level state of the enable signal, such as high level (1) being valid and low level (0) being invalid. The second state value represents the level state of the power supply ready signal, such as high level (1) being ready and low level (0) being not ready. The first preset state value is the expected valid state of the enable signal (such as 1, i.e., high level active). The second preset state value is the expected invalid state of the power supply ready signal (such as 0, i.e., low level not ready). The first power-on timeout state is a status identifier that marks the first voltage regulation module as a timeout fault module when the enable signal of a certain first voltage regulation module is valid but the power supply is not ready.

[0068] The first controller is connected to the first voltage regulation module through a signal line to ensure that the enable signal and the second power supply ready signal can be monitored in real time. Inside the first controller, there is a signal monitoring and processing unit for analyzing and processing the acquired signal status values. When the first controller determines that at least one of the at least two first voltage regulation modules has a power-on timeout, it triggers a further process of obtaining status values. The first controller reads the current status values of the enable signal and the second power supply ready signal corresponding to each first voltage regulation module respectively. For each first voltage regulation module, the first controller checks whether its enable signal is in the first preset status value and whether the second power supply ready signal is in the second preset status value. If both conditions are met, the module is marked as being in the first power-on timeout state, and this status information is integrated into the power-on timeout monitoring result; if not, it is marked as the first power-on not timed out state and also included in the monitoring result.

[0069] By obtaining and analyzing the status values of the enable signal and the second power supply ready signal, the first controller can accurately determine which specific first voltage regulation modules have power-on timeout problems, providing clear fault location information for maintenance personnel, shortening the fault troubleshooting time, and improving the maintenance efficiency.

[0070] In some embodiments, the server power-on timeout monitoring system further includes: the first controller obtains the target model of the first processor in the expansion board; the first controller looks up the target second preset duration threshold corresponding to the target model according to the pre-established mapping relationship between the model and the second preset duration threshold; the first controller determines the target second preset duration threshold as the preset duration threshold of the second monitoring module.

[0071] The first processor is the core processor on the expansion board and is responsible for executing the main functions of the expansion board. For example, the first processor can be the GPU in the GPU board. The target model is the specific hardware model of the first processor, which is used to uniquely identify the processor type and specifications. The second preset duration threshold is the maximum power-on time allowed for the expansion board (such as 500 ms), and different processor models correspond to different thresholds (determined by the difference in hardware initialization time consumption). The mapping relationship between the model and the threshold is a pre-stored table or database that associates the processor model with its corresponding power-on timeout threshold.

[0072] The first controller is connected to the first processor on the expansion board through a high-speed communication interface to ensure reliable acquisition of the processor model information. When the server is powered on, the first controller performs the following operations: The first controller sends a query instruction to the expansion board through a preset communication protocol to read the model information of the first processor. For example, by reading the model identifier in the register of the processor or by obtaining the stored model information through the electrically erasable programmable read-only memory on the expansion board. After successfully obtaining the target model, the first controller searches in the pre-established mapping relationship table. The mapping relationship table can be a two-dimensional array or a hash table, where the key is the processor model and the value is the corresponding second preset duration threshold. The search process can be implemented through simple array traversal or hash search algorithms to quickly locate the threshold corresponding to the target model. After finding the target second preset duration threshold, the first controller sends it to the second monitoring module and sets it as the preset duration threshold of the module for subsequent monitoring of the power-on time of the expansion board.

[0073] Different processor models may have different time characteristics during the power-on process. By setting a specific second preset duration threshold for each model, it is possible to more accurately determine whether the power-on time of the expansion board is normal, avoiding misjudgment or missed judgment caused by using a unified threshold.

[0074] In some embodiments, please continue to refer to Figure 1 , the second monitoring module includes: a second timer; when the first controller triggers the power-on, the first controller controls the second timer to start timing; if the first controller receives the first power ready signal, the first controller controls the second timer to stop timing and obtains the second timing duration of the second timer from the start of timing to the end of timing; if the first controller determines that the second timing duration is less than the target second preset duration threshold, it is determined that the power-on of the expansion board is not timed out; the state of the expansion board is determined as the second power-on not timed out state.

[0075] The second monitoring module refers to a hardware module for monitoring the power-on process of the expansion board, specifically responsible for timing and determining whether the expansion board completes the startup task within the preset duration. The second timer is a timer component used to record the duration of the power-on process. The target second preset duration threshold is the preset maximum duration, which refers to the maximum allowable power-on time determined according to the hardware configuration such as the processor model of the expansion board. If the power-on process is not completed within this duration, it is determined to be normal, otherwise it may indicate a fault in the power-on process. The second power-on not timed out state refers to the state of the expansion board during the power-on process, indicating that the power-on time of the expansion board does not exceed the predetermined duration threshold, that is, the expansion board can complete the startup within the specified time.

[0076] When the first controller triggers the power-on, the second timer of the second monitoring module starts timing. The first controller sends a start signal to the second timer to start the timing task. During the startup process, the first controller listens for the first power readiness signal from the server power system to confirm whether the power is ready. Once the first power readiness signal is received, the first controller controls the second timer to stop timing, obtains the time from the start of timing to the end of timing, and gets the second timing duration. The first controller compares the obtained second timing duration with the target second preset duration threshold. If the second timing duration is less than the target second preset duration threshold, it indicates that the expansion board has completed the startup task within the specified time; otherwise, it means that the power-on process of the expansion board has timed out. If the second timing duration is less than the target second preset duration threshold, the first controller determines the status of the expansion board as the "second power-on not timed out state", that is, the expansion board has started successfully and has not timed out.

[0077] The situation of the expansion board power-on timing out can be detected in a timely manner. The first controller can take further measures according to the timeout situation, such as alarming or adjusting the configuration, to avoid the system being in an unstable state for a long time and reduce the risk of failures.

[0078] In some embodiments, the server power-on timeout monitoring system further includes: if the first controller does not receive the first power readiness signal within the second target time, it is determined that the expansion board power-on has timed out; the second target time is the time after the second timer starts timing and intervals the target second preset duration threshold; the first controller determines the status of the expansion board as the second power-on timeout state; the power-on timeout monitoring result includes the second power-on timeout state or the second power-on not timed out state.

[0079] The second target time refers to the time point corresponding to the target second preset duration threshold after the second timer starts timing. The second target time is the key time node for judging whether the expansion board power-on has timed out. If the first power readiness signal is not received before this time point, it can be determined that the expansion board power-on has an abnormal timeout situation. For example, if the target second preset duration threshold is 3000 milliseconds, then the second target time is the 3000th millisecond moment after the second timer starts.

[0080] The second power-on timeout state is an abnormal state determined for the power-on state of the expansion board when the first controller does not receive the first power readiness signal within the second target time. The second power-on timeout state will be recorded and marked inside the first controller for subsequent exception handling and system diagnosis. At the same time, as part of the power-on timeout monitoring result, it provides an important basis for the fault troubleshooting and maintenance of the entire server system.

[0081] When the first controller triggers the power-on operation, the second timer starts timing immediately. At the same time, the first controller monitors the first power supply ready signal sent by the expansion board in real time through a dedicated signal monitoring pin. This monitoring process is continuous, and the controller continuously scans the level status on the signal line to determine whether the expected ready signal appears. During the timing process of the second timer, once the second target time is reached (i.e., the time point after the target second preset duration threshold has elapsed since the start of timing), the first controller immediately makes a judgment: if the first power supply ready signal has not been monitored at this time, it is determined that the power-on of the expansion board has timed out. At this time, the first controller will mark the power-on state of the expansion board as the "second power-on timeout state" in the internal status register or the corresponding status storage area, and incorporate this status information into the power-on timeout monitoring result for storage and recording for subsequent system processing and analysis.

[0082] By clearly setting the second target time and the target second preset duration threshold, it is possible to accurately determine whether there is a timeout exception during the power-on process of the expansion board. This avoids the uncertainty and potential risks of system startup delay caused by excessive waiting time, helps to promptly detect possible hardware failures (such as power component failures, power supply line problems) or software initialization exceptions during the power-on process of the expansion board, and improves the server system's recognition ability and response speed to power-on exceptions of the expansion board.

[0083] In some embodiments, please continue to refer to Figure 1 , the third monitoring module includes: a third timer; when the first controller receives the first power supply ready signal sent by the expansion board, the first controller controls the third timer to start timing; if the first controller receives a reset signal sent by the second processor of the main board, the first controller controls the third timer to stop timing and obtains the third timing duration of the third timer from the start of timing to the end of timing; if the first controller determines that the third timing duration is less than the third preset duration threshold, the first controller determines that at least two second voltage regulation modules have not timed out during power-on; the first controller determines the status of at least two second voltage regulation modules as the third power-on not timed out state.

[0084] The third monitoring module is used to monitor the power-on process of the voltage regulation module, especially the timeout detection related to the power-on duration. The third monitoring module can accurately record the time from when the voltage regulation module receives the power signal to the completion of the power-on process. The third timer is used to record the time from when the first controller receives the first power supply ready signal of the expansion board to when it receives the reset signal. The third timer helps monitor whether the power-on process complies with the specified duration. The reset signal is a signal sent by the second processor of the main board, which usually indicates that the system has completed initialization or reset. For the voltage regulation module, the reset signal means that the power-on process has been completed.

[0085] The third timing duration is the time length recorded by the third timer, representing the time between the start of timing by the first controller and the receipt of the reset signal. This duration is used to determine whether the voltage regulation module completes the power-on process within a predetermined time. The third preset duration threshold is the set upper limit of time, used to judge whether the voltage regulation module completes the power-on within the specified time. If the third timing duration is less than this threshold, it indicates that the power-on process is normal. The third power-on not timed out status is a normal status identifier determined by the first controller for the power-on status of the second voltage regulation module when the third timing duration is less than the third preset duration threshold. This status information will be stored in the internal status storage area of the first controller, and can be used as the data basis for the entire server power-on timeout monitoring system to summarize and analyze the power-on conditions of each component in the future, indicating that the power-on process of the second voltage regulation module is completed smoothly and normally without abnormal delay or failure, providing guarantee for the stable startup and operation of the server.

[0086] When the first controller detects the first power ready signal sent by the expansion board, it immediately sends an instruction to the third monitoring module through the internal control logic circuit to trigger the third timer to start the timing operation. At this time, the counter inside the third timer starts to accumulate and count under the drive of the system clock signal, real-time recording the passage of time from this moment, preparing for measuring the power-on duration of the second voltage regulation module in the future. During the continuous power-on process of the second voltage regulation module, the first controller monitors the reset signal sent by the second processor on the main board in real time. Specifically, the signal detection pin of the first controller continuously scans the signal line connected to the second processor to judge whether the level or pulse state on the signal line changes. When the reset signal is detected, the first controller quickly sends an end timing instruction to the third timer. After receiving this instruction, the third timer immediately stops timing and saves the current count value of the counter (i.e., the third timing duration) to the pre-allocated storage unit for subsequent processing. After the first controller obtains the third timing duration recorded by the third timer, it retrieves the pre-set third preset duration threshold from the internal memory and performs a comparison operation on the two through the arithmetic logic unit of the processor. If the third timing duration is less than the third preset duration threshold, according to the preset logic rules, it is determined that the power-on of the second voltage regulation module is not timed out. At this time, the first controller updates the power-on status of the second voltage regulation module to the "third power-on not timed out status" in the internal status register or the corresponding status storage area, so that the entire monitoring system can summarize and process the power-on conditions of each component in the future, providing accurate data support for the startup process control and abnormal detection of the server.

[0087] By precisely timing the entire power-on process of the second voltage regulation module from receiving the first power supply ready signal to sending out the reset signal through the third timer, it is possible to accurately measure the actual time consumption of this module, avoiding the monitoring errors caused by the traditional overall monitoring method due to the lack of component subdivision. It effectively improves the monitoring accuracy of the power-on process of the second voltage regulation module, enabling it to better adapt to the actual power-on duration characteristics of different modules in different environments, helping to promptly detect potential power-on abnormal problems, and ensuring the stability and reliability of the server motherboard power supply system.

[0088] In some embodiments, the server power-on timeout monitoring system further includes: if the first controller does not receive the reset signal within the third target time, the first controller determines that at least one of the at least two second voltage regulation modules has a power-on timeout; the third target time is the time after the third timer starts timing and intervals the third preset duration threshold.

[0089] The third target time refers to the time point corresponding to the third preset duration threshold after the third timer starts timing, which is the key time node for judging whether the power-on of the second voltage regulation module times out. For example, if the third preset duration threshold is set to 2000 milliseconds, the third target time is the 2000th millisecond moment after the third timer starts. The third preset duration threshold: a time threshold preset according to the normal power-on characteristics of the second voltage regulation module, comprehensively considering factors such as the hardware circuit characteristics, power supply requirements of the second voltage regulation module, and the collaborative working time with other components on the motherboard. This threshold is determined through a large number of experimental tests and actual application scenario analyses, and is used as a standard for judging whether the power-on time of the second voltage regulation module exceeds the normal range. The unit is generally milliseconds or seconds. For example, for a certain model of the second voltage regulation module, its third preset duration threshold may be 1800 milliseconds. The third power-on timeout state: when the first controller does not receive the reset signal within the third target time, it is determined that at least one of the at least two second voltage regulation modules has a power-on timeout, and the corresponding state is marked as the third power-on timeout state. This state information will be recorded and identified inside the first controller for subsequent abnormal handling and system diagnosis. At the same time, as part of the power-on timeout monitoring result, it provides an important basis for the fault troubleshooting and maintenance of the entire server system.

[0090] When the first controller receives the first power ready signal sent by the expansion board, the third timer starts timing. The first controller monitors the reset signal sent by the second processor on the main board in real time through a dedicated signal monitoring pin, continuously scans the signal line connected to the second processor, and determines whether the signal state has changed. When the third timer reaches the third target time (i.e., the time point after the third preset duration threshold has elapsed since the third timer started timing), if the first controller still has not monitored the reset signal, it is determined that there is a power-on timeout in at least one of the at least two second voltage regulation modules. At this time, the first controller marks the power-on state of the corresponding second voltage regulation module as the third power-on timeout state in the internal state storage area, and records this state information as part of the power-on timeout monitoring result.

[0091] By clearly setting the third target time and the third preset duration threshold, it is possible to accurately determine whether there is a timeout exception in the power-on process of the second voltage regulation module. This helps to promptly detect possible hardware failures (such as voltage regulation circuit failures, power management chip abnormalities, etc.) or software initialization problems in the second voltage regulation module, improves the server system's ability to identify power-on abnormalities in key power supply components on the main board, and avoids server startup failures or unstable operation caused by power supply abnormalities.

[0092] In some embodiments, the server power-on timeout monitoring system further includes: when the first controller determines that there is at least one second voltage regulation module with a power-on timeout among the at least two second voltage regulation modules, the first controller obtains the third state value of the enable signal corresponding to each of the at least two second voltage regulation modules, and obtains the fourth state value of the third power ready signal corresponding to each of the at least two second voltage regulation modules; the first controller determines the state of the second voltage regulation module corresponding to the third state value being the third preset state value and the fourth state value being the fourth preset state value as the third power-on timeout state; the power-on timeout monitoring result includes the third power-on timeout state or the third power-on not timed out state.

[0093] The third state value refers to the state value of the enable signal at a certain specific moment, generally represented by binary "0" or "1". For example, "1" indicates that the enable signal is in the active state, and "0" indicates that the enable signal is in the off state. The first controller can understand whether the second voltage regulation module has received a power-on command by reading this state value. The third power ready signal is a signal sent by the second voltage regulation module after completing its own power-on process and reaching a stable power supply state, used to inform the first controller that its power state is ready. This signal is also a digital signal. For example, a high level indicates power ready, and a low level indicates power not ready. It is transmitted to the first controller through a dedicated signal line, facilitating the first controller to monitor the power-on process of the second voltage regulation module. The third power ready signal can be a PWRGD signal.

[0094] The fourth status value refers to the status value of the third power supply ready signal at a specific moment, and is also represented by the binary "0" or "1". For example, "1" indicates that the second voltage regulation module has been successfully powered on and is stably supplying power, and "0" indicates that the power-on process has not been completed or a fault has occurred. By monitoring this status value, the first controller can determine the power-on result of the second voltage regulation module. The third preset status value is the expected status value of the predefined enable signal, representing the standard status in which the second voltage regulation module should be in the power-on active state. For example, in the normal power-on process, the third preset status value is set to "1", meaning that at this time, the second voltage regulation module should have received the enable signal and started to power on. The fourth preset status value is the expected status value of the third power supply ready signal, representing the standard status in which the second voltage regulation module has been successfully powered on and reached the stable power supply state. For example, when the fourth preset status value is set to "1", it means that the second voltage regulation module has completed power-on and can supply power normally. These preset status values are determined during the server system design stage according to the logical relationship of the hardware circuit and the normal working requirements, and are used as the basis for judging whether the power-on of the second voltage regulation module is normal.

[0095] When the first controller determines that there is a power-on timeout for at least one of the at least two second voltage regulation modules, it immediately starts further monitoring of these second voltage regulation modules. The first controller reads the third status value of the enable signal corresponding to each second voltage regulation module and the fourth status value of the third power supply ready signal through the internal signal monitoring circuit. Specifically, the first controller sends a monitoring request to the enable signal line and the third power supply ready signal line of each second voltage regulation module, obtains the current signal status, and stores these status values in the internal temporary register. After obtaining the third status value and the fourth status value of each second voltage regulation module, the first controller compares them with the pre-stored third preset status value and the fourth preset status value one by one. For each second voltage regulation module, if its third status value is equal to the third preset status value and at the same time the fourth status value is equal to the fourth preset status value, it is determined that the second voltage regulation module is in the third power-on timeout state. Otherwise, it is considered that the module may be in other abnormal states or the power-on has not timed out. Finally, the first controller summarizes these determination results to form a detailed power-on timeout monitoring result, which includes the specific power-on status information of each second voltage regulation module for subsequent system fault diagnosis and handling.

[0096] By obtaining and analyzing the status of the enable signal and the status of the third power supply ready signal of the second voltage regulation module, it is possible to accurately locate which specific second voltage regulation module has a power-on timeout problem. This avoids blindly checking all second voltage regulation modules, improves the efficiency and accuracy of fault diagnosis, and provides a clear direction for subsequent repair and replacement work.

[0097] In some embodiments, the server power-on timeout monitoring system further includes: if the second controller parses that the power-on timeout monitoring result contains the first power-on timeout state, the second controller determines that there is an abnormality in the first voltage regulation module corresponding to the first state value being the first preset state value and the second state value being the second preset state value; the second controller determines that there is an abnormality in the first voltage regulation module corresponding to the first state value being the first preset state value and the second state value being the second preset state value as the abnormal parsing result.

[0098] The second controller receives the power-on timeout monitoring result sent by the first controller in real time through a preset communication interface (such as an Ethernet interface or a serial communication interface). After receiving the data, it uses a pre-written parsing program to parse the monitoring result according to the preset data format and coding rules, extracts the power-on status information of each component included therein, and particularly pays attention to whether there are relevant records of the first power-on timeout state. When the second controller detects that the first power-on timeout state exists in the monitoring result, it further extracts the first state value and the second state value of the corresponding first voltage regulation module from the monitoring result. These state values are compared one by one with the pre-stored first preset state value and second preset state value. Specifically, the first preset state value and the second preset state value are read from the configuration parameters stored internally, and then in the program, the actual state value and the preset value are matched and judged through conditional judgment statements. If it is found that the first state value of a certain first voltage regulation module is equal to the first preset state value and the second state value is equal to the second preset state value at the same time, it is determined that there is an abnormality in the first voltage regulation module. At this time, the second controller records this abnormal situation in the abnormal parsing result, and the recorded content includes the type of the abnormal component (the first voltage regulation module), the specific module identifier (such as the position number of the module in the server or the circuit connection identifier), and the manifestation form of the abnormality (such as power-on timeout and the enable signal and the power ready signal conforming to the preset abnormal state combination). Finally, the abnormal parsing result can be sorted and stored in a preset format for subsequent query and analysis.

[0099] By deeply parsing the power-on timeout monitoring result, it is possible to accurately find the first voltage regulation module with the power-on timeout problem, and further determine its specific abnormal situation through the comparison of state values. This precise positioning ability avoids large-scale blind troubleshooting of numerous components of the server, improves the efficiency and accuracy of fault diagnosis, shortens the system fault repair time, and improves the availability and reliability of the server.

[0100] In some embodiments, the server power-on timeout monitoring system further includes: if the second controller parses that the power-on timeout monitoring result contains the second power-on timeout state, it is determined that there is an abnormality in the expansion board; the second controller determines that there is an abnormality in the expansion board as the abnormal parsing result.

[0101] The second controller receives in real time the power-on timeout monitoring result sent by the first controller through a preset communication interface (such as an Ethernet interface). After receiving the monitoring result, it uses a pre-written parsing program to parse the data according to a predefined data format, extracts the power-on status information of each component, and focuses on whether there is a record of the second power-on timeout status. If the second controller detects the second power-on timeout status in the monitoring result, according to the preset analysis logic, it directly determines that the expansion board is abnormal. At this time, the second controller will create a new exception record in the internal exception record module, recording the exception situation of the expansion board, including the time when the exception occurred, the identification information of the expansion board (such as slot position, hardware identification, etc.) and the exception type (power-on timeout). The second controller records the determined abnormal situation of the expansion board as the abnormal parsing result and reports the result to the management platform of the system or stores it in the local log file according to the preset reporting mechanism. At the same time, it reminds the system administrator or maintenance personnel to pay attention to the abnormal status of the expansion board by means of indicator lights, alarm sounds or warning prompts popping up on the user interface.

[0102] Through the accurate parsing of the power-on timeout monitoring result, the second controller can quickly determine whether there is a power-on timeout abnormality in the expansion board. It avoids the cumbersome process of manually checking each component of the server one by one, improves the efficiency and accuracy of fault diagnosis, shortens the system fault repair time, and improves the overall availability and reliability of the server system.

[0103] In some embodiments, the server power-on timeout monitoring system further includes: if the second controller parses that the power-on timeout monitoring result contains a third power-on timeout status, the second controller determines that the second voltage regulation module corresponding to the third status value being the third preset status value and the fourth status value being the fourth preset status value is abnormal; the second controller determines that the second voltage regulation module corresponding to the third status value being the third preset status value and the fourth status value being the fourth preset status value is abnormal as the abnormal parsing result.

[0104] The second controller receives the power-on timeout monitoring result sent by the first controller in real time through a preset communication interface (such as an Ethernet interface or a serial communication interface). After receiving the data, it uses a pre-written parsing program to parse the monitoring result according to the preset data format and encoding rules, extracts the power-on status information of each component contained therein, and particularly pays attention to whether there are relevant records of the third power-on timeout status. When the second controller detects the third power-on timeout status in the monitoring result, it further extracts the third status value and the fourth status value of the corresponding second voltage regulation module from the monitoring result. These status values are compared one by one with the pre-stored third preset status value and fourth preset status value. The specific operation is to read the third preset status value and the fourth preset status value from the configuration parameters stored internally, and then use conditional judgment statements in the program to match and judge the actual status value and the preset value. If it is found that the third status value of a certain second voltage regulation module is equal to the third preset status value, and at the same time the fourth status value is equal to the fourth preset status value, it is determined that the second voltage regulation module is abnormal. At this time, the second controller records this abnormal situation in the abnormal parsing result, and the recorded content includes the type of abnormal component (second voltage regulation module), the specific module identifier (such as the position number of the module in the server or the circuit connection identifier), and the form of abnormal manifestation (such as power-on timeout and the enable signal and the third power ready signal conforming to the preset abnormal status combination). Finally, the abnormal parsing result can be sorted and stored in a preset format for subsequent query and analysis.

[0105] Record and present the abnormal parsing result in a clear and definite manner, so that the system administrator or maintenance personnel can intuitively understand the abnormal situations that occur during the server power-on process. The abnormal parsing result can be used as a guiding basis for maintenance work, helping maintenance personnel quickly enter the maintenance process, reducing the fault diagnosis time, improving the maintenance efficiency and quality, and at the same time providing valuable data support for the subsequent optimization and improvement of the system.

[0106] To facilitate a better understanding of the server power-on timeout monitoring system, as Figure 2 shown Figure 2FIG. 0 is a schematic structural diagram of another server power-on timeout monitoring system provided by an embodiment of the present application. According to the timing relationship between the motherboard, the switching board, and the GPU board, and the power-on times of the three boards, three power-on timeout monitoring modules are set in the motherboard CPLD; the first power-on timeout monitoring module (i.e., the first monitoring module) is used to implement the power-on timeout monitoring function of P3V3 VR and P12V VR on the motherboard. Since the power-on speeds of the above two VRs are relatively fast, the set power-on timeout time of this module is relatively short; the second power-on timeout monitoring module (i.e., the second monitoring module) is used to implement the power-on timeout monitoring function of the FPGA_READY signal on the switching board and the GPU board. As known from the above, the time difference for different manufacturers' GPUs to send out the FPGA_READY signal after alternating current (AC) power-on is relatively large. Therefore, in order to ensure the universality of the server chassis, the power-on timeout time of this module needs to be set according to the longest power-on time of the GPU, so as to ensure that when the server chassis is paired with GPUs from different manufacturers, the possibility of false alarms due to too short a set power-on timeout time can be avoided. Therefore, the set power-on timeout time of the second power-on timeout monitoring module is relatively long; the third power-on timeout monitoring module (i.e., the third monitoring module) is used to implement the power-on timeout monitoring function of CPU VR and DIMM VR on the motherboard, as well as the power-on timeout monitoring function of the GPU board. The power-on speeds of CPU VR and DIMM VR are relatively fast. Although the GPU board generates the FPGA_READY signal slowly after AC, but after generating this signal and receiving the power-on signal sent by the switching board, the power-on speed of the VR on the GPU board is relatively fast. Therefore, the set power-on timeout time of the third power-on timeout monitoring module is relatively short. However, it should be clear that Figure 2 is only a schematic structure of a server power-on timeout monitoring system provided by the present application, and does not limit that the server power-on timeout monitoring system can only be Figure 2 the structure shown, and the server power-on timeout monitoring system can also be other structures.

[0107] After the motherboard CPLD collects that the power-on timeout monitoring module start signal or end signal is valid, it will start or end the timer of the corresponding power-on timeout monitoring module. If the timer reaches the set timeout time limit without being closed after it is started, the CPLD will record the relevant exception information in the Inter-Integrated Circuit (I2C) register, and at the same time will trigger an exception interrupt, and inform the BMC that there is an exception interrupt on the current motherboard by pulling down the General-purpose input / output (GPIO). After the BMC reads the register of the CPLD through I2C, it parses to obtain the specific reason for the power-on timeout.

[0108] To facilitate a better understanding of the connection relationships between different components in the server, as Figure 3 shown, Figure 3 FIG. 0000255 is a schematic structural diagram of the connection relationships between different components provided by an embodiment of the present application. The motherboard CPLD communicates with the switchboard CPLD through the GPIO interface to implement the interaction functions of signals such as the switchboard power-on signal, the switchboard power-on completion signal (SW_PWRGD), the FPGA_READY signal, and the de-reset signal; the motherboard CPLD interacts with the CPU through the GPIO to implement signals such as the Sleep Type 3 Signal (SLP_S3), the Sleep Type 4 Signal (SLP_S4), the Reference Clock READY (REFCLK_READY) signal, the Central Processing Unit Power Good (CPU_PWRGD) signal, and the reset (PLTRST) signal; the motherboard CPLD interacts with the Dual-Inline-Memory-Modules (DIMM) through the GPIO to implement the interaction function of the Dual-Inline-Memory-ModulesPWRGD FAIL (DIMM_PWRGD_FAIL) signal. Among them, SLP_S3 and SLP_S4 are response signals used to inform the motherboard CPLD to start power-on; the motherboard CPLD completes the transmission of the interrupt signal to the BMC through the GPIO, and also realizes the transmission of register data to the BMC through the I2C; the motherboard CPLD interacts with the motherboard VR chip through the GPIO, including controlling the enable signal (ENABLE) of the Voltage Regulator (VR) chip and receiving the reset (PWRGD) signal output by the VR chip.

[0109] To facilitate a better understanding of the entire process of server power-on timeout monitoring, as Figure 4 shown, Figure 4This is a schematic flowchart of the entire process of server power-on timeout monitoring provided by the embodiments of this application. After the server is connected to the alternating current (AC) power supply, the standby (STBY) power of each board card will be quickly powered on. According to the power-on timing requirements, after the main board CPLD collects the response signals SLP_S3 and SLP_S4 sent by the CPU, on the one hand, it will push up the enable signal of the main board P12V VR to power on the main board P12V, on the other hand, it will send a power-on signal to the switch board CPLD, and at the same time, it will also start the timing of the first power-on timeout monitoring module and the second power-on timeout monitoring module of the main board; after the main board CPLD receives the PWRGD signal of the P12VVR, it will then push up the enable signal of the main board P3V3 VR to power on the main board P3V3. When the main board CPLD receives the PWRGD signal of the P3V3 VR, the main board CPLD will wait for the FPGA_READY signal sent by the switch board CPLD, and at the same time, it will also generate a timing end flag for the timer of the first power-on timeout monitoring module. If the timer timing time is less than 5 seconds, it is determined that the power-on of the P12V VR and the P3V3 VR is not timed out. If the timing exceeds 5 seconds and the timing end flag is not received, the CPLD will lock the value of the current timing state machine and determine that there is a power-on timeout situation of the P12V VR or the P3V3 VR currently. Which power supply causes the power-on timeout needs to be determined according to the ENABLE signal and the PWRGD signal of the P12V VR and the P3V3 VR in the timing state machine at the moment when the timer counts to 5s. The determination principle is: if the ENABLE signal of the P12V VR is high at this time, and the PWRGD signal of the P12V VR is low, it is determined that the P12V power-on is timed out. If the ENABLE signal of the P3V3 VR is high at this time, and the PWRGD of the P3V3 VR is low, it is determined that the P3V3 power-on is timed out. When a power-on timeout exception occurs, the CPLD will inform the BMC of this state. However, it should be clear that this statement is not intended to limit the entire process of server power-on timeout monitoring as Figure 4 shown in the flowchart, and the entire process of server power-on timeout monitoring can also be implemented through other processes.

[0110] After the main board CPLD receives the FPGA_READY signal sent by the switch board, the main board CPLD will continue to push up the enable signals of the VR related to the CPU and DIMM, and at the same time, it will also start the timing of the third power-on timeout monitoring module of the main board. Finally, it will also generate a timing end flag for the timer of the second power-on timeout monitoring module. If the timer timing time is less than 12 minutes, it is determined that the power-on of the FPGA_READY signal on the switch board and the GPU board is not timed out. If the timing exceeds 12 minutes and the timing end flag is not received, the CPLD will lock the value of the current timing state machine and determine that there is a power-on timeout situation of the FPGA_READY signal on the current switch board and the GPU board; After the power-on of the VRs for the CPU and DIMMs on the mainboard is completed, the CPLD will receive the PWRGD signal of the corresponding VR. After the CPU is powered on, it will output a clock signal. After the clock is stable, the CPU will send the REFCLK_READY signal to the CPLD. After receiving this signal, the mainboard CPLD will wait for the SW_PWRGD signal sent by the switchboard CPLD; after receiving the above signals, the mainboard CPLD will send the CPU_PWRGD signal to the CPU, indicating that the CPU is powered on and ready. After receiving this signal, the CPU will send out the PLTRST system reset release indication signal. After receiving the PLTRST signal, on the one hand, the CPLD will generate a reset release signal to the CPU, PCIe devices, etc. on the mainboard, as well as the switchboard CPLD. At the same time, after the PLTRST signal is generated, it indicates that all devices on the mainboard have been powered on. At this time, the mainboard CPLD will generate a timing end flag for the timer of the third power-on timeout monitoring module. If the timing time of the timer is less than 10 seconds, it is determined that the power-on of the CPU VR, DIMM VR, and GPU board on the mainboard is not timed out. If the timing exceeds 10 seconds and the timing end flag is not received, the CPLD will lock the value of the current timing state machine and determine that there is a power-on timeout situation. The specific determination logic is the same as the determination principle of the first power-on timeout monitoring module above.

[0111] By reasonably dividing different power-on timeout monitoring areas and setting different power-on timeout times, the function of segmental monitoring of the server power-on timeout is realized; it meets the requirements of the server head (mainboard + switchboard) with different GPUs; it improves the accuracy of power-on timeout monitoring and the timeliness of reporting after a power-on timeout exception occurs.

[0112] According to an embodiment of the present application, the present application also proposes a server power-on timeout monitoring method, as Figure 5 shown Figure 5 is a schematic flowchart of a server power-on timeout monitoring method provided by an embodiment of the present application. The method is applied to a server power-on timeout monitoring system, and the method includes the following steps: Step 101, using the first controller to perform power-on timeout monitoring on different components in segments according to the power-on sequence of different components in the server, and obtaining the power-on timeout monitoring results of different components.

[0113] Step 102, using the first controller to transmit the power-on timeout monitoring results to the second controller.

[0114] Step 103, using the second controller to perform abnormal analysis on the power-on timeout monitoring results to obtain the abnormal analysis results.

[0115] Through this application, since the first controller monitors the power-on timeout of different components according to the power-on sequence of different components in the server, obtains the power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to the second controller, the second controller then performs anomaly analysis on the power-on timeout monitoring results to obtain the anomaly analysis results. Since the power-on times of different components are inconsistent, segmented monitoring can accurately capture the specific power-on timeout situations of different components, thereby improving the accuracy of the server power-on timeout monitoring. Therefore, the technical problem of low accuracy of the server power-on timeout monitoring can be solved, and the technical effect of improving the accuracy of the server power-on timeout monitoring can be achieved.

[0116] As a refinement of step 101, the first controller includes a first monitoring module, a second monitoring module, and a third monitoring module. When performing the power-on timeout monitoring of different components in segments according to the power-on sequence of different components in the server by using the first controller, it can be implemented in but not limited to the following ways, including: using the first monitoring module to monitor the power-on time of at least two first voltage regulation modules of the motherboard in different components when the first controller triggers the startup; using the second monitoring module to monitor the power-on time of the expansion board in different components when the first controller triggers the startup; using the third monitoring module to monitor the power-on time of at least two second voltage regulation modules of the motherboard when the first controller receives the first power ready signal sent by the expansion board in different components; the power-on time interval between the first voltage regulation module and the second voltage regulation module is greater than the preset interval threshold.

[0117] Since the embodiments of the server power-on timeout monitoring method part correspond to the embodiments of the server power-on timeout monitoring system part, please refer to the description of the embodiments of the server power-on timeout monitoring system part for the embodiments of the server power-on timeout monitoring method part, which will not be elaborated here for the time being. And it has the same beneficial effects as the above-mentioned server power-on timeout monitoring system.

[0118] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0119] The embodiments of the present application also provide a server power-on timeout monitoring device. Figure 6 The following is a schematic structural diagram of a server power-on timeout monitoring device provided by an embodiment of the present application, as Figure 6 shown, including: A monitoring unit 21, configured to use the first controller to perform power-on timeout monitoring on different components in segments according to the power-on sequence of different components in the server, and obtain the power-on timeout monitoring results of different components; A transmission unit 22, configured to transmit the power-on timeout monitoring result to a second controller by using a first controller; An analysis unit 23, configured to perform anomaly analysis on the power-on timeout monitoring result by using the second controller to obtain an anomaly analysis result.

[0120] With this application, since the first controller monitors the power-on timeout of different components in the server according to the power-on sequence of different components, obtains the power-on timeout monitoring results of different components, and transmits the power-on timeout monitoring results to the second controller, and the second controller then performs anomaly analysis on the power-on timeout monitoring results to obtain an anomaly analysis result. Since the power-on times of different components are inconsistent, segmented monitoring can accurately capture the specific power-on timeout conditions of different components, thereby improving the accuracy of power-on timeout monitoring of the server. Therefore, the technical problem of low accuracy of power-on timeout monitoring of the server can be solved, and the technical effect of improving the accuracy of power-on timeout monitoring of the server can be achieved.

[0121] For the description of the features in the corresponding embodiments of the server power-on timeout monitoring device, reference can be made to the relevant descriptions in the corresponding embodiments of the server power-on timeout monitoring system, which will not be elaborated here one by one.

[0122] An embodiment of this application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above embodiments of the server power-on timeout monitoring method.

[0123] An embodiment of this application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any one of the above embodiments of the server power-on timeout monitoring method when running.

[0124] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (abbreviated as ROM), random access memory (abbreviated as RAM), mobile hard disk, magnetic disk, or optical disc, and other media that can store computer programs.

[0125] An embodiment of this application further provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any one of the above embodiments of the server power-on timeout monitoring method are implemented.

[0126] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and the computer program, when executed by a processor, implements the steps in any of the above-described embodiments of the server power-on timeout monitoring method.

[0127] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0128] The above has introduced in detail a server power-on timeout monitoring system, method, medium, device, and program product provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A server power-on timeout monitoring system, characterized in that: include: a first controller and a second controller; The first controller is connected to the second controller; The first controller performs power-on timeout monitoring on different components in the server in sections according to the power-on sequence of the different components, obtains power-on timeout monitoring results of the different components, and transmits the power-on timeout monitoring results to the second controller; The second controller performs an abnormality analysis on the power-on timeout monitoring result to obtain an abnormality analysis result.

2. The server power-on timeout monitoring system according to claim 1, characterized in that: The first controller includes: a first monitoring module, a second monitoring module and a third monitoring module; The first monitoring module monitors the power-on time of at least two first voltage regulating modules of the mainboard in the different components when the first controller triggers the power-on; The second monitoring module monitors the power-on time of the expansion boards in the different components when the first controller triggers the power-on; When the first controller receives the first power-ready signal sent by the expansion board in the different components, the third monitoring module monitors the power-on time of at least two second voltage regulation modules of the main board; the power-on time interval between the first voltage regulation module and the second voltage regulation module is greater than a preset interval threshold.

3. The server power-on timeout monitoring system according to claim 2, characterized in that: The first monitoring module includes: a first timer; When the first controller triggers the power-on, the first controller controls the first timer to start timing; If the first controller receives a second power-ready signal sent by a target first voltage regulating module, the first controller controls the first timer to end timing, and obtains a first timing duration from the start timing to the end timing of the first timer; the target first voltage regulating module is the first voltage regulating module with the latest power-on time among the at least two first voltage regulating modules; If the first controller determines that the first timing duration is less than a first preset duration threshold, the first controller determines that the power-on of the at least two first voltage regulating modules has not timed out; The first controller determines the states of the at least two first voltage regulating modules as a first power-on non-timeout state.

4. The server power-on timeout monitoring system according to claim 3, characterized in that: The server power-on timeout monitoring system also includes: If the first controller does not receive the second power-ready signal within the first target time, the first controller determines that at least one of the at least two first voltage regulation modules has a power-on timeout; the first target time is the time interval between the first preset time threshold after the first timer starts timing.

5. The server power-on timeout monitoring system according to claim 4, characterized in that: The server power-on timeout monitoring system also includes: When the first controller determines that at least one of the at least two first voltage regulating modules has a power-on timeout, the first controller obtains a first state value of an enable signal corresponding to each of the at least two first voltage regulating modules, and obtains a second state value of a second power-ready signal corresponding to each of the at least two first voltage regulating modules; The first controller determines the state of the first voltage regulation module corresponding to the first state value being a first preset state value and the second state value being a second preset state value as a first power-on timeout state; the power-on timeout monitoring result includes the first power-on timeout state or the first power-on non-timeout state.

6. The server power-on timeout monitoring system according to claim 2, characterized in that: The server power-on timeout monitoring system also includes: The first controller obtains a target model of a first processor in the expansion board; The first controller searches for the target second preset time threshold corresponding to the target model according to a pre-established mapping relationship between the model and the second preset time threshold; The first controller determines the target second preset time threshold as the preset time threshold of the second monitoring module.

7. The server power-on timeout monitoring system according to claim 6, characterized in that: The second monitoring module includes: a second timer; When the first controller triggers the power-on, the first controller controls the second timer to start timing; If the first controller receives the first power-ready signal, the first controller controls the second timer to end timing, and obtains a second timing duration from the start timing to the end timing of the second timer; If the first controller determines that the second timing duration is less than the target second preset duration threshold, it is determined that the expansion board power-on has not timed out; The state of the expansion board is determined to be a second power-on non-timeout state.

8. The server power-on timeout monitoring system according to claim 7, characterized in that: The server power-on timeout monitoring system also includes: If the first controller does not receive the first power-ready signal within the second target time, it is determined that the expansion board is powered on timeout; the second target time is the time after the second timer starts timing and the interval is the second preset time threshold of the target; The first controller determines the state of the expansion board as a second power-on timeout state; and the power-on timeout monitoring result includes the second power-on timeout state or the second power-on non-timeout state.

9. The server power-on timeout monitoring system according to claim 2, characterized in that: The third monitoring module includes: a third timer; When the first controller receives the first power-ready signal sent by the expansion board, the first controller controls the third timer to start timing; If the first controller receives a reset signal sent by the second processor of the mainboard, the first controller controls the third timer to end timing, and obtains a third timing duration from the start timing to the end timing of the third timer; If the first controller determines that the third timing duration is less than a third preset duration threshold, the first controller determines that the power-on of the at least two second voltage regulating modules has not timed out; The first controller determines the states of the at least two second voltage regulating modules as a third power-on non-timeout state.

10. The server power-on timeout monitoring system according to claim 9, characterized in that: The server power-on timeout monitoring system also includes: If the first controller does not receive the reset signal within the third target time, the first controller determines that at least one of the at least two second voltage regulation modules has a power-on timeout; the third target time is the time interval between the third preset time threshold after the third timer starts timing.

11. The server power-on timeout monitoring system according to claim 10, characterized in that: The server power-on timeout monitoring system also includes: When the first controller determines that at least one of the at least two second voltage regulating modules has a power-on timeout, the first controller obtains a third state value of an enable signal corresponding to each of the at least two second voltage regulating modules, and obtains a fourth state value of a third power-ready signal corresponding to each of the at least two second voltage regulating modules; The first controller determines the state of the second voltage regulation module corresponding to the third state value being the third preset state value and the fourth state value being the fourth preset state value as the third power-on timeout state; the power-on timeout monitoring result includes the third power-on timeout state or the third power-on non-timeout state.

12. The server power-on timeout monitoring system according to claim 5, characterized in that: The server power-on timeout monitoring system also includes: If the second controller parses out that the power-on timeout monitoring result includes the first power-on timeout state, the second controller determines that the first state value is a first preset state value and the second state value is a second preset state value and the first voltage regulation module corresponding to the value has an abnormality; The second controller determines that an abnormality exists in a first voltage regulating module corresponding to the first state value being a first preset state value and the second state value being a second preset state value as the abnormality analysis result.

13. The server power-on timeout monitoring system according to claim 8, characterized in that: The server power-on timeout monitoring system also includes: If the second controller analyzes that the power-on timeout monitoring result includes the second power-on timeout state, it is determined that the expansion board is abnormal; The second controller determines that there is an abnormality in the expansion board as the abnormality analysis result.

14. The server power-on timeout monitoring system according to claim 11, characterized in that: The server power-on timeout monitoring system also includes: If the second controller analyzes that the power-on timeout monitoring result includes the third power-on timeout state, the second controller determines that the third state value is the third preset state value and the fourth state value is the fourth preset state value, and there is an abnormality in the second voltage regulation module corresponding to the third state value; The second controller determines that the second voltage regulation module corresponding to the third state value being a third preset state value and the fourth state value being a fourth preset state value has an abnormality as the abnormality analysis result.

15. A server power-on timeout monitoring method, characterized in that: include: Using the first controller to perform power-on timeout monitoring on different components in the server in sections according to the power-on sequence of the different components, and obtain power-on timeout monitoring results of the different components; Using the first controller to transmit the power-on timeout monitoring result to the second controller; The second controller is used to perform an abnormal analysis on the power-on timeout monitoring result to obtain an abnormal analysis result.

16. The server power-on timeout monitoring method according to claim 15, characterized in that: The first controller includes a first monitoring module, a second monitoring module and a third monitoring module. The first controller is used to perform power-on timeout monitoring on different components in the server in sections according to the power-on sequence of the different components, including: Using the first monitoring module to monitor the power-on time of at least two first voltage regulating modules of the mainboard in the different components when the first controller triggers the startup; Using the second monitoring module to monitor the power-on time of the expansion boards in the different components when the first controller triggers the power-on; The third monitoring module is used to monitor the power-on time of at least two second voltage regulation modules of the mainboard when the first controller receives the first power-ready signal sent by the expansion board in the different components; the power-on time interval between the first voltage regulation module and the second voltage regulation module is greater than a preset interval threshold.

17. A server power-on timeout monitoring device, characterized in that: include: A monitoring unit, configured to perform power-on timeout monitoring on different components in the server in sections according to the power-on sequence of the different components using the first controller, and obtain power-on timeout monitoring results of the different components; A transmission unit, configured to transmit the power-on timeout monitoring result to a second controller using the first controller; The analysis unit is used to use the second controller to perform abnormal analysis on the power-on timeout monitoring result to obtain an abnormal analysis result.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the server power-on timeout monitoring method as described in any one of claims 15 to 16 when executing the computer program.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the server power-on timeout monitoring method as claimed in any one of claims 15 to 16.

20. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the server power-on timeout monitoring method as claimed in any one of claims 15 to 16 are implemented.

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