Direct memory access control method and system, electronic equipment and storage medium

Abstract

The invention provides a direct memory access control method and system, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the following steps: receiving a direct memory access (DMA) descriptor sent by a driving program of input / output (IO) equipment; the DMA descriptor comprises an initial address of a virtual address corresponding to the DMA operation, length information and an identifier of the IO equipment; querying a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation in a mapping table of an input / output translation backup buffer IOTLB based on the DMA descriptor; the mapping table is stored in a cache; and in response to the fact that the target mapping relation does not exist in the mapping table of the IOTLB, querying the target mapping relation between the virtual address and the physical address corresponding to the DMA operation in a page table of the memory based on the DMA descriptor, and updating the target mapping relation to the mapping table of the IOTLB. According to the method and the device, the IOVA hit rate of the IOTLB can be improved, the DMA operation efficiency is improved, and the overall performance of the processor is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and particularly to a direct memory access control method, system, electronic device, and storage medium. Background Art

[0002] Multi-core Reduced Instruction Set Computing (RISC) server processors have numerous Input / Output (IO) resources. The most typical IO interface is the Peripheral Component Interconnect Express (PCIe), such as PCIe network cards, PCIe graphics cards, PCIe sound cards, PCIe storage, PCIe to USB, etc. When a PCIe peripheral accesses the memory of a multi-core RISC processor (such as RISC-V, i.e., the fifth generation of RISC), it needs to go through an Input and Output Memory Management Unit (IOMMU). The IOMMU is a link in the Direct Memory Access (DMA) process and can implement the function of virtual address to physical address conversion during the DMA process of PCIe and other peripherals. Among them, DMA can enable direct communication between a device and memory without passing through the Central Processing Unit (CPU).

[0003] However, due to the large number of IO interfaces with integrated DMA functions in multi-core RISC processors, problems such as low working efficiency of the IOMMU function, high memory overhead, and low storage efficiency may occur in applications, and the DMA access requirements of numerous IOs cannot be met in a timely manner, resulting in a relatively low overall performance of the multi-core RISC processor and the inability to exert the best performance of the multi-core processor. Summary of the Invention

[0004] The present disclosure provides a direct memory access control method, system, electronic device, and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, there is provided a direct memory access control method, including: receiving a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device; the DMA descriptor includes a starting address of a virtual address corresponding to a DMA operation, length information, and an identifier of the IO device; based on the DMA descriptor, querying a target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in a mapping table of an input / output translation lookaside buffer (IOTLB); the mapping table is stored in a cache; in response to the non-existence of the target mapping relationship in the mapping table of the IOTLB, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in a page table of a memory based on the DMA descriptor, and updating the target mapping relationship to the mapping table of the IOTLB.

[0006] In an implementable manner, the querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor, and updating the target mapping relationship to the mapping table of the IOTLB includes: obtaining the sending order of the DMA descriptors of each of the IO devices; based on each of the DMA descriptors, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order, and updating the target mapping relationship to the mapping table of the IOTLB.

[0007] In an implementable manner, a direct memory access control method further includes: in response to the existence of the target mapping relationship in the mapping table of the IOTLB, querying a target mapping relationship between the virtual address and the physical address corresponding to a next DMA descriptor in the mapping table of the IOTLB based on the received next DMA descriptor.

[0008] In an implementable manner, before the querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the input / output translation lookaside buffer (IOTLB) based on the DMA descriptor, the method further includes: obtaining sequentiality information of all virtual addresses and corresponding physical addresses; the sequentiality information includes a starting address and length information; generating a sequential mapping table based on the sequentiality information; and deleting mapping relationships that already exist in the sequential mapping table from the mapping table of the IOTLB.

[0009] In an implementable embodiment, after receiving the direct memory access (DMA) descriptor sent by the driver of the input / output (IO) device, the method further includes: querying, based on the DMA descriptor, a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation in the sequential mapping table; and in response to the non-existence of the target mapping relationship in the sequential mapping table, querying a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation in the mapping table of the input / output translation lookaside buffer (IOTLB).

[0010] In an implementable embodiment, a direct memory access control method further includes: obtaining a timestamp of each time the IO device sends the DMA descriptor and the length information; determining, based on timestamps corresponding to two adjacent DMA descriptors and the length information of the previous DMA descriptor, a unit data transfer time of a statistical period corresponding to the two adjacent DMA descriptors, and determining an average value of all the unit data transfer times; predicting, based on the average value, a target time for the IO device to send the next DMA descriptor; and updating the mapping table of the IOTLB based on the target time.

[0011] In an implementable embodiment, the predicting, based on the average value, a target time for the IO device to send the next DMA descriptor includes: determining a product of the average value and the length information; and determining the target time as a sum of the timestamp of the DMA descriptor last sent by the IO device and the product.

[0012] In an implementable embodiment, the predicting, based on the average value, a target time for the IO device to send the next DMA descriptor includes: determining a product of the average value and the length information; determining a difference between an actual timestamp of the DMA descriptor last sent by the IO device and the target time; and determining the target time as a sum of the actual timestamp, the product, and the difference.

[0013] In an implementable embodiment, the updating the mapping table of the IOTLB based on the target time includes: in response to the target time being greater than a first threshold, deleting a mapping relationship between a virtual address and a physical address corresponding to the IO device in the mapping table of the IOTLB.

[0014] In an implementable embodiment, a direct memory access control method further includes: in response to a priority of the IO device being greater than a second threshold, retaining a mapping relationship between a virtual address and a physical address corresponding to the IO device in the mapping table of the IOTLB.

[0015] In one implementable manner, a direct memory access control method further includes: determining an IO device with a frequency of sending the DMA descriptor greater than a third threshold as a first target IO device; determining an IO device that stores only the mapping relationship between the corresponding virtual address and physical address in the memory as a second target IO device; and updating the mapping relationship between the virtual address and physical address corresponding to the first target IO device and / or the second target IO device to the mapping table of the IOTLB.

[0016] According to a second aspect of the present disclosure, there is provided a direct memory access control system, including: a mapping table update module, the mapping table update module including a register configuration sub-module, a query sub-module, and an update sub-module; the register configuration sub-module, configured to receive a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device; the DMA descriptor including a start address of a virtual address corresponding to a DMA operation, length information, and an identifier of the IO device; the query sub-module, configured to query, based on the DMA descriptor, a target mapping relationship between the virtual address and physical address corresponding to the DMA operation in a mapping table of an input / output translation lookaside buffer (IOTLB); the mapping table being stored in a cache; the update sub-module, configured to, in response to the target mapping relationship not existing in the mapping table of the IOTLB, query, based on the DMA descriptor, the target mapping relationship between the virtual address and physical address corresponding to the DMA operation in a page table of the memory, and update the target mapping relationship to the mapping table of the IOTLB.

[0017] In one implementable manner, the mapping table update module further includes a monitoring sub-module; the monitoring sub-module, configured to monitor the sending order of the DMA descriptors of each IO device, and send the sending order to the update sub-module; the update sub-module, further configured to query, based on each DMA descriptor, the target mapping relationship between the virtual address and physical address corresponding to the DMA operation in the page table of the memory in the sending order, and update the target mapping relationship to the mapping table of the IOTLB.

[0018] In one implementable manner, the query sub-module is further configured to: in response to the target mapping relationship existing in the mapping table of the IOTLB, query, based on the received next DMA descriptor, the target mapping relationship between the virtual address and physical address corresponding to the next DMA descriptor in the mapping table of the IOTLB.

[0019] In one implementable embodiment, a direct memory access control further includes: a virtual address processing module; the virtual address processing module includes: a sequential check sub-module, a generation sub-module, and a deletion sub-module; the sequential check sub-module is further configured to obtain the sequential information of all virtual addresses and corresponding physical addresses; the sequential information includes a starting address and length information; the generation sub-module is further configured to generate a sequential mapping table based on the sequential information; the deletion sub-module is further configured to delete the mapping relationships that already exist in the sequential mapping table from the mapping table of the IOTLB.

[0020] In one implementable embodiment, the virtual address processing module further includes: a table lookup enable module, and the table lookup enable module is configured to: based on the DMA descriptor, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the sequential mapping table; in response to the non-existence of the target mapping relationship in the sequential mapping table, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the IOTLB.

[0021] In one implementable embodiment, a direct memory access control further includes: a resource release module, configured to: obtain the timestamp of each time the IO device sends the DMA descriptor and the length information; based on the timestamps corresponding to two adjacent DMA descriptors and the length information of the previous DMA descriptor, determine the unit data transfer time of the statistical period corresponding to the two adjacent DMA descriptors, and determine the average value of all the unit data transfer times; based on the average value, predict the target time for the IO device to send the next DMA descriptor; based on the target time, update the mapping table of the IOTLB.

[0022] In one implementable embodiment, the resource release module is further configured to: determine the product of the average value and the length information; determine the target time as the sum of the timestamp of the DMA descriptor last sent by the IO device and the product.

[0023] According to a third aspect of the present disclosure, there is provided an electronic device, including: a direct memory access control system as described in the present disclosure, and the direct memory access control system is capable of executing a direct memory access control method as described in the present disclosure.

[0024] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to cause the computer to execute the method as described in the present disclosure.

[0025] A direct memory access control method, system, electronic device and storage medium of the present disclosure receive a DMA descriptor, which includes the starting address of the virtual address corresponding to the DMA operation, the length information and the identifier of the IO device, and when there is no physical address corresponding to the virtual address in the mapping table of the IOTLB, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory, and update the target mapping relationship to the mapping table of the IOTLB. Thus, the present disclosure realizes updating the mapping relationship between the virtual address and the physical address required for the corresponding DMA operation to the mapping table of the IOTLB before the DMA operation instruction reaches the IOMMU, greatly improving the hit rate of the input / output virtual address (IOVA) of the IOTLB, improving the efficiency of the DMA operation, and improving the overall performance of the processor.

[0026] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become easily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, wherein: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0028] Figure 1 Shows a flowchart of a direct memory access control method according to an embodiment of the present disclosure Figure 1 ; Figure 2 Shows a flowchart of a direct memory access control method according to an embodiment of the present disclosure Figure 2 ; Figure 3 Shows a schematic structural diagram of a direct memory access control system in the prior art; Figure 4 Shows a schematic diagram of page table query in the prior art; Figure 5 Shows a schematic structural diagram of a direct memory access control system according to an embodiment of the present disclosure; Figure 6 Shows a schematic structural diagram of a mapping table update module according to an embodiment of the present disclosure; Figure 7 Shows a schematic structural diagram of a virtual address processing module according to an embodiment of the present disclosure; Figure 8The figure shows a schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0029] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0030] Figure 3 The figure shows a schematic diagram of the structure of a direct memory access control system in the prior art, as Figure 3 shown. The N+1 core RISC-V server CPU integrates M+1 IO devices with DMA functions. Among them, N+1 can be 64, 96, 128, etc., and M+1 can be 96, 128, etc. The N+1 cores are such as Figure 3 Core0~CoreN in Figure 3 and the M+1 IO devices with DMA functions are such as Figure 3 IO device 0~IO device M in

[0031] To achieve a fast translation from IOVA to the physical address (PA), the traditional solution designs an Input / Output Translation Lookaside Buffer (IOTLB) module, which is a cache of the I / O page table and caches the mapping relationship from IOVA to PA internally. If the PA corresponding to the IOVA is found in the IOTLB, there is no need to query the page table in the memory. The page table of the IOMMU is stored in the memory, and the efficiency of querying the page table in the memory is very low. Therefore, the traditional IOMMU configures an IOTLB to accelerate the lookup process from IOVA to PA. However, the cache space of the IOTLB is usually small, and the cost of the cache is also high. The cost of expanding the cache space of the IOTLB by increasing the cache is relatively high. Therefore, how to improve the working efficiency of the IOMMU and accelerate the access rate of numerous I / O devices to the DDR memory through DMA without increasing the internal cache of the IOMMU is the problem to be solved in this disclosure.

[0032] Figure 4 The schematic diagram of the page table query in the prior art is shown as Figure 4 shown. The Page Global Directory (PGD) stores the base address of the next-level page table, and the Page Table Entries (PTE) store the page table of the physical address. Both the PGD and the PTE are stored in the memory. The IOMMU obtains the base address of the first-level page table PGD by accessing the page table base address register, then combines the PGD index in the virtual address to find the base address of the next-level page table PTE, and then combines the PTE index in the virtual address to find the Page Frame Number (PFN), and then adds it to the VA to obtain the physical address. Whether it is a two-level page table, a three-level page table, or a four-level page table, the second-level page table is found through the first-level page table, the third-level page table is found through the second-level page table, and finally the physical address is found. The process of this page table query is implemented in the Figure 3 Page Table Walker (PTW) in.

[0033] The traditional multi-core RISC-V server processor IOMMU has the following disadvantages: 1. The cache capacity of the IOTLB, an internal module of the IOMMU, is limited. In the application field of server processors (such as server CPUs), there are numerous peripheral I / Os integrated with DMA functions. There are often multiple access processes accessing the IOMMU simultaneously, but there are situations where they cannot hit in the IOTLB (that is, the mapping relationship between the IOVA and PA of the corresponding process is not cached in the IOTLB). At this time, the IOVA (IO virtual address) of the process that cannot hit can only query the page table in the physical memory of the PTW module multiple times, finally obtain the PA, and then perform the DMA operation. The process of accessing the memory multiple times to look up the table not only results in low efficiency of the I / O DMA operation and slow execution of the corresponding process, but also causes additional memory overhead due to multiple page table queries, further exacerbating the overall performance degradation of the multi-core RISC-V server CPU.

[0034] 2. In the traditional solution, the mapping update strategy of the IOTLB inside the IOMMU is "update on demand". That is, when the I / O DMA wants to access an uncached I / O address, the address conversion will be performed and the IOTLB will be updated. Although such a design brings unnecessary operations, it also causes delays for some accesses and needs to wait until the address conversion is completed. For example, the IOVA accessed by I / O device 0 is 0x1000_0000 - 0x1000_2000. At this time, the PA corresponding to the IOVA is not cached in the IOTLB. In the traditional solution, the page table is first queried to obtain the PA corresponding to the IOVA, and then the IOTLB is updated, waiting for the next DMA access. However, the next DMA access address of this I / O is not necessarily the previous IOVA. Therefore, the page table query and IOTLB update will be performed again. As a result, the traditional solution causes a large number of invalid updates of the IOTLB and a large number of page table accesses. The fundamental reason is that the IOMMU cannot know the address to be accessed by the I / O DMA operation, resulting in the overall performance degradation of the multi-core RISC-V server CPU.

[0035] 3. In the traditional solution, the storage efficiency of the mapping relationship (mapping table) between the IOVA and PA cached in the cache of the IOMMU is low. That is, the cache caches the mapping relationship between the IOVA and PA. That is, 1000 IOVAs correspond to 1000 PAs. Such a mapping relationship results in low storage efficiency and cannot cache more address mappings between the IOVA and PA.

[0036] 4. In the traditional solution, the update and exit mechanism of the mapping table between the IOVA and PA cached in the cache of the IOTLB of the IOMMU is not sensitive. It cannot update and replace the mapping table corresponding to the I / O device that is no longer in need of caching for a long time in a timely manner, and thus cannot leave the cache space for more needed I / O devices, resulting in a low cache hit rate of the IOTLB, and further leading to the overall performance degradation of the multi-core RISC-V server CPU.

[0037] Figure 1 The flowchart of a direct memory access control method according to an embodiment of the present disclosure is shown Figure 1 , such as Figure 1 shown, a direct memory access control method includes: Step S101, receiving a direct memory access (DMA) descriptor sent by a driver of an input / output (I / O) device.

[0038] In this embodiment, the DMA descriptor includes the start address of the virtual address corresponding to the DMA operation, the length information, and the identifier of the I / O device. The IOMMU unit of the multi-core RISC-V server processor receives the DMA descriptors sent by the drivers of each input / output (I / O) device. These DMA descriptors contain in detail the start address of the virtual address for the upcoming DMA operation, which can clearly indicate the start position of this DMA operation in the virtual address space. At the same time, they also contain the length information, which is used to describe the amount of data involved in this DMA operation to determine the scope of the operation, and the identifier of the I / O device, which is used to accurately distinguish which specific I / O device initiated the DMA operation.

[0039] Figure 5 The structural schematic diagram of a direct memory access control system according to an embodiment of the present disclosure is shown, such as Figure 5 shown. A direct memory access control system includes a mapping table update module for updating the virtual address-physical address mapping table. In the present disclosure, the mapping table update module receives the start address information, length information, and the ID of the corresponding I / O device in the descriptors sent by each I / O device driver. At the same time, it involves software driver modification, that is, when the software driver of the I / O device issues a DMA descriptor, it not only issues the descriptor to the DDR, but also issues the DMA descriptor to the mapping table update module such as Figure 5 shown.

[0040] Step S102, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the input / output translation lookaside buffer (IOTLB) based on the DMA descriptor.

[0041] In this embodiment, when the mapping table update module receives a DMA descriptor, the IOMMU unit will query in the mapping table of the IOTLB based on information such as the starting address in the descriptor. The mapping table of the IOTLB is stored in the cache, and its function is to quickly find the correspondence between virtual addresses and physical addresses. By looking up in the IOTLB mapping table, the physical address mapped by the virtual address corresponding to this DMA operation can be quickly determined, so as to provide accurate physical address information for the DMA operation, so that subsequent data transmission can be performed at the correct physical memory location.

[0042] Step S103, in response to the non-existence of the target mapping relationship in the mapping table of the IOTLB, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor, and update the target mapping relationship to the mapping table of the IOTLB.

[0043] In this embodiment, if the mapping table update module does not find the target mapping relationship between the corresponding virtual address and physical address in the mapping table of the IOTLB, then the IOMMU unit will further query in the page table of the memory. The page table of the memory is a data structure that stores the mapping relationship between virtual addresses and physical addresses more comprehensively and in more detail. Although the query speed is relatively slow, all possible mapping relationships can be found. After querying the target mapping relationship in the memory page table, in order to improve the efficiency of subsequent queries for the same virtual address, the mapping table update module will update this newly queried target mapping relationship to the mapping table of the IOTLB, so that when the same virtual address query is encountered next time, it can be quickly hit directly in the IOTLB, thereby improving the overall address translation efficiency and the efficiency of DMA operations.

[0044] In the present disclosure, through the mapping table update module, it is possible to update the mapping table in the IOTLB required for the corresponding DMA operation before the IOMMU executes the DMA operation instruction, greatly improving the IOVA hit rate of the IOTLB, improving the efficiency of IO DMA operations, and improving the overall performance of the processor.

[0045] In another embodiment, a direct memory access control method further includes: In response to the existence of the target mapping relationship in the mapping table of the IOTLB, query the target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor in the mapping table of the IOTLB based on the received next DMA descriptor.

[0046] In this embodiment, after the target mapping relationship corresponding to the current DMA descriptor is found in the mapping table of the IOTLB, it indicates that the address mapping information required for this DMA operation is already available, and the DMA operation can be executed smoothly. At this time, the system will continue to receive the DMA descriptor sent by the next IO device, and based on this new DMA descriptor, query the target mapping relationship between the virtual address and the physical address corresponding to the next DMA operation in the mapping table of the IOTLB, so as to achieve continuous and efficient processing of multiple DMA operations, and improve the data transmission efficiency and performance of the entire system.

[0047] In another embodiment, the step of "querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor and updating the target mapping relationship to the mapping table of the IOTLB" in step S103 includes: Obtaining the sending order of the DMA descriptors of each IO device; based on each DMA descriptor, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order, and updating the target mapping relationship to the mapping table of the IOTLB.

[0048] In this embodiment, the mapping table update module will record and obtain the order in which each IO device sends the DMA descriptor, and sequentially query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory according to this order.

[0049] In an example, if there are 6 IO devices with their IDs being 0 - 5 respectively, and the order in which the IO device DMA controllers initiate the DMA descriptors is: 0 - 3 - 2 - 4 - 1 - 6 - 5, then the mapping table update module will sequentially perform page table query and update the mapping table of the IOTLB according to the order of IO device 0, IO device 3, IO device 2, IO device 4, IO device 1, IO device 6, and IO device 5.

[0050] In another embodiment, before the step S102 of "querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the input / output translation lookaside buffer (IOTLB) based on the DMA descriptor", the method further includes: Obtaining the sequential information of all virtual addresses and their corresponding physical addresses; the sequential information includes the starting address and the length information.

[0051] In this embodiment, as Figure 5The virtual address processing module shown in the figure collects and organizes the sequential information of all virtual addresses and their corresponding physical addresses. This sequential information mainly includes the starting address of each continuous segment and the length information of the continuous segment. By obtaining this sequential information, the continuity relationship between the virtual address and the physical address can be understood, which is used to optimize the storage structure and query efficiency of the mapping table in the IOTLB. For example, by analyzing this sequential information, it can be found that some virtual address segments and physical address segments are continuous. In this way, more efficient storage and query methods can be adopted in the IOTLB to process these continuous address mapping relationships, thereby improving the address conversion efficiency of the entire system.

[0052] In one example, in the traditional scheme, the IOTLB caches all the corresponding relationships between IOVA and PA. For example, IOVA = 0x1000_0000 - 0x1000_0FFC (a total of 0x1000 addresses), and the corresponding PA is 0x1F00_2000 - 0x1F00_3FFC, 0x3E00_7000 - 0x3E00_74FC, 0x68A0_5000 - 0x68A0_52FC. In the Cache of the traditional IOTLB scheme, 0x2000 addresses need to be cached, but the caching efficiency is very low and the occupancy of the Cache is too large. In this embodiment, the sequentiality of IOVA and PA will be checked, that is, the lengths of IOVA and PA that are continuous respectively and their corresponding starting addresses will be checked and counted. For example, if IOVA = 0x1000_0000 - IOVA = 0x1000_01FC maps to PA0 = 0x1F00_2000 - 0x1F00_3FFC, then IOVA = 0x1000_0000, PA = 0x1F00_2000, LENGTH = 0x200 will be extracted; if IOVA = 0x1000_0200 - IOVA = 0x1000_06FC maps to PA = 0x3E00_7000 - 0x3E00_74FC, then IOVA = 0x1000_0200, PA = 0x3E00_7000, LENGTH = 0x500 will be extracted; if IOVA = 0x1000_0700 - IOVA = 0x1000_0FFC maps to PA = 0x68A0_5000 - 0x68A0_58FC, then IOVA = 0x1000_0700, PA = 0x68A0_5000, LENGTH = 0x900 will be extracted.

[0053] Generate a sequential mapping table based on the sequential information.

[0054] In this embodiment, after obtaining the sequential information of the virtual address and the physical address, the virtual address processing module will generate a sequential mapping table according to this information. The sequential mapping table can be stored in, for example, Figure 5In the virtual address processing module shown. This sequential mapping table is specifically used to store information about continuous segments of virtual addresses and physical addresses, including key information such as the starting address and length of each continuous segment. Through this sequential mapping table, the continuous address mapping relationship can be managed and queried more efficiently. For example, when it is necessary to query the physical address corresponding to a certain virtual address, the continuous segment where the virtual address is located can be quickly found in the sequential mapping table first, and then the specific physical address can be quickly determined according to the starting address and length information of the continuous segment, thus greatly improving the efficiency of address query. Especially when dealing with a large number of continuous address mapping relationships, the advantage of this sequential mapping table is more obvious, and it can significantly improve the performance of the system.

[0055] In one example, the sequential mapping table created based on the starting address and length LENGTH of the IOVA and PA continuous segments is shown in Table 1 below: Table 1 Sequential Mapping Table

[0056] Delete the mapping relationship that already exists in the sequential mapping table from the mapping table of the IOTLB.

[0057] In this embodiment, after generating the sequential mapping table, the virtual address processing module will optimize the mapping table of the IOTLB. Specifically, the mapping relationships that already exist in the sequential mapping table will be deleted from the mapping table of the IOTLB, that is, only the mapping relationships that are not in the sequential mapping table are cached in the mapping table of the IOTLB, because the sequential mapping table can already manage and query these continuous address mapping relationships efficiently, while the mapping table of the IOTLB can focus on storing those discontinuous and more complex address mapping relationships. In this way, the storage burden of the IOTLB mapping table and cache can be reduced, and its storage efficiency and query efficiency can be improved.

[0058] In another embodiment, after step S101 "receive the direct memory access DMA descriptor sent by the driver of the input / output IO device", the method further includes: Based on the DMA descriptor, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the sequential mapping table; In response to the non-existence of the target mapping relationship in the sequential mapping table, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the IOTLB.

[0059] In this embodiment, after receiving the DMA descriptor of the IO device, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation is first queried in the sequential mapping table. Since the sequential mapping table stores the continuous segment information of the virtual address and the physical address, this query method can quickly determine whether the virtual address belongs to a certain continuous segment and can quickly determine the corresponding physical address. This method greatly improves the query efficiency. Especially in the case of dealing with a large number of continuous address mapping relationships, it can significantly reduce the query time, speed up the execution speed of the DMA operation, and thus improve the performance of the entire system.

[0060] In this embodiment, if the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation is not found in the sequential mapping table, then the target mapping relationship is further queried in the mapping table of the IOTLB. The mapping table of the IOTLB stores those discontinuous and more complex address mapping relationships. By querying in the IOTLB mapping table, the address mapping relationships that do not belong to the continuous segment can be found. Thus, both the efficient management of the continuous address mapping relationship by the sequential mapping table and the storage and query capabilities of the IOTLB mapping table for complex address mapping relationships are utilized, so as to achieve the efficient query and management of all address mapping relationships, ensure that the DMA operation can quickly obtain the required address mapping information, and improve the overall performance of the system.

[0061] Figure 2 The flowchart of a direct memory access control method according to an embodiment of the present disclosure is shown Figure 2 , as Figure 2 shown, a direct memory access control method further includes: Step S201, obtaining the timestamp and length information of each DMA descriptor sent by the IO device.

[0062] In this embodiment, the system records the timestamp of each DMA descriptor sent by each IO device, as well as the corresponding length information. The timestamp is used to accurately record the specific moment when the DMA descriptor is sent, and the length information represents the size of the data volume involved in this DMA operation. By obtaining this information, it can provide basic data for the subsequent prediction and analysis of the DMA behavior of the IO device. For example, by analyzing the timestamps and length information of two adjacent DMA descriptor transmissions, the frequency and pattern of the IO device sending DMA operations can be understood, so as to provide a basis for predicting its subsequent DMA behavior, and further realize the optimization and update of the IOTLB mapping table, improving the performance and efficiency of the system.

[0063] Step S202: Based on the timestamps corresponding to two adjacent DMA descriptors and the length information of the previous DMA descriptor, determine the unit data transfer time of the statistical period corresponding to the two adjacent DMA descriptors, and determine the average value of all unit data transfer times.

[0064] In this embodiment, after obtaining the timestamp and length information of each DMA descriptor sent by the IO device, the unit data transfer time of the statistical period corresponding to two adjacent DMA descriptors will be calculated. The specific method is to use the timestamp difference between two adjacent DMA descriptors, combined with the length information of the previous DMA descriptor, to calculate the time required to transfer unit data within this statistical period. Then, calculate the average value of the unit data transfer times of all statistical periods. This average value can reflect the average rate and pattern of the IO device sending DMA operations within a certain time range. Through this average value, the time interval and data volume of the IO device sending the subsequent DMA descriptor can be predicted more accurately, providing a more reliable basis for the optimization and update of the IOTLB mapping table, thereby improving the prediction accuracy and performance optimization effect of the system.

[0065] In an example, assume that the timestamp of the first DMA descriptor initiated by the IO device is T0, the length of the DMA descriptor is DMA_LENGTH, and the timestamp of the second DMA descriptor initiated is T1. According to the formula T0 + DMA_LENGTH × PRED_PARAM_1 = T1, PRED_PARAM_1, that is, the unit data transfer time, can be obtained. Repeat the above steps to obtain PRED_PARAM_1... PRED_PARAM_N within all statistical periods, and calculate the average value PRED_PARAM_AVERAGE of PRED_PARAM_1... PRED_PARAM_N.

[0066] Step S203: Based on the average value, predict the target time for the IO device to send the next DMA descriptor.

[0067] Step S204: Update the mapping table of the IOTLB based on the target time.

[0068] In this embodiment, after determining the average value of the unit data transfer time for all statistical periods, the target time for the IO device to send the next DMA descriptor is predicted based on this average value. The specific prediction method is to use the known average unit data transfer time and combine the currently available information, such as the timestamp of the last sent DMA descriptor, to calculate the possible time point for sending the next DMA descriptor. This prediction process is based on the past behavior patterns of the IO device. In this way, the IOTLB mapping table can be updated and adjusted accordingly in advance, enabling the system to better prepare for the upcoming DMA operation, thereby improving the efficiency of the DMA operation and the overall performance of the system. In one example, the formula T_PRED = T_N+1 + PRED_PARAM_AVERAGE × (DMA_LENGTH_N) can be used to predict the start time of the (N+2)th DMA descriptor. If this start time is greater than a certain time threshold, it is determined that the IO device will not initiate a DMA operation within a certain period of time. At this time, the address mapping relationship corresponding to this IO device in the Cache should be cleared, and the saved Cache cache can be replaced with the mapping relationship between the IOVA and PA corresponding to other IO devices, thus realizing the timely replacement and update of the Cache inside the IOMMU. If the formula T_PRED = T_N+1 + PRED_PARAM_AVERAGE × (DMA_LENGTH_N) is used to predict the start time of the (N+2)th DMA, and if this time is not greater than a certain time threshold, it is predicted that the IO device will initiate a DMA operation again within the time threshold. Therefore, the mapping relationship between the IOVA and PA corresponding to the IO device in the Cache is not processed, and the next prediction continues. It should be noted that PRED_PARAM_AVERAGE should also be synchronized and updated at all times to further improve the accuracy of the prediction.

[0069] In another embodiment, step S203, "Based on the average value, predict the target time for the IO device to send the next DMA descriptor", includes: Determine the product of the average value and the length information; Determine the target time by summing the timestamp of the last sent DMA descriptor of the IO device and the product.

[0070] In this embodiment, in order to predict the target time for the IO device to send the next DMA descriptor, the product of the average value and the current DMA descriptor length information is first calculated, and then the timestamp of the DMA descriptor last sent by the IO device is added to this product. The result obtained is the predicted target time for the IO device to send the next DMA descriptor. In one example, the target time for the IO device to send the next DMA descriptor can be calculated based on the following formula: T_PRED=T_N+1 +PRED_PARAM_AVERAGE×(DMA_LENGTH_N), where T_N+1 is the timestamp of the DMA descriptor last sent by the IO device, PRED_PARAM_AVERAGE is the average value, DMA_LENGTH_N is the current DMA descriptor length information, and T_PRED is actually the possible sending time of the N+2th DMA descriptor.

[0071] In another embodiment, step S203, "Predict the target time for the IO device to send the next DMA descriptor based on the average value", includes: Determine the product of the average value and the length information; Determine the difference between the actual timestamp of the DMA descriptor last sent by the IO device and the target time; Determine the sum of the actual timestamp, the product, and the difference as the target time.

[0072] In this embodiment, in order to further improve the prediction accuracy, in addition to calculating the product of the average value and the current DMA descriptor length information, the difference between the actual timestamp of the DMA descriptor last sent by the IO device and the previously predicted target time is also calculated. This difference reflects the deviation degree between the actual occurrence time and the predicted time of the DMA descriptor last sent by the IO device. Then, the sum of this actual timestamp, the previously calculated product of the average value and the length information, and the difference is calculated to obtain a new target time. In one example, the target time T_PRED_OPT for the IO device to send the next DMA descriptor can be calculated by the following formula: T_PRED_OPT=T_N+1 + PRED_PARAM_AVERAGE×(DMA_LENGTH_N)+(T_REAL-T_PRED), where T_N+1 is the timestamp of the DMA descriptor last (i.e., the N+1th) sent by the IO device, PRED_PARAM_AVERAGE is the average value, DMA_LENGTH_N is the current DMA descriptor length information, T_REAL is the real timestamp of the N+1th sent DMA descriptor, T_PRED is the target time of the N+1th sent DMA descriptor, and T_PRED is actually the possible sending time of the N+2th DMA descriptor. Thus, a more accurate target time can be obtained.

[0073] In another embodiment, step S204, "updating the mapping table of the IOTLB based on the target time", includes: In response to the target time being greater than the first threshold, delete the mapping relationship between the virtual address and the physical address corresponding to the IO device in the mapping table of the IOTLB.

[0074] In this embodiment, when the predicted target time for the IO device to send the next DMA descriptor is greater than the set first threshold, corresponding measures will be taken. The first threshold is a time threshold preset according to the performance requirements and actual operating conditions of the system, and is used to determine whether the IO device will initiate a DMA operation within a certain period of time. If the target time is greater than the first threshold, it means that the IO device may not initiate a DMA operation again within a relatively long period of time. At this time, in order to improve the storage efficiency and utilization rate of the IOTLB mapping table, the mapping relationship between the virtual address and the physical address corresponding to the IO device will be deleted from the mapping table of the IOTLB, thereby releasing the storage space occupied in the IOTLB mapping table, so that this space can be used by other more needed IO devices, thereby improving the resource utilization efficiency and performance of the entire system.

[0075] In another embodiment, a direct memory access control method further includes: In response to the priority of the IO device being greater than the second threshold, retain the mapping relationship between the virtual address and the physical address corresponding to the IO device in the mapping table of the IOTLB.

[0076] In this embodiment, in addition to considering the target time for the IO device to send the next DMA descriptor, the priority of the IO device will also be comprehensively considered. If the priority of the IO device is greater than the set second threshold, even if the predicted target time of the IO device is greater than the first threshold, the mapping relationship between the virtual address and the physical address corresponding to the IO device will be retained in the mapping table of the IOTLB, thereby ensuring the priority processing of important processes and the reliability of the system.

[0077] In another embodiment, a direct memory access control method further includes: Determine an IO device with a frequency of sending DMA descriptors greater than a third threshold as a first target IO device; Determine an IO device that stores the mapping relationship between the corresponding virtual address and physical address only in memory as a second target IO device; Update the mapping relationship between the virtual address and the physical address corresponding to the first target IO device and / or the second target IO device to the mapping table of the IOTLB.

[0078] In this embodiment, the first target I / O device is determined according to the frequency at which the I / O device sends DMA descriptors. If the frequency at which an I / O device sends DMA descriptors is greater than a set third threshold, then this I / O device is determined as the first target I / O device. At the same time, those I / O devices whose mapping relationships between the corresponding virtual addresses and physical addresses are only stored in the memory are also determined as the second target I / O devices, that is, low-hit devices. For these two types of target I / O devices, the mapping relationships between their corresponding virtual addresses and physical addresses are updated to the mapping table of the IOTLB, so as to improve the DMA operation efficiency of these I / O devices that frequently send DMA descriptors or need to find the mapping relationships between the corresponding virtual addresses and physical addresses in the memory. In an example, if the mapping relationships between the virtual addresses and physical addresses corresponding to I / O device 0 and I / O device 5 are deleted from the mapping table of the IOTLB, the mapping relationships between the IOVA and PA corresponding to the high-frequency access I / O device 2 and the low-hit I / O device 7 can be updated to the Cache space corresponding to the original I / O device 0 and I / O device 5.

[0079] Figure 5 FIG. shows a schematic structural diagram of a direct memory access control system according to an embodiment of the present disclosure; Figure 6 FIG. shows a schematic structural diagram of a mapping table update module according to an embodiment of the present disclosure, as Figure 5 and Figure 6 shown, a direct memory access control system includes: A mapping table update module, which includes a register configuration sub-module, a query sub-module, and an update sub-module; The register configuration sub-module is used to receive the direct memory access (DMA) descriptor sent by the driver of the input / output (I / O) device; the DMA descriptor includes the starting address of the virtual address corresponding to the DMA operation, the length information, and the identifier of the I / O device; The query sub-module is used to query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the input / output translation lookaside buffer (IOTLB) based on the DMA descriptor; the mapping table is stored in the cache; The update sub-module is used to, in response to the non-existence of the target mapping relationship in the mapping table of the IOTLB, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor, and update the target mapping relationship to the mapping table of the IOTLB.

[0080] In an implementable embodiment, the mapping table update module further includes a monitoring sub-module; the monitoring sub-module is configured to monitor the sending order of the DMA descriptors of each IO device and send the sending order to the update sub-module; the update sub-module is further configured to query, based on each DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order, and update the target mapping relationship to the mapping table of the IOTLB.

[0081] In an implementable embodiment, the query sub-module is further configured to: in response to the existence of a target mapping relationship in the mapping table of the IOTLB, query, based on the received next DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor in the mapping table of the IOTLB.

[0082] Figure 7 The structural schematic diagram of the virtual address processing module according to an embodiment of the present disclosure is shown, as Figure 5 and as Figure 7 shown, a direct memory access control system further includes a virtual address processing module, and the virtual address processing module includes: a sequence check sub-module, a generation sub-module, and a deletion sub-module; the sequence check sub-module is further configured to obtain the sequentiality information of all virtual addresses and the corresponding physical addresses; the sequentiality information includes the start address and the length information; the generation sub-module is further configured to generate a sequential mapping table based on the sequentiality information; the deletion sub-module is further configured to delete the mapping relationships that already exist in the sequential mapping table from the mapping table of the IOTLB.

[0083] In an implementable embodiment, the virtual address processing module further includes: a table lookup enable module, and the table lookup enable module is configured to: query, based on the DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the sequential mapping table; in response to the non-existence of the target mapping relationship in the sequential mapping table, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the IOTLB.

[0084] In an implementable embodiment, a direct memory access control system further includes: a resource release module, configured to: obtain the timestamp and length information of each DMA descriptor sent by the IO device; determine the unit data transfer time of the statistical period corresponding to two adjacent DMA descriptors based on the timestamps corresponding to the two adjacent DMA descriptors and the length information of the previous DMA descriptor, and determine the average value of all unit data transfer times; predict the target time for the IO device to send the next DMA descriptor based on the average value; update the mapping table of the IOTLB based on the target time.

[0085] In one implementable manner, the resource release module is further configured to: determine the product of the average value and the length information; determine the sum of the timestamp of the DMA descriptor last sent by the IO device and the product as the target time.

[0086] In one implementable manner, the resource release module is further configured to: determine the product of the average value and the length information; determine the difference between the actual timestamp of the DMA descriptor last sent by the IO device and the target time; determine the sum of the actual timestamp, the product, and the difference as the target time.

[0087] In one implementable manner, the resource release module is further configured to: in response to the target time being greater than the first threshold, delete the mapping relationship between the virtual address and the physical address corresponding to the IO device in the mapping table of the IOTLB.

[0088] In one implementable manner, a direct memory access control system further includes: an important IO processing module, configured to: in response to the priority of the IO device being greater than the second threshold, retain the mapping relationship between the virtual address and the physical address corresponding to the IO device in the mapping table of the IOTLB.

[0089] In one implementable manner, a direct memory access control system further includes: a DMA status detection module, configured to: determine an IO device with a frequency of sending DMA descriptors greater than a third threshold as a first target IO device; determine an IO device whose mapping relationship between the corresponding virtual address and physical address is stored only in the memory as a second target IO device; update the mapping relationship between the virtual address and the physical address corresponding to the first target IO device and / or the second target IO device to the mapping table of the IOTLB.

[0090] According to an embodiment of the present disclosure, the present disclosure further provides an electronic device and a readable storage medium.

[0091] Figure 8 FIG. shows a schematic block diagram of an exemplary electronic device 800 that can be used to implement the embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processing, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0092] As Figure 8As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to computer programs stored in a read-only memory (ROM) 802 or computer programs loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0093] Multiple components in device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disc, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0094] The computing unit 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 801 executes the various methods and processes described above, such as a direct memory access control method. For example, in some embodiments, a direct memory access control method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the direct memory access control method described above can be executed. Alternatively, in other embodiments, the computing unit 801 can be configured to execute a direct memory access control method in any other appropriate manner (e.g., by means of firmware).

[0095] The various embodiments of the systems and techniques described above in this specification can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from, and transmits data and instructions to, a storage system, at least one input device, and at least one output device.

[0096] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0097] In the context of the present disclosure, a machine-readable medium may be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0098] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0099] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0100] A computer system can include a client and a server. The client and the server are generally far from each other and typically interact through a communication network. The client - server relationship is created by computer programs running on the respective computers and having a client - server relationship with each other. The server can be a cloud server, or a server of a distributed system, or a server incorporating a blockchain.

[0101] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. No limitation is imposed herein.

[0102] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of this disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0103] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims described above.

Claims

1. A direct memory access control method, characterized in that, The method includes: Receiving a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device; the DMA descriptor includes a starting address of a virtual address corresponding to a DMA operation, length information, and an identifier of the IO device; Based on the DMA descriptor, querying a target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in a mapping table of an input / output translation lookaside buffer (IOTLB); the mapping table is stored in a cache; In response to the non-existence of the target mapping relationship in the mapping table of the IOTLB, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in a page table of a memory based on the DMA descriptor, and updating the target mapping relationship to the mapping table of the IOTLB.

2. The method according to claim 1, characterized in that, The querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor, and updating the target mapping relationship to the mapping table of the IOTLB includes: Obtaining the sending order of the DMA descriptors of the respective IO devices; Based on the respective DMA descriptors, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order, and updating the target mapping relationship to the mapping table of the IOTLB.

3. The method according to claim 1, characterized in that, The method further includes: In response to the existence of the target mapping relationship in the mapping table of the IOTLB, querying the target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor in the mapping table of the IOTLB based on the received next DMA descriptor.

4. The method according to claim 1, characterized in that, Before the querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the input / output translation lookaside buffer (IOTLB) based on the DMA descriptor, the method further includes: Obtaining sequentiality information of all virtual addresses and corresponding physical addresses; the sequentiality information includes a starting address and length information; Generating a sequential mapping table based on the sequentiality information; Deleting mapping relationships that already exist in the sequential mapping table from the mapping table of the IOTLB.

5. The method according to claim 4, characterized in that, After receiving the direct memory access (DMA) descriptor sent by the driver of the input / output (IO) device, the method further includes: Querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the sequential mapping table based on the DMA descriptor; In response to the non-existence of the target mapping relationship in the sequential mapping table, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the IOTLB.

6. The method according to claim 1, characterized in that, The method further includes: Obtaining a timestamp of each sending of the DMA descriptor by the IO device and the length information; Based on the timestamps corresponding to two adjacent DMA descriptors and the length information of the previous DMA descriptor, determine the unit data transfer time of the statistical period corresponding to the two adjacent DMA descriptors, and determine the average value of all the unit data transfer times; Based on the average value, predict the target time for the IO device to send the next DMA descriptor; Based on the target time, update the mapping table of the IOTLB.

7. The method according to claim 6, characterized in that, The predicting the target time for the IO device to send the next DMA descriptor based on the average value includes: Determine the product of the average value and the length information; Determine the sum of the timestamp of the DMA descriptor last sent by the IO device and the product as the target time.

8. The method according to claim 6, characterized in that, The predicting the target time for the IO device to send the next DMA descriptor based on the average value includes: Determine the product of the average value and the length information; Determine the difference between the actual timestamp of the DMA descriptor last sent by the IO device and the target time; Determine the sum of the actual timestamp, the product, and the difference as the target time.

9. The method according to claim 6, characterized in that, The updating the mapping table of the IOTLB based on the target time includes: In response to the target time being greater than the first threshold, delete the mapping relationship between the virtual address and the physical address corresponding to the IO device in the mapping table of the IOTLB.

10. The method according to claim 9, characterized in that,The method further includes: In response to the priority of the IO device being greater than the second threshold, retain the mapping relationship between the virtual address and the physical address corresponding to the IO device in the mapping table of the IOTLB.

11. The method according to claim 9, wherein, The method further includes: Determine the IO devices with the frequency of sending the DMA descriptor greater than the third threshold as the first target IO devices; Determine the IO devices with the mapping relationship between the corresponding virtual address and physical address stored only in the memory as the second target IO devices; Update the mapping relationship between the virtual address and the physical address corresponding to the first target IO device and / or the second target IO device to the mapping table of the IOTLB.

12. A direct memory access control system, wherein, The system includes: A mapping table update module, which includes a register configuration sub-module, a query sub-module, and an update sub-module; The register configuration sub-module is configured to receive a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device; the DMA descriptor includes the starting address of the virtual address corresponding to the DMA operation, the length information, and the identifier of the IO device; The query sub-module is configured to query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of an input / output translation lookaside buffer (IOTLB) based on the DMA descriptor; the mapping table is stored in the cache; The update sub-module is configured to, in response to the non-existence of the target mapping relationship in the mapping table of the IOTLB, query, based on the DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory, and update the target mapping relationship to the mapping table of the IOTLB.

13. The system according to claim 12, wherein, The mapping table update module further includes a monitoring sub-module; The monitoring sub-module is configured to monitor the sending order of the DMA descriptors of each of the IO devices, and send the sending order to the update sub-module; The update sub-module is further configured to, based on each of the DMA descriptors, query, in the page table of the memory in the sending order, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation, and update the target mapping relationship to the mapping table of the IOTLB.

14. The system according to claim 12, wherein, The query sub-module is further configured to: In response to the existence of the target mapping relationship in the mapping table of the IOTLB, query, based on the received next DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor in the mapping table of the IOTLB.

15. The system according to claim 12, wherein, The system further includes: a virtual address processing module; the virtual address processing module includes: a sequence check sub-module, a generation sub-module, and a deletion sub-module; The sequence check sub-module is further configured to obtain the sequential information of all virtual addresses and the corresponding physical addresses; the sequential information includes the start address and the length information; The generation sub-module is further configured to generate a sequential mapping table based on the sequential information; The deletion sub-module is further configured to delete, in the mapping table of the IOTLB, the mapping relationships that already exist in the sequential mapping table.

16. The system according to claim 15, wherein, The virtual address processing module further includes: a table lookup enable module, and the table lookup enable module is configured to: Based on the DMA descriptor, query, in the sequential mapping table, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation; In response to the non-existence of the target mapping relationship in the sequential mapping table, query, in the mapping table of the IOTLB, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation.

17. The system according to claim 12, wherein, The system further includes: a resource release module, which is configured to: Obtain the timestamp of each time the IO device sends the DMA descriptor and the length information; Based on the timestamps corresponding to two adjacent DMA descriptors and the length information of the previous DMA descriptor, determine the unit data transfer time of the statistical period corresponding to the two adjacent DMA descriptors, and determine the average value of all the unit data transfer times; Based on the average value, predict the target time for the IO device to send the next DMA descriptor; Based on the target time, update the mapping table of the IOTLB.

18. The system according to claim 17, wherein, The resource release module is further configured to: Determine the product of the average value and the length information; Determine the sum of the timestamp of the DMA descriptor last sent by the IO device and the product as the target time.

19. An electronic device, characterized in that, Including: A direct memory access control system according to any one of claims 12-18.

20. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are for causing the computer to execute the method according to any one of claims 1-11.

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