Chip test mode design method for sub-modules
By splitting the chip into multiple submodules and adopting a submodule test mode, the design and testing difficulty problems caused by the large chip scale are solved, and efficient test coverage and low-cost packaging are achieved.
Patent Information
- Application Number
- CN202311762211.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
AI Technical Summary
In the prior art, the chip scale and many functions are large, which makes it difficult to design the full-chip measurability, difficult to position the modular positioning during the test, slow iteration speed, and more packaging pins are required, which increases cost and complexity.
Split the chip into multiple submodules, each submodule is designed and tested independently, adopting a submodule test mode, including intest and extest test modes, by modifying the stil file to multiplex chip pins, reducing the number of packaged pins.
It reduces design difficulty and debugging difficulty, improves iteration speed and test coverage, reduces the number of package pins, and reduces the packaging cost.
Smart Images
Figure CN120181003A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip circuit testability design, and particularly relates to a design method for chip test modes with sub-modules. Background Art
[0002] In the prior art, as the functions of chips become more and more, and the scale of chips becomes larger and larger, it becomes more difficult to conduct a testability design for the entire chip at one time. Once an error occurs during the test process, it is also very difficult to debug and locate the failed area. The software runs a process that takes dozens of hours, and the iteration speed is getting slower and slower. Due to the intensification of market competition, testing will have an increasingly greater impact on the product's time to market and development cycle. In addition, chip suppliers all hope to pick out defective chips as early as possible at the wafer stage, saving the cost of subsequent packaging and also preventing defective chips from flowing into the market and causing losses to customers. Therefore, this requires the chip test coverage rate to be as high as possible. Finally, limited by the packaging form and packaging cost, the fewer the packaging pins of the chip, the better, which is also something that must be considered in advance during the design stage of this field.
[0003] There are the following two methods for implementing the existing testability design:
[0004] (1) Conduct a testability design process for the entire chip at one time;
[0005] (2) Split the entire chip into multiple sub-modules, and conduct testability design for each sub-module separately.
[0006] However, the problems existing in the prior art are as follows:
[0007] Regarding (1) Conduct a testability design process for the entire chip at one time:
[0008] 1. Advantage: It can achieve a relatively high test coverage rate;
[0009] 2. Disadvantages: The design difficulty becomes larger. Once an error occurs during the test process, it is very difficult to debug and locate the failed area; the process of inserting test logic in a large-scale chip takes dozens of hours, and the iteration speed is very slow; in the case where the number of scan chains and the length of the scan chains are the same, the block part requires M pins, and the top part requires M pins, then the entire chip requires at least 2M pins, so more packaging pins are needed.
[0010] Regarding (2) Split the entire chip into multiple sub-modules, and conduct testability design for each sub-module separately: 1. Advantage: The design difficulty is reduced. Once an error occurs during the test process, the failed area can be debugged and located relatively quickly. The process of inserting test logic in each sub-module of the chip can be parallel, and the iteration speed is fast.
[0011] 2. The disadvantages are as follows: in the case where the number of scan chains and the length of the scan chains are the same, the test mode of the block requires M pins, and the test mode of the top requires M pins. Then, the entire chip requires at least 2M pins, so more package pins are needed.
[0012] In addition, common technical terms include:
[0013] 1. stil: (standard test interface language) Standard Test Interface Language, which describes the test-related logic inserted in the chip in the file.
[0014] 2. Design for testability: The test problem should be considered at the beginning of chip design. By adding some circuits dedicated to testing, the test difficulty of the circuit is reduced, the test efficiency of the circuit is improved, the test cost is reduced, and the correctness of complex integrated circuits in the manufacturing process is comprehensively and effectively verified.
[0015] 3. extest test mode: Test the outside of the module. The boundary values of the module are all controllable.
[0016] 4. intest test mode: Test the inside of the module. Summary of the Invention
[0017] To solve the above problems, the purpose of this application is:
[0018] 1. In the design stage, the chip is split into different sub-modules, and each sub-module is designed separately, which improves the parallelism and design efficiency;
[0019] 2. The chip is split into several sub-modules, and each sub-module is tested independently. If there is an error, the error must exist within the sub-module, and the location of the failure can be quickly located, reducing the debugging difficulty; 3. If a certain sub-module fails and other modules are normal, they can be packaged separately and sold to customers who do not need to use this sub-module, reducing costs;
[0020] 4. When the top module enters the intest mode and the sub-modules enter the extest test mode, the coverage rate of the top module can be greatly improved, avoiding defective chips from flowing out;
[0021] 5. The chip pins used for testing each sub-module can be reused, reducing the number of package pins and the packaging cost.
[0022] Specifically, the present invention provides a design method for a module-based chip test mode, and the method includes the following steps:
[0023] S1, define the reuse relationship of chip pins;
[0024] S2, divide the chip into different sub - modules:
[0025] According to the functions of the chip, split the chip into multiple sub - modules. The sub - module is denoted as block_A, and the remaining logic is called the top module;
[0026] S3, define different test modes for each module:
[0027] The test modes defined for the sub - module block_A are the extest test mode and the intest test mode; the test mode defined for the remaining top module is the intest test mode;
[0028] S4, perform tests according to the test modes of the divided modules;
[0029] S5, modify the stil file of each module:
[0030] The pins described in the block.stil file of the block module automatically generated by the design compiler software tool are the internal block pins of the chip:
[0031] block_scan_input1, block_scan_input2, block_scan_input3, block_scan_output1, block_scan_output2, block_scan_output3. Change the pins of the block described in the block.stil file to the corresponding chip pin names according to the corresponding relationship designed by the chip designer in the chip, that is, according to Table 1:
[0032] Table 1
[0033]
[0034] Change to the corresponding chip pin names:
[0035] chip_pin_1, chip_pin_2, chip_pin_3, chip_pin_4, chip_pin_5, chip_pin_6;
[0036] In the top.stil file of the top module automatically generated by the design compiler software tool, add the description of the extest test mode of the sub - module.
[0037] In step S1, the chip pins used for testing each sub-module are reusable. There are a total of M pins on the chip. When testing sub-module block_A, these M pins can be used; when testing the top module, these M pins can also be used. With the same number of scan chains and scan chain lengths, the number of pins is reduced.
[0038] In step S4, when testing a sub-module, the sub-module is in the intest test mode and other modules are in the functional mode; when testing the top-level top module, by modifying the stil file, the top module is set to the intest test mode and the sub-module is in the extest mode.
[0039] In step S5, according to the corresponding relationship, that is, according to Table 1, when the chip is in the block test mode, i.e., block_test_mode = 1, top_test_mode = 0, chip_pin represents the name of the package pin of the chip, and block_* represents the input and output pins of the sub-module; the corresponding relationship between the package pins of the chip and the input and output pins of the sub-module is shown in Table 1 below.
[0040] In step S5, the description of adding the extest test mode of the sub-module further includes:
[0041] Adding a description of the extest scan chain of sub-module block_A to the stil file of the top module. The added content includes:
[0042] The name of the scan chain can be expressed as: ScanChain “blockExtestWrapper_1”
[0043] The length of the scan chain can be expressed as: ScanLength 360;
[0044] The name of the input pin of the scan chain can be expressed as: scan_input “chip_pin_1”;
[0045] The name of the output pin of the scan chain can be expressed as: ScanOut “chip_pin_4”;
[0046] The name of the enable pin of the scan chain can be expressed as: ScanEnable”chip_pin_7”.
[0047] Furthermore, the specific process steps of the method further include:
[0048] S0, Start
[0049] S1, The chip designer defines the pin multiplexing relationship, as shown in Table 1;
[0050] S2, split the chip into multiple sub - modules;
[0051] S3, define a test mode for each module, and use the dft compiler software tool to generate the defined test mode in the chip. Among them,
[0052] sub - module block_A includes the intest test mode and the extest test mode; execute step S4.1; the Top module includes the intest test mode; execute step S4.2;
[0053] S4.1, when testing the sub - module block_A, block_A is in the intest test mode, and other modes are in the functional test mode; execute step S5.1;
[0054] S4.2, when testing the top module, block_A is in the extest test mode, and top is in the intest test mode; execute step S5.2;
[0055] S5.1, according to the pin correspondence, change the pins of the block in the stil file to the corresponding chip - level pins; execute step S6;
[0056] S5.2, in the stil file of top, add the description of the extest mode of the block module; execute step S6;
[0057] S6, according to the results of steps S5.1 and S5.2, read the netlist and the modified stil file in the tetramax software tool to generate a high - coverage pattern; the netlist is the designed chip, not only including Table 1; the pattern is the file generated by the tetramax software, and this file describes the input data and the expected output data of the chip;
[0058] S7, end.
[0059] The method is applicable to splitting a large - scale soc chip into several small sub - modules for independent testing. If there is an error, the error must exist within the sub - module, and the location of the failure can be quickly located.
[0060] Therefore, the advantage of this application is the testability design method proposed in this application:
[0061] 1. It can achieve a relatively high test coverage;
[0062] 2. The design difficulty is reduced. Once an error occurs during the test, the failure area can be debugged and located relatively quickly;
[0063] 3. The process of inserting test logic into each sub-module of the chip can be parallel, with a fast iteration speed;
[0064] 4. With the same number of scan chains and the same scan chain length, fewer package pins are required. Brief Description of the Drawings
[0065] The drawings described herein are used to provide a further understanding of the present invention, form a part of this application, and do not limit the present invention.
[0066] Figure 1 It is a schematic diagram of splitting the chip into two modules.
[0067] Figure 2 It is a schematic diagram of sub-module block_A in the intest test mode.
[0068] Figure 3 It is a schematic diagram of sub-module block_A in the extest test mode.
[0069] Figure 4 It is a schematic diagram of the top module in the intest test mode, sub-module block_A in the extest test mode, and the test area is the outer gray area.
[0070] Figure 5(1)-Figure 5(3) It is a schematic diagram of the chip pin multiplexing relationship, where
[0071] Figure 5(1) represents the schematic diagram of output pin allocation;
[0072] Figure 5(2) represents the schematic diagram of input pin allocation when testing the top module;
[0073] Figure 5(3) represents the schematic diagram of input pin allocation when testing the block module.
[0074] Figure 6 It is the flowchart of the test mode for each module in the embodiment of this application. Detailed Embodiments
[0075] In order to more clearly understand the technical content and advantages of the present invention, the present invention will be further described in detail below with reference to the drawings.
[0076] This application relates to testability design technology, and is particularly applicable to the situation of large circuit scale, few chip pins, and high coverage requirements.
[0077] The present invention provides a method for designing a test mode for each module. The method divides the chip into multiple sub-modules, defines different test modes for each module respectively, modifies the stil file of each module, and the chip pins of each module can be multiplexed. As Figure 6As shown in the figure, the specific implementation process of this method further includes:
[0078] S0. Start;
[0079] S1. The chip designer defines the multiplexing relationship of the chip pins, as shown in Table 1; the chip pins of each module can be multiplexed. There are a total of M pins on the chip. When testing the sub-module block_A, these M pins can be used; when testing the top module, these M pins can also be used; in the case of the same number of scan chains and scan chain lengths, the number of pins is reduced; as Figure 5(1)-Figure 5(3) shown, among which, Figure 5(1) shows the multiplexing of output pins; Figure 5(2) shows the multiplexing of input pins of the top module; Figure 5(3) shows the multiplexing of input pins of the block sub-module. Further:
[0080] Figure 5(1) represents the schematic diagram of output pin allocation: when top_test_mode = 1 and block_test_mode = 0, chip_pin = top_scan_output; when top_test_mode = 0 and block_test_mode = 1, chip_pin = block_scan_output;
[0081] Figure 5(2) represents the schematic diagram of input pin allocation when testing the top module: when top_test_mode = 1 and block_test_mode = 0, top_scan_input = chip_pin; when top_test_mode = 0 and block_test_mode = 1, top_scan_input = 0;
[0082] Figure 5(3) represents the schematic diagram of input pin allocation when testing the block module: when top_test_mode = 1 and block_test_mode = 0, top_scan_input = 0; when top_test_mode = 0 and block_test_mode = 1, top_scan_input = chip_in.
[0083] S2. The chip is split into multiple sub-modules. Splitting the chip into different sub-modules means splitting the chip into multiple sub-modules according to the functions of the chip. For example, block_A, and the remaining logic is called the top module; as Figure 1 shown, among which, there is a large outer top module and a small inner sub-module block_A module.
[0084] S3. Each module defines different test patterns respectively; each module defines a test module for synthesis, and uses the dft compiler software tool of Synopsys to generate the defined test patterns in the chip. Among them, the test patterns defined by the sub-module block_A include the extest test pattern (as shown in Figure 3 ), the test area is the middle strip-shaped shaded area, and the values in this shaded area are all controllable), and the intest test pattern (as shown in Figure 2 ), the test area is the middle gray shaded area); the test pattern defined by the remaining top module is the intest test pattern.
[0085] S4. Test according to the test patterns of each module:
[0086] S4.1. When testing the sub-module block_A, the sub-module is in the intest test mode, and other modules are in the functional mode. As shown in Figure 2 , execute step S5.1;
[0087] S4.2. When testing the top-level top module, by modifying the stil file, make the top module in the intest test mode and the sub-module in the extest mode. As shown in Figure 4 , because the values in the middle strip-shaped shaded area are controllable, the data in the outer gray area in contact with this strip-shaped shaded area is controllable, improving the coverage rate of the outer gray top area; execute step S5.2;
[0088] S5. Modify the stil file of each module:
[0089] The pins described in the block.stil file of the block module automatically generated by using the design compiler software tool of Synopsys are the internal block pins of the chip:
[0090] block_scan_input1, block_scan_input2, block_scan_input3, block_scan_output1, block_scan_output2, block_scan_output3. Change the pins of block described in the block.stil file to the names of the corresponding chip pins according to the corresponding relationship in the chip designed by the chip designer, that is, according to Table 1:
[0091] chip_pin_1, chip_pin_2, chip_pin_3, chip_pin_4, chip_pin_5, chip_pin_6;
[0092] In the top.stil file of the top module automatically generated by the design compiler software tool of Synopsys, add the description of the extest test mode of the sub-module; as shown in Figure 5, among which, in Figure 5(1), the output pins are multiplexed; in Figure 5(2), the input pins of the top module are multiplexed; in Figure 5(3), the input pins of the block sub-module are multiplexed.
[0093] Further include:
[0094] S5.1, According to the pin correspondence, change the pins of the block in the stil file to the corresponding chip-level pins; execute step S6;
[0095] S5.2, In the stil file of the top, add the description of the extest mode of the block module; execute step S6;
[0096] S6, According to the results of steps S5.1 and S5.2, read the netlist and the modified stil file in the tetramax software tool of Synopsys to generate a high-coverage pattern; the netlist is the designed chip, not only including Table 1; the pattern is the file generated by the tetramax software, and this file describes the input data and the expected output data of the chip.
[0097] The function of the tetramax software tool is: to test whether the chip is a good chip or not, it is necessary to input data to the chip and also know the correct output data of a normal chip. The function of the tetramax software is to generate a file, and this file describes the input data and the expected output data of the chip;
[0098] The high coverage rate is that using the method of the present invention, in the ideal state (and when other aspects are also well designed), it can even reach more than 99%; if this method is not used, it is very difficult to reach 99%, and it depends on how much the block module affects the top module (data interaction);
[0099] S7, End.
[0100] In step S5, the so-called according to the correspondence relationship, that is, according to Table 1, when the chip is in the block test mode, that is, block_test_mode = 1, top_test_mode = 0, chip_pin represents the name of the package pin of the chip, and block_* represents the input and output pins of the sub-module; the correspondence relationship between the package pins of the chip and the input and output pins of the sub-module is as follows in Table 1:
[0101] Table 1
[0102]
[0103] In the top.stil file of the top module automatically generated by the design compiler software of Synopsys, Inc., it is necessary to add the description of the extest test mode of the sub-module.
[0104] Add the description of the extest scan chain of sub-module block_A in the top stil. The added content is as follows:
[0105] ScanChain “blockExtestWrapper_1” {
[0106] ScanLength 360;
[0107] ScanIn “chip_pin_1”;
[0108] ScanOut “chip_pin_4”;
[0109] ScanEnable ”chip_pin_7”
[0110] }。
[0111] In summary, through the test mode design method of sub-modules, this application achieves:
[0112] 1. High coverage rate: When testing the top-level top module, by modifying the stil file to make the top module in the intest test mode and the sub-module in the extest mode, a very high test coverage rate of the top module can be achieved.
[0113] 2. Reduced design difficulty: Split the large-scale soc chip into several small sub-modules, and each sub-module is tested independently. If there is an error, the error must exist within the sub-module, which can quickly locate the failure position and reduce the debugging difficulty;
[0114] 3. High efficiency: Split the chip into different sub-modules, and each sub-module is designed separately, which improves the parallelism, design efficiency, and iteration speed;
[0115] 4. Fewer package pins: There are a total of M pins on the entire chip. When testing sub-module block_A, these M pins can be used; when testing the top module, these M pins can also be used. With the same number of scan chains and scan chain lengths, the number of pins is greatly reduced.
[0116] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A method for designing a chip test mode with modules, characterized in that, The method includes the following steps: S1. Define the multiplexing relationship of the chip pins; S2. Divide the chip into different sub-modules: According to the functions of the chip, split the chip into multiple sub-modules, denoted as block_A, and the remaining logic is called the top module; S3. Define different test modes for each module respectively: The test modes defined for the sub-module block_A are the extest test mode and the intest test mode; the test mode defined for the remaining top module is the intest test mode; S4. Perform tests according to the test modes of the divided modules; S5. Modify the stil file of each module: The pins described in the block.stil file of the block module automatically generated by the design compiler software tool are the internal block pins of the chip: block_scan_input1, block_scan_input2, block_scan_input3, block_scan_output1, block_scan_output2, block_scan_output3. Change the pins of the block described in the block.stil file to the names of the corresponding chip pins according to the corresponding relationship designed by the chip designer in the chip, that is, according to Table 1, Table 1 to the corresponding chip pin names: chip_pin_1, chip_pin_2, chip_pin_3, chip_pin_4, chip_pin_5, chip_pin_6; In the top.stil file of the top module automatically generated by the design compiler software tool, add the description of the extest test mode of the sub-module.
2. The method for designing a chip test mode with modules according to claim 1, characterized in that, In step S1, the chip pins used when testing each sub-module are reusable. The chip has a total of M pins. When testing the sub-module block_A, these M pins can be used; when testing the top module, these M pins can also be used; when the number of scan chains and the length of the scan chains are the same, the number of pins is reduced.
3. The method for designing a chip test mode with modules according to claim 1, characterized in that, In step S4, when testing the sub-module, the sub-module is in the intest test mode, and other modules are in the functional mode; When testing the top-level top module, by modifying the stil file, make the top module in the intest test mode and the sub-module in the extest mode.
4. The method for designing a chip test mode with modules according to claim 3, characterized in that, In step S5, according to the corresponding relationship, that is, according to Table 1, when the chip is in the block test mode, that is, block_test_mode = 1, top_test_mode = 0, chip_pin represents the name of the chip package pin, and block_* represents the input and output pins of the sub-module; the corresponding relationship between the chip package pins and the input and output pins of the sub-module is shown in Table 1.
5. The method for designing a chip test mode with modules according to claim 4, characterized in that, In step S5, the adding the description of the extest test mode of the sub-module further includes: Add the description of the extest scan chain of sub-module block_A in the stil file of the top module. The added content includes: The name of the scan chain, which can be expressed as: ScanChain "blockExtestWrapper_1" The length of the scan chain, which can be expressed as: ScanLength 360; The name of the input pin of the scan chain, which can be expressed as: scan_input "chip_pin_1"; The name of the output pin of the scan chain, which can be expressed as: ScanOut "chip_pin_4"; The name of the enable pin of the scan chain, which can be expressed as: ScanEnable "chip_pin_7".
6. The method for designing a chip test mode with modules according to claim 3, characterized in that, The specific process steps of the method further include: S0, Start S1, The chip designer defines the pin multiplexing relationship, as shown in Table 1; S2, The chip is split into multiple sub-modules; S3, Each module defines a test mode, and the defined test mode is generated in the chip using the dft compiler software tool. Among them, Sub-module block_A includes the intest test mode and the extest test mode; Step S4.1 is executed; The Top module includes the intest test mode; Step S4.2 is executed; S4.1, When testing sub-module block_A, block_A is in the intest test mode, and other modules are in the functional test mode; Step S5.1 is executed; S4.2, When testing the top module, block_A is in the extest test mode, and the top is in the intest test mode; Step S5.2 is executed; S5.1, According to the pin correspondence, change the pins of the block in the stil file to the corresponding chip-level pins; Step S6 is executed; S5.2, In the stil file of the top, add the description of the extest mode of the block module; Step S6 is executed; S6, According to the results of Steps S5.1 and S5.2, read the netlist and the modified stil file in the tetramax software tool to generate a high-coverage pattern; The netlist is the designed chip, which not only includes Table 1; The pattern is the file generated by the tetramax software, and this file describes the input data and the expected output data of the chip; S7, End 7. A method for designing a chip test mode with sub - modules, characterized in that, The method is applicable to splitting a large-scale soc chip into several small sub-modules for independent testing. If there is an error, the error must exist within the sub-module, and the location of the failure can be quickly located.