Scan chain reordering method, computer equipment and storage medium

Abstract

The invention provides a scan chain reordering method, computer equipment and a storage medium. The method comprises the following steps: acquiring a chip design layout; determining a plurality of first scanning chains according to the chip design layout, and combining the plurality of first scanning chains into a second scanning chain; reordering the second scan chain to generate a third scan chain; and determining the number of elements of each first scanning chain, segmenting the third scanning chain according to the number of the elements, and generating a plurality of reordered fourth scanning chains with the same number as the plurality of first scanning chains.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip layout planning, and in particular, to a scan chain reordering method, a computer device, and a storage medium. Background Art

[0002] A scan chain is a commonly used digital integrated circuit (IC) testing technology and belongs to the category of design for testability (DFT). Scan reorder refers to the process of reorganizing the scan chain during the chip design process.

[0003] During the chip design process, multiple scan chains may be set. When reordering these scan chains, if reordering a single scan chain cannot meet the overall wire length requirement, further consideration will be given to completing the scan chain reordering by swapping components between multiple scan chains. However, there are currently few methods to achieve reordering in this way and the methods are very rough. Once the number of scan chains increases, the corresponding time consumption will be very large, seriously affecting the overall efficiency.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides a scan chain reordering method, a computer device, and a storage medium to solve or partially solve the above problems.

[0006] Based on the above objectives, in a first aspect, the present disclosure provides a scan chain reordering method, including: Obtain a chip design layout; Determine multiple first scan chains according to the chip design layout, and merge the multiple first scan chains into a second scan chain; Reorder the second scan chain to generate a third scan chain; Determine the number of components of each of the first scan chains, and split the third scan chain according to the number of components to generate multiple reordered fourth scan chains with the same number as the multiple first scan chains.

[0007] In a second aspect, the present disclosure provides a computer device, including one or more processors, a memory; and one or more programs, where the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to the first aspect.

[0008] In a third aspect, the present disclosure provides a non-volatile computer-readable storage medium including a computer program, which, when executed by one or more processors, causes the processors to execute the method described in the first aspect.

[0009] As can be seen from the above, the present disclosure provides a scan chain reordering method, a computer device, and a storage medium. First, the present disclosure determines multiple first scan chains according to the chip design layout. Then, these scan chains can be merged into a single second scan chain using certain merging rules, thereby enabling holistic reordering of a single entire scan chain without restricting components to different scan chains. After completing the reordering to form a third scan chain, it is necessary to restore the scan chains to the same number as the multiple first scan chains. During restoration, the third scan chain is directly segmented according to the number of components in each first scan chain. This not only ensures that the number of fourth scan chains formed by segmentation is the same as the number of first scan chains but also enables the number of components included in each fourth scan chain to correspond to the number of components included in one first scan chain, thus ensuring the correctness of the chain length after reordering multiple scan chains. Moreover, during the entire reordering process, obstacles between different scan chains are avoided, and the reordering efficiency for a single scan chain is generally high. Ultimately, this can significantly optimize the running time of scan chain reordering and improve the overall efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only the embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 Shows a schematic diagram of the hardware structure of an exemplary computer device provided by an embodiment of the present disclosure.

[0012] Figure 2 Shows a schematic diagram of the basic structure of an EDA tool provided by an embodiment of the present disclosure.

[0013] Figure 3 Shows a schematic diagram of the basic execution flow of a calculation command of an EDA tool provided by an embodiment of the present disclosure.

[0014] Figure 4 Shows a schematic diagram of the flow of an exemplary method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] To make the objectives, technical solutions, and advantages of this specification more clear and understandable, the following further elaborates on this specification in detail with reference to specific embodiments and the accompanying drawings.

[0016] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of this disclosure should have the ordinary meanings understood by those of ordinary skill in the field to which this disclosure belongs. The "first", "second", and similar terms used in the embodiments of this disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements, objects, or method steps appearing before this word cover the elements, objects, or method steps listed after this word and their equivalents, without excluding other elements, objects, or method steps. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0017] Figure 1 The structural schematic diagram of a computer device 100 provided by the embodiments of this disclosure is shown. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Among them, the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 achieve communication connections with each other inside the device through the bus 110.

[0018] The processor 102 may be a central processing unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to execute functions related to the technologies described in this disclosure. In some embodiments, the processor 102 may further include multiple processors integrated into a single logic component. As Figure 1 shown, the processor 102 may include multiple processors 102a, 102b, and 102c.

[0019] The memory 104 may be configured to store data (such as instruction sets, computer codes, intermediate data, etc.). For example, as Figure 1As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solutions of the present disclosure) and data to be processed. The processor 102 can also access the stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard disk, a solid state drive (SSD), a flash memory, a memory stick, etc.

[0020] The network interface 106 can be configured to provide communication with other external devices to the computer device 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of the network is not limited to the above specific examples. In some embodiments, the network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0021] The peripheral interface 108 can be configured to connect the computer device 100 to one or more peripheral devices to implement information input and output. For example, the peripheral devices may include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, various sensors, etc. and output devices such as a display, a speaker, a vibrator, an indicator light, etc.

[0022] The bus 110 can be configured to transmit information between various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), etc.

[0023] It should be noted that although the above devices only show the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above devices may also only include the components necessary for implementing the solution of the embodiments of the present disclosure, and do not necessarily include all the components shown in the figure.

[0024] Figure 2 Shows a schematic diagram of the basic structure of an EDA tool 200 according to an embodiment of the present disclosure.

[0025] As Figure 2As shown, the part above the dashed line is the user part; the part below the dashed line is the EDA tool 200, which can be implemented by the device 100 shown in Figure 1 In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software for performing placement and routing based on chip design. The EDA tool 200 can include a Tcl command (or graphical / window interface) module 204, various calculation modules (such as a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.), and a database system 212. The user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command (or graphical / window interface) module 204.

[0026] The Tcl command module 204 mainly functions as message passing or command passing. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can, according to the specific content of the instructions, allocate and pass them to the corresponding calculation modules to execute specific tasks.

[0027] According to different calculation tasks, the various calculation modules can be divided into, for example, a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc. The Place calculation module 206 can be used to calculate a reasonable placement position for all components, the Route calculation module 208 can be used to calculate a reasonable wire connection method between the components, and the Optimization calculation module 210 can be used to optimize the placement positions and wire connection methods between the components. The calculation processes of these calculation modules can be performed in, for example, Figure 1 the processor 102.

[0028] The database system 212 can be used to completely and comprehensively record and store all information of the chip being simulated or designed (such as position, orientation, size, structure, wire connection method, etc.). This information can be stored, for example, in Figure 1 the memory 104.

[0029] Figure 3 shows a basic execution flow 300 of a calculation command of the EDA tool 200 according to an embodiment of the present disclosure. As Figure 3As shown, in step 302, user 202 can issue a command (e.g., do_place command) to the EDA tool 200 through the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses this command and distributes it to the corresponding computing module (e.g., Place computing module 206). In step 306, each computing module performs the specific calculations it needs to perform. During this period, as shown in step 308, each computing module needs to (frequently and repeatedly) retrieve data from the database system 212 for calculations. After the calculations are completed, as shown in step 310, each computing module can write the calculation results to the database system 212 and return the calculation results to the Tcl command module 204. In step 312, the Tcl command module 204 returns the calculation results to the user 202 through the command interface or graphical user interface (GUI), and the processing of a calculation command by the EDA tool 200 ends. In step 314, the user can evaluate based on the calculation results and then determine the next plan.

[0030] In some embodiments, a scan chain is a design-for-testability technique that allows testers to externally control and observe the signal values of internal flip-flops in a circuit by implanting shift registers. Its basic principle is to connect all the flip-flops in the design into a chain, driven by a unified scan clk, and shift each bit into the chip one by one through a pre-designed scan pattern. Then, the capture enable is turned on, and the output of the Q terminal (output terminal) of each flip-flop will be fed into the combinational circuit it drives. The D terminal (input terminal) of the next-level flip-flop will capture the output of this combinational circuit, and finally, a set of result vectors will be obtained at the output of the scan chain and compared with the expected values pre-calculated by the tool to determine whether there are manufacturing errors in the chip. Scan Reorder refers to the process of reordering the scan chain during the chip design process. A scan chain is a design method in design for testability (DFT). By replacing ordinary registers with registers with scan functions and connecting them into a chain through specific input and output ports, it is possible to perform shift operations through external control during testing, thereby enabling the testing of the internal logic of the chip. The main role of scan chain reordering is to optimize the connection method of the scan chain to ensure that data can flow quickly and safely.

[0031] With the increasing complexity of chip design, in some scenarios, multiple scan chains are involved. For these scan chains, corresponding scan chain reordering (Scan Reorder) can be performed separately. If the reordering effect does not meet the requirements, further reordering of the components (insts) between the scan chains can be carried out, that is, by using an EDA tool to execute the scan_reorder -repartition true instruction, dividing multiple scan chains into at least one repartition group, and performing component swapping and component connection relationship rearrangement among the scan chains within a repartition group. However, when executing this instruction currently, the corresponding reordering method is relatively rough, with many loopholes, highly dependent on manual intervention, and once the number of scan chains within the group increases, the corresponding reordering time will increase exponentially, seriously affecting the overall efficiency.

[0032] In view of this, the present disclosure proposes a scan chain reordering method. First, the present disclosure determines multiple first scan chains according to the chip design layout. Then, these scan chains can be merged into a single second scan chain using certain merging rules, so as to perform overall reordering on a single whole scan chain without restricting components to different scan chains. After the reordering is completed to form a third scan chain, it is necessary to restore the scan chains to the same number as the multiple first scan chains. When restoring, the third scan chain is directly segmented according to the number of components in each first scan chain. This not only ensures that the number of the segmented fourth scan chains is the same as the number of the first scan chains, but also enables the number of components included in each fourth scan chain to correspond to the number of components included in a first scan chain, thus ensuring the correctness of the chain length after reordering of multiple scan chains. And during the entire reordering process, the obstacles between different scan chains are avoided, and the reordering efficiency for a single scan chain is generally high. Finally, this can greatly optimize the running time of scan chain reordering and improve the overall efficiency.

[0033] Figure 4 shows a schematic flowchart of an exemplary method 400 provided by an embodiment of the present disclosure. This method 400 can be implemented by Figure 1 a computer device 100 and can be implemented as Figure 2 a part of the function of an EDA tool 200. As Figure 4 shown, this method 400 can further include the following steps.

[0034] Step 402, obtain the chip design layout.

[0035] Generally, a chip design layout includes each layer structure for chip processing, specifically transistor layout, wiring, routing, channel via interlayer connection positions, etc. According to this chip design layout, a chip processing service provider can directly run and carry out batch processing production of the chip. Further, the chip design layout itself is drawn step by step, accompanied by various optimizations, and finally the entire chip design layout is completed. In the initial stage of the chip design layout, it may only indicate the functional information of the layers, such as one layer is a routing layer, one layer is an insulating layer, etc.; or only set each functional element and mark the position, size, etc. of each functional element. Then, step-by-step design and optimization are carried out using EDA tools, etc., and finally a complete version of the chip design layout is formed. Here, the so-called element (inst) can be a standard processing unit, module or hardcore, input / output terminal, register, etc. in the chip.

[0036] In this step, since this embodiment is related to operations on the scan chain, generally, a chip design layout with the relevant scan chain drawn needs to be obtained. Through this chip design layout, the specific form and relevant attribute data of the current scan chain can be determined, such as the starting position of the scan chain (which can be represented by coordinates, etc.), the ending position, the connection relationship between each element in the scan chain, the setting positions of these elements (which can be represented by coordinates, etc.), and so on. In a specific application scenario, initial data information such as scan chain data and element positions can be obtained through the DEF (Design Exchange File, physical information of the design library) file and / or LEF (Library Exchange File, physical information of the process library) file of the chip design layout.

[0037] It should be noted that scan chain reordering generally involves re-determining the connection relationship between elements. During the whole process, the physical positions of the elements generally do not change, and only the connection relationship between different elements or the scan chain to which the elements belong changes.

[0038] In addition, in this step, the chip design layout can be partial (for example, dividing the entire design layout into a large number of sub-regions) or it can be the whole.

[0039] Step 404, determine multiple first scan chains according to the chip design layout, and merge the multiple first scan chains into a second scan chain.

[0040] In this step, after obtaining the chip design layout, at least one scan chain can be determined according to the records therein. These scan chains generally have a starting position, and then pass through multiple series-connected and / or parallel-connected elements from the starting position to reach the ending position. The at least one scan chain determined here is the first scan chain.

[0041] After determining multiple first scan chains, these scan chains can be merged into a single whole, that is, a second scan chain is generated. The merging process here can be directly connecting the first scan chains end to end to form a single second scan chain; it can also be disassembling the components included in each first scan chain and then reorganizing them into a complete second scan chain; it can also be directly determining the components included in these first scan chains and then directly connecting them into a second scan chain according to specific connection rules, and so on. That is, in some embodiments, the merging of the multiple first scan chains into a second scan chain includes: splicing the multiple first scan chains according to a set rule to generate the second scan chain; or disassembling the components of the multiple first scan chains and reorganizing the disassembled components into the second scan chain. The set rule can be the aforementioned end-to-end connection rule, or can be specifically set according to the specific application scenario.

[0042] In a more specific application scenario, when the first scan chain is determined, other related attributes of the first scan chain can generally be determined, such as the starting position of the scan chain, the setting position of each component, etc. In this scenario, these attributes generally do not change and can be regarded as fixed attributes.

[0043] Step 406, reorder the second scan chain to generate a third scan chain.

[0044] In this step, it is necessary to perform a reordering operation on the second scan chain, and it can directly reorder the second scan chain according to a conventional reordering method. For example, directly perform a full-scale reordering calculation with the components included in the entire second scan chain as a unit, and then reconnect each component according to the reordering result to form a third scan chain.

[0045] However, due to the complexity of chip design, the merged second scan chain may contain a very large number of components. If a normal reordering is directly performed, it may consume too much time and have low efficiency. Therefore, in order to improve efficiency, the reordering process can be further optimized. First, it is possible to first determine the multiple components included in the second scan chain. After determining the multiple components included in the second scan chain, the number of components included in this scan chain can be determined by reading the chip design layout data or by statistical means. Further, these components can be grouped according to this number to generate at least one component set.

[0046] In some embodiments, the number of groups to be divided can be preset, and these components can be grouped accordingly. For example, if it is necessary to divide into 5 groups, after determining the number of components, these components can be divided into 5 groups and 5 component sets can be generated by means of randomization, equal division, or proximity clustering (clustering components with close distances with distance as a reference). In other embodiments, these components can also be grouped by setting the maximum number of components in each group. For example, if the number of components is 200 and the maximum number of components in a group is 20, then the components need to be divided into 10 groups and 10 component sets can be generated.

[0047] After determining the component sets, since these component sets are essentially part of a scan chain, the component sets can be reordered according to the original reordering rules for the scan chain. Here, it can be understood that the scan chain is cut into multiple sub-chains and these sub-chains are reordered. The specific reordering rules can be specifically set according to the specific application scenario, and its main purpose is to optimize the component connection relationship. By reordering at least one group of component sets and adjusting the connection relationship of the components in each group of component sets, after optimizing the connection relationship, at least one reordered sub-chain can be generated, where one sub-chain corresponds to one group of component sets. When the reordering of each sub-chain is completed, these sub-chains need to be spliced together to restore a complete scan chain, that is, to form a third scan chain. For splicing, it can be performed according to a preset setting. For example, before reordering, the order of the sub-chains corresponding to each component set during splicing is determined, and this order can be set manually or determined according to other requirements. That is, in some embodiments, the reordering of the second scan chain includes: determining the multiple components included in the second scan chain; grouping according to the number of the multiple components to generate at least one group of component sets; reordering the at least one group of component sets to generate at least one sub-chain corresponding to the at least one group of component sets; and splicing the at least one sub-chain.

[0048] Further, when arranging and connecting components in chip design, there is an important parameter to consider, namely the wirelength gain. Each time the connection method of components is adjusted, it is expected to minimize the loss of wirelength gain. For the scenario of this embodiment, if considering minimizing the loss of wirelength gain, during the reordering process, components with close distances should be rearranged together or grouped into one group as much as possible. In a specific application scenario, first, according to the chip design layout, etc., determine the distances between the components in the scan chain, and then use a clustering algorithm to cluster these components based on these distances, thereby completing the grouping of these components. Finally, make the components in each group of component sets as close as possible to reduce the optimization loss of the global wirelength gain. For example, assume that 100 components need to be divided into 5 groups of component sets. The clustering algorithm can be used to randomly select 5 origin points first, and then, according to the distances between the components, perform clustering centered on these 5 origin points. After the initial clustering, re-determine the center origin points for each clustering set and perform clustering again. Iterate in this way until the set termination condition is reached, and complete the grouping of the 5 groups of component sets. That is, in some embodiments, the grouping according to the number of the multiple components includes: determining the distances between the multiple components; clustering the multiple components using a clustering algorithm according to the distances; and performing the grouping according to the clustering result.

[0049] Further, in some more specific application scenarios, for a variety of clustering algorithms, considering the application scenario of this embodiment and the requirements for aspects such as convergence speed and scalability, the K-means clustering algorithm can be selected to perform the clustering. That is, in some embodiments, the clustering algorithm includes the K-means clustering algorithm.

[0050] Furthermore, in a specific application scenario, during the process of clustering components in the scan chain using a clustering algorithm, due to reasons such as an excessive number of clustering objects (components), the particularity of the clustering objects (components), or the particularity of the connection relationships of the clustering objects (components), the clustering convergence process sometimes takes a long time, which may also affect the overall efficiency. Therefore, it is possible to consider accelerating the clustering algorithm. For example, it can be accelerated by reducing dimensions (such as principal component analysis PCA), using an efficient database (such as using the NumPy library), local sensitive hashing (LSH), etc. Due to its outstanding performance in optimizing data structures, automatic vectorization, etc., the Eigen template library can be selected to accelerate the clustering algorithm, and in the specific application scenario of this embodiment, the Eigen template library also demonstrates relatively prominent advantages, significantly reducing the clustering process for components. Among them, the Eigen template library is a C++ template library for linear algebra: for matrices, vectors, numerical solvers, and related algorithms. That is, in some embodiments, clustering the multiple components using the clustering algorithm according to the distance includes: accelerating the clustering algorithm using the Eigen template library.

[0051] Step 408: Determine the number of components in each of the first scan chains, and partition the third scan chain according to the number of components to generate multiple reordered fourth scan chains with the same number as the multiple first scan chains.

[0052] In this step, after forming the reordered third scan chain, according to the relevant rules of chip design, the number of scan chains needs to be restored to be equivalent to that before reordering. That is, before reordering, there are 50 scan chains in one repartition group, and after reordering, there still need to be 50 scan chains in one repartition group. Therefore, in this embodiment, it is necessary to partition the third scan chain.

[0053] In this embodiment, first, the number of elements in each of the previous first scan chains is determined, and then the third scan chain is directly segmented based on these numbers of elements. For example, there are 4 first scan chains in total: chain1, chain2, chain3, and chain4, which contain 10, 20, 20, and 30 elements respectively. According to the foregoing steps, both the second scan chain and the third scan chain contain 80 elements. When segmenting, it can be directly segmented according to "10, 20, 20, 30" to generate four fourth scan chains: chain1' with 10 elements, chain2' with 20 elements, chain3' with 20 elements, and chain4' with 30 elements. This not only ensures that the number of generated fourth scan chains is the same as that of the first scan chains, but also for any first scan chain, a fourth scan chain with the corresponding number of elements can be found. This also facilitates the connection of each scan chain to the corresponding scan chain start position and end position. For example, chain1' corresponds to chain1, and the connection can be made according to the start position and end position of chain1. This can improve the corresponding connection efficiency. At the same time, in a more specific application scenario, when executing the scan_reorder -repartition true instruction, the maxbit attribute needs to be considered, that is, after the reordering of each scan chain, the number of elements contained cannot exceed a corresponding threshold, and this threshold is the maxbit. Generally, the maxbit of a scan chain is greater than or equal to the number of elements contained in the scan chain before reordering. For example, if scan chain A contains 10 elements before reordering, then the maxbit of scan chain A is generally greater than or equal to 10. Returning to this embodiment, the fourth scan chain is directly segmented based on the number of elements in the first scan chain. According to the foregoing segmentation method, the segmented fourth scan chains not only have the same number as the first scan chains, but also each first scan chain can correspond to a fourth scan chain with the same number of elements, and thus necessarily meet the relevant reordering requirements. This can improve the reordering efficiency while further simplifying the relevant detection process and improving the detection efficiency, thereby further improving the overall efficiency.

[0054] In some embodiments, to further improve the splitting efficiency, the splitting process can be further refined. According to the number of components in different first scan chains, a corresponding set of numbers can be generated. For example, for the aforementioned chain1 to chain4, the corresponding set of numbers is {10, 20, 20, 30}. Then, the number of different numbers included in this set of numbers can be counted. For example, the set {10, 20, 20, 30} contains 3 different numbers, namely 10, 20, and 30. After that, the splitting scheme can be determined based on these 3 numbers. The splitting scheme here is the scheme for one cut. Simply put, it is to determine how to make the "first cut" or the "second cut", etc. Combining the aforementioned example, the generated splitting schemes are to cut 10, 20, or 30 components. Then, the third scan chain can be split and simulated according to these splitting schemes. Taking the "first cut" as an example, Scheme A is to cut out the first 10 components, Scheme B is to cut out the first 20 components, and Scheme C is to cut out the first 30 components. In this way, 3 simulation results are generated. Then, these simulation results can be screened according to the wire length requirements, gain requirements, etc. in some specific application scenarios, and one target simulation result can be selected, and the target splitting scheme corresponding to the target simulation result can be determined. Then, the third scan chain can be directly split according to the target splitting scheme; or the determination of the next splitting scheme can be carried out until all the splitting schemes are determined, and then the third scan chain can be split. That is, in some embodiments, the splitting of the third scan chain according to the number of components includes: generating a set of numbers according to the number of components in different first scan chains; determining the number of different numbers included in the set of numbers, and determining at least one splitting scheme according to the number of different numbers, where the at least one splitting scheme is a scheme for one cut of the third scan chain; performing splitting simulation on the third scan chain according to the at least one splitting scheme to generate at least one simulation result corresponding to the at least one splitting scheme; screening the at least one simulation result according to the set requirements to determine the target simulation result and the target splitting scheme corresponding to the target simulation result; splitting the third scan chain according to the target splitting scheme.

[0055] Furthermore, according to the introduction of the foregoing embodiments, during the reordering process, wirelength gain is highly emphasized. Thus, during the segmentation process, wirelength gain can also be considered to optimize the segmentation, especially the foregoing screening process. According to the foregoing, for a scan chain, before and after reordering, its starting position and ending position generally do not change. At the same time, the positions of the components participating in the reordering generally do not change either. Thus, during segmentation, this can be used as a basis for screening. Taking the foregoing chain1 to chain4 as an example, when determining the first segmentation scheme, three segmentation results are generated. Result A is to segment 10 components, corresponding to chain1; Result B is to segment 20 components, corresponding to chain2 and chain3; Result C is to segment 30 components, corresponding to chain4. At this time, the component closest to the starting position of chain1 can be found in Result A as the starting component. After that, since the 10 components in Result A can be connected end to end, after determining the starting component, unfolding Result A can determine the ending component in Result A. Then, the first distance from the starting component to the starting position of chain1 and the second distance from the ending component to the ending position of chain1 can be calculated, and then the sum of the first distance and the second distance can be used as the screening condition for Result A corresponding to chain1. Repeating the above process can determine the screening conditions for Result B corresponding to chain2, the screening conditions for Result B corresponding to chain3, and the screening conditions for Result C corresponding to chain4. Finally, based on the magnitudes of these 4 screening conditions (the one with the smallest screening condition can be selected), it can be determined which result to use for the first segmentation and which first scan chain the segmented scan chain corresponds to. That is, in some embodiments, the screening of the at least one simulation result according to the set requirements includes: determining multiple pieces of attribute information corresponding to the multiple first scan chains; where each piece of the attribute information includes at least a starting position, an ending position, and a first number of components; for any simulation result, determining the second number of components of the any simulation result, and selecting at least one piece of target attribute information whose first number of components is equal to the second number of components from the multiple pieces of attribute information; for any piece of target attribute information, determining the starting component in the any simulation result that is closest to the starting position of the any target attribute information, and determining the ending component of the any segmentation result based on the starting component; calculating the first distance between the starting component and the starting position of the any target attribute information, and the second distance between the ending component and the ending position of the any target attribute information, and generating the screening condition for the any simulation result for the any target attribute information based on the first distance and the second distance; statistically analyzing and sorting all the screening conditions of the at least one simulation result, and performing screening according to the sorting result.

[0056] Further, in order to reduce the process of repeated calculation or repeated determination. After determining a segmentation scheme, when determining the next segmentation scheme, first determine whether there has been a segmentation scheme before. If so, all the previously performed segmentation schemes can be counted to determine which attribute information corresponds to each segmentation scheme. Here, the attribute information corresponding to each determined segmentation scheme can be referred to as segmentation attribute information. Then, when determining the current segmentation scheme, after determining multiple pieces of attribute information, the segmentation attribute information can be removed from these pieces of attribute information. For example, on the basis of the foregoing example, assume "the first cut". The first segmentation scheme is finally determined to be segmented according to the B result corresponding to chain2, that is, first cut 20 components of the third scan chain, and these components will be connected to the start position and end position of chain2 to form chain2'. Then, for "the second cut", when determining the second segmentation scheme, since there is the first segmentation scheme, the segmentation attribute information corresponding to the first segmentation scheme, which is the relevant information corresponding to chain2 or chain2' here, can be excluded from the attribute information, and only 3 sets of screening conditions for corresponding relationships (the screening conditions for the A result corresponding to chain1, the screening conditions for the B result corresponding to chain3, and the screening conditions for the C result corresponding to chain4) are generated, and a selection is made among these three sets of screening conditions. Assume that the second segmentation scheme is finally determined to be segmented according to the B result corresponding to chain3. Then, for "the third cut", according to a similar process as described above, finally only 2 sets of screening conditions for corresponding relationships (the screening conditions for the A result corresponding to chain1 and the screening conditions for the C result corresponding to chain4) are generated, and then a selection is made among these two sets of screening conditions, and so on. That is, in some embodiments, after determining the multiple pieces of attribute information corresponding to the multiple first scan chains, the method further includes: determining whether there is a previous segmentation scheme; in response to the existence of the previous segmentation scheme, counting the previous segmentation schemes to determine the segmentation attribute information of each segmentation scheme; and removing the attribute information corresponding to the segmentation attribute information from the multiple pieces of attribute information.

[0057] As can be seen above, the embodiments of the present disclosure provide a scan chain reordering method. First, the present disclosure determines multiple first scan chains according to the chip design layout. After that, these scan chains can be merged into an entire second scan chain by using certain merging rules, so as to perform an overall reordering on a single entire scan chain, without restricting components to different scan chains. After the reordering is completed to form a third scan chain, it is necessary to restore the scan chain to the same number as the number of multiple first scan chains. When restoring, the third scan chain is directly segmented according to the number of components of each first scan chain. This not only ensures that the number of the fourth scan chains formed by segmentation is the same as the number of the first scan chains, but also enables the number of components included in each fourth scan chain to correspond to the number of components included in a first scan chain, thereby ensuring the correctness of the chain length after the reordering of multiple scan chains. And during the entire reordering process, the obstacles between different scan chains are avoided, and the reordering efficiency for a single scan chain is generally high. Finally, this can greatly optimize the running time of the scan chain reordering and improve the overall efficiency.

[0058] It should be noted that the method of the embodiments of the present disclosure can be executed by a single device, such as a computer or a server. The method of the embodiments of the present disclosure can also be applied to a distributed scenario and completed by the cooperation of multiple devices. In this case of a distributed scenario, one of these multiple devices can only execute one or more steps of the method of the embodiments of the present disclosure, and these multiple devices will interact with each other to complete the described method.

[0059] It should be noted that the above describes specific embodiments of the present disclosure. In some cases, the actions or steps recorded in the above embodiments of the present disclosure can be executed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0060] Based on the same inventive concept, corresponding to the method of any of the above embodiments, the present application also provides a non-volatile computer-readable storage medium containing a computer program. The non-volatile computer-readable storage medium containing the computer program stores computer instructions, and the computer instructions are used to cause the computer to execute the method 400 described in any of the above embodiments.

[0061] The computer-readable storage medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0062] The computer instructions stored in the storage medium of the above embodiment are used to cause the computer to execute the method 400 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be elaborated here.

[0063] Based on the same inventive concept, corresponding to the method 400 in any of the above embodiments, the present application also provides a computer program product, which includes a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to execute the method 400. Corresponding to the execution subjects of each step in the embodiments of the method 400, the processors that execute the corresponding steps can belong to the corresponding execution subjects.

[0064] The computer program product of the above embodiment is used to cause the processor to execute the method 400 described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated here.

[0065] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present application is limited to these examples; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity.

[0066] In addition, for simplicity of explanation and discussion, and in order not to make the embodiments of the present application difficult to understand, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Further, the devices may be shown in block diagram form in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In cases where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application may be practiced without these specific details or with variations of these specific details. Accordingly, these descriptions should be considered illustrative rather than restrictive.

[0067] Although the present application has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0068] Embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the above-described embodiments. Accordingly, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A scan chain reordering method, characterized in that: include: Obtain chip design layout; Determine a plurality of first scan chains according to the chip design layout, and merge the plurality of first scan chains into a second scan chain; reordering the second scan chains to generate a third scan chain; The number of components in each of the first scan chains is determined, and the third scan chain is divided according to the number of components to generate a plurality of reordered fourth scan chains having the same number as the plurality of first scan chains.

2. The method according to claim 1, characterized in that The dividing the third scan chain according to the number of components includes: generating a quantity set according to the quantity of the components of different first scan chains; Determine the quantity types included in the quantity set, and determine at least one segmentation scheme according to the quantity types; wherein the at least one segmentation scheme is a scheme for segmenting the third scan chain once; Performing a segmentation simulation on the third scan chain according to the at least one segmentation scheme, and generating at least one simulation result corresponding to the at least one segmentation scheme; Screening the at least one simulation result according to the set requirements to determine a target simulation result and a target segmentation scheme corresponding to the target simulation result; The third scan chain is segmented according to the target segmentation scheme.

3. The method according to claim 2, characterized in that The screening of the at least one simulation result according to the set requirements includes: Determine a plurality of pieces of attribute information corresponding to the plurality of first scan chains; wherein each piece of the attribute information at least includes a starting position, an ending position and the number of first elements; For any simulation result, determine the number of second elements of the simulation result, and select at least one target attribute information in which the number of the first elements is equal to the number of the second elements from the multiple attribute information; For any target attribute information, determine a starting element in any simulation result that is closest to a starting position of any target attribute information, and determine an ending element of any segmentation result according to the starting element; Calculating a first distance between the starting element and a starting position of any target attribute information, and a second distance between the ending element and a terminating position of any target attribute information, and generating a screening condition for any simulation result for any target attribute information according to the first distance and the second distance; All screening conditions of the at least one simulation result are counted and sorted, and screening is performed according to the sorting result.

4. The method according to claim 3, characterized in that: After determining the plurality of pieces of attribute information corresponding to the plurality of first scan chains, the method further includes: Determine whether there is a previous segmentation plan; In response to the existence of the previous segmentation scheme, statistics are collected on the previous segmentation schemes to determine segmentation attribute information of each segmentation scheme; The attribute information corresponding to the segmented attribute information is removed from the plurality of pieces of attribute information.

5. The method according to claim 1, characterized in that The reordering of the second scan chain includes: determining a plurality of elements included in the second scan chain; Grouping the plurality of components according to the number of components to generate at least one set of components; Reordering the at least one set of component sets to generate at least one subchain corresponding to the at least one set of component sets; The at least one daughter strand is spliced.

6. The method according to claim 5, characterized in that The grouping according to the number of the plurality of elements comprises: determining distances between the plurality of elements; Clustering the plurality of elements using a clustering algorithm according to the distance; The grouping is performed according to the clustering result.

7. The method according to claim 6, characterized in that The clustering of the plurality of elements by using a clustering algorithm according to the distance comprises: The clustering algorithm is accelerated using the Eigen template library.

8. The method according to claim 1, characterized in that The step of merging the plurality of first scan chains into a second scan chain comprises: splicing the plurality of first scan chains according to a set rule to generate the second scan chain; Or the plurality of first scan chains are split into components, and the split components are reassembled into the second scan chains.

9. A computer device, characterized in that: The method comprises one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 8.

10. A non-volatile computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 8.

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