Multi-channel state machine and signal processing method and device based on multi-channel state machine

Abstract

The invention discloses a multi-channel state machine and a signal processing method and device based on the multi-channel state machine. The multi-channel state machine comprises an input processing module, a random access memory (RAM) module, a state jump module and an output processing module, the input processing module is used for acquiring an input signal sent by a channel; the RAM module is used for receiving and storing a state value of a channel and an intermediate register variable; the state jump module is used for processing an event to be processed according to the input signal, the first state value, the first intermediate register variable value and the second intermediate register variable value to generate a second state value and a third intermediate register variable value; the output processing module is used for determining and outputting an output signal according to the channel number, the second state value and the third intermediate register variable value, the number of registers can be reduced, and the resource utilization rate is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of state machines, and particularly to a multi-channel state machine, a signal processing method and device based on the multi-channel state machine. Background Art

[0002] This section aims to provide background or context for embodiments of the present invention. The description herein is not admitted to be prior art merely by virtue of being included in this section.

[0003] A state machine is a commonly used method in digital circuit design. It jumps to a state according to the input conditions, and then determines the output according to the input and the current state. In digital circuit design, registers are generally used to save states. Registers have a relatively fast read and write speed, and can perform read and write operations simultaneously in the same cycle. The read data is the value of the register in the current cycle, and the written data is saved by the register and can be read in the next cycle.

[0004] The method of saving states by registers has a fast response speed and a relatively simple design; however, it consumes more register resources, especially in some application scenarios that process data with a large number of channels simultaneously, and the increase in resource consumption is particularly significant. For example, for the maintenance of a communication link, there are usually three states: establishing a connection, data transmission, and releasing the connection. If single-bit encoding is used, three registers are required to save its state. Assuming a module needs to process 1024 links, then a total of 1024×3 = 3072 registers are required. Summary of the Invention

[0005] Embodiments of the present invention provide a multi-channel state machine to save the number of registers and improve resource utilization. The multi-channel state machine includes: an input processing module, a RAM (Random Access Memory) module, a state jump module, and an output processing module;

[0006] The input processing module is configured to obtain an input signal sent by a channel; buffer the input signal into an input queue; the input signal is used to represent whether a to-be-processed event occurs in the channel;

[0007] The RAM module is configured to receive and save the state value of the channel and intermediate register variables;

[0008] A status jump module, which is used to read input signals from an input queue; determine the channel number and the value of the first intermediate register variable of the channel where the event to be processed is located according to the input signals; read the first status value and the value of the second intermediate register variable of the channel where the event to be processed is located from a RAM module according to the channel number; perform a status jump on the channel where the event to be processed is located according to the logical information of the event to be processed, and jump the first status value to the second status value; assign the value of the intermediate register variable of the channel where the event to be processed is located to the value of the third intermediate register variable according to the logical information of the event to be processed, and the values of the first intermediate register variable and the second intermediate register variable of the channel where the event to be processed is located; write the second status value and the value of the third intermediate register variable to the channel where the event to be processed is located in the RAM module; cache the channel number, the second status value and the value of the third intermediate register variable of the channel where the event to be processed is located into an output queue;

[0009] An output processing module, which is used to obtain the channel number, the second status value and the value of the third intermediate register variable of the channel where the event to be processed is located from an output queue; determine an output signal and output it according to the channel number, the second status value and the value of the third intermediate register variable of the channel where the event to be processed is located.

[0010] An embodiment of the present invention provides a signal processing method based on a multi-channel state machine to save the number of registers and improve resource utilization. The method includes:

[0011] Obtain an input signal sent by a channel, the status value of the channel and the value of the intermediate register variable; the input signal is used to indicate whether an event to be processed occurs in the channel;

[0012] Determine the channel number and the value of the first intermediate register variable of the channel where the event to be processed is located according to the input signal;

[0013] Read the first status value and the value of the second intermediate register variable of the channel where the event to be processed is located according to the channel number;

[0014] Perform a status jump on the channel where the event to be processed is located according to the logical information of the event to be processed, and jump the first status value to the second status value;

[0015] Assign the value of the intermediate register variable of the channel where the event to be processed is located to the value of the third intermediate register variable according to the logical information of the event to be processed, and the values of the first intermediate register variable and the second intermediate register variable of the channel where the event to be processed is located;

[0016] Write the second status value and the value of the third intermediate register variable to the channel where the event to be processed is located; cache the channel number, the second status value and the value of the third intermediate register variable of the channel where the event to be processed is located into an output queue;

[0017] Determine the output signal according to the channel number, the second status value, and the value of the third intermediate register variable of the channel where the event to be processed is located, which is obtained from the output queue, and then output the signal.

[0018] An embodiment of the present invention further provides a signal processing device based on a multi-channel state machine, which is used to save the number of registers and improve resource utilization. The device includes:

[0019] An acquisition module, configured to acquire an input signal sent by a channel, the status value of the channel, and an intermediate register variable; the input signal is used to indicate whether a to-be-processed event occurs in the channel;

[0020] A determination module, configured to determine the channel number and the value of the first intermediate register variable of the channel where the to-be-processed event is located according to the input signal;

[0021] A reading module, configured to read the first status value and the value of the second intermediate register variable of the channel where the to-be-processed event is located according to the channel number;

[0022] A second status value determination module, configured to perform a status jump on the channel where the to-be-processed event is located according to the logical information of the to-be-processed event, and jump the first status value to the second status value;

[0023] An intermediate register variable assignment module, configured to assign the value of the intermediate register variable of the channel where the to-be-processed event is located to the value of the third intermediate register variable according to the logical information of the to-be-processed event, the value of the first intermediate register variable, and the value of the second intermediate register variable of the channel where the to-be-processed event is located;

[0024] A writing module, configured to write the second status value and the value of the third intermediate register variable into the channel where the to-be-processed event is located; cache the channel number, the second status value, and the value of the third intermediate register variable of the channel where the to-be-processed event is located into the output queue;

[0025] An output module, configured to determine the output signal according to the channel number, the second status value, and the value of the third intermediate register variable of the channel where the to-be-processed event is located, which is obtained from the output queue, and then output the signal.

[0026] An embodiment of the present invention further provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, a signal processing method based on a multi-channel state machine is implemented. The method includes:

[0027] Acquire an input signal sent by a channel, the status value of the channel, and an intermediate register variable; the input signal is used to indicate whether a to-be-processed event occurs in the channel;

[0028] Determine the channel number and the value of the first intermediate register variable of the channel where the to-be-processed event is located according to the input signal;

[0029] Read the first status value and the second intermediate register variable value of the channel where the event to be processed is located according to the channel number;

[0030] Perform a status jump on the channel where the event to be processed is located according to the logical information of the event to be processed, and jump the first status value to the second status value;

[0031] Assign the intermediate register variable of the channel where the event to be processed is located to the third intermediate register variable value according to the logical information of the event to be processed, the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located;

[0032] Write the second status value and the third intermediate register variable value to the channel where the event to be processed is located; cache the channel number, the second status value and the third intermediate register variable value of the channel where the event to be processed is located into the output queue;

[0033] Determine the output signal according to the channel number, the second status value and the third intermediate register variable value of the channel where the event to be processed is obtained from the output queue, and then output it.

[0034] An embodiment of the present invention also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, a signal processing method based on a multi-channel state machine is implemented. The method includes:

[0035] Obtain an input signal sent by a channel, the status value of the channel, and an intermediate register variable; the input signal is used to indicate whether a to-be-processed event occurs in the channel;

[0036] Determine the channel number and the first intermediate register variable value of the channel where the event to be processed is located according to the input signal;

[0037] Read the first status value and the second intermediate register variable value of the channel where the event to be processed is located according to the channel number;

[0038] Perform a status jump on the channel where the event to be processed is located according to the logical information of the event to be processed, and jump the first status value to the second status value;

[0039] Assign the intermediate register variable of the channel where the event to be processed is located to the third intermediate register variable value according to the logical information of the event to be processed, the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located;

[0040] Write the second status value and the third intermediate register variable value to the channel where the event to be processed is located; cache the channel number, the second status value and the third intermediate register variable value of the channel where the event to be processed is located into the output queue;

[0041] Determine the output signal according to the channel number, the second status value, and the value of the third intermediate register variable of the channel where the event to be processed obtained from the output queue is located, and then output it.

[0042] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements a signal processing method based on a multi-channel state machine. The method includes:

[0043] Obtain an input signal sent by a channel, the status value of the channel, and an intermediate register variable; the input signal is used to indicate whether a to-be-processed event occurs in the channel.

[0044] Determine the channel number and the value of the first intermediate register variable of the channel where the to-be-processed event is located according to the input signal.

[0045] Read the first status value and the value of the second intermediate register variable of the channel where the to-be-processed event is located according to the channel number.

[0046] Perform a status jump on the channel where the to-be-processed event is located according to the logical information of the to-be-processed event, and jump the first status value to the second status value.

[0047] Assign the value of the third intermediate register variable to the intermediate register variable of the channel where the to-be-processed event is located according to the logical information of the to-be-processed event, the value of the first intermediate register variable, and the value of the second intermediate register variable of the channel where the to-be-processed event is located.

[0048] Write the second status value and the value of the third intermediate register variable into the channel where the to-be-processed event is located; cache the channel number, the second status value, and the value of the third intermediate register variable of the channel where the to-be-processed event is located into the output queue.

[0049] Determine the output signal according to the channel number, the second status value, and the value of the third intermediate register variable of the channel where the to-be-processed event obtained from the output queue is located, and then output it.

[0050] Compared with the technical solutions in the prior art that process data for a large number of channels simultaneously, the embodiments of the present invention include an input processing module, a RAM module, a state jump module, and an output processing module. The input processing module is used to obtain the input signals sent by the channels, buffer the input signals into an input queue, and the input signals are used to represent whether a to-be-processed event occurs in the channels. The RAM module is used to receive and save the state values and intermediate register variables of the channels. The state jump module is used to read the input signals from the input queue, determine the channel number and the value of the first intermediate register variable of the channel where the to-be-processed event is located according to the input signals, read the first state value and the value of the second intermediate register variable of the channel where the to-be-processed event is located from the RAM module according to the channel number, perform a state jump on the channel where the to-be-processed event is located according to the logical information of the to-be-processed event, and change the first state value to the second state value. According to the logical information of the to-be-processed event, the value of the first intermediate register variable and the value of the second intermediate register variable of the channel where the to-be-processed event is located, assign the value of the intermediate register variable of the channel where the to-be-processed event is located to the value of the third intermediate register variable, write the second state value and the value of the third intermediate register variable to the channel where the to-be-processed event is located in the RAM module, and buffer the channel number, the second state value and the value of the third intermediate register variable of the channel where the to-be-processed event is located into an output queue. The output processing module is used to obtain the channel number, the second state value and the value of the third intermediate register variable of the channel where the to-be-processed event is located from the output queue, and determine and output the output signals according to the channel number, the second state value and the value of the third intermediate register variable of the channel where the to-be-processed event is located, which can save the number of registers and improve resource utilization rate. Brief Description of the Drawings

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0052] Figure 1 is a structural block diagram of a multi-channel state machine provided in an embodiment of the present invention;

[0053] Figure 2 is a schematic diagram of the logical information of a to-be-processed event provided in an embodiment of the present invention;

[0054] Figure 3 is a flowchart of a signal processing method based on a multi-channel state machine provided in an embodiment of the present invention;

[0055] Figure 4Schematic diagram of a signal processing device based on a multi-channel state machine provided in an embodiment of the present invention;

[0056] Figure 5 Schematic diagram of a computer device provided in an embodiment of the present invention. Detailed implementation manners

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer and more understandable, the following further describes the embodiments of the present invention in detail with reference to the accompanying drawings. Herein, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but not to limit the present invention.

[0058] In the technical solutions of this application, the acquisition, storage, use, processing, etc. of data all comply with the relevant regulations of laws and regulations.

[0059] The term "and / or" in this article only describes an association relationship and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" in this article means any one of multiple types or any combination of at least two of multiple types. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set composed of A, B, and C.

[0060] In the description of this specification, the terms "include", "comprise", "have", "contain", etc. are all open terms, that is, they are intended to include but not limited to. The descriptions referring to terms such as "an embodiment", "a specific embodiment", "some embodiments", "for example", etc. mean that the specific features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. The step sequences involved in each embodiment are used to schematically illustrate the implementation of this application, and the step sequences are not limited and can be adjusted appropriately as needed.

[0061] Based on the problems of the prior art, the embodiments of the present invention propose a design scheme of a multi-channel state machine based on RAM, which saves the state values in RAM; when there is an input signal, according to the input signal and its channel number, the state value of the corresponding channel is read, the state jump and output settings are completed, and then the state is written back to RAM for storage; then wait for the next input signal. For the situation where a large number of channels process data with the same state jump, this design scheme can greatly save the number of registers and improve the resource utilization rate of the system.

[0062] The application scenarios of multi-channels are numerous. For example, the maintenance of voice communication links, the maintenance of TCP (Transmission Control Protocol) connection status, the pointer synchronization of VC (Virtual Container) channels in an SDH (Synchronous Digital Hierarchy) network, and so on. The common feature of these application scenarios is that there are a large number of channels, the state changes infrequently, and the state transitions can wait within a relatively short time range. Such application scenarios can all use the RAM-based multi-channel state machine design solution proposed in the embodiments of the present invention.

[0063] Figure 1 As shown in the structural block diagram of a multi-channel state machine provided in the embodiments of the present invention, Figure 1 the multi-channel state machine may include: an input processing module, a RAM module, a state transition module, and an output processing module;

[0064] The input processing module is configured to obtain the input signal sent by the channel; buffer the input signal into the input queue; the input signal is used to represent whether a pending event occurs in the channel.

[0065] The RAM module is configured to receive and save the state value and the intermediate register variable of the channel.

[0066] The state transition module is configured to read the input signal from the input queue; determine the channel number and the first intermediate register variable value of the channel where the pending event is located according to the input signal; read the first state value and the second intermediate register variable value of the channel where the pending event is located from the RAM module according to the channel number; perform a state transition on the channel where the pending event is located according to the logical information of the pending event, and change the first state value to the second state value; assign the intermediate register variable of the channel where the pending event is located to the third intermediate register variable value according to the logical information of the pending event, the first intermediate register variable value, and the second intermediate register variable value of the channel where the pending event is located; write the second state value and the third intermediate register variable value to the channel where the pending event is located in the RAM module; buffer the channel number, the second state value, and the third intermediate register variable value of the channel where the pending event is located into the output queue.

[0067] The output processing module is configured to obtain the channel number, the second state value, and the third intermediate register variable value of the channel where the pending event is located from the output queue; determine the output signal and output it according to the channel number, the second state value, and the third intermediate register variable value of the channel where the pending event is located.

[0068] The multi-channel state machine provided by the embodiments of the present invention can avoid the necessity of using a large number of registers in application scenarios where a large number of channels simultaneously process data, greatly saving the number of registers and improving the resource utilization rate of the system.

[0069] In one embodiment, the multi-channel state machine as a whole can include four parts:

[0070] 1) Input processing module: Processes the input signal, processes the input signal into a standard form, and caches the processed standard form into the input queue.

[0071] 2) RAM module: Used to store the state values and intermediate register variables of each different channel, and can perform read and write access according to the channel number to read or write the state values and intermediate register variables of a certain channel.

[0072] 3) State jump module: According to the standard input in the input queue, reads the state values and intermediate register variables of the corresponding channel, performs a state jump, and writes the new state values and intermediate register variables back to the RAM module after the jump; at the same time, writes the state values and related input values to the output queue.

[0073] 4) Output processing module: Reads the state and related output values of a certain channel from the output queue to determine the output value of the channel.

[0074] The following will introduce each module in detail:

[0075] The input processing module generally processes the input signal into two formats. In this embodiment, the input signal can include a pulse signal. The input processing module is further configured to: predict the occurrence times of the event to be processed at the current moment according to the occurrence of the historical event to be processed; if the occurrence times are greater than a preset threshold, perform a first preset format processing on the pulse signal; if the occurrence times are less than the preset threshold, perform a second preset format processing on the pulse signal; and cache the pulse signal after format processing into the input queue.

[0076] In this embodiment, the first preset format processing includes: naming the pulse signal according to the channel number corresponding to the pulse signal; if a pulse appears in a pulse signal at a certain moment, it indicates that at this moment, an event to be processed has occurred in the channel corresponding to the channel number included in the name of the pulse signal; the second preset format processing includes: uniformly naming the pulse signals corresponding to different channels; if a pulse appears in a pulse signal at a certain moment, it indicates that at this moment, an event to be processed has occurred in the channel corresponding to the channel number of the pulse signal.

[0077] To adapt to the situation where events change too frequently, in one embodiment, the input signals for multi-channel processing are in two forms: 1. One-hot encoding is adopted, that is, there are as many input signals as there are channels; 2. A shared signal is used, and the channel number is used to indicate which channel the current signal value belongs to.

[0078] Assume that the total number of channels is N. The first form uses a total of N signals S1, S2, ……, SN as inputs. The events to be processed are usually expressed by changes in signals, such as rising edges, falling edges, or pulse signals, etc. For example, taking a pulse signal to express an event, if a pulse appears on S2, it means that an event to be processed has occurred in the channel corresponding to channel number 2.

[0079] The second form uses a shared signal S as the input, and uses the channel number C (taking values from 1 to N) to indicate which channel the current signal value belongs to. If a pulse appears on S, and the value of the channel number C at this moment is 2, it means that an event to be processed has occurred in channel 2.

[0080] The first form can represent the situation where events occur simultaneously in multiple channels. The second form is used for the situation where events do not occur simultaneously in multiple channels. When the event changes are not too frequent, that is, when it is predicted according to the occurrence of historical events to be processed that the number of events to be processed at the current moment is less than a preset threshold, the first form can be converted into the second form. The state jump module takes the second form as the standard input, and the input processing module is also responsible for this conversion.

[0081] In one embodiment, the input processing module can also be used to: if the occurrence times are greater than the preset threshold and the input processing module is in an idle state, select one input signal from the input signals corresponding to all the events to be processed for processing, and cache the other input signals; the other input signals are: the other input signals except the selected input signal among the input signals corresponding to all the events to be processed that occur; if the occurrence times are greater than the preset threshold and the input processing module is not in an idle state, cache the input signals corresponding to all the events to be processed that occur.

[0082] When the input is one-hot encoding, that is, the first form, multiple channels need to be processed when events occur simultaneously during conversion. Since event changes do not occur frequently, a cache can be made for the events to be processed for each channel. If the current input processing module is idle, the event to be processed for this channel can be directly processed without caching; if the current input processing module is processing the events to be processed for other channels, the event to be processed for this channel will be stored in the cache and processed when it becomes idle. After processing, the input events and related data are all written into the input queue.

[0083] In addition to transforming the form of the input signal, the input processing module is also responsible for the interactive processing of the input signal. For example, if the input signal comes from the bus, a response to the bus is required; if the input signal comes from the queue, it needs to be read from the queue. If the input signal does not require a response, the processing is the simplest, as long as the signal is correctly received to ensure that no events are lost.

[0084] Between the input processing module and the state jump module, the input queue is used as the interface. Each element stored in the input queue represents the occurrence of an event, and the data in the element includes the channel number and related data.

[0085] In one embodiment, the input signal further includes a first data valid signal; the first data valid signal indicates whether other data in the input signal except the data valid signal is valid data. In the design of the input processing module, a 1-bit data valid signal valid should also be input, and the pulse of the data valid signal indicates that this cycle is valid data.

[0086] The RAM module is responsible for caching the current state value and related intermediate register variables. The RAM module provides read and write interfaces, and the state value and intermediate variable value can be accessed through the channel number. The channel number is the input address of the RAM module, and the state value and intermediate variable value are the data written or read out by the RAM module. In the design of the RAM module, factors such as storage capacity and data access width mainly need to be considered.

[0087] In one embodiment, the read and write width of the RAM module is determined by the size of a single state value and the size of a single intermediate register variable value; the storage space size of the RAM module is determined by the number of channels and the read and write width of the RAM module.

[0088] The RAM module uses random access memory as the core storage unit and has storage capabilities. According to the number of channels and the data width to be saved, the size of the required storage space can be determined. For example, if the number of channels is 1024, the number of state bits to be stored for each channel is 16 bits, and the intermediate variable is 48 bits, then the required storage space size is: 1024×(16 + 48) = 64 Kbits = 8 Kbytes.

[0089] In addition to the storage space, the read and write access width of the data also needs to be considered. According to different internal designs, the storage unit usually has a certain fixed data read access width, such as 32 bits, 64 bits, etc. When the number of bits of the state and intermediate variables is less than the data width, each access to the RAM module can be completed within one clock cycle; when it is greater than the data width, multiple cycles are required to complete. That is to say, the larger the data width of the storage unit, the shorter the access time of the RAM module, but the greater the implementation cost. The read and write access width should be selected according to the actual application.

[0090] The state transition module is the core part of the entire design. The input processing module writes the event and the channel number together into the input queue.

[0091] In one embodiment, the state transition module is specifically configured to read the input signal from the input queue when it is determined that the input queue is not empty and the state transition module is in an idle state. If the input queue is not empty, it indicates that there is an event in the queue, and at this time, the state transition module is also in an idle state, then the first event at the head of the input queue can be processed.

[0092] In one embodiment, when the processing conditions are met, the state transition module reads the input event from the input queue. According to the channel number associated with the input event, it can be known that an event has occurred on this channel. The state transition module reads the state value and the intermediate variable value in the RAM module according to the channel number. The state value is used to restore the current state of the channel, and the intermediate variable value is used to restore the intermediate variable of the channel. As described in the content of the RAM module above, due to the different RAM access widths, it may take multiple cycles to complete the reading.

[0093] After the reading is completed, the state transition module performs a state transition according to the current input event. For example, for communication link maintenance, when currently in the data transmission state, if an event of link release is received, it should transition from the data transmission state to the connection release state. After the transition is completed, the new state value and the intermediate variable value should be written back to the RAM. Similarly, the write-back process may also take multiple cycles.

[0094] Finally, the state transition module must write the new state, the input value used to determine the output signal, the intermediate variable value, and the channel number to the output queue. These values determine the output signal of this channel.

[0095] The output processing module receives the state value, the input value, the intermediate variable value, and the channel number and other information in the output queue, and determines the value of the output signal according to the specific requirements of the service. Similar to the input processing module, its output usually also has two forms: one-hot encoding and common signal. After the output processing module completes the calculation of the output signal value, it should also select one of the forms for output according to the needs of the subsequent module. Since the output queue organizes data in the second form, if the subsequent module needs the second form, it can be directly output; if the subsequent module needs the first form, it should be converted, and one-hot decoding should be completed according to the channel number information to output events for each signal line of multiple channels.

[0096] In one embodiment, the output processing module is further configured to output a second data valid signal; the second data valid signal indicates whether the output signal is valid data.

[0097] In addition, the output processing module is also responsible for the interactive processing of output signals. For example, when outputting to the self-bus, it is necessary to be responsible for responding to the bus; when outputting to a column, it is necessary to process the write timing of the queue, etc.

[0098] Taking the pointer synchronization of VC channels in the SDH network as an example, the design method will be further described below. In the SDH network, data of multiple VC channels is transmitted in a time-division multiplexing manner. For example, in an SDH channel with a STM-64 rate, its total rate is about 10 Gbps, and it may transmit 64 VC-4 channels with a rate of 155 Mbps each. Each VC-4 channel needs to independently judge its pointer synchronization state, and the judgment method is based on the change of the pointer value. Usually, if the pointers of three consecutive frames are the same, it is considered to enter the pointer synchronization state; if the pointers of three consecutive frames are abnormal in the synchronization state, it is considered to enter the out-of-sync state.

[0099] Figure 2 It is a schematic diagram of the logical information of an event to be processed provided in the embodiment of the present invention. As Figure 2 shown, if the multi-channel state machine of the embodiment of the present invention is adopted, it is in the out-of-sync state of NOT_SYNC after reset, enters the SYNC_1 state after receiving 1 pointer, enters the SYNC_2 state when the pointers of two consecutive frames are equal, enters the SYNC synchronization state when the pointer of the third frame is equal again, and outputs a synchronization success event; if the pointer is abnormal, it retreats from SYNC to the SYNC_2 state, retreats to the SYNC_1 state again if it is abnormal again, and retreats to the NOT_SYNC state for the third time, outputting an out-of-sync event.

[0100] The design of the RAM module needs to first calculate the storage space and read / write width of the RAM module. Assuming that the number of channels N = 64, the values to be stored in the RAM include the status value and the pointer value. The status value state uses one-hot encoding and requires 4 bits. The pointer value pointer of the VC channel is generally 10 bits. Then a total of 14 bits are required. The read / write width of the RAM can be designed to be 16 bits. The total storage space of the required RAM is: 64 x 16 bits = 1024 bits.

[0101] In the design of the input processing module, assuming that the input data is in the form of a common signal, the design of the input module is relatively simple in this case. The number of channels N = 64, then the input signal must include the channel coding channel, which should be 6 bits; at the same time, the pointer value of the VC channel, the 10-bit pointer value pointer, and the 1-bit data valid signal valid should also be input. The pulse of the data valid signal indicates that this cycle is valid data. The input module simply processes these signals and converts them into write transactions of the input queue, and then the input events can be written into the input queue.

[0102] The state transition module reads the pointer value and the channel value from the input queue, and then uses the channel value as the address to read the current state value state and the pointer value of the previous frame (assumed to be pointer_former) of this channel from the RAM module. Then, it performs state transition and variable assignment according to the input, the current state value, and the intermediate variables. The specific transition process is as follows:

[0103] 1) Determine whether the current pointer pointer is equal to the pointer pointer_former of the previous frame;

[0104] 2) Taking whether the pointers are equal as a condition, according to the state transition diagram and the current state value state, perform a transition to obtain the next state value next_state:

[0105] 3) Assign the current state value state to next_state to obtain a new state.

[0106] 4) Assign the previous pointer pointer_former to pointer to obtain a new pointer value.

[0107] After obtaining the new state value state and the intermediate variable value pointer_former value, write them back to the RAM module.

[0108] Finally, if the state value state is in the NOT_SYNC or SYNC state, output an event to the output queue. The signals written to the output queue include the channel number channel and the event information event. The channel number channel is still 6 bits, and the event information needs to indicate synchronization or desynchronization, and only 1 bit is used.

[0109] The state transition module writes the 6-bit channel number channel and the 1-bit event information event to the output processing module. The output processing module should read out this information and be responsible for output. If the output data is also in the form of a shared signal, then read out the information in the output queue and handle the interaction of the output signal. For example, it may be necessary to generate a valid data valid signal on the output side, and the pulse of valid indicates that the output data is valid.

[0110] The embodiment of the present invention also proposes a signal processing method based on the above multi-channel state machine, and its principle is similar to that of the above multi-channel state machine, which will not be elaborated here.

[0111] Figure 3 It is a flowchart of a signal processing method based on a multi-channel state machine provided in the embodiment of the present invention. As Figure 3 shown, the method may include:

[0112] Step 301: Obtain the input signal sent by the channel, the status value of the channel, and the intermediate register variable; the input signal is used to indicate whether a to-be-processed event occurs in the channel.

[0113] Step 302: Determine the channel number and the first intermediate register variable value of the channel where the to-be-processed event is located according to the input signal.

[0114] Step 303: Read the first status value and the second intermediate register variable value of the channel where the to-be-processed event is located according to the channel number.

[0115] Step 304: Perform a status jump on the channel where the to-be-processed event is located according to the logical information of the to-be-processed event, and jump the first status value to the second status value.

[0116] Step 305: Assign the intermediate register variable of the channel where the to-be-processed event is located to the third intermediate register variable value according to the logical information of the to-be-processed event, the first intermediate register variable value, and the second intermediate register variable value of the channel where the to-be-processed event is located.

[0117] Step 306: Write the second status value and the third intermediate register variable value to the channel where the to-be-processed event is located; cache the channel number, the second status value, and the third intermediate register variable value of the channel where the to-be-processed event is located into the output queue.

[0118] Step 307: Determine the output signal according to the channel number, the second status value, and the third intermediate register variable value of the channel where the to-be-processed event is located obtained from the output queue, and then output it.

[0119] In one embodiment, the input signal includes a pulse signal.

[0120] The signal processing method based on the multi-channel state machine further includes:

[0121] Predict the occurrence times of the to-be-processed event at the current moment according to the occurrence situation of the historical to-be-processed events.

[0122] If the occurrence times are greater than the preset threshold, perform a first preset format processing on the pulse signal.

[0123] If the occurrence times are less than the preset threshold, perform a second preset format processing on the pulse signal.

[0124] In one embodiment, the first preset format processing includes: naming the pulse signal according to the channel number corresponding to the pulse signal; if a pulse appears in a pulse signal at a certain moment, it indicates that a to-be-processed event occurs in the channel corresponding to the channel number included in the name of the pulse signal at that moment.

[0125] The second preset format processing includes: uniformly naming the pulse signals corresponding to different channels; if a pulse appears in a pulse signal at a certain moment, it indicates that a to-be-processed event has occurred in the channel corresponding to the channel number of the pulse signal at that moment.

[0126] In one embodiment, the signal processing method based on the multi-channel state machine further includes:

[0127] If the occurrence times are greater than a preset threshold and the input processing module is in an idle state, select one input signal from the input signals corresponding to all the to-be-processed events that occur for processing, and cache the other input signals; the other input signals are: the other input signals except the selected input signal among the input signals corresponding to all the to-be-processed events that occur.

[0128] If the occurrence times are greater than a preset threshold and the input processing module is not in an idle state, cache the input signals corresponding to all the to-be-processed events that occur.

[0129] In one embodiment, the input signal further includes a first data valid signal; the first data valid signal indicates whether other data except the data valid signal in the input signal is valid data.

[0130] The signal processing method based on the multi-channel state machine further includes:

[0131] Output a second data valid signal; the second data valid signal indicates whether the output signal is valid data.

[0132] The embodiments of the present invention can greatly save the number of registers and improve resource utilization through the above steps, and are applicable to multi-channel application scenarios such as the maintenance of voice communication links, the maintenance of TCP connection status, and the pointer synchronization of VC channels in the SDH network.

[0133] The embodiments of the present invention also propose a signal processing device based on the multi-channel state machine, the principle of which is similar to the signal processing method based on the multi-channel state machine, and will not be elaborated here.

[0134] Figure 4 As shown in the schematic diagram of a signal processing device based on the multi-channel state machine provided in the embodiments of the present invention, Figure 4 As shown in the figure, the signal processing device based on the multi-channel state machine may include:

[0135] An acquisition module 401, configured to acquire an input signal sent by a channel, a status value of the channel, and an intermediate register variable; the input signal is used to indicate whether a to-be-processed event occurs in the channel.

[0136] A determination module 402, configured to determine, according to the input signal, the channel number and the value of the first intermediate register variable of the channel where the to-be-processed event is located.

[0137] A reading module 403, configured to read a first status value and a second intermediate register variable value of a channel where an event to be processed is located according to a channel number;

[0138] A second status value determination module 404, configured to perform a status jump on the channel where the event to be processed is located according to the logical information of the event to be processed, and jump the first status value to a second status value;

[0139] An intermediate register variable assignment module 405, configured to assign the intermediate register variable of the channel where the event to be processed is located to a third intermediate register variable value according to the logical information of the event to be processed, the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located;

[0140] A writing module 406, configured to write the second status value and the third intermediate register variable value into the channel where the event to be processed is located; cache the channel number, the second status value and the third intermediate register variable value of the channel where the event to be processed is located into an output queue;

[0141] An output module 407, configured to determine an output signal and output it according to the channel number, the second status value and the third intermediate register variable value of the channel where the event to be processed is located obtained from the output queue.

[0142] In one embodiment, the input signal includes a pulse signal;

[0143] The signal processing device based on a multi-channel state machine further includes: a format processing module, configured to:

[0144] Predict the occurrence times of the event to be processed at the current moment according to the occurrence situation of historical events to be processed;

[0145] If the occurrence times are greater than a preset threshold, perform a first preset format processing on the pulse signal;

[0146] If the occurrence times are less than the preset threshold, perform a second preset format processing on the pulse signal.

[0147] In one embodiment, the first preset format processing includes: naming the pulse signal according to the channel number corresponding to the pulse signal; if a pulse appears in a pulse signal at a moment, it indicates that at the moment, an event to be processed has occurred in the channel corresponding to the channel number included in the name of the pulse signal;

[0148] The second preset format processing includes: uniformly naming the pulse signals corresponding to different channels; if a pulse appears in a pulse signal at a moment, it indicates that at the moment, an event to be processed has occurred in the channel corresponding to the channel number of the pulse signal.

[0149] In one embodiment, the signal processing device based on the multi-channel state machine further includes: a buffer module, configured to:

[0150] If the occurrence times are greater than a preset threshold and the input processing module is in an idle state, select one input signal from all the input signals corresponding to the to-be-processed events that occur for processing, and buffer the other input signals; the other input signals are: the other input signals except the selected input signal among all the input signals corresponding to the to-be-processed events that occur.

[0151] If the occurrence times are greater than a preset threshold and the input processing module is not in an idle state, buffer all the input signals corresponding to the to-be-processed events that occur.

[0152] In one embodiment, the input signal further includes a first data valid signal; the first data valid signal indicates whether other data except the data valid signal in the input signal is valid data.

[0153] The signal processing device based on the multi-channel state machine further includes: a second data valid signal output module, configured to:

[0154] Output a second data valid signal; the second data valid signal indicates whether the output signal is valid data.

[0155] Compared with the technical solution of processing data by a large number of channels simultaneously in the prior art, the embodiment of the present invention includes an input processing module, a RAM module, a state jump module, and an output processing module; the input processing module is used to obtain an input signal sent by a channel; buffer the input signal into an input queue; the input signal is used to represent whether a to-be-processed event occurs in the channel; the RAM module is used to receive and save the state value and intermediate register variables of the channel; the state jump module is used to read the input signal from the input queue; determine the channel number and the value of the first intermediate register variable of the channel where the to-be-processed event is located according to the input signal; read the first state value and the value of the second intermediate register variable of the channel where the to-be-processed event is located from the RAM module according to the channel number; perform a state jump on the channel where the to-be-processed event is located according to the logical information of the to-be-processed event, and jump the first state value to the second state value; assign the value of the intermediate register variable of the channel where the to-be-processed event is located to the value of the third intermediate register variable according to the logical information of the to-be-processed event, the value of the first intermediate register variable, and the value of the second intermediate register variable of the channel where the to-be-processed event is located; write the second state value and the value of the third intermediate register variable to the channel where the to-be-processed event is located in the RAM module; buffer the channel number, the second state value, and the value of the third intermediate register variable of the channel where the to-be-processed event is located into an output queue; the output processing module is used to obtain the channel number, the second state value, and the value of the third intermediate register variable of the channel where the to-be-processed event is located from the output queue; determine and output an output signal according to the channel number, the second state value, and the value of the third intermediate register variable of the channel where the to-be-processed event is located, which can save the number of registers and improve resource utilization rate.

[0156] A design scheme of a multi-channel state machine based on RAM proposed by the embodiment of the present invention saves the state value in the RAM; when there is an input signal, according to the input signal and its channel number, the state value of the corresponding channel is read, the state jump and output setting are completed, and then the state is written back to the RAM for storage; then wait for the next input signal. For the situation where a large number of channels process data with the same state jump, this method can greatly save the number of registers and improve the resource utilization rate of the system. There are many application scenarios for multi-channels, such as the maintenance of voice communication links, the maintenance of TCP connection states, the pointer synchronization of VC channels in the SDH network, etc. The common feature of these application scenarios is that the number of channels is large, the state changes infrequently, and the state jump can wait within a relatively small time range. Such application scenarios can all use the design scheme of the multi-channel state machine based on RAM proposed by the embodiment of the present invention.

[0157] The embodiment of the present invention also provides a computer device, Figure 5Schematic diagram of a computer device in an embodiment of the present invention. The computer device 500 includes a memory 510, a processor 520, and a computer program 530 stored on the memory 510 and executable on the processor 520. When the processor 520 executes the computer program 530, the signal processing method based on the multi-channel state machine described above is implemented.

[0158] An embodiment of the present invention also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the signal processing method based on the multi-channel state machine described above is implemented.

[0159] An embodiment of the present invention also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the signal processing method based on the multi-channel state machine described above is implemented.

[0160] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0161] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one or more of the processes or multiple processes and / or blocks Figure 1 one or more of the blocks or multiple blocks.

[0162] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in Figure 1 one or more of the processes or multiple processes and / or blocks Figure 1 one or more of the blocks or multiple blocks.

[0163] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions for implementing the steps of the process Figure 1 in one process or a plurality of processes and / or blocks Figure 1 or steps for implementing the functions specified in one block or a plurality of blocks.

[0164] In the above specific embodiments, the objectives, technical solutions and beneficial effects of the present invention are further described in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-channel state machine, characterized in that: include: Input processing module, random access memory RAM module, state jump module and output processing module; Input processing module, used to obtain input signals sent by the channel; Buffering an input signal in an input queue; the input signal is used to indicate whether a to-be-processed event occurs in the channel; RAM module, used to receive and save channel status values ​​and intermediate register variables; A state jump module is used to read an input signal from an input queue; determine the channel number and the first intermediate register variable value of the channel where the event to be processed is located according to the input signal; read the first state value and the second intermediate register variable value of the channel where the event to be processed is located from a RAM module according to the channel number; perform a state jump on the channel where the event to be processed is located according to the logic information of the event to be processed, and jump the first state value to the second state value; assign the intermediate register variable of the channel where the event to be processed is located to the third intermediate register variable value according to the logic information of the event to be processed and the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located; write the second state value and the third intermediate register variable value to the channel where the event to be processed is located in the RAM module; cache the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located in an output queue; The output processing module is used to obtain the channel number, second state value and third intermediate register variable value of the channel where the event to be processed is located from the output queue; according to the channel number, second state value and third intermediate register variable value of the channel where the event to be processed is located, determine the output signal and then output it.

2. The multi-channel state machine according to claim 1, characterized in that: The input signal comprises a pulse signal; The input processing module is further used to: predict the number of occurrences of the pending events at the current moment according to the occurrence of the pending events in history; If the number of occurrences is greater than a preset threshold, the pulse signal is processed in a first preset format; If the occurrence number is less than a preset threshold, the pulse signal is processed in a second preset format; The pulse signal after format processing is cached in the input queue.

3. The multi-channel state machine according to claim 2, characterized in that: The first preset format processing includes: naming the pulse signal according to the channel number corresponding to the pulse signal; if a pulse signal has a pulse at a moment, it indicates that at the moment, an event to be processed has occurred in the channel corresponding to the channel number contained in the name of the pulse signal; The second preset format processing includes: uniformly naming the pulse signals corresponding to different channels; if a pulse signal has a pulse at a moment, it indicates that at the moment, an event to be processed has occurred in the channel corresponding to the channel number corresponding to the pulse signal.

4. The multi-channel state machine according to claim 2, characterized in that: The input processing module is further configured to: if the number of occurrences is greater than a preset threshold and the input processing module is in an idle state, select an input signal from input signals corresponding to all the events to be processed to process, and cache other input signals; The other input signals are: other input signals except the selected input signal among the input signals corresponding to all the events to be processed that have occurred; If the number of occurrences is greater than a preset threshold and the input processing module is not in an idle state, input signals corresponding to all the events to be processed that have occurred are cached.

5. The multi-channel state machine according to claim 1, characterized in that: The read / write width of the RAM module is determined by the size of a single state value and the size of a single intermediate register variable value; the storage space size of the RAM module is determined by the number of channels and the read / write width of the RAM module.

6. A signal processing method based on the multi-channel state machine according to any one of claims 1 to 5, characterized in that: include: Obtaining an input signal sent by a channel, a state value of the channel, and an intermediate register variable; the input signal is used to indicate whether an event to be processed occurs in the channel; Determine, according to the input signal, the channel number and the first intermediate register variable value of the channel where the event to be processed is located; Read the first state value and the second intermediate register variable value of the channel where the event to be processed is located according to the channel number; According to the logic information of the event to be processed, the state of the channel where the event to be processed is located is jumped, and the first state value is jumped to the second state value; According to the logic information of the event to be processed, and the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located, assigning the intermediate register variable of the channel where the event to be processed is located to the third intermediate register variable value; Write the second state value and the third intermediate register variable value to the channel where the event to be processed is located; cache the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located into the output queue; According to the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located obtained from the output queue, the output signal is determined and then output.

7. A signal processing device based on the multi-channel state machine according to any one of claims 1 to 5, characterized in that: include: An acquisition module is used to acquire an input signal sent by a channel, a state value of the channel, and an intermediate register variable; the input signal is used to indicate whether an event to be processed occurs in the channel; A determination module, used to determine, according to an input signal, the channel number and the first intermediate register variable value of the channel where the event to be processed is located; A reading module, used for reading, according to the channel number, the first state value and the second intermediate register variable value of the channel where the event to be processed is located; A second state value determination module, used for performing a state jump on the channel where the event to be processed is located according to the logic information of the event to be processed, and jumping the first state value to the second state value; An intermediate register variable assignment module, used for assigning a third intermediate register variable value to the intermediate register variable of the channel where the event to be processed is located according to the logic information of the event to be processed and the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located; A writing module is used to write the second state value and the third intermediate register variable value to the channel where the event to be processed is located; and cache the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located into an output queue; The output module is used to determine the output signal and then output it according to the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located obtained from the output queue.

8. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, a signal processing method based on a multi-channel state machine is implemented, the method comprising: Obtaining an input signal sent by a channel, a state value of the channel, and an intermediate register variable; the input signal is used to indicate whether an event to be processed occurs in the channel; Determine, according to the input signal, the channel number and the first intermediate register variable value of the channel where the event to be processed is located; Read the first state value and the second intermediate register variable value of the channel where the event to be processed is located according to the channel number; According to the logic information of the event to be processed, the state of the channel where the event to be processed is located is jumped, and the first state value is jumped to the second state value; According to the logic information of the event to be processed, and the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located, assigning the intermediate register variable of the channel where the event to be processed is located to the third intermediate register variable value; Write the second state value and the third intermediate register variable value to the channel where the event to be processed is located; cache the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located into the output queue; According to the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located obtained from the output queue, the output signal is determined and then output.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, a signal processing method based on a multi-channel state machine is implemented, the method comprising: Obtaining an input signal sent by a channel, a state value of the channel, and an intermediate register variable; the input signal is used to indicate whether an event to be processed occurs in the channel; Determine, according to the input signal, the channel number and the first intermediate register variable value of the channel where the event to be processed is located; Read the first state value and the second intermediate register variable value of the channel where the event to be processed is located according to the channel number; According to the logic information of the event to be processed, the state of the channel where the event to be processed is located is jumped, and the first state value is jumped to the second state value; According to the logic information of the event to be processed, and the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located, assigning the intermediate register variable of the channel where the event to be processed is located to the third intermediate register variable value; Write the second state value and the third intermediate register variable value to the channel where the event to be processed is located; cache the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located into the output queue; According to the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located obtained from the output queue, the output signal is determined and then output.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, a signal processing method based on a multi-channel state machine is implemented, the method comprising: Obtaining an input signal sent by a channel, a state value of the channel, and an intermediate register variable; the input signal is used to indicate whether an event to be processed occurs in the channel; Determine, according to the input signal, the channel number and the first intermediate register variable value of the channel where the event to be processed is located; Read the first state value and the second intermediate register variable value of the channel where the event to be processed is located according to the channel number; According to the logic information of the event to be processed, the state of the channel where the event to be processed is located is jumped, and the first state value is jumped to the second state value; According to the logic information of the event to be processed, and the first intermediate register variable value and the second intermediate register variable value of the channel where the event to be processed is located, assigning the intermediate register variable of the channel where the event to be processed is located to the third intermediate register variable value; Write the second state value and the third intermediate register variable value to the channel where the event to be processed is located; cache the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located into the output queue; According to the channel number, the second state value and the third intermediate register variable value of the channel where the event to be processed is located obtained from the output queue, the output signal is determined and then output.

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