A physical design method, device, server and storage medium

Abstract

The present application provides a physical design method, device, server and storage medium, which are applied to the field of computer technology. After merging the netlists of the first module and the second module to generate the netlist of the general module, the method performs physical design based on the netlist of the general module, and splits the physical design of the general module into a first module database and a second module database. Finally, physical verification and timing verification are performed on the first module database and the second module database respectively. Compared with the physical design method in the prior art that requires physical design and verification of the first module and the second module respectively, the method reduces one physical design process by merging the first module and the second module into a general module and performing physical design on the general module, and can also simplify the subsequent physical verification and timing verification processes, which helps to improve the design efficiency of integrated circuits.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a physical design method, device, server, and storage medium. Background Art

[0002] As integrated circuit design complexity continues to increase, hierarchical design has become an important means of improving design efficiency. Traditional hierarchical design divides the IC functionality into multiple independent functional modules, flattens each module, and finally assembles them at the top level. This approach has the advantage of supporting the parallel development of multiple modules, significantly shortening the overall design cycle.

[0003] However, existing technologies have significant limitations in practical applications. When the logical functions of functional modules are the same but the physical layout requirements are different, such as the physical layout direction cannot be flipped or the logical encapsulation has directional requirements, traditional hierarchical design cannot directly reuse functional modules. Different physical designs need to be performed based on the same logical design to meet the physical layout requirements. Since the physical design needs to be completed multiple times, it not only wastes a lot of manpower and material resources, but also causes the design cycle of integrated circuits to be too long. Summary of the Invention

[0004] In view of this, the present application is dedicated to providing a physical design method, device, server and storage medium to solve the problem that the non-reusable physical design modules lead to a complicated design process and a long integrated circuit design cycle.

[0005] In a first aspect, the present application provides a physical design method, which is applied to a first module and a second module having the same logical function but different physical layouts, wherein the first module includes a main module and a first submodule, and the second module includes the main module and a second submodule, and the first submodule and the second submodule are multiplexed based on the same submodule. The method includes:

[0006] Merging the netlists of the first module and the second module to generate a netlist of a general module, wherein the netlist of the general module includes the netlists of the main module, the first submodule, and the second submodule, as well as the external ports of the first module and the second module;

[0007] Performing physical design based on the netlist of the universal module;

[0008] Splitting the physical design of the universal module into a first module database and a second module database;

[0009] Physical verification and timing verification are performed on the first module database and the second module database respectively.

[0010] In an optional embodiment, merging the netlists of the first module and the second module to generate a netlist of a common module includes:

[0011] copying the netlist of the first module as a basic netlist;

[0012] The external port of the second module and the netlist of the second submodule are added to the basic netlist to obtain the netlist of the general module.

[0013] In an optional implementation, adding an external port connecting the second module and the second submodule and a netlist of the second submodule to the basic netlist includes:

[0014] Extracting a first external port list, where the first external port list includes external ports in the second module that are connected to the main module and the second submodule;

[0015] Add external ports to the basic netlist according to the first external port list, and connect the external ports to the netlist of the main module

[0016] The netlist of the second submodule is added to the basic netlist, and the netlist of the second submodule is connected to the netlist of the main module.

[0017] In an optional implementation, performing physical design based on the netlist of the universal module includes:

[0018] Importing the timing library and physical feature library of the first submodule and the second submodule;

[0019] adding a buffer at a target position in the netlist of the general module to obtain a preprocessed netlist;

[0020] The target position includes a position where the first submodule is connected to the main module, and a position where the second submodule is connected to the main module;

[0021] Perform physical design based on the pre-processed netlist.

[0022] In an optional embodiment, performing physical design based on the preprocessed netlist includes:

[0023] Performing physical layout based on the pre-processed netlist to obtain an initial physical layout of the general module;

[0024] Determining a target area for prohibiting routing in the initial physical layout according to the layout information of the first submodule and the second submodule;

[0025] Wiring is performed in a local area outside the target area in the initial physical layout to complete the physical design of the universal module.

[0026] In an optional embodiment, the physical design of the universal module is split into a first module database and a second module database, including:

[0027] Extracting the netlist of the first module from the netlist of the general module, and extracting the physical library file of the first module from the physical library file of the general module;

[0028] synthesizing the netlist and physical library file of the first module into a first module database;

[0029] Extracting the netlist of the second module from the netlist of the general module, and extracting the physical library file of the second module from the physical library file of the general module;

[0030] The netlist and physical library file of the second module are synthesized into a second module database.

[0031] In an optional implementation, extracting the netlist of the first module from the netlist of the general module includes:

[0032] Removing the second submodule and the external port of the second module from the netlist of the general module to obtain a netlist of the first module;

[0033] Extracting a netlist of the second module from a netlist of the general module includes:

[0034] The first submodule and the external port of the first module are removed from the netlist of the general module to obtain a netlist of the second module.

[0035] In an optional implementation, extracting the physical library file of the first module from the physical library file of the general module includes:

[0036] Deleting the second submodule from the physical library file of the general module according to the physical size and layout coordinates of the second submodule to obtain the physical library file of the first module;

[0037] Extracting the physical library file of the second module from the physical library file of the general module includes:

[0038] According to the physical size and layout coordinates of the first submodule, the first submodule is deleted from the physical library file of the general module to obtain the physical library file of the second module.

[0039] In a second aspect, the present application provides a physical design device, which is applied to a first module and a second module with the same logical function but different physical layouts, wherein the first module includes a main module and a first submodule, and the second module includes the main module and a second submodule, and the first submodule and the second submodule are multiplexed based on the same submodule. The device includes:

[0040] a merging unit, configured to merge the netlists of the first module and the second module to generate a netlist of a common module, wherein the netlist of the common module includes the netlists of the main module, the first submodule, and the second submodule, as well as the external ports of the first module and the second module;

[0041] A design unit, configured to perform physical design based on a netlist of the universal module;

[0042] a splitting unit, configured to split the physical design of the universal module into a first module database and a second module database;

[0043] A verification unit is used to perform physical verification and timing verification on the first module database and the second module database respectively.

[0044] In a third aspect, the present application provides a server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein when the processor executes the computer program, the steps of the physical design method as described in any one of the first aspects of the present application are implemented.

[0045] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the physical design method as described in any one of the first aspects of the present application.

[0046] Based on the above content, the physical design method provided by the present application, after merging the netlists of the first module and the second module to generate the netlist of the general module, performs physical design based on the netlist of the general module, and splits the physical design of the general module into the first module database and the second module database, and finally performs physical verification and timing verification on the first module database and the second module database respectively. Compared with the physical design method in the prior art that requires physical design and verification of the first module and the second module respectively, the present method reduces the physical design process by merging the first module and the second module into a general module and performing physical design on the general module. Accordingly, it can also simplify the subsequent physical verification and timing verification processes, which helps to improve the design efficiency of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 This is a flow chart of a physical design method provided by this application.

[0049] Figure 2 This is a schematic diagram of an integrated circuit module mentioned in this application.

[0050] Figure 3 This is a schematic diagram of a general module provided by this application.

[0051] Figure 4 This is a schematic diagram of another general module provided by this application.

[0052] Figure 5a This is a schematic diagram of the first module after splitting provided in this application.

[0053] Figure 5b This is a schematic diagram of the split second module provided in this application.

[0054] Figure 6 This is a structural block diagram of a physical design device provided by this application.

[0055] Figure 7 This is a structural block diagram of a server provided by this application. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0057] As mentioned above, although the hierarchical design method can achieve multi-module parallel development and significantly shorten the overall design cycle by dividing the integrated circuit functions into multiple independent functional modules and flattening the design of each functional module, when the logical functions of the functional modules in the integrated circuit are the same but the physical layout requirements are different, such as the physical layout direction cannot be flipped or the logical encapsulation has a direction requirement, the traditional hierarchical design cannot directly reuse the functional modules. Different physical designs need to be performed on the same logical design to meet the physical layout requirements. Since the physical design needs to be completed multiple times, it not only wastes a lot of manpower and material resources, but also causes the design cycle of the integrated circuit to be too long.

[0058] To solve the above problems, the present application provides a physical design method, which is applied to the physical design of a first module and a second module with the same logical function but different physical layout. Compared with the physical design method in the prior art that requires physical design and verification of the first module and the second module respectively, the present method reduces the physical design process by merging the first module and the second module into a common module and physically designing the common module. Accordingly, it can also simplify the subsequent physical verification and timing verification processes, which helps to improve the design efficiency of integrated circuits.

[0059] The physical design method provided in this application can be applied to electronic devices, which can be laptops, personal computers (PCs), tablet computers, and other electronic devices that can run the application corresponding to the physical design method provided in this application. These are not listed here one by one. Of course, in some cases, it can also be applied to servers on the network side. Figure 1 As shown, the physical design method provided by this application includes the following steps.

[0060] S100 , merging the netlists of the first module and the second module to generate a netlist of the general module.

[0061] First of all, it should be noted that the physical design method provided in this application can be applied to the physical design of two or more functional modules in an integrated circuit. The first module and the second module mentioned in this application can be any two modules in the integrated circuit that can be physically designed using the physical design method provided in this application. The physical design process of the remaining functional modules can be completed by referring to the physical design method provided in this application.

[0062] See also Figure 2As shown, assume that the integrated circuit includes three first-level modules, labeled A1, M, and Ar. A1 also includes a second-level submodule a0, and Ar also includes a second-level submodule a1. A1 and Ar are physically arranged sequentially and cannot be flipped. That is, the right side of A1 is connected to M, and its left side is connected to other modules in the integrated circuit located to the left of A1 via second-level submodule a0. Correspondingly, the left side of Ar is connected to M, and its right side is connected to other modules in the integrated circuit located to the right of Ar via second-level submodule a1. It should be noted that for ease of presentation, module A1 is considered the first module, and module Ar is considered the second module. The connection between any first-level module and any other first-level module is represented by a rectangular port (i.e., the black rectangle in the figure), and the corresponding pins are defined as external ports. The connection between any first-level module and its own second-level submodule is represented by a circular port (i.e., the black circle in the figure), and the corresponding pins are defined as internal ports.

[0063] In the present application, the first module A1 and the second module Ar have the same logical functions, but due to the limitations of the connection relationship with the module M, that is, the physical layout, the physical layout of the first module A1 and the second module Ar is different. Furthermore, the first module A1 includes a main module (not shown in the figure) and a first sub-module a0, and the second module Ar also includes the main module (not shown in the figure) and a second sub-module a1. The main modules in the first module A1 and the second module Ar are the same and are used to implement their main logical functions. In addition, the first sub-module a0 and the second sub-module a1 are obtained by reusing the same sub-module, that is, the secondary sub-modules are isomorphically reusable. In actual applications, they can be instantiated and deployed in the first module A1 and the second module Ar respectively to configure the corresponding first sub-module a0 and second sub-module a1.

[0064] Based on the above premise, the physical design method provided in this application first merges the netlist of the first module with the netlist of the second module, that is, takes the union of the two, and uses the merged netlist as the netlist of the general module. In order to ensure that the netlist of the general module can cover all functions of the first module and the second module and facilitate the subsequent module separation, the netlist of the general module obtained includes the netlist of the main module, the netlist of the first submodule, and the netlist of the second submodule, as well as the external ports of the first module and the second module.

[0065] Combine Figure 3 As shown, the general module obtained after merging is marked as A. Assuming that the physical width of the first module A1 or the second module Ar is x1, and the physical widths of the first submodule a0 and the second submodule a1 are both x0, the physical width of the general module A obtained after merging is x0+x1. It can be understood that Figure 3The figure is only an example, and the layout operation of the general module has not actually been performed.

[0066] Assume that the netlist of the first module Al is Al.v.gz, and the corresponding netlist of the second module Ar is Ar.v.gz. Based on this, as an optional implementation, first copy the netlist of the first module Al as the base netlist (of course, the netlist of the second module Ar can also be copied as the base netlist). Based on the base netlist, add the external ports of the second module Ar and the netlist of the second sub-module a1 to obtain the netlist of the universal module A. Referring to the above description of the first module Al and the second module Ar, the netlist of the universal module A can be expressed as Avgz.

[0067] Specifically, based on the netlist of the second module Ar, it can be determined that the main module in the second module Ar is connected to the second submodule a1 and serves as the external port of the second module Ar. By counting the corresponding external ports, a first external port list Arr-port.list can be obtained. Furthermore, by counting the internal ports of the main module and the second submodule a1 in the second module Ar, a first internal port list Arl-port.list can be obtained. Accordingly, based on the netlist of the first module Al, it can be determined that the main module in the first module Al is connected to the first submodule a0 and serves as the external port of the first module Al. By counting the corresponding external ports, a second external port list All-port.list can be obtained. Furthermore, by counting the internal ports of the main module and the first submodule a0 in the first module Al, a second internal port list Alr-port.list can be obtained.

[0068] Based on the above statistics, according to the external ports recorded in the first external port list Arr-port.list and the arrangement order of each external port, the corresponding external ports are added to the basic netlist. At the same time, the newly added external ports are connected to the netlist of the main module. For details, please refer to the connection relationship of the external ports between the main module and the second sub-module a1 in the second module Ar.

[0069] Furthermore, the netlist of the second sub-module a1 is added to the basic netlist, that is, the aforementioned reusable sub-module is instantiated to obtain the corresponding second sub-module a1, the netlist of the second sub-module a1 is added to the basic netlist, and the netlist of the second sub-module a1 is connected to the netlist of the main module. For details, please refer to the connection relationship between the internal ports between the main module and the second sub-module a1 in the second module Ar.

[0070] After completing the above-mentioned processing of the netlist and connection relationships, the netlist of the general module A can be obtained.

[0071] S110. Perform physical design based on the netlist of common modules.

[0072] It is understandable that since the general module includes both the first submodule a0 and the second submodule a1, during physical design, it is necessary to import the timing library and physical signature library of the first submodule a0 and the second submodule a1 to perform corresponding verification on the first submodule a0 and the second submodule a1.

[0073] In the physical design process of the related art, after obtaining the netlists of the first module Al and the second module Ar, the physical design of the first module Al and the second module Ar will be performed separately, that is, the physical design process is performed twice. Compared with the prior art, the present application has merged the first module Al and the second module Ar into a common module through the aforementioned steps and obtained the corresponding netlist. Therefore, in the physical design process, only one physical design needs to be performed for the netlist of the common module, reducing the physical design process by one time.

[0074] Furthermore, it can be understood that the ultimate goal of the design is to obtain the first module Al and the second module Ar. Therefore, after completing the corresponding physical design based on the netlist of the general module A, the obtained general module A needs to be split. In order to facilitate the subsequent splitting process, this application provides a preferred implementation method.

[0075] Specifically, a buffer is added to the target position in the netlist of the general module A to obtain a preprocessing netlist, and physical design is performed based on the obtained preprocessing netlist. Combined with the above content, it can be seen that the general module A includes a main module, a first submodule a0 and a second submodule a1. The connection relationship between the modules mainly involves the connection relationship between the main module and the first submodule a0, and the connection relationship between the main module and the second submodule a1. By splitting out the second submodule a1 in the general module A, the first module Al can be obtained. Correspondingly, by splitting out the first submodule a0 in the general module A, the second module Ar can be obtained. Based on this, combined with Figure 4 As shown, the target position mentioned in this embodiment may include the position where the first submodule a0 is connected to the main module Am, that is, the right edge of the first module A1, and the position where the second submodule a1 is connected to the main module Am, that is, the left edge of the second module Ar. Of course, in actual applications, other positions where the submodule is connected to the main module can also be used as the target position. Figure 4 The examples shown are for reference only and are not intended to limit the choice of target location.

[0076] Combine Figure 4As shown, the triangular module represents the buffer. In the actual physical layout process, the logic network directly connected to the ports listed in All-port.list can be extracted from the netlist Al.v.gz of the first module Al, and the buffer can be added as the target location, as shown in Figure 4 As shown, compared with the first module A_1, the view of the universal module A is that a column of buffers is connected to the right side of the first module Al. It should be noted that when placing the buffers, the metal wires connected thereto should be arranged in the order of the metal layers on the right side of the original first module Al. Correspondingly, compared with the second module Ar, the view of the universal module A is that the network where the left port of the second module Ar is located is used as the target position, and a column of buffers is connected thereto. Similar to the deployment process of the first module Al, when placing the buffers, the metal wires connected thereto should be arranged in the order of the metal layers on the left side of the original second module Ar, and finally the addition of two columns of buffers is completed.

[0077] After the above steps, the processing of the pre-processed netlist has been completed. Further, physical layout is performed based on the obtained pre-processed netlist, that is, the physical area of ​​the universal module A is pre-processed to obtain the initial physical layout of the universal module A. Based on this, the target area for prohibiting wiring can be further determined in the initial physical layout based on the layout information of the first submodule a0 and the second submodule a1. Figure 4 As shown, since the physical height dimensions of the first submodule a0 and the second submodule a1 are generally not greater than the physical height dimensions of the modules to which they belong, it is necessary to set corresponding prohibited wiring areas in the initial physical layout during wiring, i.e., the target areas mentioned in this embodiment. Figure 4 The hatched area shown in the figure is the target area for no-routing. Of course, in actual applications, corresponding no-routing areas can also be set in combination with the external dimensions of the submodule and the module to which it belongs, as well as other wiring rules. These are not listed here one by one. Without exceeding the core concept of this application, they also fall within the scope of protection of this application. It can be understood that the purpose of setting the target area for no-routing is to ensure that when the submodule is subsequently separated, the submodule can be separated independently without affecting other logical units.

[0078] After determining the target area where routing is prohibited, routing can be performed in the local area outside the target area in the initial physical layout to complete the physical design of the universal module A.

[0079] S120: Split the physical design of the general module into a first module database and a second module database.

[0080] As previously mentioned, the ultimate goal of the design is to obtain the first module A1 and the second module Ar. After completing the physical design of universal module A, it is necessary to split it based on universal module A to obtain the first module A1 and the second module Ar. In actual physical design processes, the functional modules in the integrated circuit are recorded with corresponding design results using netlists and physical library files. Based on this, the netlist of the first module A1 and the netlist of the second module Ar can be extracted from the netlist of universal module A. Furthermore, the physical library files of the first module A1 and the second module Ar can be extracted from the physical library files of universal module A obtained in S110.

[0081] Specifically, based on the generation process of general module A, it can be seen that since the connection relationship between the main module and the second sub-module a1 was added to general module A in the aforementioned operation, when removing the second sub-module a1, it is first necessary to disconnect the connection between the two, delete the redundant ports, namely the ports in the aforementioned Arr.port.list, and simultaneously remove the netlist of the second sub-module a1 from the general module netlist. It can be understood that since the buffer was added in S110, when executing this step, the corresponding buffer can be directly disconnected, thereby simplifying the process of splitting the sub-module netlist.

[0082] Accordingly, the netlist of the first submodule a0 and its external ports are removed from the netlist of the general module A, thereby obtaining the netlist of the second module Ar. Similar to the process of splitting and obtaining the first module A1, when removing the first submodule a0, the connection between the two modules must be disconnected and the redundant ports, namely those in the aforementioned All.port.list, must be deleted. Since buffers were also added in S110, the corresponding buffers can be simply disconnected during this step.

[0083] In an optional embodiment, after the netlist of the first module is obtained by splitting the netlist of the general module, a logical equivalence check can be performed on the netlist of the first module and the original netlist of the first module to ensure that the logical functions of the first module are not affected. Correspondingly, after the netlist of the second module is obtained by splitting the netlist of the general module, a logical equivalence check can also be performed on the netlist of the second module and the original netlist of the second module.

[0084] Furthermore, the physical library file of the general module A is adjusted, and the physical library file of the second submodule a1 is deleted from the physical library file of the general module A, that is, the physical library file of the first module A1 is obtained. Since the physical library file is used to record the physical size and layout coordinates of the functional module, the second submodule a1 can be deleted from the physical library file of the general module A according to the physical size and layout coordinates of the second submodule a1 recorded in the physical library file, that is, the physical library file of the first module A1 is obtained. Figure 4 As an example, delete the content with a horizontal coordinate greater than x1 in the physical library file of the general module A, and modify the module size recorded in the physical library file from x1+x0 to x1, so as to obtain the physical library file of the first module A1. For example, the physical library file can be stored as A1.def. The physical layout of the first module A1 can be seen in Figure 5a shown.

[0085] Adjust the physical library file of the general module A again, delete the first submodule a0 in the physical library file of the general module A according to the physical size and layout coordinates of the first submodule a0, and then obtain the physical library file of the second module Ar. Figure 4 As shown in the example, delete the content with horizontal coordinate less than x0 in the physical library file of the general module A, and subtract x0 from the horizontal coordinates of all related modules recorded in the physical library file, and then obtain the physical library file of the second module Ar. For example, the physical library file can be stored as Ar.def. The physical layout of the second module Ar can be seen in Figure 5b shown.

[0086] After the aforementioned steps, the netlist and physical library file of the first module A1 are obtained and combined to form the first module database. In an alternative embodiment, the netlist Al.v.gz and physical library file Al.def of the first module A1 can be imported into a place and route tool to combine and obtain the first module database. Similarly, the netlist and physical library file of the second module can be combined to form the second module database using the same method.

[0087] S130 , performing physical verification and timing verification on the first module database and the second module database respectively.

[0088] After the above steps, the first module database and the second module database have been obtained. They need to be further physically verified and timing verified. The physical verification includes at least the design rule check (DRC) and the layout and principle Figure 1Consistency checking (Layout Versus Schematic, LVS), and timing verification at least includes static timing analysis (STA). The specific verification process can be implemented by referring to related technologies and will not be detailed here.

[0089] To sum up, compared with the physical design method in the prior art which requires physical design and verification of the first module and the second module separately, this method merges the first module and the second module into a common module, and obtains the databases of the two modules by physically designing the common module, which can reduce the physical design process once. Accordingly, it can also simplify the subsequent physical verification and timing verification processes, and help improve the design efficiency of integrated circuits.

[0090] It should be noted that the physical design method provided in this application can be applied to the physical design of functional modules within an integrated circuit, and can also be applied to the physical design of molecular systems within an integrated circuit.

[0091] The following describes the physical design device provided by the present invention. The physical design device provided by the present invention is based on the same concept as the physical design method provided in the embodiments of this application. It can execute the physical design method provided in any of the embodiments of this application and has the corresponding functional modules and beneficial effects of executing the physical design method. For technical details not fully described in this embodiment, please refer to the physical design method provided in the embodiments of this application and will not be repeated here.

[0092] The physical design device provided in the present application is applied to a first module and a second module with the same logical function but different physical layout. The first module includes a main module and a first sub-module, and the second module includes a main module and a second sub-module. The first sub-module and the second sub-module are multiplexed based on the same sub-module.

[0093] See also Figure 6 As shown, the physical design device provided by this application includes:

[0094] a merging unit 10, configured to merge the netlists of the first module and the second module to generate a netlist of the general module, wherein the netlist of the general module includes the netlists of the main module, the first submodule, and the second submodule, as well as the external ports of the first module and the second module;

[0095] A design unit 20, configured to perform physical design based on a netlist of a general module;

[0096] A splitting unit 30, configured to split the physical design of the general module into a first module database and a second module database;

[0097] The verification unit 40 is configured to perform physical verification and timing verification on the first module database and the second module database respectively.

[0098] In an optional embodiment, the merging unit 10 is configured to merge the netlists of the first module and the second module to generate a netlist of a common module, specifically including:

[0099] copying the netlist of the first module as a basic netlist;

[0100] The external port of the second module and the netlist of the second submodule are added to the basic netlist to obtain the netlist of the general module.

[0101] In an optional embodiment, the merging unit 10 is configured to add the external port connecting the second module and the second submodule and the netlist of the second submodule to the basic netlist, specifically including:

[0102] Extracting a first external port list, the first external port list including external ports connected to the main module and the second submodule in the second module;

[0103] Add external ports to the basic netlist according to the first external port list and connect the external ports to the netlist of the main module

[0104] Add the netlist of the second submodule to the basic netlist, and connect the netlist of the second submodule to the netlist of the main module.

[0105] Below, reference Figure 7 To describe the server provided by an embodiment of the present invention, the server provided by this embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0106] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 communicate with each other through the communication bus 400; obviously, Figure 7 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are merely optional;

[0107] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0108] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0109] The processor 100 is specifically configured to execute the application program in the memory to implement the steps of the above-mentioned physical design method.

[0110] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive, an SD (Secure Digital Memory Card), or an MMC (Multimedia Card). The computer-readable storage medium stores one or more instructions for implementing the aforementioned steps. When executed by one or more processors, these one or more instructions cause the processors to perform the physical design method described above. For details on the implementation, please refer to the aforementioned description and will not be elaborated upon here.

[0111] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the steps of the physical design method according to various embodiments of the present application described in the above content of this specification.

[0112] The computer program product may be written in any combination of one or more programming languages ​​to implement the program code for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0113] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented through hardware, software, firmware, or a combination of some or all of the three.

[0114] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0115] Flowcharts are used in this disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or following steps do not necessarily need to be performed in exact order. Instead, the various steps may be performed in reverse order or simultaneously. Furthermore, other operations may be added to these processes.

[0116] Those skilled in the art will appreciate that all or part of the steps in the above method can be performed by instructing the relevant hardware using a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Alternatively, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software functional modules. The present disclosure is not limited to any particular combination of hardware and software.

[0117] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or highly formal sense unless expressly defined as such herein.

[0118] The above is an illustration of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the above is an illustration of the present disclosure and should not be considered as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A physical design method, characterized in that: Applied to a first module and a second module with the same logical function but different physical layouts, the first module includes a main module and a first submodule, the second module includes the main module and a second submodule, the main module is used to implement the main logical functions of the first module and the second module, and the first submodule and the second submodule are multiplexed based on the same submodule, the method includes: Merging the netlists of the first module and the second module to generate a netlist of a general module, wherein the netlist of the general module includes the netlists of the main module, the first submodule, and the second submodule, as well as the external ports of the first module and the second module; Performing physical design based on the netlist of the universal module; Splitting the physical design of the universal module into a first module database and a second module database; Physical verification and timing verification are performed on the first module database and the second module database respectively.

2. The method according to claim 1, characterized in that Merging the netlists of the first module and the second module to generate a netlist of a common module includes: copying the netlist of the first module as a basic netlist; The external port of the second module and the netlist of the second submodule are added to the basic netlist to obtain the netlist of the general module.

3. The method according to claim 2, characterized in that Adding the external port connecting the second module and the second submodule and the netlist of the second submodule to the basic netlist includes: Extracting a first external port list, where the first external port list includes external ports in the second module that are connected to the main module and the second submodule; Add external ports to the basic netlist according to the first external port list, and connect the external ports to the netlist of the main module The netlist of the second submodule is added to the basic netlist, and the netlist of the second submodule is connected to the netlist of the main module.

4. The method according to claim 1, wherein Perform physical design based on the netlist of the general module, including: Importing the timing library and physical feature library of the first submodule and the second submodule; adding a buffer at a target position in the netlist of the general module to obtain a preprocessed netlist; The target position includes a position where the first submodule is connected to the main module, and a position where the second submodule is connected to the main module; Perform physical design based on the pre-processed netlist.

5. The method according to claim 4, characterized in that Performing physical design based on the pre-processed netlist includes: Performing physical layout based on the pre-processed netlist to obtain an initial physical layout of the general module; Determining a target area for prohibiting routing in the initial physical layout according to the layout information of the first submodule and the second submodule; Wiring is performed in a local area outside the target area in the initial physical layout to complete the physical design of the universal module.

6. The method according to claim 1, characterized in that Splitting the physical design of the universal module into a first module database and a second module database includes: Extracting the netlist of the first module from the netlist of the general module, and extracting the physical library file of the first module from the physical library file of the general module; synthesizing the netlist and physical library file of the first module into a first module database; Extracting the netlist of the second module from the netlist of the general module, and extracting the physical library file of the second module from the physical library file of the general module; The netlist and physical library file of the second module are synthesized into a second module database.

7. The method according to claim 6, characterized in that Extracting the netlist of the first module from the netlist of the general module includes: Removing the second submodule and the external port of the second module from the netlist of the general module to obtain a netlist of the first module; Extracting a netlist of the second module from a netlist of the general module includes: The first submodule and the external port of the first module are removed from the netlist of the general module to obtain a netlist of the second module.

8. The method according to claim 6, characterized in that Extracting the physical library file of the first module from the physical library file of the general module includes: Deleting the second submodule from the physical library file of the general module according to the physical size and layout coordinates of the second submodule to obtain the physical library file of the first module; Extracting the physical library file of the second module from the physical library file of the general module includes: According to the physical size and layout coordinates of the first submodule, the first submodule is deleted from the physical library file of the general module to obtain the physical library file of the second module.

9. A physical design device, characterized in that Applicable to a first module and a second module with the same logical function but different physical layouts, the first module including a main module and a first submodule, the second module including the main module and a second submodule, the main module being used to implement the main logical functions of the first module and the second module, the first submodule and the second submodule being multiplexed based on the same submodule, the device comprising: a merging unit, configured to merge the netlists of the first module and the second module to generate a netlist of a common module, wherein the netlist of the common module includes the netlists of the main module, the first submodule, and the second submodule, as well as the external ports of the first module and the second module; A design unit, configured to perform physical design based on a netlist of the universal module; a splitting unit, configured to split the physical design of the universal module into a first module database and a second module database; A verification unit is used to perform physical verification and timing verification on the first module database and the second module database respectively.

10. A server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein: When the processor executes the computer program, the steps of the physical design method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the physical design method according to any one of claims 1 to 8 are implemented.

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