Memory and electronic equipment
By stacking the memory array chip and sensing amplification zone in layers to form a three-dimensional memory chip, the challenges of existing memory in storage capacity and sensing amplifier processes are solved, and more efficient storage and simplified manufacturing processes are achieved.
Patent Information
- Application Number
- CN202311747513.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-18
- Publication Date
- 2025-06-20
AI Technical Summary
Existing memory faces many challenges in structural design and manufacturing processes, especially in improving storage capacity and avoiding blur and flawed edges of sensing amplifier metal wires.
By stacking the memory array chip and sensing amplification zone in layers, a three-dimensional memory chip is formed to increase the storage capacity, and by adjusting the layout and connection points of the sensing amplifier, avoiding the use of dual graphics technology and simplifying the process steps.
The memory capacity is improved, avoiding the blurring and defects of metal wire edges in the sensing amplifier, and reducing process complexity and cost.
Smart Images
Figure CN120183449A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor memories, and more particularly to a memory and an electronic device. Background Art
[0002] With the continuous progress of industrial technology, memories are widely used in various electronic devices and electronic products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor storage device in computers.
[0003] However, existing memories still face many challenges in terms of structural design and manufacturing processes. Summary of the Invention
[0004] The present disclosure provides a memory and an electronic device.
[0005] The technical solution of the present disclosure is implemented as follows:
[0006] In a first aspect, an embodiment of the present disclosure provides a memory, including a first chip and a second chip stacked along a third direction;
[0007] The first chip includes N memory array slices arranged along a first direction, and each memory array slice includes a plurality of memory cells arranged in an array. A plurality of memory cells aligned along a second direction are connected to the same word line, and a plurality of memory cells aligned along the first direction are connected to the same bit line; the first direction and the second direction intersect; where N is a positive integer greater than or equal to 2;
[0008] The second chip includes (N - 1) sense amplifier regions arranged along the first direction. Part of the bit lines of the j-th memory array slice and part of the bit lines of the (j + 1)-th memory array slice are both connected to the j-th sense amplifier region; where j is a positive integer less than or equal to (N - 1);
[0009] Each sense amplifier region includes a first sensor array and a second sensor array arranged along the first direction; for the j-th sense amplifier region, the projection of the first sensor array therein along the third direction is located on the j-th memory array slice, and the projection of the second sensor array therein along the third direction is located on the (j + 1)-th memory array slice.
[0010] In some embodiments, for each sense amplifier region, the first sensor array therein includes a plurality of first sense amplifiers arranged in an array, and the second sensor array therein includes a plurality of second sense amplifiers arranged in an array;
[0011] The (4a - 3)-th bit line of the i-th storage array chip and the (4a - 3)-th bit line of the (i + 1)-th storage array chip are each connected to the same second sense amplifier in the i-th sense amplification region; where a is a positive integer; 1 ≤ i ≤ (N - 1), and i is a positive odd number;
[0012] The (4a - 1)-th bit line of the i-th storage array chip and the (4a - 1)-th bit line of the (i + 1)-th storage array chip are each connected to the same first sense amplifier in the i-th sense amplification region.
[0013] In some embodiments, the surface of the i-th storage array chip close to the i-th sense amplification region further includes a plurality of first connection points and a plurality of first complementary connection points. The (4a - 1)-th bit line of the i-th storage array chip is connected to the a-th first connection point, the (4a - 1)-th bit line of the (i + 1)-th storage array chip is connected to the a-th first complementary connection point, and the a-th first connection point and the a-th first complementary connection point are connected to the same first sense amplifier;
[0014] The surface of the (i + 1)-th storage array chip close to the i-th sense amplification region further includes a plurality of second connection points and a plurality of second complementary connection points. The (4a - 3)-th bit line of the i-th storage array chip is connected to the a-th second connection point, the (4a - 3)-th bit line of the (i + 1)-th storage array chip is connected to the a-th second complementary connection point, and the a-th second connection point and the a-th second complementary connection point are connected to the same second sense amplifier.
[0015] In some embodiments, the first connection point is aligned with the first end of the connected first sense amplifier along a third direction, and the first connection point is connected to the first end of the first sense amplifier along the third direction through a wire and / or a bonding structure;
[0016] The first complementary connection point is aligned with the second end of the connected first sense amplifier along the third direction, and the first complementary connection point is connected to the second end of the first sense amplifier along the third direction through a wire and / or a bonding structure.
[0017] In some embodiments, the second connection point is aligned with the first end of the connected second sense amplifier along the third direction, and the second connection point is connected to the first end of the second sense amplifier along the third direction through a wire and / or a bonding structure;
[0018] The second complementary connection point is aligned with the second end of the connected second sense amplifier along the third direction, and the second complementary connection point is connected to the second end of the second sense amplifier along the third direction through a wire and / or a bonding structure.
[0019] In some embodiments, the (4a - 2)-th bit lines of the (i + 1)-th and (i + 2)-th storage array chips are each connected to the same second sense amplifier in the (i + 1)-th sense amplification region;
[0020] The (4a)-th first bit lines of the (i + 1)-th and (i + 2)-th storage array chips are each connected to the same first sense amplifier in the (i + 1)-th sense amplification region.
[0021] In some embodiments, the surface of the (i + 2)-th storage array chip close to the (i + 1)-th sense amplification region further includes a plurality of third connection points and a plurality of third complementary connection points. The (4a - 2)-th bit lines of the (i + 2)-th storage array chip are connected to the a-th third connection point, the (4a - 2)-th bit lines of the (i + 1)-th storage array chip are connected to the a-th third complementary connection point, and the a-th third connection point and the a-th third complementary connection point are connected to the same second sense amplifier;
[0022] The surface of the (i + 1)-th storage array chip close to the (i + 1)-th sense amplification region further includes a plurality of fourth connection points and a plurality of fourth complementary connection points. The (4a)-th bit lines of the (i + 2)-th storage array chip are connected to the a-th fourth connection point, the (4a)-th bit lines of the (i + 1)-th storage array chip are connected to the a-th fourth complementary connection point, and the a-th fourth connection point and the a-th fourth complementary connection point are connected to the same first sense amplifier.
[0023] In some embodiments, the third connection point is aligned with the first end of the connected second sense amplifier along a third direction, and the third connection point is connected to the first end of the second sense amplifier along the third direction through a wire and / or a bonding structure;
[0024] The third complementary connection point is aligned with the second end of the connected second sense amplifier along the third direction, and the third complementary connection point is connected to the second end of the second sense amplifier along the third direction through a wire and / or a bonding structure.
[0025] In some embodiments, the fourth connection point is aligned with the first end of the connected first sense amplifier along a third direction, and the fourth connection point is connected to the first end of the first sense amplifier along the third direction through a wire and / or a bonding structure;
[0026] The fourth complementary connection point is aligned with the second end of the second sense amplifier to which it is connected along a third direction, and the fourth complementary connection point is connected to the second end of the first sense amplifier along the third direction through a wire and / or a bonding structure.
[0027] In some embodiments, each of the memory array chips includes 512 of the bit lines;
[0028] Each of the sensor arrays includes 256 sense amplifiers, and 64 of the sense amplifiers are included in the second direction, and 4 of the sense amplifiers are included in the first direction.
[0029] In some embodiments, the first chip and the second chip are bonded by hybrid bonding.
[0030] In a second aspect, an embodiment of the present disclosure further provides an electronic device, and the electronic device includes a memory as described in any of the above embodiments.
[0031] In the embodiments of the present disclosure, the first chip and the second chip together form a three-dimensional memory chip, that is, the memory array chips are on one chip, and the sense amplification regions are distributed on another chip, improving the storage capacity; at the same time, in the embodiments of the present disclosure, the projection of each sensor array in each sense amplification region along the Z direction will be located on a corresponding memory array chip, rather than on the intermediate region between adjacent memory array chips. It can be understood that the area of each memory array chip is much larger than the area of the intermediate region between adjacent memory array chips, so that the area occupied by a single sense amplifier in the sense amplification region can be larger. Therefore, when manufacturing the sense amplifiers in the memory shown in the embodiments of the present disclosure, it is not necessary to use double patterning technology to accurately manufacture, which can not only avoid problems such as blurring and defects at the edges of the metal lines in the sense amplifiers, improving the yield of the memory, but also save process steps, thereby saving process costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 Schematic diagrams of memories provided for some embodiments;
[0033] Figure 2 Schematic diagram of the memory provided by the embodiment of the present disclosure Figure 1 ;
[0034] Figure 3 Schematic diagram of the memory provided by the embodiment of the present disclosure Figure 2 ;
[0035] Figure 4 Schematic diagram of the memory provided by the embodiment of the present disclosure Figure 3 ;
[0036] Figure 5A top view schematic diagram of a memory provided for some embodiments;
[0037] Figure 6 A top view schematic diagram of a memory provided for an embodiment of the present disclosure;
[0038] Figure 7 A schematic diagram of an electronic device provided for an embodiment of the present disclosure. Detailed implementation manners
[0039] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, rather than limiting the application. Additionally, it should be noted that for the sake of description, only the parts related to the related application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be pointed out that the terms "first / second / third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than the illustrated or described order.
[0040] In some embodiments, as Figure 1 shown, the memory 1000 includes a first chip 100 and a second chip 200 stacked along the Z direction. The first chip 100 can be a storage chip for storing data. The second chip 200 can be a logic chip for performing logical processing on the data read from the storage chip and / or for performing logical processing on the data to be stored in the storage chip.
[0041] The first chip 100 includes N memory array slices 110 arranged along the X direction, and there is an intermediate region between adjacent memory array slices 110. The second chip 200 includes (N - 1) sense amplifier regions 210 arranged along the X direction. Each sense amplifier region 210 includes a plurality of sense amplifiers 211, and the projection of each sense amplifier region 210 along the Z direction is located in the intermediate region between adjacent memory array slices 110.
[0042] The kth memory array slice 110 and the (k + 1)th memory array slice 110 are a group of adjacent memory array slices 110, and k is a positive odd number less than or equal to (N - 1).
[0043] The k-th memory array slice 110 includes a plurality of bit lines (e.g., BLb0, BLb1, BLb2, BLb3...).
[0044] The (k + 1)-th memory array slice 110 includes a plurality of bit lines (e.g., BL0, BL1, BL2, BL3...).
[0045] The k-th sense amplifier region 210 corresponding to the k-th memory array slice 110 and the (k + 1)-th memory array slice 110 includes a plurality of sense amplifiers 211. Among them, the first sense amplifier 211 in the k-th sense amplifier region 210 can be respectively connected to BLb0 in the k-th memory array slice 110 and BL0 in the (k + 1)-th memory array slice 110. The second sense amplifier 211 in the k-th sense amplifier region 210 can be respectively connected to BLb2 in the k-th memory array slice 110 and BL2 in the (k + 1)-th memory array slice 110... and so on.
[0046] The (k - 1)-th sense amplifier region 210 corresponding to the k-th memory array slice 110 and the (k - 1)-th memory array slice 110 includes a plurality of sense amplifiers 211. Among them, the first sense amplifier 211 in the (k - 1)-th sense amplifier region 210 can be respectively connected to BLb1 in the k-th memory array slice 110 and BL1 in the (k - 1)-th memory array slice 110. The second sense amplifier 211 in the (k - 1)-th sense amplifier region 210 can be respectively connected to BLb3 in the k-th memory array slice 110 and BL3 in the (k - 1)-th memory array slice 110... and so on.
[0047] The (k + 1)-th sense amplifier region 210 corresponding to the (k + 1)-th memory array slice 110 and the (k + 2)-th memory array slice 110 includes a plurality of sense amplifiers 211. Among them, the first sense amplifier 211 in the (k + 1)-th sense amplifier region 210 can be respectively connected to BL1 in the (k + 1)-th memory array slice 110 and BLb1 in the (k + 2)-th memory array slice 110. The second sense amplifier 211 in the (k + 1)-th sense amplifier region 210 can be respectively connected to BL3 in the (k + 1)-th memory array slice 110 and BLb3 in the (k + 2)-th memory array slice 110... and so on.
[0048] In this embodiment, the pitch between adjacent sense amplifiers 211 in the same sense amplification region 210 in the Y direction is 4BL pitch (bit line pitch), and the pitch is relatively close. Therefore, when manufacturing the sense amplifier 211, during the lithography process, the pitch between adjacent light rays is too small, and interference is likely to occur between them, which will cause problems such as blurring and defects at the edges of the metal lines in the sense amplifier 211, and even affect the yield of the memory. To solve the above problems, in some embodiments, double patterning technology (DPT) can be used to manufacture the sense amplifier 211. However, this not only increases the process complexity but also increases the process cost.
[0049] To solve the above problems, embodiments of the present disclosure provide a memory. The first direction in the embodiments of the present disclosure may be the X direction in the drawings of the present disclosure, the second direction may be the Y direction in the drawings of the present disclosure, and the third direction may be the Z direction in the drawings of the present disclosure. The present disclosure is described by taking the first direction perpendicular to the second direction as an example, and it should be understood that the present disclosure is not limited thereto.
[0050] As Figure 2 shown, the memory 1000 includes a first chip 100 and a second chip 200 stacked along the third direction (Z direction); the first chip 100 may be a storage chip for storing data. The second chip 200 may be a logic chip for performing logical processing on the data read from the storage chip and / or for performing logical processing on the data to be stored in the storage chip. In the embodiments of the present disclosure, the second chip 200 is stacked on the first chip 100. In some other embodiments, the first chip 100 may be stacked on the second chip 200.
[0051] The first chip 100 includes N memory array slices 110 arranged along the first direction (X direction), and each memory array slice 110 includes a plurality of memory cells arranged in an array. A plurality of memory cells aligned along the second direction (Y direction) are connected to the same word line (not shown), and a plurality of memory cells aligned along the first direction are connected to the same bit line; the first direction and the second direction intersect (for example, are perpendicular); where N is a positive integer greater than or equal to 2;
[0052] The second chip 200 includes (N - 1) sense amplification regions 210 arranged along the first direction. Part of the bit lines of the jth memory array slice 110 and part of the bit lines of the (j + 1)th memory array slice 110 are both connected to the jth sense amplification region 210; where j is a positive integer less than or equal to (N - 1).
[0053] As Figure 2 shown, for example, BLb2 of the jth memory array slice 110 and BL2 of the (j + 1)th memory array slice 110 are both connected to the jth sense amplification region 210.
[0054] Each sensing and amplifying region 210 includes a first sensor array 220 and a second sensor array 230 arranged along a first direction; for the j-th sensing and amplifying region 210, the projection of the first sensor array 220 therein along a third direction is located on the j-th memory array slice 110, and the projection of the second sensor array 230 therein along the third direction is located on the (j + 1)-th memory array slice 110.
[0055] In the embodiments of the present disclosure, the first chip 100 and the second chip 200 together form a three-dimensional memory, that is, the memory array slices 110 are on one chip, and the sensing and amplifying regions 210 are distributed on another chip, improving the storage capacity; at the same time, in the embodiments of the present disclosure, the projection of each sensor array in each sensing and amplifying region 210 along the Z direction will be located on a corresponding memory array slice 110, rather than on the intermediate region between adjacent memory array slices 110. It can be understood that the area of each memory array slice 110 is much larger than the area of the intermediate region between adjacent memory array slices 110, so that the area occupied by a single sense amplifier 211 in the sensing and amplifying region 210 can be larger. Therefore, when manufacturing the sense amplifier 211 in the memory 1000 shown in the embodiments of the present disclosure, it is not necessary to use double patterning technology to accurately manufacture, which can not only avoid problems such as blurring and defects at the edges of the metal wires in the sense amplifier 211, but also improve the yield of the memory. It can also save process steps, thereby saving process costs.
[0056] The embodiments provided in the present disclosure are applicable to and not limited to Dynamic Random-Access Memory (DRAM), Static Random-Access Memory (SRAM). Among them, DRAM includes but is not limited to Double Data Rate SDRAM (DDR), Low Power DDR (LPDDR). Double Data Rate SDRAM also includes DDR4, DDR5, and DDR6, etc. Low Power DDR also includes LPDDR4, LPDDR5, and LPDDR6, etc.
[0057] In some embodiments, as Figure 3 shown, for each sensing and amplifying region 210, the first sensor array 220 therein includes a plurality of first sense amplifiers 211a arranged in an array, and the second sensor array 230 therein includes a plurality of second sense amplifiers 211b arranged in an array;
[0058] The (4a - 3)-th bit lines of the i-th memory array slice 110 and the (i + 1)-th memory array slice 110 are each connected to the same second sense amplifier 211b in the i-th sense amplification region 210; where a is a positive integer; 1 ≤ i ≤ (N - 1), and i is a positive odd number;
[0059] The (4a - 1)-th bit lines of the i-th memory array slice 110 and the (i + 1)-th memory array slice 110 are each connected to the same first sense amplifier 211a in the i-th sense amplification region 210.
[0060] In the embodiments of the present disclosure, the multiple bit lines in each memory array slice 110 are numbered starting from 0, and the multiple bit lines in each memory array slice 110 include BL0, BL1, BL2,.... Among them, the BL0 bit line is called the first bit line, and the BL1 bit line is called the second bit line. In some other embodiments, the bit lines in each memory array slice 110 can also be numbered starting from 1. At this time, the bit lines in each memory array slice 110 include BL1, BL2, BL3,.... Among them, the BL1 bit line is called the first bit line, and the BL2 bit line is called the second bit line. Other rules can also be used to number the multiple bit lines, and the present disclosure does not limit the numbering rules. The first bit line and the second bit line in the present disclosure refer to the physical order of the bit lines. While BL0, BL1, BL2 refer to the numbering order of the bit lines. The present disclosure gives a correspondence relationship between the physical order and the numbering order of the bit lines. It should be understood that the numbering order of the bit lines can be changed according to different numbering rules, while the physical order of the bit lines will not change accordingly, and the correspondence relationship between the physical order and the numbering order of the bit lines will change accordingly.
[0061] In the embodiments of the present disclosure, a bit line in the i-th memory array slice and a bit line in the (i + 1)-th memory array slice can form a pair of complementary bit lines. Among them, the bit line in the i-th memory array slice is denoted as the complementary bit line BLb, and the bit line in the (i + 1)-th memory array slice is denoted as the bit line BL. In some other embodiments, the bit line in the i-th memory array slice can be denoted as the bit line BL, and the bit line in the (i + 1)-th memory array slice can be denoted as the complementary bit line BLb.
[0062] For example, when i takes the value of 1, for the first sensing and amplifying region 210, it includes a first sensor array 220 and a second sensor array 230. The first sensor array 220 includes a plurality of first sense amplifiers 211a arranged in an array, and the second sensor array 230 includes a plurality of second sense amplifiers 211b arranged in an array. The projection of the first sensor array 220 of the first sensing and amplifying region 210 in the Z direction is located on the first memory array slice 110, and the projection of the second sensor array 230 of the first sensing and amplifying region 210 in the Z direction is located on the second memory array slice 110.
[0063] The (4a - 3)th bit lines (BLb0 / 4 / 8 / 12...) in the first memory array slice 110 and the (4a - 3)th bit lines (BL0 / 4 / 8 / 12...) in the second memory array slice 110 are connected to the same second sense amplifier 211b in the second sensor array 230 of the first sensing and amplifying region 210.
[0064] The (4a - 1)th bit lines (BLb2 / 6 / 10 / 14...) in the first memory array slice 110 and the (4a - 1)th bit lines (BL2 / 6 / 10 / 14...) in the second memory array slice 110 are connected to the same first sense amplifier 211a in the first sensor array 220 of the first sensing and amplifying region 210.
[0065] Each sense amplifier 211 (including the first sense amplifier 211a and the second sense amplifier 211b) is configured to perform sensing and amplifying processing based on the two connected bit lines.
[0066] In some embodiments, as Figure 3 shown, the surface of the ith memory array slice 110 close to the ith sensing and amplifying region 210 further includes a plurality of first connection points P1 and a plurality of first complementary connection points P1B. The (4a - 1)th bit line of the ith memory array slice 110 is connected to the ath first connection point P1, and the (4a - 1)th bit line of the (i + 1)th memory array slice 110 is connected to the ath first complementary connection point P1B. The ath first connection point P1 and the ath first complementary connection point P1B are connected to the same first sense amplifier 211a; where a is a positive integer.
[0067] The surface of the (i + 1)-th memory array chip 110 adjacent to the surface of the i-th sense amplifier region 210 further includes a plurality of second connection points P2 and a plurality of second complementary connection points P2B. The (4a - 3)-th bit line of the i-th memory array chip 110 is connected to the a-th second connection point P2, and the (4a - 3)-th bit line of the (i + 1)-th memory array chip 110 is connected to the a-th second complementary connection point P2B. The a-th second connection point P2 and the a-th second complementary connection point P2B are connected to the same second sense amplifier 211b.
[0068] In an embodiment of the present disclosure, the surface of each memory array chip 110 adjacent to the surface of the sensor array (including the first sensor array and the second sensor array) in the corresponding sense amplifier region 210 further includes a plurality of connection points and a plurality of complementary connection points. And through these connection points and complementary connection points, the bonding between the first chip 100 and the second chip 200 can be realized.
[0069] For example, when i is 1, the surface of the first memory array chip 110 adjacent to the first sensor array 220 in the first sense amplifier region 210 further includes a plurality of first connection points P1 and a plurality of first complementary connection points P1B. The (4a - 1)-th bit line (BLb2 / 6 / 10 / 14...) of the first memory array chip 110 is connected to the a-th first connection point P1. (For example, the third bit line BLb2 in the first memory array chip 110 is connected to the first first connection point P1 corresponding to the first sense amplifier region 210, the seventh bit line BLb6 in the first memory array chip 110 is connected to the second first connection point P1 corresponding to the first sense amplifier region 210, and so on). The (4a - 1)-th bit line (BL2 / 6 / 10 / 14...) of the second memory array chip 110 is connected to the first first complementary connection point P1B. (For example, the third bit line BL2 in the second memory array chip 110 is connected to the first first complementary connection point P1B corresponding to the first sense amplifier region 210, the seventh bit line BL6 in the second memory array chip 110 is connected to the second first complementary connection point P1B corresponding to the first sense amplifier region 210, and so on).
[0070] The a-th first connection point P1 and the a-th first complementary connection point P1B (for example, the first first connection point P1 and the first first complementary connection point P1B) are connected to the same first sense amplifier 211a.
[0071] The second memory array chip 110 further includes a plurality of second connection points P2 and a plurality of second complementary connection points P2B on the surface close to the second sensor array 230 in the first sense amplifier region 210. The (4a - 3)th bit line (BLb0 / 4 / 8 / 12...) of the first memory array chip 110 is connected to the ath second connection point P2. (For example, the first bit line BLb0 in the first memory array chip 110 is connected to the first second connection point P2 corresponding to the first sense amplifier region 210, the fifth bit line BLb4 in the first memory array chip 110 is connected to the second first connection point P1 corresponding to the first sense amplifier region 210, and so on). The (4a - 3)th bit line (BL0 / 4 / 8 / 12...) of the second memory array chip 110 is connected to the ath second complementary connection point P2B. (For example, the first bit line BL0 in the second memory array chip 110 is connected to the first second complementary connection point P2B corresponding to the first sense amplifier region 210, the fifth bit line BL4 in the second memory array chip 110 is connected to the second second complementary connection point P2B corresponding to the first sense amplifier region 210, and so on).
[0072] The ath second connection point P2 and the ath second complementary connection point P2B (for example, the first second connection point P2 and the first second complementary connection point P2B) are connected to the same second sense amplifier 211b.
[0073] In some embodiments, the first connection point P1 is aligned with the first end of the connected first sense amplifier 211a in the third direction, and the first connection point P1 is connected to the first end of the first sense amplifier 211a in the third direction through a wire and / or a bonding structure;
[0074] The first complementary connection point P1B is aligned with the second end of the connected first sense amplifier 211a in the third direction, and the first complementary connection point P1B is connected to the second end of the first sense amplifier 211a in the third direction through a wire and / or a bonding structure.
[0075] In some embodiments, the second connection point P2 is aligned with the first end of the connected second sense amplifier 211b in the third direction, and the second connection point P2 is connected to the first end of the second sense amplifier 211b in the third direction through a wire and / or a bonding structure;
[0076] The second complementary connection point P2B is aligned with the second end of the connected second sense amplifier 211b in the third direction, and the second complementary connection point P2B is connected to the second end of the second sense amplifier 211b in the third direction through a wire and / or a bonding structure.
[0077] In some embodiments, the first chip 100 may include a first bonding layer on the surface of the first chip 100. The first bonding layer includes a plurality of first bonding structures and / or first wires. The second chip 200 further includes a second bonding layer on the surface of the second chip 200. The second bonding layer includes a plurality of second bonding structures and / or second wires.
[0078] In some embodiments, the bonding points between the first bonding structure and the second bonding structure include the above-mentioned connection points (the first connection point P1, the first complementary connection point P1B, the second connection point P2, and the second complementary connection point P2B) located in the first bonding structure.
[0079] The above-mentioned connection points are connected to the second bonding structure and / or the second wire in the second crystal along the Z direction to be connected to the first end and the second end of the corresponding sense amplifier 211.
[0080] In the embodiments of the present disclosure, the connection point corresponding to the first end of the sense amplifier 211 and the first end of the sense amplifier are in the same Z direction, and the connection point corresponding to the second end of the sense amplifier 211 and the second end of the sense amplifier are in the same Z direction. This can save the wiring length between the first end and the second end of the sense amplifier 211 and the corresponding connection points, improve the signal transmission rate, and also improve the signal quality.
[0081] In the embodiments of the present disclosure, the first chip 100 and the second chip 200 are bonded to each other through a plurality of first bonding structures and / or first wires in the first bonding layer, and the second chip 200 is bonded through a plurality of second bonding structures and / or second wires in the second bonding layer. The interface between the first bonding layer and the second bonding layer is the bonding surface between the first chip 100 and the second chip 200, and the above-mentioned connection points may be located on the bonding surface.
[0082] In some embodiments, the first chip 100 and the second chip 200 are bonded by a hybrid bonding method.
[0083] The first chip 100 and the second chip 200 can be hybrid-bonded through dielectric-to-dielectric bonding and metal-to-metal bonding.
[0084] In some embodiments, the materials of the plurality of connection points (the first connection point P1, the first complementary connection point P1B, the second connection point P2, and the second complementary connection point P2B) included in the first bonding structure may be metal materials (for example, copper).
[0085] Such as Figure 4As shown, the surface of the i-th sense amplifier region 210 adjacent to the surface of the i-th memory array slice 110 further includes a plurality of fifth connection points P5 and fifth complementary connection points P5B; the fifth connection points P5 are bonded to the first connection points P1 correspondingly, and the fifth complementary connection points P5B are bonded to the first complementary connection points P1B correspondingly.
[0086] The surface of the i-th sense amplifier region 210 adjacent to the surface of the (i + 1)-th memory array slice 110 further includes a plurality of sixth connection points P6 and sixth complementary connection points P6B; the sixth connection points P6 are bonded to the second connection points P2 correspondingly, and the sixth complementary connection points P6B are bonded to the second complementary connection points P2B correspondingly.
[0087] The materials of the plurality of connection points (the fifth connection points P5, the fifth complementary connection points P5B, the sixth connection points P6, and the sixth complementary connection points P6B) included in the second bonding structure may be metal materials (for example, copper).
[0088] In some embodiments, the first chip 100 and the second chip 200 are bonded by means such as wire bonding, flip chip bonding, and through silicon via process. The first chip 100 and the second chip 200 can be bonded in a suitable manner, and the present disclosure does not limit the bonding manner of the first chip 100 and the second chip 200.
[0089] In some embodiments, as Figure 4 shown, for each sense amplifier region, the first sensor array 220 therein includes a plurality of first sense amplifiers 211a distributed in an array, and the second sensor array 230 therein includes a plurality of second sense amplifiers 211b distributed in an array;
[0090] The (4a - 2)-th bit lines of the (i + 1)-th memory array slice 110 and the (i + 2)-th memory array slice 110 are each connected to the same second sense amplifier 211b in the (i + 1)-th sense amplifier region 210;
[0091] The (4a)-th first bit lines of the (i + 1)-th memory array slice 110 and the (i + 2)-th memory array slice 110 are each connected to the same first sense amplifier 211a in the (i + 1)-th sense amplifier region 210.
[0092] For example, when i takes the value of 1, for the second sense amplification region 210, it includes a first sensor array 220 and a second sensor array 230. The first sensor array 220 includes a plurality of first sense amplifiers 211a arranged in an array, and the second sensor array 230 includes a plurality of second sense amplifiers 211b arranged in an array. The projection of the first sensor array 220 of the second sense amplification region 210 in the Z direction is located on the second memory array slice 110, and the projection of the second sensor array 230 of the second sense amplification region 210 in the Z direction is located on the third memory array slice 110.
[0093] The (4a - 2)th bit lines (BL1 / 5 / 9 / 13...) in the second memory array slice 110 and the (4a - 2)th bit lines (BLb1 / 5 / 9 / 13...) in the third memory array slice are connected to the same second sense amplifier 211b in the second sensor array 230 of the second sense amplification region 210. The (4a)th bit lines (BL3 / 7 / 11 / 15...) in the second memory array slice 110 and the (4a)th bit lines (BLb3 / 7 / 11 / 15...) in the third memory array slice are connected to the same first sense amplifier 211a in the first sensor array 220 of the second sense amplification region 210.
[0094] Each sense amplifier 211 (including the first sense amplifier 211a and the second sense amplifier 211b) is configured to perform sense amplification processing based on the two connected bit lines.
[0095] In some embodiments, as Figure 4 shown, the surface of the (i + 2)th memory array slice 110 close to the (i + 1)th sense amplification region 210 further includes a plurality of third connection points P3 and a plurality of third complementary connection points P3B. The (4a - 2)th bit line of the (i + 2)th memory array slice 110 is connected to the ath third connection point P3, the (4a - 2)th bit line of the (i + 1)th memory array slice 110 is connected to the ath third complementary connection point P3B, and the ath third connection point P3 and the ath third complementary connection point P3B are connected to the same second sense amplifier 211b;
[0096] The surface of the (i + 1)th memory array slice 110 close to the (i + 1)th sense amplification region 210 further includes a plurality of fourth connection points P4 and a plurality of fourth complementary connection points P4B. The (4a)th bit line of the (i + 2)th memory array slice 110 is connected to the ath fourth connection point P4, the (4a)th bit line of the (i + 1)th memory array slice 110 is connected to the ath fourth complementary connection point P4B, and the ath fourth connection point P4 and the ath fourth complementary connection point P4B are connected to the same first sense amplifier 211a.
[0097] In the embodiments of the present disclosure, the surface of each memory array chip 110 near the surface of the sensor arrays (including the first sensor array 220 and the second sensor array 230) in the corresponding sense amplifier region 210 further includes a plurality of connection points and a plurality of complementary connection points. And through these connection points and complementary connection points, the bonding between the first chip 100 and the second chip 200 can be realized.
[0098] For example, when i is 1, the surface of the 3rd memory array chip 110 near the first sensor array 220 in the 2nd sense amplifier region 210 further includes a plurality of third connection points P3 and a plurality of third complementary connection points P3B. The (4a - 2)th bit line (BLb1 / 5 / 9 / 13...) of the 3rd memory array chip 110 is connected to the a-th third connection point P3. (For example, the second bit line BLb1 in the 3rd memory array chip is connected to the first third connection point P3 corresponding to the 2nd sense amplifier region 210, the sixth bit line BLb5 in the 3rd memory array chip is connected to the second third connection point P3 corresponding to the 2nd sense amplifier region 210, and so on).
[0099] The (4a - 2)th bit line (BL1 / 5 / 9 / 13...) of the 2nd memory array chip 110 is connected to the a-th third complementary connection point P3B. (For example, the second bit line BL1 in the 2nd memory array chip is connected to the first third complementary connection point P3B corresponding to the 2nd sense amplifier region 210, the sixth bit line BL5 in the 2nd memory array chip is connected to the second third complementary connection point P3B corresponding to the 2nd sense amplifier region 210, and so on).
[0100] The a-th third connection point P3 and the a-th third complementary connection point P3B (for example, the first third connection point P3 and the first third complementary connection point P3B) are connected to the same second sense amplifier 211b.
[0101] The surface of the second memory array chip 110 close to the second sensor array 230 in the second sense amplifier region 210 further includes a plurality of fourth connection points P4 and a plurality of fourth complementary connection points P4B. The (4a)th bit line (BLb3 / 7 / 11 / 15...) of the third memory array chip 110 is connected to the ath fourth connection point P4. (For example, the fourth bit line BL3 in the third memory array chip is connected to the first fourth connection point P4 corresponding to the second sense amplifier region 210, the eighth bit line BL7 in the third memory array chip is connected to the second fourth connection point P4 corresponding to the second sense amplifier region 210, and so on). The (4a)th bit line (BL3 / 7 / 11 / 15...) of the second memory array chip 110 is connected to the ath fourth complementary connection point P4B. (For example, the fourth bit line BL3 in the second memory array chip 110 is connected to the first fourth complementary connection point P4B corresponding to the second sense amplifier region 210, the eighth bit line BL7 in the second memory array chip 110 is connected to the second fourth complementary connection point P4B corresponding to the second sense amplifier region 210, and so on).
[0102] The ath fourth connection point P4 and the ath fourth complementary connection point P4B (for example, the first fourth connection point P4 and the first fourth complementary connection point P4B) are connected to the same first sense amplifier 211a.
[0103] In some embodiments, as Figure 4 shown, the third connection point P3 is aligned with the first end of the connected second sense amplifier 211b along the third direction, and the third connection point P3 is connected to the first end of the second sense amplifier 211b along the third direction through a wire and / or a bonding structure;
[0104] The third complementary connection point P3B is aligned with the second end of the connected second sense amplifier 211b along the third direction, and the third complementary connection point P3B is connected to the second end of the second sense amplifier 211b along the third direction through a wire and / or a bonding structure.
[0105] In some embodiments, as Figure 4 shown, the fourth connection point P4 is aligned with the first end of the connected first sense amplifier 211a along the third direction, and the fourth connection point P4 is connected to the first end of the first sense amplifier 211a along the third direction through a wire and / or a bonding structure;
[0106] The fourth complementary connection point P4B is aligned with the second end of the connected first sense amplifier 211a along the third direction, and the fourth complementary connection point P4B is connected to the second end of the first sense amplifier 211a along the third direction through a wire and / or a bonding structure.
[0107] In some embodiments, the bonding points of the first bonding structure and the second bonding structure include the above-mentioned connection points (the third connection point P3, the third complementary connection point P3B, the fourth connection point P4, and the fourth complementary connection point P4B) located in the first bonding structure.
[0108] The above-mentioned connection points are connected to the second bonding structure and / or the second wire located in the second crystal along the Z direction to be connected to the first end and the second end of the corresponding sense amplifier 211.
[0109] In the embodiments of the present disclosure, the connection point corresponding to the first end of the sense amplifier 211 and the first end of the sense amplifier are in the same Z direction, and the connection point corresponding to the second end of the sense amplifier 211 and the second end of the sense amplifier are in the same Z direction, which can save the wiring length between the first end and the second end of the sense amplifier 211 and the corresponding connection points, improve the signal transmission rate, and can also improve the signal quality.
[0110] In the embodiments of the present disclosure, the first chip 100 is bonded to the second chip 200 through a plurality of first bonding structures and / or first wires in the first bonding layer, and the second chip 200 is bonded to the first chip 100 through a plurality of second bonding structures and / or second wires in the second bonding layer. The interface between the first bonding layer and the second bonding layer is the bonding surface between the first chip 100 and the second chip 200, and the above-mentioned connection points can be located on the bonding surface.
[0111] In some embodiments, each memory array slice 110 includes 512 bit lines;
[0112] Each sensor array includes 256 sense amplifiers 211, and includes 64 sense amplifiers 211 in the second direction and 4 sense amplifiers 211 in the first direction. Therefore, each sense amplification region 210 includes 512 sense amplifiers 211.
[0113] Figure 5 It is a top view schematic diagram of the memory 1000 in some embodiments. Combining Figure 1 and Figure 5 In some embodiments, adjacent memory array slices 110 correspond to one sense amplification region 210. Each sense amplification region 210 includes 512 sense amplifiers 211. The projection of each sense amplification region 210 along the Z direction is located in the middle region between adjacent memory array slices 110. Each sense amplification region 210 includes 512 sense amplifiers 211. Among them, there are 2 sense amplifiers 211 in the X direction and 256 sense amplifiers 211 in the Y direction. The length of each sense amplifier 211 in the Y direction is 4BL pitch (bit line pitch). The area occupied by each sense amplifier 211 is S1.
[0114] Figure 6It is a top view schematic diagram of the memory 1000 provided by an embodiment of the present disclosure. In combination with Figure 3 and Figure 6 , in an embodiment of the present disclosure, adjacent memory array chips 110 correspond to a sense amplifier region 210. Each sense amplifier region 210 includes a first sensor array 220 and a second sensor array 230. The projection of the first sensor array 220 in the Z direction is located on one of the adjacent memory array chips 110, and the projection of the second sensor array 230 in the Z direction is located on the other of the adjacent memory array chips 110.
[0115] Each sensor array includes 256 sense amplifiers 211, and includes 64 sense amplifiers 211 in the Y direction and 4 sense amplifiers 211 in the X direction. The length of each sense amplifier 211 in the Y direction is 16BL pitch (bit line pitch). The area occupied by each sense amplifier 211 is S2, and S2 is greater than S1.
[0116] In an embodiment of the present disclosure, by disposing the first sensor array 220 on one of the adjacent memory array chips 110 and the second sensor array 230 on the other of the adjacent memory array chips 110, the length of the sense amplifier 211 in the Y direction is increased, and the area of the sense amplifier 211 is increased. Therefore, when manufacturing the sense amplifier 211 in the memory 1000 shown in the embodiment of the present disclosure, it is possible to accurately manufacture without using double patterning technology, which can not only avoid problems such as blurring and defects at the edges of the metal lines in the sense amplifier 211, but also improve the yield of the memory. It can also save process steps, thereby saving process costs.
[0117] In some other embodiments, each memory array chip 110 includes 1024 bit lines;
[0118] Each sensor array includes 516 sense amplifiers 211, and includes 128 sense amplifiers 211 in the first direction and 4 sense amplifiers 211 in the second direction.
[0119] The number of bit lines in each of the above memory array chips 110, the number of sense amplifiers 211 in each sensor array, and the number of sense amplifiers 211 in the first direction and the second direction of each sensor array are all examples, and the present disclosure does not limit this.
[0120] As Figure 7 shown, an embodiment of the present disclosure also provides an electronic device 1100. The electronic device 1100 includes the memory 1000 according to any of the above embodiments.
[0121] The electronic device 1100 may include a host 1001 and a memory system 1003. Among them, the electronic device 1100 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device 1100 having the memory 1000 provided in the above embodiments; the host 1001 may be a processor of the electronic device 1100 (e.g., a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP))).
[0122] The memory system 1003 may include a memory controller 1002 and at least one memory 1000 as in any of the above embodiments. The memory controller 1002 may be used to control the memory 1000 to read data, and to control the interaction between the memory 1000 and the host 1001.
[0123] The above are only the preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element. The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only the specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims
1. A memory, characterized in that, including a first chip and a second chip stacked along a third direction; the first chip includes N memory array slices arranged along a first direction, and each of the memory array slices includes a plurality of memory cells distributed in an array, a plurality of memory cells aligned along a second direction are connected to the same word line, and a plurality of memory cells aligned along the first direction are connected to the same bit line; the first direction and the second direction intersect; wherein, N is a positive integer greater than or equal to 2; the second chip includes (N - 1) sense amplifier regions arranged along the first direction, a partial bit line of the jth memory array slice and a partial bit line of the (j + 1)th memory array slice are both connected to the jth sense amplifier region; wherein, j is a positive integer less than or equal to (N - 1); each of the sense amplifier regions includes a first sensor array and a second sensor array arranged along the first direction; for the jth sense amplifier region, the projection of the first sensor array therein along the third direction is located on the jth memory array slice, and the projection of the second sensor array therein along the third direction is located on the (j + 1)th memory array slice.
2. The memory according to claim 1, characterized in that, for each of the sense amplifier regions, the first sensor array therein includes a plurality of first sense amplifiers distributed in an array, and the second sensor array therein includes a plurality of second sense amplifiers distributed in an array; the (4a - 3)th bit line of the ith memory array slice and the (4a - 3)th bit line of the (i + 1)th memory array slice are both connected to the same second sense amplifier in the ith sense amplifier region; wherein, a is a positive integer; 1 ≤ i ≤ (N - 1), and i is a positive odd number; the (4a - 1)th bit line of the ith memory array slice and the (4a - 1)th bit line of the (i + 1)th memory array slice are both connected to the same first sense amplifier in the ith sense amplifier region.
3. The memory according to claim 2, characterized in that, the surface of the ith memory array slice close to the ith sense amplifier region further includes a plurality of first connection points and a plurality of first complementary connection points, the (4a - 1)th bit line of the ith memory array slice is connected to the ath first connection point, the (4a - 1)th bit line of the (i + 1)th memory array slice is connected to the ath first complementary connection point, and the ath first connection point and the ath first complementary connection point are connected to the same first sense amplifier; the surface of the (i + 1)th memory array slice close to the ith sense amplifier region further includes a plurality of second connection points and a plurality of second complementary connection points, the (4a - 3)th bit line of the ith memory array slice is connected to the ath second connection point, the (4a - 3)th bit line of the (i + 1)th memory array slice is connected to the ath second complementary connection point, and the ath second connection point and the ath second complementary connection point are connected to the same second sense amplifier.
4. The memory according to claim 3, characterized in that, the first connection point is aligned with the first end of the first sense amplifier to which it is connected along the third direction, and the first connection point is connected to the first end of the first sense amplifier along the third direction through a wire and / or a bonding structure; The first complementary connection point is aligned with the second end of the connected first sense amplifier along a third direction, and the first complementary connection point is connected to the second end of the first sense amplifier along the third direction through a wire and / or a bonding structure.
5. The memory according to claim 3, characterized in that, The second connection point is aligned with the first end of the connected second sense amplifier along a third direction, and the second connection point is connected to the first end of the second sense amplifier along the third direction through a wire and / or a bonding structure; The second complementary connection point is aligned with the second end of the connected second sense amplifier along a third direction, and the second complementary connection point is connected to the second end of the second sense amplifier along the third direction through a wire and / or a bonding structure.
6. The memory according to claim 2, characterized in that, The (4a - 2)-th bit lines of the (i + 1)-th and (i + 2)-th memory array chips are connected to the same second sense amplifier in the (i + 1)-th sense amplification region; The (4a)-th first bit lines of the (i + 1)-th and (i + 2)-th memory array chips are connected to the same first sense amplifier in the (i + 1)-th sense amplification region.
7. The memory according to claim 2, characterized in that, The surface of the (i + 2)-th memory array chip close to the (i + 1)-th sense amplification region further includes a plurality of third connection points and a plurality of third complementary connection points. The (4a - 2)-th bit line of the (i + 2)-th memory array chip is connected to the a-th third connection point, the (4a - 2)-th bit line of the (i + 1)-th memory array chip is connected to the a-th third complementary connection point, and the a-th third connection point and the a-th third complementary connection point are connected to the same second sense amplifier; The surface of the (i + 1)-th memory array chip close to the (i + 1)-th sense amplification region further includes a plurality of fourth connection points and a plurality of fourth complementary connection points. The (4a)-th bit line of the (i + 2)-th memory array chip is connected to the a-th fourth connection point, the (4a)-th bit line of the (i + 1)-th memory array chip is connected to the a-th fourth complementary connection point, and the a-th fourth connection point and the a-th fourth complementary connection point are connected to the same first sense amplifier.
8. The memory according to claim 7, characterized in that, The third connection point is aligned with the first end of the connected second sense amplifier along a third direction, and the third connection point is connected to the first end of the second sense amplifier along the third direction through a wire and / or a bonding structure; The third complementary connection point is aligned with the second end of the connected second sense amplifier along a third direction, and the third complementary connection point is connected to the second end of the second sense amplifier along the third direction through a wire and / or a bonding structure.
9. The memory according to claim 7, characterized in that, The fourth connection point is aligned with the first end of the connected first sense amplifier along a third direction, and the fourth connection point is connected to the first end of the first sense amplifier along the third direction through a wire and / or a bonding structure; The fourth complementary connection point is aligned with the second end of the second sense amplifier to which it is connected along a third direction, and the fourth complementary connection point is connected to the second end of the first sense amplifier along the third direction through a wire and / or a bonding structure.
10. The memory according to claim 1, characterized in that, Each of the memory array chips includes 512 of the bit lines; Each of the sensor arrays includes 256 sense amplifiers, and 64 of the sense amplifiers are included in the second direction and 4 of the sense amplifiers are included in the first direction.
11. The memory according to claim 1, characterized in that, The first chip and the second chip are bonded by a hybrid bonding method.
12. An electronic device, characterized in that, The electronic device includes the memory according to any one of claims 1 to 11.