Method for realizing surface planarization of semiconductor device through etching process and semiconductor device

Abstract

The invention discloses a method for realizing surface planarization of a semiconductor device through an etching process and the semiconductor device. The method at least comprises the following steps: providing a substrate with a non-planarized surface; forming a sacrificial layer with a planarized surface on the substrate; removing the sacrificial layer and a part of the substrate material through etching so as to realize surface planarization of the substrate; wherein the ratio of the etching rate of the substrate to the etching rate of the sacrificial layer meets the requirement of the subsequent process on the flatness of the surface of the substrate. According to the semiconductor device surface planarization method, the cost of required materials is low, the process steps are simple, the surface treatment efficiency of the semiconductor device can be greatly improved, and the performance of the obtained semiconductor device can be improved by performing surface treatment through the method.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor etching, and particularly to a method for realizing surface planarization of a semiconductor device through an etching process and a semiconductor device. Background Art

[0002] In the process of semiconductor manufacturing, it is usually necessary to perform planarization treatment on the surface of a semiconductor device. For example, after filling polysilicon on the surface of a substrate with silicon trenches, a planarization manufacturing process such as Chemical Mechanical Planarization (CMP) is required to make the surface of the substrate planar, so as to provide a planar manufacturing process surface for subsequent manufacturing process steps.

[0003] However, for CMP, it uses chemical oxidation and mechanical grinding to remove materials to achieve flat topography and the formation of device structures. In the process, it is necessary to use a combination of chemical reactions and mechanical grinding for treatment, so the cost is high and the process is complex. Summary of the Invention

[0004] The object of the present invention is to overcome the defects of the existing semiconductor device surface planarization treatment process being cumbersome and costly, thereby improving the surface flatness of the semiconductor and further improving the performance of the semiconductor device.

[0005] To achieve the above object, the present invention provides a method for realizing surface planarization of a semiconductor device through an etching process, at least including:

[0006] Providing a substrate with a non-planarized surface;

[0007] Forming a planarized sacrificial layer on the substrate;

[0008] Removing the sacrificial layer and part of the substrate material through etching to achieve surface planarization of the substrate;

[0009] Wherein, the ratio of the etching rate of the substrate to the etching rate of the sacrificial layer meets the requirements of the subsequent process for the surface flatness of the substrate.

[0010] Optionally, the ratio range of the etching rate of the substrate to the etching rate of the sacrificial layer is optionally, and the sacrificial layer is an organic layer.

[0011] Optionally, the providing a substrate with a non-planarized surface includes:

[0012] Providing a first substrate with a first trench, and filling the first trench by depositing polysilicon.

[0013] Optionally, the forming a planarized sacrificial layer on the substrate includes:

[0014] A sacrificial layer with a planarized surface is formed on the substrate through a spin coating process.

[0015] Optionally, the etching gas is selected from any one or any combination of SF6, CHF3, CF4, C4F8, Cl2, and HBr.

[0016] Optionally, the method is applied to the planarization process of polysilicon for a CMOS image sensor.

[0017] Optionally, the substrate includes single-crystalline silicon with trenches.

[0018] The present invention also provides a semiconductor device prepared by the method described above.

[0019] Compared with the prior art, the present invention has at least the following beneficial effects:

[0020] In the present invention, a sacrificial layer with a planarized surface is spin-coated on a substrate with a non-planarized surface, an etching gas is introduced therein for etching, the sacrificial layer is etched to completely remove the sacrificial layer, the substrate is etched to remove the substrate material of the uneven surface part, and the ratio of the etching rate of the substrate to the etching rate of the sacrificial layer meets the requirements of the subsequent process for the flatness of the substrate surface, so as to obtain a substrate with a flat surface at the end of etching; further, for a substrate with trenches, after filling a polysilicon layer in the trenches, a sacrificial layer with a flat surface is spin-coated on the surface of the polysilicon layer, the sacrificial layer is etched to completely remove the sacrificial layer, and the polysilicon layer is etched to remove the uneven part of the polysilicon layer, thereby obtaining a substrate with a flat surface. The above method has simple process and low cost, and greatly improves the production efficiency while improving the performance of semiconductor devices. Description of the Drawings

[0021] Figure 1 It is a flowchart of the method for realizing the surface planarization of a semiconductor device through an etching process according to the present invention.

[0022] Figure 2 It is a process diagram of the method for realizing the surface planarization of a semiconductor device through an etching process according to the present invention.

[0023] Figure 3 It is a process diagram of the method for realizing the surface planarization of a semiconductor device through an etching process in an embodiment of the present invention.

[0024] Wherein, 1 - substrate, 2 - polysilicon layer, 3 - sacrificial layer. Detailed Embodiments

[0025] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0026] In the present invention, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0027] CMP is a key process for achieving global uniform planarization of wafers in the semiconductor manufacturing process. The wafer manufacturing process mainly includes 7 independent process flows: lithography, etching, thin film growth, diffusion, ion implantation, chemical mechanical polishing, and metallization. As one of the key manufacturing processes for wafers, chemical mechanical polishing refers to the efficient removal of excess materials on the wafer surface and global nanoscale planarization through the synergistic cooperation of chemical corrosion and mechanical grinding. The main working principle of the CMP process is: through the synergistic cooperation of chemical corrosion and mechanical grinding, the efficient removal of excess materials on the wafer surface and global nanoscale planarization are achieved. The CMP polishing process can be divided into (1) chemical process and (2) physical process.

[0028] (1) The chemical process refers to: the chemical components in the polishing liquid react with the materials on the wafer surface, and by converting insoluble substances into soluble substances or softening high-hardness substances, substances that are relatively easy to remove are generated.

[0029] (2) The physical process refers to: the abrasive grains in the polishing liquid mechanically physically rub against the materials on the wafer surface, removing these chemical reaction products from the wafer surface and dissolving them into the flowing liquid and taking them away.

[0030] In order to achieve a better planarization effect, many variables usually need to be optimized in the CMP process, such as time, pressure (the force applied to the wafer and the polishing pad), the speeds of the polishing head and the polishing platen, temperature, the supply rate of the polishing liquid, the type of the polishing liquid, the elasticity of the polishing pad, the hardness of the polishing pad, etc. If any one of the variables is not properly controlled, it will directly affect the effect of the surface planarization treatment of semiconductor devices. Moreover, there are many consumables used in the process, the cost is high, and the process flow is complex, which greatly affects the efficiency of the surface planarization treatment of semiconductor devices. In addition, the common polishing liquid in the CMP process is the AB component, and the polishing liquid is usually used in combination with hydrogen peroxide. Therefore, when using the CMP process for surface planarization, due to the certain roughness of the surface of the semiconductor device, the polishing liquid will enter the uneven places on the surface of the semiconductor device, and the components in the polishing liquid will corrode the materials at the uneven places, thereby damaging the surface of the semiconductor device and being unfavorable for the surface planarization treatment.

[0031] To solve the above problems, the present invention provides a method for planarizing the surface of a semiconductor device through an etching process. A sacrificial layer is spin-coated on the surface of a non-planarized substrate. Through the etching process, the sacrificial layer is etched to complete the removal of the sacrificial layer, and the substrate is etched to remove the uneven parts of the substrate. The etching rate of the substrate and the etching rate of the sacrificial layer meet the requirements for the surface flatness of the substrate in the process.

[0032] In some embodiments, after depositing a polysilicon layer on a substrate with grooves to fill the grooves, the surface is uneven and needs to be planarized. The present invention can deposit a sacrificial layer on the surface of the polysilicon layer, etch the sacrificial layer to completely remove the sacrificial layer, and etch the polysilicon layer to remove the uneven parts of the polysilicon layer, finally obtaining a substrate with a planar polysilicon layer surface. Compared with the CMP process, the surface planarization method of the present invention uses lower raw material costs and a simpler method, greatly improving the production efficiency while improving the performance of semiconductor devices.

[0033] As Figure 1 、 Figure 2 shown, the method for planarizing the surface of a semiconductor device through an etching process of the present invention at least includes the following steps:

[0034] Step S1, providing a substrate with a non-planarized surface.

[0035] The substrate is a substrate with a non-planarized surface. The non-planarized substrate can be a substrate with grooves or protrusions on the surface. It can be understood that the substrate can be any suitable material known in the art, for example, any one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), etc. The substrate in the embodiments of the present invention is selected from silicon substrates.

[0036] The substrate can also be a substrate with a natural oxide layer deposited on its surface after being unpacked and used for a period of time. In the process of manufacturing, the silicon atoms on the surface of the silicon substrate combine with oxygen molecules to form a silicon oxide film. The silicon oxide film tightly wraps the surface of the silicon substrate and continues to react with oxygen molecules in the air, thereby forming an oxide film that continuously thickens. In subsequent metal deposition, ion implantation, and etching processes, it will affect the stability of the corresponding processes, thereby affecting the final performance of semiconductor devices. Therefore, before performing surface planarization treatment on the above substrate, it is necessary to remove the natural oxide layer. Chemical methods can be used for removal. Under certain temperature and pressure, the natural oxide layer is removed by adding alkaline or acidic liquids such as hydrofluoric acid and sodium hydroxide.

[0037] Step S2, form a surface-planarized sacrificial layer on the substrate.

[0038] To fill the non-planarized substrate, deposit a surface-planarized sacrificial layer on the substrate. The sacrificial layer is formed by spin coating. Place the substrate on a variable-speed rotating table with appropriate safety barriers. Use an organic substance as the spin coating material, such as polyimide, photoresist, etc. Drop the organic substance in the form of a liquid solution onto the center of the substrate using a nozzle. Rotate the substrate at a speed of 500 rpm to 5000 rpm for 30 s to 60 s until the thickness of the sacrificial layer covers the non-planar part of the substrate. Stop spin coating to obtain a sacrificial layer with a uniform thickness and a flat surface. Bake the substrate with the spin-coated sacrificial layer at a high temperature to evaporate the solvent, thereby forming a solid sacrificial layer. The high temperature is 300 °C to 500 °C, and the baking time is 30 min to 60 min.

[0039] In practical applications, to spin coat a sacrificial layer with a certain thickness, the characteristics of the spin coating material and the spin coating process parameters can be adjusted: for the characteristics of the spin coating material, such as changing the concentration and viscosity of the spin coating material, the drying rate of the spin coating material, the solid percentage of the spin coating material, the surface tension of the spin coating material, etc.; for the spin coating process parameters, such as changing the rotation speed of the rotating table, the rotation time, etc. Further, to control the thickness of the sacrificial layer, it can be achieved by controlling the temperature of the high-temperature baking. Preparing the sacrificial layer by the spin coating process, the process is relatively simple and efficient. By adjusting the spin coating parameters, the control of the film thickness and uniformity can be realized, and it is applicable to the preparation of different types of substrates.

[0040] Step S3, remove the sacrificial layer and part of the substrate material by etching to achieve surface planarization of the substrate.

[0041] The ratio of the etching rate of the substrate to the etching rate of the sacrificial layer meets the requirements of the subsequent process for the surface flatness of the substrate.

[0042] The sacrificial layer and the substrate are etched by means of dry etching. As an example, the substrate can be placed in a reaction chamber, and an etching gas is introduced into the reaction chamber to perform an etching process. The etching gas can be selected from any one or any combination of SF6, CHF3, CF4, C4F8, Cl2, and HBr. The etching gas forms a plasma under the excitation of a source radio frequency power source, reacts with the sacrificial layer and the substrate material to form gaseous products, and the gaseous products are discharged from the reaction chamber. The power of the source radio frequency power source is 500 W to 800 W, and the etching time is 100 s to 200 s. According to the requirements of the subsequent process for the flatness of the substrate surface, the ratio range of the etching rate of the substrate to the etching rate of the sacrificial layer is between 0.8 and 1.2. It can be understood that within the ratio range of 0.8 to 1.2, the specific mixing methods can be the following several types:

[0043] (1) The etching rate of the substrate is less than the etching rate of the sacrificial layer;

[0044] (2) The etching rate of the substrate is equal to the etching rate of the sacrificial layer;

[0045] (3) The etching rate of the substrate is greater than the etching rate of the sacrificial layer.

[0046] In practical applications, the method that can be adopted for partial removal of the substrate and complete removal of the sacrificial layer is: select an etching gas with similar etching rates for the substrate and the sacrificial layer to etch the substrate and the sacrificial layer. Further, the etching rate can be made similar by adjusting parameters such as the concentration of the etching gas, the composition ratio of the introduced etching gas, the flow rate of the etching gas, the pressure in the etching reaction chamber, the radio frequency power, the etching time, and the temperature.

[0047] The etching gas further contains a carrier gas, and the carrier gas can be selected from any one or any combination of chlorine gas (Cl2), hydrogen bromide (HBr), ammonia gas (NH3), nitrogen gas (N2), oxygen gas (O2), and argon gas (Ar). While introducing the etching gas for etching, the carrier gas is introduced. In the embodiment of the present invention, the carrier gas is argon gas (Ar), and the functions of the carrier gas at least include:

[0048] (1) Carry the etching gas into the reaction chamber for a sufficient etching reaction;

[0049] (2) Dilute the etching gas to adjust the excessive concentration of the etching gas in the reaction chamber, thereby controlling the etching rate and uniformity.

[0050] In the semiconductor manufacturing process, the surface planarization method of the present invention can also be used for a single-crystalline silicon substrate with grooves. After growing an epitaxial layer on the substrate, trench etching is performed with a mask for protection. After the etching is completed to obtain a substrate with grooves, polysilicon is usually used to fill the grooves, that is, a polysilicon layer with a film thickness of several tens of nanometers to several micrometers is deposited on the substrate by chemical vapor deposition. Due to process limitations, a certain depression usually forms on the surface of the polysilicon layer on the filled substrate, which then leads to the unevenness of the polysilicon layer surface. And the defect of the uneven surface will seriously affect the performance of the subsequent formed semiconductor devices; especially for the grooves with larger openings, the formed surface unevenness is particularly serious. After filling the grooves with polysilicon, the etching method of the semiconductor device surface planarization of the present invention is used for etching to obtain a substrate with a flat surface. The following will introduce the manufacturing process in combination with specific embodiments.

[0051] It can be understood that in practical applications, the substrate can also be a single-crystalline silicon substrate including multiple grooves such as a second groove and a third groove.

[0052] Embodiment

[0053] As Figure 3 shown, in this embodiment, the method for realizing the surface planarization of a semiconductor device by an etching process of the present invention is used to perform surface planarization treatment on a substrate with grooves, including the following steps:

[0054] Step S1: Provide a single-crystalline silicon substrate with grooves, and clean and pre-treat the single-crystalline silicon substrate to remove impurities and oxides on the surface;

[0055] Step S2: Place the single-crystalline silicon substrate in a reaction chamber, and prepare a polysilicon thin film by LPCVD method. Pass SiH4 through the first gas pipeline and pass argon (Ar) through the second gas pipeline. The volume ratio of SiH4 to Ar is 1:8. The mixed gas of SiH4 and Ar reaches the surface of the single-crystalline silicon substrate and adsorbs on the surface. The temperature in the reaction chamber is 600 °C. Under the action of high temperature, the adsorbed gas molecules are heated and decomposed to generate Si atoms and by-products. The Si atoms nucleate on the surface of the single-crystalline silicon substrate and finally form a polysilicon thin film. The by-products detach from the single-crystalline silicon surface and are discharged. The polysilicon fills the grooves and deposits a polysilicon layer on the surface of the single-crystalline silicon substrate;

[0056] Step S3: Place the single-crystalline silicon substrate deposited with a polysilicon layer on a variable-speed rotating table, and spin-coat an anti-reflection coating (BARC layer) on the surface of the polysilicon layer with an organic coating. After the spin-coating is completed, perform high-temperature baking to cure the anti-reflection coating;

[0057] Step S4: Place the monocrystalline silicon substrate obtained in Step S3 on the pedestal in the etching reaction chamber, and introduce etching gases CF4, O2, and Ar into the etching reaction chamber simultaneously to etch the anti-reflection coating and the polysilicon layer. The etching rate of the anti-reflection coating is equal to that of the polysilicon layer. After etching for a period of time, when the entire anti-reflection coating is etched away and the uneven parts on the surface of the polysilicon layer are completely etched away, exposing the flat polysilicon layer, stop introducing the etching gases.

[0058] In summary, the present invention forms a surface-flattened sacrificial layer on a substrate with non-flattened surface. Through the etching process by introducing etching gases, the sacrificial layer is etched to completely remove the sacrificial layer, and the substrate is etched to remove the non-flattened part of the substrate material, thereby obtaining a surface-flattened substrate. For a substrate with grooves, after filling the grooves with polysilicon, the surface of the polysilicon layer usually shows unevenness. A sacrificial layer is formed on the surface of the polysilicon layer. By introducing etching gases, the sacrificial layer is etched to completely remove the sacrificial layer, and the polysilicon layer is etched to remove the non-flattened part of the polysilicon layer, thereby obtaining a surface-flattened substrate. When the method is used for the planarization treatment of polysilicon in a CMOS image sensor, it will not corrode the substrate, the process materials are simple, the steps are few, and the performance of semiconductor devices can be improved through the method, which is suitable for large-scale surface treatment of semiconductor devices.

[0059] Although the content of the present invention has been introduced in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and alternatives to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A method for planarizing the surface of a semiconductor device through an etching process, characterized in that, At least including: Providing a substrate with a non-planarized surface; Forming a sacrificial layer with a planarized surface on the substrate; Removing the sacrificial layer and part of the substrate material through etching to achieve planarization of the substrate surface; Wherein, the ratio of the etching rate of the substrate to the etching rate of the sacrificial layer meets the requirements of subsequent processes for the flatness of the substrate surface.

2. The method according to claim 1, characterized in that, The ratio range of the etching rate of the substrate to the etching rate of the sacrificial layer is 0.8 to 1.

2.

3. The method according to claim 1, characterized in that, The sacrificial layer is an organic layer.

4. The method according to claim 1, characterized in that, The upper part of the substrate includes polysilicon with trenches.

5. The method according to claim 4, characterized in that, The providing a substrate with a non-planarized surface includes: Providing a first substrate with a first trench, and filling the first trench by depositing the polysilicon.

6. The method according to claim 1, characterized in that, The forming a sacrificial layer with a planarized surface on the substrate includes: Forming a sacrificial layer with a planarized surface on the substrate through a spin coating process.

7. The method according to claim 1, characterized in that, The gas for the etching is selected from any one or any combination of SF6, CHF3, CF4, C4F8, Cl2, and HBr.

8. The method according to claim 1, characterized in that, The method is applied to the planarization process of polysilicon in a CMOS image sensor.

9. The method according to claim 1, characterized in that, The substrate includes single crystal silicon with trenches.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by using the method according to any one of claims 1 to 9.

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