Modular integrated packaging technology is used as a high-density assembly method for memory chips.

Abstract

This invention relates to the field of memory chip packaging technology, and discloses a modular integrated packaging technology for high-density assembly of memory chips. The method includes: acquiring the memory chip to be assembled and packaging components; obtaining geometric data through high-precision scanning; constructing an assembly model; defining assembly constraints for the chip to obtain assembly relationships; searching for optimal paths; constructing and segmenting the assembly space; adjusting the path through collision testing to obtain the target assembly path; querying path parameters to construct assembly equipment parameters; completing parameter configuration through dynamic simulation to obtain the target assembly equipment; sending the chip and components to a workstation to obtain pre-assembled parts; adjusting the orientation deviation to obtain the target assembly parts; and packaging with the target equipment and path to obtain a preliminary packaged chip; performing electrical performance testing; if normal, performing packaging enhancement treatment; conducting non-destructive testing; classifying quality; and then integrating and packaging again to finally obtain the target packaged chip. This invention can improve the quality of high-density assembly of memory chips.

Description

Technical Field

[0001] This invention relates to a high-density assembly method for memory chips using modular integrated packaging technology, and belongs to the field of memory chip packaging technology. Background Technology

[0002] Memory chips play a core supporting role in modern electronic devices, and their high-density assembly methods are crucial to achieving greater storage capacity and superior performance within a limited space. Modular integrated packaging technology is of great significance in the high-density assembly process of memory chips. It enables the integration and packaging of multiple memory chip modules according to specific rules and methods, allowing the memory chip to accommodate more storage cells per unit area or volume. This improves the overall storage density and data read / write efficiency of the memory chip, while also helping to optimize heat dissipation and reduce signal interference. This positively impacts the applicability of memory chips in various high-performance electronic devices.

[0003] Currently, high-density assembly of memory chips generally employs traditional assembly processes. This involves manually or semi-automatically assembling the memory chips and related components one by one according to a pre-defined circuit layout and connection method. However, this method, when faced with the demands of large-scale memory chip assembly and the continuous pursuit of higher density, suffers from increased complexity in the connections between components, cumbersome assembly steps, and a lack of systematic integration mechanisms. This leads to problems such as inaccurate component alignment and unstable circuit connections, resulting in unsatisfactory high-density assembly performance that fails to meet the high-quality requirements of current electronic devices. Summary of the Invention

[0004] This invention provides a modular integrated packaging technology for high-density assembly of memory chips, and its main purpose is to improve the quality of high-density assembly of memory chips.

[0005] To achieve the above objectives, the present invention provides a modular integrated packaging technology for high-density assembly of memory chips, comprising:

[0006] The process involves acquiring the memory chip to be assembled and the packaging element, performing high-precision scanning on the memory chip to be assembled and the packaging element to obtain corresponding geometric shape data, and constructing an assembly model of the memory chip to be assembled based on the geometric shape data.

[0007] Assembly constraints are defined for the memory chip to be assembled to obtain assembly relationships. Based on the assembly relationships, the preferred assembly path for the memory chip to be assembled is searched. Based on the preferred assembly path, the assembly space for the memory chip to be assembled is constructed. The assembly space is divided into multiple small regions. The memory chip to be assembled is subjected to an assembly collision test in the small regions. Based on the test results of the assembly collision test, the preferred assembly path is adjusted to obtain an adjusted path. The adjusted path is subjected to a path test. When the path test result is excellent, the target assembly path is obtained.

[0008] The assembly path parameters of the target assembly path are queried to construct the assembly equipment parameters of the assembly equipment corresponding to the memory chip to be assembled. Based on the assembly equipment parameters, the assembly equipment is subjected to dynamic simulation. Based on the dynamic simulation results, the assembly equipment is configured with assembly parameters to obtain the target assembly equipment.

[0009] The memory chip to be assembled and the packaging element are input to the assembly station to obtain a pre-assembled part. The pose deviation of the pre-assembled part is calculated, and the pose of the pre-assembled part is adjusted based on the pose deviation to obtain a target assembled part. According to the target assembly equipment, the target assembled part is packaged into a chip using the target assembly path to obtain a preliminary packaged chip.

[0010] Electrical performance testing is performed on the pre-packaged chip. When the electrical performance test result is normal, the pre-packaged chip undergoes packaging enhancement processing to obtain a pre-processed chip. Non-destructive testing is performed on the pre-processed chip. Based on the non-destructive testing results, the pre-processed chip is classified into quality categories to obtain quality-classified chips. The quality-classified chips are then integrated and packaged to obtain the target packaged chip.

[0011] Optionally, defining assembly constraints for the memory chips to be assembled to obtain assembly relationships includes:

[0012] Identify the component features and interface functions of the memory chip to be assembled;

[0013] Based on the component characteristics, component bonding constraints and component alignment constraints are applied to the memory chip to be assembled to obtain positional constraint relationships.

[0014] Based on the interface function, electrical connection constraints and mechanical connection constraints are applied to the memory chip to be assembled to obtain the link constraint relationship.

[0015] Query the component structure of the memory chip to be assembled;

[0016] Based on the component structure, the assembly sequence constraints of the memory chip to be assembled are constructed;

[0017] Based on the positional constraints, the link constraints, and the assembly order constraints, the assembly constraints of the memory chip to be assembled are defined to obtain the assembly relationship.

[0018] Optionally, the step of searching for the preferred assembly path of the memory chip to be assembled based on the assembly relationship includes:

[0019] Construct the initial assembly path for the memory chip to be assembled;

[0020] Using the assembly relationship, the initial assembly path is filtered to obtain the filtered path;

[0021] A pheromone search is performed on the filtering path to obtain the search pheromone;

[0022] The search pheromone is updated using the following formula to obtain the updated pheromone:

[0023]

[0024] Where PM represents the update pheromone, and e represents the decay coefficient of the search pheromone. This represents the concentration of pheromones searched along path i to path j at time t. This represents the newly added pheromone concentration, and T represents the time when the search for pheromones began.

[0025] Based on the updated pheromone, the probability value of each path in the screening path is calculated, and the assembly path of the memory chip to be assembled is selected based on the probability value to obtain the preferred assembly path.

[0026] Optionally, calculating the probability value of each path being selected in the filtering path based on the updated pheromone includes:

[0027] Query the pheromone concentration of the updated pheromone;

[0028] Based on the pheromone concentration, the probability of each path being selected in the screening path is calculated using the following formula:

[0029]

[0030] Where p represents the probability value. Indicates pheromone concentration. Factors indicating the importance of pheromones Factors representing the importance of heuristic information This represents the set of the next paths that can be chosen from the current node k. This represents heuristic information, specifically the attractiveness from node k to node j. This represents the overall attractiveness of the path from node k to node j.

[0031] Optionally, the assembly collision test of the memory chip to be assembled in the small area includes:

[0032] The dimensions of the small area are queried to construct a precise test space for the memory chip to be assembled.

[0033] Construct collision detection rules for the memory chip to be assembled;

[0034] The preferred assembly path of the memory chip to be assembled is queried to simulate the assembly of the memory chip to be assembled;

[0035] During the assembly simulation process, the collision detection rules are used to perform collision detection on the memory chip to be assembled;

[0036] After evaluating the results of the collision detection, the assembly collision test of the memory chip to be assembled is realized.

[0037] Optionally, the step of performing a dynamic simulation of the assembly equipment based on the assembly equipment parameters includes:

[0038] Construct a physical model of the assembly equipment;

[0039] In the physical model, after defining the motion constraint relationships between the components of the assembly equipment, external loads and driving forces are applied to the physical model to obtain the preliminary setup model;

[0040] By setting the time range, time step, and integration algorithm of the preliminary model, the target dynamic model is obtained.

[0041] The assembly equipment is subjected to dynamic simulation using the target dynamic model.

[0042] Optionally, calculating the pose deviation of the pre-assembled part includes:

[0043] A high-precision three-dimensional coordinate system is set in the assembly station corresponding to the pre-assembled part;

[0044] Using pre-defined assembly requirements and the target assembly path, the preferred position and preferred orientation parameters of the pre-assembled parts are constructed.

[0045] The pre-assembled parts are visually positioned to obtain positioning parameters;

[0046] The preferred coordinates of the pre-assembled part are constructed in the three-dimensional coordinate system using the preferred position and the preferred attitude parameters;

[0047] The positioning parameters are used to construct the real-time coordinates of the pre-assembled part in the three-dimensional coordinate system;

[0048] Based on the preferred coordinates and the real-time coordinates, the pose deviation of the pre-assembled part is calculated.

[0049] Optionally, the step of performing chip packaging on the target assembly component using the target assembly path according to the target assembly equipment to obtain a preliminary packaged chip includes:

[0050] The target assembly equipment is initialized to obtain an initialized equipment;

[0051] The target assembly path is loaded into the initialization device to obtain the prepared device;

[0052] The target assembly parts are surface treated and pre-linked to obtain the prepared assembly parts;

[0053] The prepared assembly parts are packaged using the prepared equipment to obtain a preliminary packaged chip.

[0054] Optionally, the non-destructive testing of the preliminary processing chip includes:

[0055] Acquire X-ray images of the preliminary processing chip;

[0056] The X-ray image is enhanced to obtain an enhanced image;

[0057] Edge detection algorithms are used to perform edge detection on the enhanced image to identify the surface defect contours of the preliminary processing chip;

[0058] The quantitative characteristics of the surface defect profile are analyzed to detect the surface defect degree of the preliminary processing chip;

[0059] The enhanced image is used to identify the circuit wiring features of the preliminary processing chip;

[0060] After detecting the circuit integrity of the preliminary processing chip using the circuit wiring features, the non-destructive testing of the preliminary processing chip is completed.

[0061] Optionally, the step of integrating and packaging the quality classification chip to obtain the target packaged chip includes:

[0062] Configure the packaging platform for the quality classification chip;

[0063] The target packaged chip is packaged and deployed in the packaging platform to obtain a deployed chip;

[0064] The deployed chip is coated with a material to obtain a coated chip;

[0065] The coated chip is then dispensed with adhesive to obtain a dispensing chip;

[0066] The dispensing chip is then subjected to shell injection molding to obtain the target packaged chip.

[0067] To address the aforementioned problems, the present invention also provides a modular integrated packaging technology for a high-density assembly system of memory chips, the system comprising:

[0068] An assembly model building module is used to acquire the memory chip to be assembled and the packaging element, perform high-precision scanning on the memory chip to be assembled and the packaging element to acquire the corresponding geometric shape data, and construct an assembly model of the memory chip to be assembled based on the geometric shape data.

[0069] The path testing module is used to define assembly constraints for the memory chip to be assembled, obtain assembly relationships, search for the preferred assembly path of the memory chip to be assembled based on the assembly relationships, construct the assembly space of the memory chip to be assembled based on the preferred assembly path, divide the assembly space into multiple small area spaces, perform assembly collision tests on the memory chip to be assembled in the small area spaces, adjust the preferred assembly path based on the test results of the assembly collision tests to obtain an adjusted path, perform path tests on the adjusted path, and obtain the target assembly path when the path test results are excellent.

[0070] The device parameter configuration module is used to query the assembly path parameters of the target assembly path to construct the assembly device parameters of the assembly device corresponding to the memory chip to be assembled, perform dynamic simulation on the assembly device based on the assembly device parameters, and configure the assembly parameters of the assembly device based on the dynamic simulation results to obtain the target assembly device.

[0071] The chip preliminary packaging module is used to input the memory chip to be assembled and the packaging element to the assembly station to obtain a pre-assembled part, calculate the pose deviation of the pre-assembled part, adjust the pose of the pre-assembled part based on the pose deviation to obtain a target assembled part, and perform chip packaging on the target assembled part using the target assembly path according to the target assembly equipment to obtain a preliminary packaged chip.

[0072] A chip integration and packaging module is used to perform electrical performance testing on the pre-packaged chip. When the electrical performance test result is normal, the pre-packaged chip is subjected to packaging enhancement processing to obtain a pre-processed chip. The pre-processed chip is subjected to non-destructive testing. Based on the non-destructive testing results, the pre-processed chip is classified into quality categories to obtain quality-classified chips. The quality-classified chips are integrated and packaged to obtain a target packaged chip.

[0073] Compared to the problems described in the background technology, by obtaining precise geometric data through high-precision scanning of the memory chips and packaged components to be assembled, and constructing an assembly model, the assembly scheme can be evaluated in advance in a virtual environment. This avoids errors caused by unreasonable spatial layout and infeasible connection methods in actual production, thereby significantly improving assembly accuracy. Furthermore, by defining assembly constraints and establishing assembly relationships, the relative position, orientation, and matching requirements between the memory chips and packaged components are clarified, further ensuring assembly accuracy and ensuring that the final product meets design requirements. Assembly collision testing can check whether the memory chips and packaged components will collide or interfere in a small area under the predetermined preferred assembly path, identifying and resolving interference problems that may lead to assembly failure in advance, reducing the risk of errors during the assembly process. Furthermore, this embodiment of the invention constructs assembly equipment parameters based on the assembly path parameters of the target assembly path and performs dynamic simulation on the assembly equipment. This allows for the evaluation and optimization of equipment performance before actual manufacturing or debugging, avoiding equipment failures and quality problems, reducing production costs and risks. The assembly parameters are configured using the dynamic simulation results to obtain the target assembly equipment, ensuring that the equipment finally put into use can efficiently, stably, and accurately complete the memory chip assembly task. Furthermore, in this embodiment of the invention, by inputting the memory chip to be assembled and the packaging element into the assembly station to obtain the pre-assembled part, and calculating and adjusting the pose deviation to obtain the target assembled part, the pre-assembled part can be made close to the ideal state, meeting the high precision requirements of chip packaging; by using the target assembly equipment and the target assembly path to perform chip packaging on the target assembled part to obtain the preliminary packaged chip, the orderliness and high quality of chip packaging are guaranteed. Furthermore, by conducting electrical performance tests on the pre-packaged chip, this invention ensures that the electrical performance of the packaged chip meets design requirements, enabling it to function normally. Through packaging enhancement processing, the robustness and protective capabilities of the package are strengthened, extending the chip's lifespan and enhancing its stability and durability in different application scenarios. Moreover, by performing non-destructive testing on the packaged chip, this invention can detect microscopic defects and component misalignments within the package. Based on the test results, quality classification is performed to ensure that only chips meeting quality requirements enter the integrated packaging process, improving resource utilization efficiency and providing chips of different quality levels for different users or application scenarios. The quality-classified chips are then integrated and packaged to obtain the target packaged chip, completing the final packaging. By integrating multiple functional modules, the chip's functionality and applicability are improved, providing high-quality core components for electronic product manufacturing, thereby improving the high-density assembly quality of memory chips. Attached Figure Description

[0074] Figure 1 This is a flowchart illustrating a high-density assembly method for memory chips using modular integrated packaging technology provided in an embodiment of the present invention.

[0075] Figure 2This is a schematic diagram of a module for implementing the modular integrated packaging technology for high-density assembly of memory chips according to an embodiment of the present invention.

[0076] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0077] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0078] This application provides a modular integrated packaging technology for high-density assembly of memory chips. The execution entity of this method includes, but is not limited to, at least one electronic device configured to execute the method provided in this application, such as a server or a terminal. In other words, the modular integrated packaging technology for high-density assembly of memory chips can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0079] Example 1:

[0080] Reference Figure 1 The diagram shown is a flowchart illustrating a high-density assembly method for memory chips using modular integrated packaging technology according to an embodiment of the present invention. In this embodiment, the high-density assembly method for memory chips using modular integrated packaging technology includes:

[0081] S1. Obtain the memory chip to be assembled and the packaging element, perform high-precision scanning on the memory chip to be assembled and the packaging element to obtain the corresponding geometric shape data, and construct the assembly model of the memory chip to be assembled based on the geometric shape data.

[0082] The present invention provides a physical object for subsequent assembly processes by obtaining the memory chip to be assembled and the packaging components.

[0083] The term "memory chip to be assembled" refers to a bare memory chip die that has not yet undergone packaging. It is the core component for storing data, possessing basic data storage and read / write functions. However, it is relatively fragile in its unpackaged state and requires packaging protection to operate stably in various electronic devices. Examples include common NAND flash memory chips and DRAM chips, which, after completing the chip manufacturing process, are now memory chips awaiting assembly and further packaging. The term "packaging components" refers to various parts used to package the memory chip. These components provide physical protection, electrical connections, and heat dissipation for the memory chip.

[0084] Furthermore, by performing high-precision scanning on the memory chip to be assembled and the packaged component to obtain corresponding geometric data, the actual shape and size of the component can be understood, providing a reliable basis for constructing an accurate assembly model.

[0085] Optionally, the geometric shape data can be obtained by using a high-precision 3D laser scanner, placing the memory chip and packaged components to be assembled within its scanning range, then using the scanner to emit a laser beam onto the object surface, accurately measuring the spatial position of each point on the object surface based on the laser reflection time and angle, collecting point data to form a point cloud, and then using an algorithm to convert the point cloud data into precise geometric shape data, thereby obtaining the 3D geometric shape information of the memory chip and packaged components to be assembled.

[0086] Furthermore, by constructing an assembly model of the memory chip to be assembled based on the geometric data, the embodiments of the present invention can evaluate different assembly schemes in a virtual environment, identify potential problems in advance, such as unreasonable spatial layout or infeasible connection methods, thereby avoiding errors in actual production, saving time and costs, and improving the efficiency and quality of product research and development and production.

[0087] The assembly model refers to a virtual representation of the memory chip and its packaging components. It is created based on precise geometric data and can be constructed using three-dimensional laser scanning technology. By irradiating the memory chip and packaging components to be assembled with a laser beam, and by measuring the time difference between the laser beam's emission and reflection, as well as the angle of the laser, the three-dimensional coordinates of each point on the object's surface are calculated, generating a large amount of point cloud data.

[0088] S2. Define assembly constraints for the memory chip to be assembled to obtain assembly relationships. Based on the assembly relationships, search for the preferred assembly path for the memory chip to be assembled. Based on the preferred assembly path, construct the assembly space for the memory chip to be assembled. Divide the assembly space into multiple small regions. Perform an assembly collision test on the memory chip to be assembled in each small region. Based on the test results of the assembly collision test, adjust the preferred assembly path to obtain an adjusted path. Perform a path test on the adjusted path. When the path test result is excellent, obtain the target assembly path.

[0089] The present invention defines assembly constraints for the memory chip to be assembled, thereby clarifying the relative position, orientation, and matching requirements between the memory chip and other packaged components during assembly. This improves the accuracy and reliability of the assembly, ensuring that the final product meets the design requirements.

[0090] As an embodiment of the present invention, the step of defining assembly constraints for the memory chip to be assembled to obtain assembly relationships includes: identifying the component features and interface functions of the memory chip to be assembled; performing component fitting constraints and component alignment constraints on the memory chip to be assembled based on the component features to obtain positional constraint relationships; performing electrical connection constraints and mechanical connection constraints on the memory chip to be assembled based on the interface functions to obtain link constraint relationships; querying the component structure of the memory chip to be assembled; constructing assembly sequence constraints for the memory chip to be assembled based on the component structure; and defining assembly constraints for the memory chip to be assembled based on the positional constraint relationships, the link constraint relationships, and the assembly sequence constraints to obtain assembly relationships.

[0091] Optionally, the component characteristics can be identified by consulting product manuals and design drawings of the memory chip and packaged components, and by using high-precision measuring tools to accurately measure the component's size, shape, number of pins, and pin spacing. The interface functions can be determined by querying the functional pins of the memory chip (such as data, power, and control pins) and their functions. The positional constraint relationship for the memory chip to be assembled based on the component characteristics can be obtained by importing the models of the memory chip and packaged components into 3D modeling or assembly planning software. For component bonding constraints, the overlap relationship between the bottom surface of the memory chip and the upper surface of the substrate can be set. For component alignment constraints, the alignment relationship between the edge of the memory chip and specific marks or lines on the substrate can be set, thus obtaining a precise positional constraint relationship. The electrical connection constraints can be obtained by associating the memory chip pins with the corresponding pads on the substrate in 3D software, setting electrical conductivity requirements and electrical performance parameters. The mechanical connection constraints can be obtained by determining, for example, the connection method between the heat sink and the memory chip, specifying its connection position, connection strength, etc. The assembly sequence constraint can be determined by analyzing the structure of the memory chip and its packaged components, and based on the ease of assembly and logical order, in the assembly planning software, which component to assemble first and which to assemble later. For example, the chip can be fixed on the substrate first, and then the pin connection settings can be configured.

[0092] Furthermore, by searching for the preferred assembly path of the memory chip to be assembled based on the assembly relationship, the assembly constraints of the components can be transformed into operable assembly steps, making the abstract assembly relationship a specific sequence of assembly actions, and providing guidance for the operation of automated assembly equipment.

[0093] As an embodiment of the present invention, the step of searching for the preferred assembly path of the memory chip to be assembled based on the assembly relationship includes: constructing an initial assembly path for the memory chip to be assembled; using the assembly relationship to perform path filtering on the initial assembly path to obtain a filtered path; performing pheromone search on the filtered path to obtain a search pheromone; and updating the search pheromone using the following formula to obtain an updated pheromone:

[0094]

[0095] Where PM represents the update pheromone, and e represents the decay coefficient of the search pheromone. This represents the concentration of pheromones searched along path i to path j at time t. This represents the newly added pheromone concentration, and T represents the time when the search for pheromones began.

[0096] Based on the updated pheromone, the probability value of each path in the screening path is calculated, and the assembly path of the memory chip to be assembled is selected based on the probability value to obtain the preferred assembly path.

[0097] The search pheromone refers to an information indicator used to guide the search process in the pheromone search algorithm.

[0098] Optionally, the initial assembly path can be formed by analyzing the chip's structure and the conventional logic of assembly sequence, connecting the assembly order of each component. For example, for a chip with multiple memory cells and connection modules, it might be constructed by assembling the core memory cells first, followed by connecting the peripheral circuit modules. The filtering path can be based on the assembly relationship of the memory chip, such as physical connection requirements between components, electrical connection rules, space constraints, and other limitations, to filter the initial assembly path, removing assembly steps or connection methods that do not conform to the assembly relationship, and retaining only paths that meet all assembly conditions. For example, if the installation position of a component must be after another component, then assembly paths that do not conform to this sequence will be excluded. The pheromone search of the filtered path to obtain the search pheromone can be implemented using an ant colony algorithm.

[0099] Furthermore, as an optional embodiment of the present invention, calculating the probability value of each path in the filtering path being selected based on the updated pheromone includes: querying the pheromone concentration of the updated pheromone, and calculating the probability value of each path in the filtering path being selected based on the pheromone concentration using the following formula:

[0100]

[0101] Where p represents the probability value. Indicates pheromone concentration. Factors indicating the importance of pheromones Factors representing the importance of heuristic information This represents the set of the next paths that can be chosen from the current node k. This represents heuristic information, specifically the attractiveness from node k to node j. This represents the overall attractiveness of the path from node k to node j.

[0102] The pheromone concentration refers to a quantitative indicator used in pheromone algorithms (such as ant colony algorithms) to represent the attractiveness or priority of different paths or decision options.

[0103] The present invention, by constructing the assembly space of the memory chip to be assembled based on the preferred assembly path, can visualize and quantify the assembly path in space, extending the assembly process from planar, linear operation steps to a three-dimensional operation scenario with spatial range, providing a spatial basis for subsequent segmentation and collision testing.

[0104] The assembly space refers to the three-dimensional spatial area planned to complete the chip assembly operation when assembling the memory chip to be assembled, based on the preferred assembly path and taking into account factors such as the physical size, shape, installation position, connection requirements, operating range of the operating tools, and accessibility of personnel or robot arms.

[0105] Optionally, the assembly space can be constructed by analyzing the preferred assembly path, determining the physical space requirements of the components, planning the layout of the assembly space, considering the operating space and tool requirements, and finally verifying the construction through simulation.

[0106] The present invention divides the assembly space into multiple small areas, which facilitates the individual management and inspection of each small area, making subsequent collision tests more accurate and efficient.

[0107] Furthermore, by performing an assembly collision test on the memory chip to be assembled in the small area space, the embodiments of the present invention can check whether collisions or interferences will occur between the memory chip and the packaged components during the assembly process in each small area space under a predetermined preferred assembly path, thereby discovering and resolving interference problems that may lead to assembly failure in advance.

[0108] As an embodiment of the present invention, the assembly collision test of the memory chip to be assembled in the small area space includes: querying the size information of the small area space to construct a precise test space for the memory chip to be assembled; constructing collision detection rules for the memory chip to be assembled; querying the preferred assembly path for the memory chip to be assembled to simulate the assembly of the memory chip; using the collision detection rules to perform collision detection on the memory chip to be assembled during the assembly simulation; and evaluating the detection results of the collision detection to realize the assembly collision test of the memory chip to be assembled.

[0109] The collision detection rules refer to a series of judgment criteria and principles established to ensure that there are no physical collisions or mutual interferences between components and between components and the test space boundary during the assembly collision test of the memory chips to be assembled.

[0110] Optionally, the precise test space can be obtained by acquiring dimensional information such as the length, width, height, and shape of a small area using measurement tools or stored design documents, and then created using this dimensional data in computer-aided design (CAD) software or simulation tools. The collision detection rules can be obtained by determining safe distance standards between different components, defining which component parts cannot overlap or contact, and considering the physical characteristics of the components and assembly operations, setting collision rules such as those between wires and components, and between chips. The evaluation of the collision detection results can be achieved by analyzing the collision detection results to identify the location of the collision and the components involved.

[0111] In this embodiment of the invention, the preferred assembly path is adjusted based on the test results of the assembly collision test. The adjusted path can modify and optimize the original preferred assembly path according to the problems found in the collision test, so as to improve the feasibility and safety of the assembly path and ensure the smooth progress of the actual assembly process.

[0112] Optionally, the process of adjusting the preferred assembly path based on the test results of the assembly collision test to obtain the adjusted path is as follows: First, analyze the results of the assembly collision test to find the assembly steps that cause the collision and the position information of the components involved; then, based on this information, modify the assembly order, position or direction of the corresponding components in the preferred assembly path; finally, regenerate an adjusted path to avoid collision, which can be achieved by adjusting the order of component assembly or changing their position in the assembly space.

[0113] In this embodiment of the invention, by performing path testing on the adjusted path, when the test result of the path test is excellent, the obtained target assembly path can ensure the smooth progress of the actual production process, and also provide a reliable basis for subsequent equipment parameter configuration and actual assembly operations.

[0114] It should be explained that when the test result of the path test is excellent, it means that there is no collision or the degree of collision is within an acceptable range when the memory chip to be assembled is simulated. The settings need to be combined with the actual application. For example, if the number of collisions is less than a fixed number or the physical offset caused to the memory chip to be assembled is within a preset range when there is a collision.

[0115] S3. Query the assembly path parameters of the target assembly path to construct the assembly equipment parameters of the assembly equipment corresponding to the memory chip to be assembled. Perform dynamic simulation on the assembly equipment based on the assembly equipment parameters. Configure the assembly parameters of the assembly equipment based on the dynamic simulation results to obtain the target assembly equipment.

[0116] In this embodiment of the invention, by querying the assembly path parameters of the target assembly path, the assembly equipment parameters of the assembly equipment corresponding to the memory chip to be assembled can be constructed, which can map the requirements of the assembly path to the assembly equipment, ensuring that the performance of the equipment matches the assembly task.

[0117] The assembly path parameters refer to a series of quantitative data describing the movement and operation details of the memory chip and packaged components during the assembly process, such as position coordinates, movement sequence parameters, movement speed, and time parameters.

[0118] Optionally, the assembly equipment parameters can be extracted using the software module of the memory chip assembly system, from which various data of the target assembly path are extracted, including parameters such as position, speed, acceleration, and movement sequence. Then, based on the extracted assembly path parameters, combined with the size, weight, and assembly process requirements of the memory chip, an algorithm or rule base is used to convert them into the performance parameters required by the assembly equipment (such as a robotic arm, conveying device, etc.), such as the working range, movement speed range, and load capacity of the robotic arm.

[0119] Furthermore, by performing dynamic simulation on the assembled equipment based on the assembly equipment parameters, the embodiments of the present invention can evaluate and optimize the equipment performance before actual manufacturing or debugging, thereby avoiding serious equipment failures or quality problems in actual production and reducing production costs and risks.

[0120] As an embodiment of the present invention, the dynamic simulation of the assembly equipment based on the assembly equipment parameters includes: constructing a physical model of the assembly equipment; defining the motion constraint relationships between the components of the assembly equipment in the physical model; applying external loads and driving forces to the physical model to obtain a preliminary setup model; setting the time range, time step, and integration algorithm of the preliminary setup model to obtain a target dynamic model; and using the target dynamic model to perform dynamic simulation of the assembly equipment.

[0121] The external load refers to the forces acting on the equipment and its operated components during the assembly of memory chips, in addition to the equipment's own driving force. The driving force refers to the force or torque that causes the assembly equipment to move according to the predetermined assembly path and motion requirements, and is the main power source for the equipment to work normally. The time range refers to the time period from the start time to the end time of the simulation in the dynamic simulation process. This time period covers the entire or part of the working process of the assembly equipment. The time step refers to the step size of dividing the time range into multiple discrete time intervals in the dynamic simulation process. The integral algorithm refers to the mathematical method used by the dynamic simulation software to solve the dynamic equations, such as the Euler method.

[0122] Optionally, the physical model can be created using professional 3D modeling software (such as SolidWorks). The motion constraints can be manipulated within the interface of the dynamics simulation software, targeting each connection point of the physical model. For rotary joints, their rotational degrees of freedom and angle ranges are set; for translational joints, the translational direction and stroke range are specified. For example, in a robotic arm model, the rotation type (such as pitch, yaw, etc.) and allowable rotation angle range for each joint are clearly defined. The initial model setup can be achieved by adding external loads to the model based on the actual force conditions during assembly. For example, for a robotic arm, the weight of the components is considered as a load applied to the end effector; for a conveyor belt, the weight of the components and friction are considered as loads applied to the conveyor belt. Simultaneously, the magnitude and direction of the driving force are determined according to the assembly equipment parameters, for example, by adding motor torque at the robotic arm joints and motor rotation torque at the conveyor belt rollers.

[0123] Furthermore, in this embodiment of the invention, the assembly parameters of the assembly equipment are configured based on the dynamic simulation results, so that the target assembly equipment can ensure that the final assembly equipment can efficiently, stably and accurately complete the assembly task of memory chips.

[0124] Optionally, the target assembly equipment can be obtained by inputting the motion parameters of the assembly equipment during simulated operation into the equipment and setting them.

[0125] S4. Input the memory chip to be assembled and the packaging element to the assembly station to obtain a pre-assembled part. Calculate the pose deviation of the pre-assembled part. Adjust the pose of the pre-assembled part based on the pose deviation to obtain a target assembled part. According to the target assembly equipment, use the target assembly path to package the target assembled part into a chip to obtain a preliminary packaged chip.

[0126] The present invention, by inputting the memory chip to be assembled and the packaging element to the assembly station, obtains pre-assembled parts that clearly define the physical location of the assembly work, ensuring that all required components are concentrated in an easily operable space, laying the foundation for orderly and efficient assembly operations, and is a necessary prerequisite for realizing memory chip packaging.

[0127] Optionally, the process of inputting the memory chip to be assembled and the packaging element to the assembly station to obtain pre-assembled parts is as follows: using an automated guided vehicle (AGV) or conveyor belt system to transport the memory chip to be assembled and the packaging element from the warehouse or the previous process station to the designated assembly station, and then, in the assembly station, using a vision recognition system or a mechanical positioning device to place the memory chip and the packaging element in a predetermined position.

[0128] In this embodiment of the invention, the difference between the current actual position and orientation of the pre-assembled part (i.e., the assembly of the memory chip and the packaged component to be assembled) and the ideal position and orientation can be determined by calculating the pose deviation of the pre-assembled part, so as to facilitate position adjustment.

[0129] As an embodiment of the present invention, the calculation of the pose deviation of the pre-assembled part includes: setting a high-precision three-dimensional coordinate system in the assembly station corresponding to the pre-assembled part; constructing the preferred position and preferred posture parameters of the pre-assembled part using the pre-set assembly requirements and the target assembly path; performing visual positioning on the pre-assembled part to obtain positioning parameters; constructing the preferred coordinates of the pre-assembled part in the three-dimensional coordinate system using the preferred position and the preferred posture parameters; constructing the real-time coordinates of the pre-assembled part in the three-dimensional coordinate system using the positioning parameters; and calculating the pose deviation of the pre-assembled part based on the preferred coordinates and the real-time coordinates.

[0130] Optionally, the three-dimensional coordinate system can be established by selecting a fixed position at the assembly station as the origin, such as the center of the robotic arm base or a corner of the assembly platform. Then, laser measurement and calibration tools are used to precisely determine the directions and unit lengths of the x, y, and z axes to ensure they meet the required accuracy. Alternatively, high-precision linear guides and angle measuring instruments can be used to precisely calibrate and mark the x, y, and z axes. The preferred position can store the design specifications and target assembly path information of the chip and packaged components, determining, for example, the coordinates of the chip center and pin positions in three-dimensional space. The preferred attitude parameters can be determined according to the assembly process requirements, such as the angular relationship between the chip's plane and the coordinate axes, obtained through theoretical calculations or extracted from a virtual assembly model. The positioning parameters can be obtained by visually positioning the pre-assembled parts using a vision sensor and then extracting the parameters generated from the positioning. The preferred coordinates can be represented in the established three-dimensional coordinate system based on pre-set ideal positions and attitude information, obtaining the coordinates and rotation angles of the pre-assembled parts on the x, y, and z axes under ideal conditions. The real-time coordinates can be obtained by accurately representing the positioning parameters obtained from visual positioning, i.e., the transformed actual physical position information, in the same three-dimensional coordinate system. The pose deviation can be obtained by subtracting the coordinate values ​​of the preferred coordinates and the real-time coordinates on the x, y, and z axes, respectively.

[0131] In this embodiment of the invention, the pose adjustment of the pre-assembled part based on the pose deviation is performed to obtain the target assembled part, which can correct the position and orientation of the pre-assembled part to make it as close as possible to the ideal state, so as to meet the high precision requirements of chip packaging.

[0132] Optionally, the process of adjusting the pose of the pre-assembled part based on the pose deviation to obtain the target assembled part is as follows: using precision motion control equipment (such as a high-precision multi-axis robotic arm or electric translation stage), the required displacement and rotation amounts are determined according to the calculated pose deviation information. For example, if the pose deviation indicates that the pre-assembled part has shifted a certain distance in the x-axis direction, the robotic arm or translation stage is controlled to move accordingly in the x-axis direction; for posture deviation, the joint angles of the robotic arm are controlled to rotate and adjust.

[0133] In this embodiment of the invention, the target assembly parts are chip packaged using the target assembly path according to the target assembly equipment to obtain a preliminary packaged chip. This chip can perform actual packaging operations on the target assembly parts after pose adjustment, combining the memory chip and the packaging element in a predetermined manner to form a preliminary packaged chip.

[0134] As an embodiment of the present invention, the step of chip packaging the target assembly parts according to the target assembly equipment and the target assembly path to obtain a preliminary packaged chip includes: initializing the target assembly equipment to obtain an initialization equipment; loading the target assembly path into the initialization equipment to obtain a prepared equipment; performing surface treatment and pre-linking on the target assembly parts to obtain a prepared assembly part; and packaging the prepared assembly part using the prepared equipment to obtain a preliminary packaged chip.

[0135] Optionally, the initialization device can be obtained by starting the target assembly device, including turning on the power, checking whether the hardware connection of the device is normal, and then performing self-tests on each subsystem of the device, such as checking the joint range of motion of the robotic arm, checking the function of the heating element and welding head of the welding equipment, and calibrating the sensors, to ensure that the device is in a normal and operable state. The prepared device is obtained by inputting the target assembly path information (including motion trajectory, action sequence, speed, acceleration and other parameters) required for memory chip assembly into the device through the device's control system. The prepared assembly parts can be obtained by performing surface treatment on the target assembly parts, such as cleaning the surface of the memory chip and packaging elements to remove contaminants and oxides that may affect the packaging quality, and then performing a pre-linking operation to initially align and fix the memory chip and substrate, using temporary fixing jigs or adhesives to ensure that they will not shift during the subsequent packaging process.

[0136] S5. Perform electrical performance testing on the preliminary packaged chip. When the electrical performance test result is normal, perform packaging enhancement processing on the preliminary packaged chip to obtain a preliminary processed chip. Perform non-destructive testing on the preliminary processed chip. Based on the non-destructive testing results, classify the preliminary processed chip according to quality to obtain a quality-classified chip. Perform integrated packaging on the quality-classified chip to obtain a target packaged chip.

[0137] The embodiments of the present invention ensure that the electrical performance of the pre-packaged chip meets the design requirements and can function normally by performing electrical performance tests on the pre-packaged chip.

[0138] Optionally, the process of performing electrical performance testing on the pre-packaged chip is as follows: prepare and calibrate testing equipment such as a semiconductor parameter analyzer and oscilloscope; install the pre-packaged chip in the test socket and connect the test probe to the corresponding pin; perform tests on conductivity, I-V characteristics, signal transmission, and power performance; analyze the data and compare it with the specifications to determine whether the electrical performance is qualified.

[0139] In this embodiment of the invention, when the electrical performance test results are normal, the pre-packaged chip is subjected to a packaging enhancement process. The resulting pre-processed chip can enhance the robustness and protection of the packaging, prevent the influence of external environment (such as moisture, dust, mechanical vibration, etc.) on the internal circuit of the chip, extend the service life of the chip, enhance the stability and durability of the chip in different application scenarios, and ensure that the chip will not fail due to packaging damage during subsequent use and storage.

[0140] The phrase "when the electrical performance test results are normal" means that after the electrical performance test, all electrical indicators of the initially packaged chip meet the established design standards and quality requirements. Specifically, this includes no short circuits or open circuits between pins, normal I-V characteristic curves, compliant signal transmission parameters, and power supply performance within the specified range.

[0141] Optionally, the preliminary processing chip can be achieved by thermoforming the preliminary packaged chip.

[0142] The embodiments of the present invention can detect whether there are microscopic defects such as voids, delamination, and cracks that are invisible to the naked eye inside the package by performing non-destructive testing on the chip in the preliminary processing stage, and at the same time observe whether the position of the components inside the chip has shifted.

[0143] As one embodiment of the present invention, the non-destructive testing of the preliminary processing chip includes: acquiring an X-ray image of the preliminary processing chip; performing image enhancement on the X-ray image to obtain an enhanced image; performing edge detection on the enhanced image using an edge detection algorithm to identify the surface defect contours of the preliminary processing chip; analyzing the quantitative features of the surface defect contours to detect the surface defect degree of the preliminary processing chip; identifying the circuit wiring features of the preliminary processing chip using the enhanced image; and after detecting the circuit integrity of the preliminary processing chip using the circuit wiring features, completing the non-destructive testing of the preliminary processing chip.

[0144] Optionally, the X-ray image can be acquired using a high-precision X-ray imaging device. The enhanced image can be obtained by importing the acquired X-ray image into image processing software. Image details can be highlighted by adjusting basic parameters such as contrast and brightness. Filtering techniques, such as median filtering, can also be used to remove noise and make the image clearer. The surface defect contour can be obtained using a suitable edge detection algorithm, such as the Canny edge detection algorithm. By setting algorithm parameters, such as thresholds, the enhanced image is processed to identify areas in the image with drastic grayscale changes. These areas may be the edges of chip surface defects, thus outlining the surface defect contour. The process of analyzing the quantitative features of the surface defect contour to detect surface defects in the pre-processed chip involves measuring the length, area, shape, and other quantitative features of the surface defect contour. By comparing it with pre-set standard defect features or calculating the defect level using a mathematical model, it is determined whether the chip surface defects are within an acceptable range, thus assessing the surface quality. The circuit wiring features can be obtained by using image recognition algorithms to distinguish the circuit wiring paths, connection points, and other features in the enhanced image.

[0145] Furthermore, in this embodiment of the invention, the preliminary processed chip is classified according to the test results based on the non-destructive testing. The chips with different quality levels can be processed differently to ensure that only chips that meet the quality requirements will enter the final integration and packaging process, thereby improving resource utilization efficiency, reducing costs, and providing different quality levels of chip selection for different users or different application scenarios.

[0146] Optionally, the process of classifying the pre-processed chip based on the non-destructive testing results to obtain quality-classified chips is as follows: First, different quality standards are set according to the surface defects and circuit integrity of the chip in the non-destructive testing results; then, the test results are compared with these standards, and chips with no obvious defects and complete circuits are classified as high-quality products, chips with some problems but not affecting the main functions are classified as second-grade products, and chips with serious defects are classified as substandard products; finally, the chips are marked accordingly to complete the quality classification.

[0147] Furthermore, in this embodiment of the invention, by integrating and packaging the quality-classified chips, a target packaged chip is obtained, which can complete the final packaging process of the chip, integrate multiple functional modules together, facilitate user use, improve the functionality and applicability of the chip, meet the integration needs of different systems, and ultimately form a complete target packaged chip, providing high-quality core components for the production of electronic products.

[0148] As an embodiment of the present invention, the step of integrating and packaging the quality classification chip to obtain a target packaged chip includes: configuring a packaging platform for the quality classification chip, packaging and deploying the target packaged chip in the packaging platform to obtain a deployment chip, coating the deployment chip with a material to obtain a coated chip, dispensing adhesive onto the coated chip to obtain a dispensing chip, and performing shell injection molding on the dispensing chip to obtain the target packaged chip.

[0149] Optionally, the packaging platform can be obtained by debugging and calibrating equipment such as packaging molds, dispensing machines, pick-and-place machines, wire bonding machines, and soldering machines. The chip deployment can be achieved by placing selected chips according to a predetermined layout and design within a packaging mold or on a substrate, then using a pick-and-place machine to precisely mount the chips to designated positions, and finally using a wire bonding machine to bond the chip pins or pads to external circuitry or pins. Material coating of the deployed chip can be performed using a spin coater, dispensing of the coated chip can be done using a dispensing machine, and injection molding of the dispensed chip's casing can be performed using an injection molding machine.

[0150] Example 2:

[0151] like Figure 2 The diagram shown is a functional block diagram of a high-density assembly system for memory chips using a modular integrated packaging technology according to the present invention.

[0152] The modular integrated packaging technology of this invention provides a high-density assembly system 200 for memory chips, which can be installed in electronic devices. Depending on the functions implemented, the modular integrated packaging technology for memory chips can include an assembly model building module 201, a path testing module 202, a device parameter configuration module 203, a chip preliminary packaging module 204, and a chip integrated packaging module 205. The module described in this invention can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and perform a fixed function, stored in the memory of the electronic device.

[0153] In this embodiment of the invention, the functions of each module / unit are as follows:

[0154] The assembly model construction module 201 is used to acquire the memory chip to be assembled and the packaging element, perform high-precision scanning on the memory chip to be assembled and the packaging element to acquire the corresponding geometric shape data, and construct the assembly model of the memory chip to be assembled based on the geometric shape data.

[0155] The path testing module 202 is used to define assembly constraints for the memory chip to be assembled, obtain assembly relationships, search for the preferred assembly path of the memory chip to be assembled based on the assembly relationships, construct the assembly space of the memory chip to be assembled based on the preferred assembly path, divide the assembly space into multiple small area spaces, perform assembly collision tests on the memory chip to be assembled in the small area spaces, adjust the preferred assembly path based on the test results of the assembly collision tests to obtain an adjusted path, perform path tests on the adjusted path, and obtain the target assembly path when the path test results are excellent.

[0156] The device parameter configuration module 203 is used to query the assembly path parameters of the target assembly path to construct the assembly device parameters of the assembly device corresponding to the memory chip to be assembled, perform dynamic simulation on the assembly device based on the assembly device parameters, and configure the assembly parameters of the assembly device based on the dynamic simulation results to obtain the target assembly device.

[0157] The chip preliminary packaging module 204 is used to input the memory chip to be assembled and the packaging element to the assembly station to obtain a pre-assembled part, calculate the pose deviation of the pre-assembled part, adjust the pose of the pre-assembled part based on the pose deviation to obtain a target assembled part, and perform chip packaging on the target assembled part using the target assembly path according to the target assembly equipment to obtain a preliminary packaged chip.

[0158] The chip integration and packaging module 205 is used to perform electrical performance testing on the preliminary packaged chip. When the electrical performance test result is normal, the preliminary packaged chip is subjected to packaging enhancement processing to obtain a preliminary processed chip. The preliminary processed chip is subjected to non-destructive testing. Based on the non-destructive testing results, the preliminary processed chip is classified into quality categories to obtain quality-classified chips. The quality-classified chips are integrated and packaged to obtain the target packaged chip.

[0159] In detail, the modular integrated packaging technology described in this embodiment of the invention is used in the high-density assembly system 200 for memory chips, where each module employs the same approach as described above. Figure 1 The modular integrated packaging technology described herein is the same as the high-density assembly method for memory chips and can produce the same technical effect, so it will not be elaborated here.

[0160] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A modular integrated packaging technology for high-density assembly of memory chips, characterized in that, The method includes: The process involves acquiring the memory chip to be assembled and the packaging element, performing high-precision scanning on the memory chip to be assembled and the packaging element to obtain corresponding geometric shape data, and constructing an assembly model of the memory chip to be assembled based on the geometric shape data. Assembly constraints are defined for the memory chip to be assembled to obtain assembly relationships. Based on the assembly relationships, the preferred assembly path for the memory chip to be assembled is searched. Based on the preferred assembly path, the assembly space for the memory chip to be assembled is constructed. The assembly space is divided into multiple small regions. The memory chip to be assembled is subjected to an assembly collision test in the small regions. Based on the test results of the assembly collision test, the preferred assembly path is adjusted to obtain an adjusted path. The adjusted path is subjected to a path test. When the path test result is excellent, the target assembly path is obtained. The assembly path parameters of the target assembly path are queried to construct the assembly equipment parameters of the assembly equipment corresponding to the memory chip to be assembled. Based on the assembly equipment parameters, the assembly equipment is subjected to dynamic simulation. Based on the dynamic simulation results, the assembly equipment is configured with assembly parameters to obtain the target assembly equipment. The memory chip to be assembled and the packaging element are input to the assembly station to obtain a pre-assembled part. The pose deviation of the pre-assembled part is calculated, and the pose of the pre-assembled part is adjusted based on the pose deviation to obtain a target assembled part. According to the target assembly equipment, the target assembled part is packaged into a chip using the target assembly path to obtain a preliminary packaged chip. Electrical performance testing is performed on the pre-packaged chip. When the electrical performance test result is normal, the pre-packaged chip undergoes packaging enhancement processing to obtain a pre-processed chip. Non-destructive testing is performed on the pre-processed chip. Based on the non-destructive testing results, the pre-processed chip is classified into quality categories to obtain quality-classified chips. The quality-classified chips are then integrated and packaged to obtain the target packaged chip.

2. The modular integrated packaging technology as described in claim 1 for high-density assembly of memory chips, characterized in that, The process of defining assembly constraints for the memory chips to be assembled to obtain assembly relationships includes: Identify the component features and interface functions of the memory chip to be assembled; Based on the component characteristics, component bonding constraints and component alignment constraints are applied to the memory chip to be assembled to obtain positional constraint relationships. Based on the interface function, electrical connection constraints and mechanical connection constraints are applied to the memory chip to be assembled to obtain the link constraint relationship. Query the component structure of the memory chip to be assembled; Based on the component structure, the assembly sequence constraints of the memory chip to be assembled are constructed; Based on the positional constraints, the link constraints, and the assembly order constraints, the assembly constraints of the memory chip to be assembled are defined to obtain the assembly relationship.

3. The modular integrated packaging technology as described in claim 1 for high-density assembly of memory chips, characterized in that, The step of searching for the preferred assembly path of the memory chip to be assembled based on the assembly relationship includes: Construct the initial assembly path for the memory chip to be assembled; Using the assembly relationship, the initial assembly path is filtered to obtain the filtered path; A pheromone search is performed on the filtering path to obtain the search pheromone; The search pheromone is updated using the following formula to obtain the updated pheromone: Where PM represents the update pheromone, and e represents the decay coefficient of the search pheromone. This represents the concentration of pheromones searched along path i to path j at time t. This represents the newly added pheromone concentration, and T represents the time when the search for pheromones began. Based on the updated pheromone, the probability value of each path in the screening path is calculated, and the assembly path of the memory chip to be assembled is selected based on the probability value to obtain the preferred assembly path.

4. The modular integrated packaging technology as described in claim 3 for high-density assembly of memory chips, characterized in that, The step of calculating the probability value of each path being selected in the filtering path based on the updated pheromone includes: Query the pheromone concentration of the updated pheromone; Based on the pheromone concentration, the probability of each path being selected in the screening path is calculated using the following formula: Where p represents the probability value. Indicates pheromone concentration. Factors indicating the importance of pheromones Factors representing the importance of heuristic information This represents the set of the next paths that can be chosen from the current node k. This represents heuristic information, specifically the attractiveness from node k to node j. This represents the overall attractiveness of the path from node k to node j.

5. The modular integrated packaging technology as described in claim 1 for high-density assembly of memory chips, characterized in that, The assembly collision test of the memory chip to be assembled in the small area includes: The dimensions of the small area are queried to construct a precise test space for the memory chip to be assembled. Construct collision detection rules for the memory chip to be assembled; The preferred assembly path of the memory chip to be assembled is queried to simulate the assembly of the memory chip to be assembled; During the assembly simulation process, the collision detection rules are used to perform collision detection on the memory chip to be assembled; After evaluating the results of the collision detection, the assembly collision test of the memory chip to be assembled is realized.

6. The modular integrated packaging technology as described in claim 1 for high-density assembly of memory chips, characterized in that, The dynamic simulation of the assembly equipment based on the assembly equipment parameters includes: Construct a physical model of the assembly equipment; In the physical model, after defining the motion constraint relationships between the components of the assembly equipment, external loads and driving forces are applied to the physical model to obtain the preliminary setup model; By setting the time range, time step, and integration algorithm of the initial model, the target dynamic model is obtained. The assembly equipment is subjected to dynamic simulation using the target dynamic model.

7. The modular integrated packaging technology as described in claim 1 for high-density assembly of memory chips, characterized in that, The calculation of the pose deviation of the pre-assembled part includes: A high-precision three-dimensional coordinate system is set in the assembly station corresponding to the pre-assembled part; Using pre-defined assembly requirements and the target assembly path, the preferred position and preferred orientation parameters of the pre-assembled parts are constructed; The pre-assembled parts are visually positioned to obtain positioning parameters; The preferred coordinates of the pre-assembled part are constructed in the three-dimensional coordinate system using the preferred position and the preferred attitude parameters; The positioning parameters are used to construct the real-time coordinates of the pre-assembled part in the three-dimensional coordinate system; Based on the preferred coordinates and the real-time coordinates, the pose deviation of the pre-assembled part is calculated.

8. The modular integrated packaging technology as described in claim 1 for high-density assembly of memory chips, characterized in that, The step of performing chip packaging on the target assembly parts according to the target assembly equipment and the target assembly path to obtain a preliminary packaged chip includes: The target assembly equipment is initialized to obtain an initialized equipment; The target assembly path is loaded into the initialization device to obtain the prepared device; The target assembly parts are surface treated and pre-linked to obtain the prepared assembly parts; The prepared assembly parts are packaged using the prepared equipment to obtain a preliminary packaged chip.

9. The modular integrated packaging technology as described in claim 1 for high-density assembly of memory chips, characterized in that, The non-destructive testing of the preliminary processing chip includes: Acquire X-ray images of the preliminary processing chip; The X-ray image is enhanced to obtain an enhanced image; Edge detection algorithms are used to perform edge detection on the enhanced image to identify the surface defect contours of the preliminary processing chip; The quantitative characteristics of the surface defect profile are analyzed to detect the surface defect degree of the preliminary processing chip; The enhanced image is used to identify the circuit wiring features of the preliminary processing chip; After detecting the circuit integrity of the preliminary processing chip using the circuit wiring features, the non-destructive testing of the preliminary processing chip is completed.

10. The modular integrated packaging technology as described in claim 1 for high-density assembly of memory chips, characterized in that, The process of integrating and packaging the quality classification chip to obtain the target packaged chip includes: Configure the packaging platform for the quality classification chip; The target packaged chip is packaged and deployed in the packaging platform to obtain a deployed chip; The deployed chip is coated with a material to obtain a coated chip; The coated chip is then dispensed with adhesive to obtain a dispensing chip; The dispensing chip is then subjected to shell injection molding to obtain the target packaged chip.

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