An output OVP protection circuit and its control method

Abstract

The present invention discloses an output OVP protection circuit and its control method, which includes a VIN sampling circuit, a VCS sampling circuit, a timer Timer, an output overvoltage protection control module OVP Control, an RS flip-flop G3, an OR gate G2, and a GATE generation circuit. The output overvoltage protection control module OVP Control includes a voltage division module Divider2, a filter Filter2, a compensation module Compensation, a comparator CMP4, an RS flip-flop G5, an AND gate G6, and an inverter G7. The overvoltage protection point of the present invention has high accuracy and stability, so that there is no need to leave a large margin in the selection of the output capacitor, thereby reducing the cost of the power supply system.

Description

Technical Field

[0001] The present invention relates to a protection circuit and its control method, in particular to an output OVP protection circuit and its control method, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] With the increasing application scale of AC / DC power converters, the cost requirements for power systems are also getting higher and higher. The cost of the output capacitor of a power system is related to its maximum operating voltage, and the maximum operating voltage of the output capacitor depends on the accuracy of the output overvoltage protection of the power system. When the output overvoltage protection accuracy of the power system is poor, the selection of the output capacitor has to be made according to the highest boundary of the output overvoltage protection value, which usually increases additional cost expenditures. In order to improve the accuracy of the protection point, it is usually necessary to add additional detection devices outside the control chip, or add high-voltage detection pins and high-voltage devices inside the control chip, but these methods themselves increase the cost of the power system and do not fundamentally solve the problem.

[0003] As Figure 5 shown, the existing AC / DC power system includes a rectifier bridge B1, a capacitor C1, a capacitor C2, a capacitor C3, a diode D1, a diode D2, a diode D3, a resistor RO, a resistor RS, an inductor L1, a power switch M1, and a power controller U1. The first input terminal of the rectifier bridge B1 is connected to the AC L line and the anode of the diode D2, the second input terminal of the rectifier bridge B1 is connected to the AC N line and the anode of the diode D3, the first output terminal of the rectifier bridge B1 is connected to one end of the capacitor C1, the cathode of the diode D1, one end of the capacitor C2, and one end of the resistor R0, the second output terminal of the rectifier bridge B1 is connected to the other end of the capacitor C1 and grounded, the cathode of the diode D2 is connected to the cathode of the diode D3 and the VIN terminal of the power controller U1 to generate a signal VIN, the VCC terminal of the power controller U1 is connected to one end of the capacitor C3, the GND terminal of the power controller U1 is connected to the other end of the capacitor C3 and grounded, the GATE terminal of the power controller U1 is connected to the gate of the power switch M1, the CS terminal of the power controller U1 is connected to one end of the power switch M1 and one end of the resistor RS to generate a signal VCS, the other end of the resistor RS is grounded, the other end of the power switch M1 is connected to the anode of the diode D1 and one end of the inductor L1 to generate a signal VDRAIN, and the other end of the inductor L1 is connected to the other end of the capacitor C2 and the other end of the resistor R0.

[0004] As Figure 6As shown, the control circuit where the output overvoltage protection circuit of the prior art is located is integrated in the power supply controller U1, and includes a voltage division module Divider1, a switch SW1, a switch SW2, a filter Filter1, a sample and hold module Sample&Hold, a ramp generator Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, a comparator CMP3, a timer Timer, an RS flip-flop G1, an RS flip-flop G3, an OR gate G2, an inverter G4, and a drive module Driver. The input end of the voltage division module Divider1 is connected to the signal VIN, the output end of the voltage division module Divider1 is connected to one end of the switch SW1, the other end of the switch SW1 is connected to the input end of the filter Filter1 and one end of the switch SW2, the other end of the switch SW2 is grounded, the control end of the switch SW1 is connected to the control signal PWM, the control end of the switch SW2 is connected to the output end of the inverter G4, the input end of the inverter G4 is connected to the control signal PWM, the output end of the filter Filter1 is connected to the non-inverting input end of the comparator CMP3, the inverting input end of the comparator CMP3 is connected to the reference voltage Reference2, the output end of the comparator CMP3 is connected to the input end of the timer Timer and the S end of the RS flip-flop G3, the Q end of the RS flip-flop G3 is connected to the first input end of the OR gate G2, the input end of the sample and hold module Sample&Hold is connected to the signal VCS, the output end of the sample and hold module Sample&Hold is connected to the inverting input end of the error amplifier EA, the non-inverting input end of the error amplifier EA is connected to the reference voltage Reference1, the output end of the error amplifier EA is connected to the inverting input end of the comparator CMP1, the output end of the ramp generator Ramp Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the second input end of the OR gate G2, the output end of the OR gate G2 is connected to the R end of the RS flip-flop G1, the non-inverting input end of the comparator CMP2 is grounded, the inverting input end of the comparator CMP2 is connected to the signal GATE, the output end of the comparator CMP2 is connected to the S end of the RS flip-flop G1 and generates the signal ZCD, the Q end of the RS flip-flop G1 is connected to the input end of the drive module Driver and generates the control signal PWM, and the output end of the drive module Driver outputs the signal GATE.

[0005] The principle of the output overvoltage protection circuit in the prior art is as follows: when the GATE pin of the power supply controller U1 outputs to turn on the power switch M1, the current slope of the inductor L1 is (VIN - VOUT) / L, where L is the inductance of the inductor L1; when the GATE pin of the power supply controller U1 outputs to turn off the power switch M1, the current slope of the inductor L1 is -VOUT / L; the conduction time within each cycle is TON, the turn-off time is TOFF, and the inductor current operates in the critical conduction mode. According to the volt-second balance, (VIN - VOUT) / L * TON = VOUT / L * TOFF. Further, that is: VIN * TON = VOUT * (TON + TOFF). Therefore, by collecting the value of VIN and multiplying it by the duty cycle Duty, and then filtering through a filter to take the average value, the sampled value of the output voltage VOUT can be obtained, where Duty = TON / (TON + TOFF). This can simplify the circuit design and reduce the overhead of high-voltage pins and high-voltage devices and circuits within the power supply controller. When the sampled value of VOUT exceeds the internally set reference value, the OVP protection is triggered, causing the power switch M1 to be constantly off, and a timer is started for timing. When the timing time of the timer reaches, it enters the re-detection state, and the power switch M1 resumes switching. If the condition for triggering OVP is lifted at this time, the power supply system enters the normal working state. If the condition for triggering OVP still exists at this time, the sampled value of VOUT exceeds the internally set reference value again after a certain time, triggering OVP again, and so on.

[0006] As Figure 7The following is a schematic waveform diagram of the AC / DC power supply system where the output overvoltage protection circuit of the prior art is located. Among them, VIN is the voltage on the VIN pin of the power supply controller U1, VOUT is the voltage difference across the second capacitor C2, GATE is the voltage on the GATE pin of the power supply controller U1, and VCS is the voltage on the CS pin of the power supply controller U1. At time T0, the system is in the output voltage overvoltage protection state, there is no switching wave on GATE, and the VCS voltage is also zero; at time T1, the system reaches the output voltage overvoltage protection timing restart condition, a switching wave starts on GATE, and the VCS voltage also follows GATE with a pulsed voltage, and the pulse peak follows the VIN trajectory. Since the power supply system transfers energy to the output, the output voltage VOUT starts to rise; at time T2, with the transfer of power supply energy, the sampled value of VOUT obtained by indirect sampling through VIN*Duty exceeds the reference voltage Reference3, and it enters the OVP protection state again, and the switching wave on GATE is terminated and remains zero; at time T3, the timer timing time condition is reached, and it enters the re-detection state, the GATE switch is initiated, and the output voltage VOUT rises again; at time T4, with the transfer of power supply energy, the sampled value of VOUT obtained by indirect sampling through VIN*Duty exceeds the reference voltage Reference3, and it enters the OVP protection state again, and the switching wave on GATE is terminated and remains zero; at time T5, the timer timing time condition is reached, and it enters the re-detection state, the GATE switch is initiated, and the output voltage VOUT rises again; at time T6, with the transfer of power supply energy, the sampled value of VOUT obtained by indirect sampling through VIN*Duty exceeds the reference voltage Reference3, and it enters the OVP protection state again, and the switching wave on GATE is terminated and remains zero. Since the timer timing and the period of the input voltage VIN are asynchronous, the phase of the start time of each re-detection state relative to VIN is random, resulting in different VOUT voltage values corresponding to the re-entry into the OVP protection state at times T2, T4, and T6, and there are random fluctuations in the protection points. In addition, when the amplitude of the input voltage VIN is different, it will also cause different energy transfer states during each re-detection, resulting in differences in the OVP protection points between high and low input voltages. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide an output OVP protection circuit and its control method to eliminate the random jitter of the protection point and the fluctuation of the protection point caused by the amplitude of the input voltage.

[0008] To solve the above technical problem, the technical solution adopted by the present invention is:

[0009] An output OVP protection circuit includes a VIN sampling circuit, a VCS sampling circuit, a timer Timer, an output overvoltage protection control module OVP Control, an RS flip-flop G3, an OR gate G2, and a GATE generation circuit. The first input terminal of the VIN sampling circuit and the output overvoltage protection control module OVP Control is connected to the signal VIN. The output terminal of the VIN sampling circuit is connected to the input terminal of the timer Timer and the S terminal of the RS flip-flop G3. The output terminal of the timer Timer is connected to the second input terminal of the output overvoltage protection control module OVP Control and generates a signal Restart1. The output terminal of the output overvoltage protection control module OVP Control is connected to the R terminal of the RS flip-flop G3. The Q terminal of the RS flip-flop G3 is connected to the first input terminal of the OR gate G2. The input terminal of the VCS sampling circuit is connected to the signal VCS. The output terminal of the VCS sampling circuit is connected to the second input terminal of the OR gate G2. The output terminal of the OR gate G2 is connected to the input terminal of the GATE generation circuit. The output terminal of the GATE generation circuit outputs a signal GATE.

[0010] Further, the VIN sampling circuit includes a voltage dividing module Divider1, a switch SW1, a switch SW2, a filter Filter1, and a comparator CMP3. The input terminal of the voltage dividing module Divider1 serves as the input terminal of the VIN sampling circuit and is connected to the signal VIN. The output terminal of the voltage dividing module Divider1 is connected to one end of the switch SW1. The other end of the switch SW1 is connected to the input terminal of the filter Filter1 and one end of the switch SW2. The other end of the switch SW2 is grounded. The control terminal of the switch SW1 is connected to a control signal PWM. The control terminal of the switch SW2 is connected to the output terminal of an inverter G4. The input terminal of the inverter G4 is connected to the control signal PWM. The output terminal of the filter Filter1 is connected to the positive input terminal of the comparator CMP3. The negative input terminal of the comparator CMP3 is connected to a reference voltage Reference2. The output terminal of the comparator CMP3 serves as the output terminal of the VIN sampling circuit.

[0011] Further, the VCS sampling circuit includes a sample and hold module Sample&Hold, a ramp generator RampGenerator, an error amplifier EA, and a comparator CMP1. The input terminal of the sample and hold module Sample&Hold serves as the input terminal of the VCS sampling circuit and is connected to the signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is connected to the reference voltage Reference1. The output terminal of the error amplifier EA is connected to the inverting input terminal of the comparator CMP1. The output terminal of the ramp generator Ramp Generator is connected to the non-inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 serves as the output terminal of the VCS sampling circuit.

[0012] Further, the GATE generation circuit includes an RS flip-flop G1, a comparator CMP2, and a driver module Driver. The R terminal of the RS flip-flop G1 serves as the input terminal of the GATE generation circuit. The non-inverting input terminal of the comparator CMP2 is grounded. The inverting input terminal of the comparator CMP2 is connected to the signal GATE. The output terminal of the comparator CMP2 is connected to the S terminal of the RS flip-flop G1 and generates the signal ZCD. The Q terminal of the RS flip-flop G1 is connected to the input terminal of the driver module Driver and generates the control signal PWM. The output terminal of the driver module Driver serves as the output terminal of the GATE generation circuit and outputs the signal GATE.

[0013] Further, the output overvoltage protection control module OVP Control includes a voltage divider module Divider2, a filter Filter2, a compensation module Compensation, a comparator CMP4, an RS flip-flop G5, an AND gate G6, and an inverter G7. The input terminal of the voltage divider module Divider2 serves as the first input terminal of the output overvoltage protection control module OVP Control and is connected to the signal VIN. The output terminal of the voltage divider module Divider2 is connected to the input terminal of the filter Filter2 and the non-inverting input terminal of the comparator CMP4. The output terminal of the filter Filter2 is connected to the input terminal of the compensation module Compensation. The output terminal of the compensation module Compensation is connected to the inverting input terminal of the comparator CMP4 and generates the reference voltage Reference3. The output terminal of the comparator CMP4 is connected to the S terminal of the RS flip-flop G5. The input terminal of the inverter G7 is connected to the signal Restart1. The output terminal of the inverter G7 is connected to the R terminal of the RS flip-flop G5. The Q terminal of the RS flip-flop G5 is connected to the first input terminal of the AND gate G6. The second input terminal of the AND gate G6 is connected to the signal Restart1. The output terminal of the AND gate G6 serves as the output terminal of the output overvoltage protection control module OVPControl and generates the signal OVP_REST.

[0014] A control method for an output OVP protection circuit includes the following steps: When the voltage amplitude of the signal VIN remains unchanged, after the timing condition of the timer Timer is satisfied, the overvoltage protection control module OVP Control controls the restart detection state to start at a fixed phase of the trajectory of the signal VIN, ensuring that the state of the power system transmitting energy to the output remains consistent during each restart detection;

[0015] When the voltage amplitude of the signal VIN changes, the compensation module Compensation adjusts the magnitude of the reference voltage Reference3 according to the amplitude of the signal VIN, thereby adjusting the position of the fixed phase where the restart detection state starts, and further compensating to ensure that the state of the power system transmitting energy to the output remains consistent during each restart detection under different input voltage amplitude conditions.

[0016] Compared with the prior art, the present invention has the following advantages and effects:

[0017] 1. The present invention provides an output OVP protection circuit. Through the fixed-phase control mode, it ensures that the state of the power system transmitting energy to the output remains consistent during each restart detection, thereby eliminating the random jitter of the protection point;

[0018] 2. On the basis of the fixed-phase control, the present invention introduces compensation of the phase point relative to the input voltage amplitude to ensure that the state of the power system transmitting energy to the output remains consistent during each restart detection under different input voltage amplitude conditions, and eliminates the fluctuation of the protection point caused by the input voltage amplitude;

[0019] 3. The overvoltage protection point of the present invention has high accuracy and stability, so that a large margin does not need to be left in the selection of the output capacitor, thereby reducing the cost of the power system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of an output OVP protection circuit of the present invention.

[0021] Figure 2 is a schematic diagram of the output overvoltage protection control module OVP Control of the present invention.

[0022] Figure 3 is a schematic waveform diagram of an output OVP protection circuit of the present invention.

[0023] Figure 4 is a schematic waveform diagram of an output OVP protection circuit of the present invention applied to an AC / DC power system.

[0024] Figure 5 is a schematic diagram of a prior art AC / DC power system.

[0025] Figure 6 It is a schematic diagram of an output overvoltage protection circuit of the prior art.

[0026] Figure 7 It is a schematic waveform diagram of the AC / DC power supply system where the output overvoltage protection circuit of the prior art is located. Detailed implementation manners

[0027] In order to elaborate in detail on the technical solutions adopted by the present invention to achieve the predetermined technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments. Moreover, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0028] As Figure 1 shown, an output OVP protection circuit of the present invention includes a VIN sampling circuit, a VCS sampling circuit, a timer Timer, an output overvoltage protection control module OVP Control, an RS flip-flop G3, an OR gate G2, and a GATE generation circuit. The first input terminal of the VIN sampling circuit and the output overvoltage protection control module OVP Control is connected to the signal VIN. The output terminal of the VIN sampling circuit is connected to the input terminal of the timer Timer and the S terminal of the RS flip-flop G3. The output terminal of the timer Timer is connected to the second input terminal of the output overvoltage protection control module OVP Control and generates a signal Restart1. The output terminal of the output overvoltage protection control module OVP Control is connected to the R terminal of the RS flip-flop G3. The Q terminal of the RS flip-flop G3 is connected to the first input terminal of the OR gate G2. The input terminal of the VCS sampling circuit is connected to the signal VCS. The output terminal of the VCS sampling circuit is connected to the second input terminal of the OR gate G2. The output terminal of the OR gate G2 is connected to the input terminal of the GATE generation circuit. The output terminal of the GATE generation circuit outputs a signal GATE.

[0029] The VIN sampling circuit includes a voltage division module Divider1, a switch SW1, a switch SW2, a filter Filter1, and a comparator CMP3. The input terminal of the voltage division module Divider1 serves as the input terminal of the VIN sampling circuit and is connected to the signal VIN. The output terminal of the voltage division module Divider1 is connected to one end of the switch SW1. The other end of the switch SW1 is connected to the input terminal of the filter Filter1 and one end of the switch SW2. The other end of the switch SW2 is grounded. The control terminal of the switch SW1 is connected to the control signal PWM. The control terminal of the switch SW2 is connected to the output terminal of the inverter G4. The input terminal of the inverter G4 is connected to the control signal PWM. The output terminal of the filter Filter1 is connected to the positive input terminal of the comparator CMP3. The negative input terminal of the comparator CMP3 is connected to the reference voltage Reference2. The output terminal of the comparator CMP3 serves as the input terminal of the VIN sampling circuit.

[0030] The VCS sampling circuit includes a sample and hold module Sample&Hold, a ramp generator Ramp Generator, an error amplifier EA, and a comparator CMP1. The input terminal of the sample and hold module Sample&Hold serves as the input terminal of the VCS sampling circuit and is connected to the signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the negative input terminal of the error amplifier EA. The positive input terminal of the error amplifier EA is connected to the reference voltage Reference1. The output terminal of the error amplifier EA is connected to the negative input terminal of the comparator CMP1. The output terminal of the ramp generator Ramp Generator is connected to the positive input terminal of the comparator CMP1. The output terminal of the comparator CMP1 serves as the output terminal of the VCS sampling circuit.

[0031] The GATE generation circuit includes an RS flip-flop G1, a comparator CMP2, and a driver module Driver. The R terminal of the RS flip-flop G1 serves as the input terminal of the GATE generation circuit. The positive input terminal of the comparator CMP2 is grounded. The negative input terminal of the comparator CMP2 is connected to the signal GATE. The output terminal of the comparator CMP2 is connected to the S terminal of the RS flip-flop G1 and generates the signal ZCD. The Q terminal of the RS flip-flop G1 is connected to the input terminal of the driver module Driver and generates the control signal PWM. The output terminal of the driver module Driver serves as the output terminal of the GATE generation circuit and outputs the signal GATE.

[0032] Such as Figure 2As shown in the figure, the output overvoltage protection control module OVP Control includes a voltage division module Divider2, a filter Filter2, a compensation module Compensation, a comparator CMP4, an RS flip-flop G5, an AND gate G6, and an inverter G7. The input terminal of the voltage division module Divider2 serves as the first input terminal of the output overvoltage protection control module OVP Control and is connected to the signal VIN. The output terminal of the voltage division module Divider2 is connected to the input terminal of the filter Filter2 and the positive input terminal of the comparator CMP4. The output terminal of the filter Filter2 is connected to the input terminal of the compensation module Compensation. The output terminal of the compensation module Compensation is connected to the negative input terminal of the comparator CMP4 and generates a reference voltage Reference3. The output terminal of the comparator CMP4 is connected to the S terminal of the RS flip-flop G5. The input terminal of the inverter G7 is connected to the signal Restart1. The output terminal of the inverter G7 is connected to the R terminal of the RS flip-flop G5. The Q terminal of the RS flip-flop G5 is connected to the first input terminal of the AND gate G6. The second input terminal of the AND gate G6 is connected to the signal Restart1. The output terminal of the AND gate G6 serves as the output terminal of the output overvoltage protection control module OVP Control and generates a signal OVP_REST.

[0033] A control method for an output OVP protection circuit includes the following steps: When the voltage amplitude of the signal VIN remains unchanged, after the timing condition of the timer Timer is satisfied, the output overvoltage protection control module OVP Control controls the restart detection state to start at a fixed phase of the trajectory of the signal VIN, ensuring that the state of the power system transmitting energy to the output remains consistent during each restart detection.

[0034] When the voltage amplitude of the signal VIN changes, the compensation module Compensation adjusts the magnitude of the reference voltage Reference3 according to the amplitude of the signal VIN, thereby adjusting the position of the fixed phase where the restart detection state starts, and further compensating for the consistency of the state of the power system transmitting energy to the output during each restart detection under different input voltage amplitude conditions.

[0035] As Figure 3The following is a schematic waveform diagram of an output OVP protection circuit according to the present invention. Among them, Reference3 is the reference voltage output by the compensation module Compensation, VIN_AVE is the output of the filter Filter2, Vref1 and Vref2 are constants, AVE1 and AVE2 are constants, and Vref2 > Vref1, AVE2 > AVE1. When VIN_AVE ≤ AVE1, Reference3 remains at Vref1; when AVE1 ≤ VIN_AVE ≤ AVE2, Reference3 gradually increases from Vref1 to Vref2; when VIN_AVE ≥ AVE2, Reference3 remains at Vref2.

[0036] As Figure 4 The following is a schematic waveform diagram of an output OVP protection circuit according to the present invention applied to an AC / DC power supply system. Among them, VIN is the voltage signal on the VIN pin of the power supply controller U1, VOUT is the voltage difference across the capacitor C2, GATE is the voltage signal on the GATE pin of the power supply controller U1, and VCS is the voltage signal on the CS pin of the power supply controller U1. At time T0, the system is in the output voltage overvoltage protection state, there is no switching wave on GATE, and the VCS voltage is also zero; at time T1, the system reaches the output voltage overvoltage protection timing restart condition, a switching wave starts on GATE, and the VCS voltage also follows GATE with a pulsed voltage, and the pulse peak follows the VIN trajectory. Since the power supply system transfers energy to the output, the output voltage VOUT starts to rise; at time T2, with the transfer of power supply energy, the VOUT sampling value obtained by indirect sampling through VIN*Duty exceeds the reference voltage Reference3, and it enters the OVP protection state again, and the switching wave on GATE is terminated and remains at zero; at time T3, the timer timing time condition is reached, and at the same time the phase condition of VIN is also satisfied, it enters the re-detection state, the GATE switching wave is initiated, and the output voltage VOUT rises again; at time T4, with the transfer of power supply energy, the VOUT sampling value obtained by indirect sampling through VIN*Duty exceeds the reference voltage Reference3, and it enters the OVP protection state again, and the switching wave on GATE is terminated and remains at zero; at time T5, the timer timing time condition is reached, but the phase condition of VIN is not reached, and it does not enter the re-detection state; at time T6, the phase condition of VIN is satisfied, and at this time it enters the re-detection state, the GATE switch is initiated, and the output voltage VOUT rises again; at time T7, with the transfer of power supply energy, the VOUT sampling value obtained by indirect sampling through VIN*Duty exceeds the reference voltage Reference3, and it enters the OVP protection state again, and the switching wave on GATE is terminated and remains at zero.

[0037] The present invention provides an output OVP protection circuit. Through a fixed-phase control mode, it ensures that during each restart detection period, the state of the power supply system transmitting energy to the output remains consistent, thereby eliminating the random jitter of the protection point. On the basis of the fixed-phase control, the present invention introduces compensation of the phase point relative to the input voltage amplitude to ensure that during each restart detection period under different input voltage amplitude conditions, the state of the power supply system transmitting energy to the output remains consistent, and eliminates the fluctuation of the protection point caused by the input voltage amplitude. The overvoltage protection point of the present invention has high precision and stability, so that a large margin does not need to be reserved in the selection of the output capacitor, thereby reducing the cost of the power supply system.

[0038] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention and is based on the technical essence of the present invention, any simple modification, equivalent replacement and improvement of the above embodiments still fall within the protection scope of the technical solution of the present invention.

Claims

1. An output OVP protection circuit, characterized in that: It includes a VIN sampling circuit, a VCS sampling circuit, a timer Timer, an output overvoltage protection control module OVP Control, an RS flip-flop G3, an OR gate G2, and a GATE generation circuit. The first input terminal of the VIN sampling circuit and the output overvoltage protection control module OVP Control is connected to the signal VIN. The output terminal of the VIN sampling circuit is connected to the input terminal of the timer Timer and the S terminal of the RS flip-flop G3. The output terminal of the timer Timer is connected to the second input terminal of the output overvoltage protection control module OVP Control and generates a signal Restart1. The output terminal of the output overvoltage protection control module OVP Control is connected to the R terminal of the RS flip-flop G3. The Q terminal of the RS flip-flop G3 is connected to the first input terminal of the OR gate G2. The input terminal of the VCS sampling circuit is connected to the signal VCS. The output terminal of the VCS sampling circuit is connected to the second input terminal of the OR gate G2. The output terminal of the OR gate G2 is connected to the input terminal of the GATE generation circuit. The output terminal of the GATE generation circuit outputs a signal GATE; The output overvoltage protection control module OVP Control includes a voltage division module Divider2, a filter Filter2, a compensation module Compensation, a comparator CMP4, an RS flip-flop G5, an AND gate G6, and an inverter G7. The input terminal of the voltage division module Divider2 serves as the first input terminal of the output overvoltage protection control module OVP Control and is connected to the signal VIN. The output terminal of the voltage division module Divider2 is connected to the input terminal of the filter Filter2 and the non-inverting input terminal of the comparator CMP4. The output terminal of the filter Filter2 is connected to the input terminal of the compensation module Compensation. The output terminal of the compensation module Compensation is connected to the inverting input terminal of the comparator CMP4 and generates a reference voltage Reference3. The output terminal of the comparator CMP4 is connected to the S terminal of the RS flip-flop G5. The input terminal of the inverter G7 is connected to the signal Restart1. The output terminal of the inverter G7 is connected to the R terminal of the RS flip-flop G5. The Q terminal of the RS flip-flop G5 is connected to the first input terminal of the AND gate G6. The second input terminal of the AND gate G6 is connected to the signal Restart1. The output terminal of the AND gate G6 serves as the output terminal of the output overvoltage protection control module OVP Control and generates a signal OVP_REST.

2. An output OVP protection circuit according to claim 1, wherein: The VIN sampling circuit includes a voltage division module Divider1, a switch SW1, a switch SW2, a filter Filter1, and a comparator CMP3. The input terminal of the voltage division module Divider1 serves as the input terminal of the VIN sampling circuit and is connected to the signal VIN. The output terminal of the voltage division module Divider1 is connected to one end of the switch SW1. The other end of the switch SW1 is connected to the input terminal of the filter Filter1 and one end of the switch SW2. The other end of the switch SW2 is grounded. The control terminal of the switch SW1 is connected to the control signal PWM. The control terminal of the switch SW2 is connected to the output terminal of the inverter G4. The input terminal of the inverter G4 is connected to the control signal PWM. The output terminal of the filter Filter1 is connected to the non-inverting input terminal of the comparator CMP3. The inverting input terminal of the comparator CMP3 is connected to the reference voltage Reference2. The output terminal of the comparator CMP3 serves as the input terminal of the VIN sampling circuit.

3. An output OVP protection circuit according to claim 1, characterized in that: The VCS sampling circuit includes a sample and hold module Sample&Hold, a ramp generator Ramp Generator, an error amplifier EA, and a comparator CMP1. The input terminal of the sample and hold module Sample&Hold serves as the input terminal of the VCS sampling circuit and is connected to the signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is connected to the reference voltage Reference1. The output terminal of the error amplifier EA is connected to the inverting input terminal of the comparator CMP1. The output terminal of the ramp generator Ramp Generator is connected to the non-inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 serves as the output terminal of the VCS sampling circuit.

4. An output OVP protection circuit according to claim 1, wherein: The GATE generation circuit includes an RS flip-flop G1, a comparator CMP2, and a driver module Driver. The R terminal of the RS flip-flop G1 serves as the input terminal of the GATE generation circuit. The non-inverting input terminal of the comparator CMP2 is grounded. The inverting input terminal of the comparator CMP2 is connected to the signal GATE. The output terminal of the comparator CMP2 is connected to the S terminal of the RS flip-flop G1 and generates a signal ZCD. The Q terminal of the RS flip-flop G1 is connected to the input terminal of the driver module Driver and generates a control signal PWM. The output terminal of the driver module Driver serves as the output terminal of the GATE generation circuit and outputs the signal GATE.

5. A control method for an output OVP protection circuit according to claim 1, characterized in that It includes the following steps: When the voltage amplitude of the signal VIN remains unchanged, after the timing condition of the timer Timer is satisfied, the overvoltage protection control module OVPControl outputs to start the restart detection state at a fixed phase of the trajectory of the signal VIN, ensuring that the state of the power system transmitting energy to the output remains consistent during each restart detection; When the voltage amplitude of the signal VIN changes, the compensation module Compensation adjusts the magnitude of the reference voltage Reference3 according to the amplitude of the signal VIN, so as to adjust the position at the fixed phase where the restart detection state starts, and further compensate to keep the state of the power system transmitting energy to the output consistent during each restart detection under different input voltage amplitude conditions.

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