Slope compensation circuit, DC-DC converter, chip and electronic device

Abstract

The invention provides a slope compensation circuit, a DC-DC converter, a chip and electronic equipment, and belongs to the technical field of power supply control. The slope compensation circuit comprises a first current generation circuit, a second current generation circuit, a current mirror circuit and a current output circuit. When the high-side power transistor is switched on, the control circuit sends a low-level signal, the first current generating circuit generates a first current which changes along with the switching-on time of the high-side power transistor, and the second current generating circuit generates a constant second current. The current mirror circuit carries out superposition processing on the first current and the second current to obtain a third current, the third current is mirrored to the current output circuit, and the current output circuit generates a slope compensation current based on the third current. The circuit provided by the invention can effectively inhibit the generation of subharmonic oscillation under the condition of high duty ratio, avoids the phenomena of overcompensation and output voltage ripple increase under the condition of low duty ratio, and facilitates the guarantee of the dynamic response capability and control precision of a system.

Description

Technical Field

[0001] The present application relates to the technical field of power control, and particularly to a ramp compensation circuit, a DC-DC converter, a chip and an electronic device. Background Art

[0002] A direct current-direct current (DC-DC) converter can convert an input DC voltage signal into an output DC voltage signal. The DC-DC converter usually adopts peak current mode control to control the output DC voltage by adjusting the system duty cycle (the ratio of the conduction time of the high-side power transistor to a complete switching cycle). However, when the system duty cycle is greater than 50%, and no ramp compensation circuit is added, sub-harmonic oscillation is likely to occur, resulting in a decrease in the anti-noise ability of the system, an increase in the output voltage ripple, and significantly affecting the stability of the system.

[0003] In the related art, in order to avoid the occurrence of sub-harmonic oscillation, a ramp compensation circuit is usually added to the DC-DC converter. The ramp compensation circuit can improve the stability and anti-interference ability of the system. Research shows that as the system duty cycle increases, the risk of sub-harmonic oscillation increases significantly. Therefore, the slope of the ramp compensation current also needs to be increased accordingly to ensure the stability of the system.

[0004] However, in the prior art, the ramp compensation circuit usually adopts a design with a fixed compensation slope, and applies a fixed and relatively large compensation slope to the full range of duty cycles. Although this design can effectively suppress sub-harmonic oscillation at high duty cycles, it will cause over-compensation at low duty cycles. Over-compensation not only weakens the dynamic response ability of the system, but also may increase the output voltage ripple and reduce the control accuracy, thereby affecting the overall performance of the DC-DC converter. Summary of the Invention

[0005] The present application provides a ramp compensation circuit, a DC-DC converter, a chip and an electronic device to solve the problem that the fixed compensation slope design in the prior art causes over-compensation at low duty cycles, thereby affecting the dynamic response ability and control accuracy of the DC-DC converter.

[0006] In a first aspect, the present application provides a ramp compensation circuit applied to a DC-DC converter. The DC-DC converter includes a control circuit and a high-side power transistor. The ramp compensation circuit includes a first current generation circuit, a second current generation circuit, a current mirror circuit and a current output circuit;

[0007] The first terminal of the first current generating circuit is electrically connected to an external voltage. The second terminal of the first current generating circuit is for receiving a control signal sent by the control circuit. The third terminal of the first current generating circuit is electrically connected to the first terminal of the current mirror circuit. The first terminal of the second current generating circuit is electrically connected to the first terminal of the current mirror circuit. The second terminal of the second current generating circuit is grounded. The second terminal of the current mirror circuit is electrically connected to the external voltage. The third terminal of the current mirror circuit is electrically connected to the first terminal of the current output circuit. The second terminal of the current output circuit is for receiving the control signal. The third terminal of the current output circuit is electrically connected to the control circuit.

[0008] When the high-side power transistor is turned on, the control signal sent by the control circuit is a low-level signal. The first current generating circuit is used to generate a first current, and the first current varies with the conduction time of the high-side power transistor. The second current generating circuit is used to generate a constant second current. The current mirror circuit is used to superimpose the first current and the second current to obtain a third current, and mirror the third current to the first terminal of the current output circuit. The current output circuit is used to generate a ramp compensation current based on the third current, and the ramp compensation current is output to the control circuit.

[0009] In a possible design, the first current generating circuit includes a first constant current source, a first transistor, a second transistor, a third transistor, a first capacitor, and a first resistor.

[0010] The first terminal of the first constant current source is electrically connected to the external voltage. The second terminal of the first constant current source is respectively electrically connected to the first terminal of the first transistor, the third terminal of the first transistor, the first terminal of the first capacitor, and the first terminal of the second transistor.

[0011] The second terminal of the first transistor is electrically connected to the third terminal of the third transistor. The first terminal of the third transistor is for receiving the control signal. The second terminal of the third transistor is grounded.

[0012] The second terminal of the second transistor is electrically connected to the first terminal of the first resistor. The third terminal of the second transistor is electrically connected to the first terminal of the current mirror circuit.

[0013] The second terminal of the first resistor and the second terminal of the first capacitor are both grounded.

[0014] In a possible design, when the high-side power transistor is turned off, the control signal sent by the control circuit is a high-level signal. The first transistor and the third transistor are both turned on, the second transistor is turned off, and the first current generating circuit is used to reset the first capacitor. The voltage of the first capacitor after reset is the gate-source voltage of the first transistor.

[0015] When the control signal is a low-level signal, the first transistor and the third transistor are both turned off, the second transistor is turned on, and the first current generated by the first current generating circuit is proportional to the conduction time of the high-side power transistor.

[0016] In a possible design, the second current generating circuit includes a second constant current source;

[0017] The first end of the second constant current source is electrically connected to the first end of the current mirror circuit, and the second end of the second constant current source is grounded.

[0018] In a possible design, the current mirror circuit includes a fourth transistor and a fifth transistor;

[0019] The first end of the fourth transistor is electrically connected to the third end of the fourth transistor and the first end of the fifth transistor respectively. The second end of the fourth transistor is electrically connected to the external voltage, and the third end of the fourth transistor is electrically connected to the third end of the first current generating circuit and the first end of the second current generating circuit respectively;

[0020] The second end of the fifth transistor is electrically connected to the external voltage, and the third end of the fifth transistor is electrically connected to the first end of the current output circuit.

[0021] In a possible design, the current output circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor and a second resistor;

[0022] The first end and the third end of the sixth transistor are both electrically connected to the first end of the second capacitor, and the second end of the sixth transistor is electrically connected to the third end of the eighth transistor;

[0023] The first end of the eighth transistor is used to access the control signal, and the second end of the eighth transistor is grounded;

[0024] The first end of the seventh transistor is electrically connected to the first end of the second capacitor, the second end of the seventh transistor is connected to the first end of the second resistor, the third end of the seventh transistor is electrically connected to the control circuit, and the second end of the second resistor is grounded;

[0025] The first end of the second capacitor is also electrically connected to the third end of the current mirror circuit, and the second end of the second capacitor is grounded.

[0026] In a possible design, when the high-side power transistor is turned off, the control signal sent by the control circuit is a high-level signal, the sixth transistor and the eighth transistor are both turned on, the seventh transistor is turned off, and the current output circuit is used to reset the second capacitor. The voltage of the second capacitor after reset is the gate-source voltage of the sixth transistor.

[0027] When the control signal is a low-level signal, the sixth transistor and the eighth transistor are both turned off, the seventh transistor is turned on, and the ramp compensation current output by the current output circuit is related to the first current and the second current.

[0028] In a second aspect, the present application provides a DC-DC converter, including: a control circuit, a bridge circuit, and the ramp compensation circuit according to any one of the first aspect;

[0029] The first end of the control circuit is electrically connected to the first end of the ramp compensation circuit, and the second end of the control circuit is electrically connected to the first end of the bridge circuit;

[0030] Wherein, the ramp compensation circuit transmits a ramp compensation current to the control circuit, and the control circuit controls the bridge circuit to output a set output voltage according to the ramp compensation current.

[0031] In a third aspect, the present application provides a chip, including: the ramp compensation circuit according to any one of the first aspect.

[0032] In a fourth aspect, the present application provides an electronic device, including: the DC-DC converter according to the second aspect, or the chip according to the third aspect.

[0033] The present application provides a ramp compensation circuit, a DC-DC converter, a chip and an electronic device. The ramp compensation circuit includes a first current generation circuit, a second current generation circuit, a current mirror circuit and a current output circuit. When the high-side power transistor is turned on, the control circuit sends a low-level signal. The first current generation circuit generates a first current that varies with the conduction time of the high-side power transistor. The second current generation circuit generates a constant second current. The current mirror circuit superimposes the first current and the second current to obtain a third current, and mirrors the third current to the current output circuit. The current output circuit is used to generate a ramp compensation current based on the third current, and the ramp compensation current is output to the control circuit. In the present application, since the first current varies dynamically with the duty cycle of the DC-DC converter and the second current is constant, the ramp compensation current generated based on the first current and the second current also varies dynamically with the duty cycle of the DC-DC converter. Under high duty cycle conditions, the first current gradually increases as the conduction time of the high-side power transistor increases, and the compensation slope of the ramp compensation current also increases accordingly, which can effectively suppress the occurrence of sub-harmonic oscillations, improve the stability and anti-noise ability of the system, and reduce the output voltage ripple. Under low duty cycle conditions, the first current is small, but due to the superimposed effect of the constant second current, the compensation slope of the ramp compensation current still remains within a reasonable range, effectively avoiding the over-compensation and the increase in output voltage ripple caused by the traditional fixed-slope compensation circuit, facilitating the guarantee of the dynamic response ability and control accuracy of the system, and improving the overall performance of the DC-DC converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. is a schematic diagram of an application scenario of a ramp compensation circuit provided by an embodiment of the present application;

[0035] Figure 2 FIG. is a circuit principle block diagram of a ramp compensation circuit provided by an embodiment of the present application;

[0036] Figure 3 FIG. is a circuit schematic diagram of a ramp compensation circuit provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs; the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion.

[0039] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of this application. The phrase "embodiments" appearing in various places in the specification does not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0040] In addition, the terms "first", "second", etc. in the specification, claims or the above-mentioned drawings of this application are used to distinguish different objects and not to describe a specific order, and may explicitly or implicitly include one or more of such features.

[0041] In the description of this application, unless otherwise specified, the meanings of "a plurality" and "at least two" refer to more than two (including two). Similarly, "multiple groups" and "at least two groups" refer to more than two groups (including two groups).

[0042] In the description of this application, it should be noted that, unless otherwise clearly specified and defined, the terms "connected" and "coupled" should be understood in a broad sense. For example, "connected" or "coupled" can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or can be indirectly connected through at least one intermediate element, as long as the circuit is connected; it can also be the internal connection of two elements; a signal connection can refer not only to a signal connection through a circuit, but also to a signal connection through a media medium, such as radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

[0043] In order to enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, without conflict, different technical features in this application can be combined with each other.

[0044] Figure 1 It is a schematic diagram of an application scenario of a ramp compensation circuit provided for an embodiment of this application. As Figure 1As shown, the DC-DC converter includes a controller, a high-side drive circuit HDRV, a low-side drive circuit LDRV, a current comparator CMP, an LC filter circuit, and a load resistor RL.

[0045] The input end of the controller is electrically connected to the output end of the current comparator CMP. The first output end of the controller is electrically connected to the input end of the high-side drive circuit HDRV. The second output end of the controller is electrically connected to the input end of the low-side drive circuit LDRV.

[0046] The output end of the high-side drive circuit HDRV is electrically connected to the gate of the high-side power transistor M9 in the half-bridge circuit. The output end of the low-side drive circuit LDRV is electrically connected to the gate of the low-side power transistor M10 in the half-bridge circuit.

[0047] The high-side drive circuit HDRV is used to process the drive signal HSON0 (which can also be understood as a control signal) of the high-side power transistor M9 output by the controller, and keep the phase of the signal unchanged before and after processing, so as to drive the high-side power transistor M9. The low-side drive circuit LDRV is used to process the drive signal LSON0 of the low-side power transistor M10 output by the controller, and keep the phase of the signal unchanged before and after processing, so as to drive the low-side power transistor M10.

[0048] It should be understood that at the same moment, the HSON0 and LSON0 signals output by the controller are opposite, and the output signals of the high-side drive circuit HDRV and the low-side drive circuit LDRV are also opposite.

[0049] In Figure 1 In the illustrated embodiment, the high-side power transistor M9 and the low-side power transistor M10 in the half-bridge circuit are taken as NMOS as an example for illustration. Among them, the drain of the high-side power transistor M9 receives the bias voltage VIN. The source of the high-side power transistor M9 is electrically connected to the drain of the low-side power transistor M10. The source of the low-side power transistor M10 is grounded.

[0050] The LC filter circuit includes an inductor L0 and a third capacitor C3. The first end of the inductor L0 is electrically connected to the voltage output end SW0 of the half-bridge circuit. The second end of the inductor L0 is electrically connected to the first end of the load resistor RL. The second end of the load resistor RL is grounded. The first end of the third capacitor C3 is electrically connected to the second end of the inductor L0. The second end of the third capacitor C3 is grounded.

[0051] The inverting input end of the current comparator CMP is electrically connected to the output end of the inductor current peak signal IPEAK. The non-inverting input end of the current comparator CMP is electrically connected to the output end of the inductor current sampling signal IL_SENS and the output end of the ramp compensation circuit respectively.

[0052] Among them, the inductor current peak signal IPEAK is generated by the controller according to the requirement of the load resistance RL, and the inductor current peak signal IPEAK determines the maximum value of the current flowing through the inductor L0.

[0053] The inductor current sampling signal IL_SENS is obtained by sampling the current flowing through the inductor L0, and the inductor current sampling signal IL_SENS can reflect the real-time change of the current flowing through the inductor L0.

[0054] The ramp compensation circuit is used to generate a ramp compensation current signal I_SLOPE, and the ramp compensation current signal I_SLOPE is a compensation amount that changes with the duty cycle.

[0055] It should be noted that the current comparator CMP is used to superimpose the inductor current sampling signal IL_SENS and the ramp compensation current signal I_SLOPE to obtain an input current signal ICOMP, and compare the input current signal ICOMP with the inductor current peak signal IPEAK to generate a turn-off signal for the high-side power transistor M9.

[0056] When the input current signal ICOMP < the inductor current peak signal IPEAK, the controller keeps the high-side power transistor M9 conducting.

[0057] When the input current signal ICOMP ≥ the inductor current peak signal IPEAK, the controller generates a turn-off signal for the high-side power transistor M9, the high-side power transistor M9 turns off, and the DC-DC converter enters the stage where the low-side power transistor M9 conducts, completing a full switching cycle.

[0058] In the above DC-DC converter based on the peak current mode, the system controls the output voltage by adjusting the duty cycle (the ratio of the on-time T on of the high-side power transistor M9 to a full switching cycle T s ). However, when the system duty cycle is greater than 50% and no ramp compensation circuit is added, due to the mismatch between the rising slope and the falling slope of the inductor current, the inner-loop current control loop may become unstable, thereby triggering subharmonic oscillation, reducing the anti-noise ability of the system, and significantly affecting the stability of the system and the output voltage quality.

[0059] In the related art, in order to avoid the occurrence of subharmonic oscillation, a ramp compensation circuit is usually added to the DC-DC converter. Through the ramp compensation circuit, a compensation signal that changes linearly with time can be superimposed on the inductor current sampling signal, improving the dynamic stability of the inner-loop current control loop, thereby enhancing the stability and anti-interference ability of the system. Research shows that as the system duty cycle increases, the risk of subharmonic oscillation increases significantly, so the slope of the ramp compensation signal also needs to be increased accordingly to ensure the stability of the system.

[0060] However, in the prior art, the slope compensation circuit usually adopts a design with a fixed compensation slope, and applies a fixed and relatively large compensation slope to the duty cycle in the full range. Although this design can effectively suppress sub-harmonic oscillation at high duty cycles, it will cause over-compensation at low duty cycles. Over-compensation not only weakens the dynamic response ability of the system, but may also increase the output voltage ripple and reduce the control accuracy, thus affecting the overall performance of the DC-DC converter.

[0061] Based on the problems existing in the related art, the present application provides a slope compensation circuit, which includes a first current generation circuit, a second current generation circuit, a current mirror circuit and a current output circuit. When the high-side power transistor is turned on, the control circuit sends a low-level signal. The first current generation circuit generates a first current that changes with the on-time of the high-side power transistor, and the second current generation circuit generates a constant second current. The current mirror circuit superimposes the first current and the second current to obtain a third current, and mirrors the third current to the current output circuit. The current output circuit is used to generate a slope compensation current based on the third current and output the slope compensation current to the control circuit. In the present application, since the first current changes dynamically with the duty cycle of the DC-DC converter and the second current remains constant, the slope compensation current generated based on the first current and the second current also changes dynamically with the duty cycle of the DC-DC converter. Under high duty cycle conditions, the first current gradually increases as the on-time of the high-side power transistor increases, and the compensation slope of the slope compensation current also increases accordingly, which can effectively suppress the occurrence of sub-harmonic oscillation, improve the stability and anti-noise ability of the system, and reduce the output voltage ripple; under low duty cycle conditions, the first current is small, but due to the superimposed effect of the constant second current, the compensation slope of the slope compensation current still remains within a reasonable range, effectively avoiding the over-compensation and the increase of output voltage ripple caused by the traditional fixed slope compensation circuit, facilitating the guarantee of the dynamic response ability and control accuracy of the system, and improving the overall performance of the DC-DC converter.

[0062] The slope compensation circuit provided by the present application can be applied to a DC-DC converter, a buck-boost converter, a boost converter or other power converter structures, and the present embodiment does not make specific limitations on this.

[0063] Next, the slope compensation circuit provided by the present application will be introduced in detail through some specific embodiments and drawings.

[0064] Figure 2 is a circuit principle block diagram of a slope compensation circuit provided by an embodiment of the present application. As Figure 2As shown in the figure, the ramp compensation circuit provided by the embodiment of the present application includes a first current generation circuit 10, a second current generation circuit 20, a current mirror circuit 30, and a current output circuit 40.

[0065] The first end of the first current generation circuit 10 is electrically connected to an external voltage VDD. The second end of the first current generation circuit 10 is used to receive a control signal sent by a control circuit 50. The third end of the first current generation circuit 10 is electrically connected to the first end of the current mirror circuit 30. The first end of the second current generation circuit 20 is electrically connected to the first end of the current mirror circuit 30. The second end of the second current generation circuit 20 is grounded. The second end of the current mirror circuit 30 is electrically connected to the external voltage VDD. The third end of the current mirror circuit 30 is electrically connected to the first end of the current output circuit 40. The second end of the current output circuit 40 is used to receive a control signal sent by the control circuit 50. The third end of the current output circuit 40 is electrically connected to the control circuit 50.

[0066] It should be noted that the external voltage VDD is the external voltage that supplies power to the first current generation circuit 10, the second current generation circuit 20, the current mirror circuit 30, and the current output circuit 40 in the ramp compensation circuit. The first end of the control circuit 50 outputs a control signal. The third end of the current output circuit 40 is electrically connected to the second end of the control circuit 50.

[0067] Figure 3 This is the circuit schematic diagram of a ramp compensation circuit provided by the embodiment of the present application. As Figure 3 shown, in some embodiments, the first current generation circuit 10 includes a first constant current source I1, a first transistor M1, a second transistor M2, a third transistor M3, a first capacitor C1, and a first resistor R1.

[0068] The first end of the first constant current source I1 is electrically connected to the external voltage VDD. The second end of the first constant current source I1 is respectively electrically connected to the first end of the first transistor M1, the third end of the first transistor M1, the first end of the first capacitor C1, and the first end of the second transistor M2.

[0069] The second end of the first transistor M1 is electrically connected to the third end of the third transistor M3. The first end of the third transistor M3 is used to receive a control signal RST. The second end of the third transistor M3 is grounded.

[0070] The second end of the second transistor M2 is electrically connected to the first end of the first resistor R1. The third end of the second transistor M2 is electrically connected to the first end of the current mirror circuit 30.

[0071] The second end of the first resistor R1 and the second end of the first capacitor C1 are both grounded.

[0072] As Figure 3As shown, RST is the control signal sent by the control circuit 50; I_SLOPE is the ramp compensation current output by the current output circuit 40 to the control circuit 50.

[0073] As Figure 1 and Figure 3 shown, the control signal RST sent by the control circuit 50 can be a low-level signal or a high-level signal. When the high-side power transistor M9 is turned on, the control signal RST sent by the control circuit 50 is a low-level signal; when the high-side power transistor M9 is turned off, the control signal RST sent by the control circuit 50 is a high-level signal.

[0074] Among them, whether the high-side power transistor M9 is turned on or off, the first constant current source I1 always outputs a constant current to the first capacitor C1 to charge the first capacitor C1.

[0075] Among them, the first transistor M1, the second transistor M2, and the third transistor M3 are all NMOS transistors.

[0076] It should be noted that when the signal received by the gate of the NMOS transistor is a high-level signal, the NMOS transistor is turned on; when the signal received by the gate of the NMOS transistor is a low-level signal, the NMOS transistor is turned off.

[0077] In this embodiment, the first end of the first transistor M1 is the gate of the first transistor M1, the second end of the first transistor M1 is the source of the first transistor M1, and the third end of the first transistor M1 is the drain of the first transistor M1. The first end of the second transistor M2 is the gate of the second transistor M2, the second end of the second transistor M2 is the source of the second transistor M2, and the third end of the second transistor M2 is the drain of the second transistor M2. The first end of the third transistor M3 is the gate of the third transistor M3, the second end of the third transistor M3 is the source of the third transistor M3, and the third end of the third transistor M3 is the drain of the third transistor M3.

[0078] Specifically, the gate of the third transistor M3 is used to access the control signal RST, the source of the third transistor M3 is grounded, the drain of the third transistor M3 is electrically connected to the source of the first transistor M1, and both the gate and the drain of the first transistor M1 are electrically connected to the second end of the first constant current source I1. The gate of the second transistor M2 is electrically connected to the second end of the first constant current source I1, the source of the second transistor M2 is electrically connected to the first end of the first resistor R1, and the drain of the second transistor M2 is electrically connected to the first end of the current mirror circuit 30.

[0079] It should be noted that the first end of the first constant current source I1 is the first end of the first current generation circuit 10, the gate of the third transistor M3 is the second end of the first current generation circuit 10, and the drain of the second transistor M2 is the third end of the first current generation circuit 10.

[0080] As Figure 3 shown, in some embodiments, when the high-side power transistor M9 is turned off, the control signal RST sent by the control circuit 50 is a high-level signal. The first transistor M1 and the third transistor M3 are both turned on, the second transistor M2 is turned off, and the first current generation circuit 10 is used to reset the first capacitor C1. The voltage of the first capacitor C1 after reset is the gate-source voltage of the first transistor M1.

[0081] When the control signal RST is a high-level signal, the first transistor M1 and the third transistor M3 are controlled to be turned on, and the second transistor M2 is controlled to be turned off. At this time, the first transistor M1 operates in the saturation region, the third transistor M3 operates in the deep linear region, and the drain voltage of the third transistor M3 is approximately equal to the source voltage of the third transistor M3. In the first current generation circuit 10, the first transistor M1 is connected in parallel with the first capacitor C1, and the first transistor M1 resets the first capacitor C1 so that the voltage across the first capacitor C1 is equal to the gate-source voltage of the first transistor M1. The first current generation circuit 10 does not generate a first current.

[0082] When the second transistor M2 is controlled to be turned off, the gate-source voltage of the second transistor M2 approaches the conduction threshold voltage of the second transistor M2, so that when the second transistor M2 needs to be turned on subsequently, the second transistor M2 can be quickly turned on.

[0083] When the control signal is a low-level signal, the first transistor M1 and the third transistor M3 are both turned off, the second transistor M2 is turned on, and the first current generated by the first current generation circuit 10 is proportional to the conduction time of the high-side power transistor M9.

[0084] When the high-side power transistor M9 switches from the off state to the on state, the control signal RST switches from a high-level signal to a low-level signal.

[0085] When the control signal RST is a low-level signal, the first transistor M1 and the third transistor M3 are controlled to be turned off, and the second transistor M2 is controlled to be turned on. At this time, since the gate-source voltage of the second transistor M2 approaches the conduction voltage of the second transistor M2 when the second transistor M2 is controlled to be turned off, when the control signal RST switches from a high-level signal to a low-level signal, the second transistor M2 can be quickly turned on and generate current.

[0086] In this embodiment, when the high-side power transistor M9 is turned on, that is, when the control signal RST is a low-level signal, the gate voltage of the second transistor M2 changes with the on-time T of the high-side power transistor M9 on and the gate voltage V of the second transistor M2 G2 satisfies Equation (1):

[0087]

[0088] In Equation (1), V GS1 represents the gate-source voltage of the first transistor M1. I1 represents the current output by the first constant current source I1. C1 represents the resistance value of the first capacitor C1.

[0089] The gate voltage V of the second transistor M2 S2 satisfies Equation (2):

[0090]

[0091] In Equation (2), V GS2 represents the gate-source voltage of the second transistor M2.

[0092] It should be noted that since the gate-source voltage V of the first transistor M1 GS1 is approximately equal to the gate-source voltage V of the second transistor M2 GS2 , the current IM2 flowing through the second transistor M2 satisfies Equation (3):

[0093]

[0094] In Equation (3), R1 represents the resistance value of the first resistor R1.

[0095] It should be noted that when the control signal RST is a low-level signal, the current IM2 flowing through the second transistor M2 is the first current generated by the first current generation circuit 10.

[0096] According to Equation (3), the first current IM2 generated by the first current generation circuit 10 is proportional to the on-time T of the high-side power transistor M9 on . The first current IM2 generated by the first current generation circuit 10 changes linearly with the on-time T of the high-side power transistor M9 on .

[0097] As Figure 3 shown, in some embodiments, the second current generation circuit 20 includes a second constant current source I2.

[0098] The first end of the second constant current source I2 is electrically connected to the first end of the current mirror circuit 30, and the second end of the second constant current source I2 is grounded.

[0099] It should be noted that regardless of whether the high-side power transistor M9 is turned on or off, the second constant current source I2 always outputs a constant second current to the current mirror circuit 30.

[0100] In this embodiment, the first end of the second constant current source I2 is the first end of the second current generation circuit 20, and the second end of the second constant current source I2 is the second end of the second current generation circuit 20.

[0101] As Figure 3 shown, in some embodiments, the current mirror circuit 30 includes a fourth transistor M4 and a fifth transistor M5.

[0102] The first end of the fourth transistor M4 is electrically connected to the third end of the fourth transistor M4 and the first end of the fifth transistor M5 respectively. The second end of the fourth transistor M4 is electrically connected to the external voltage VDD. The third end of the fourth transistor M4 is electrically connected to the third end of the first current generation circuit 10 and the first end of the second current generation circuit 20 respectively.

[0103] The second end of the fifth transistor M5 is electrically connected to the external voltage VDD. The third end of the fifth transistor M5 is electrically connected to the first end of the current output circuit 40.

[0104] Among them, both the fourth transistor M4 and the fifth transistor M5 are PMOS transistors.

[0105] It should be noted that when the signal received by the gate of the PMOS transistor is a high-level signal, the PMOS transistor is turned off; when the signal received by the gate of the PMOS transistor is a low-level signal, the PMOS transistor is turned on.

[0106] In this embodiment, the first end of the fourth transistor M4 is the gate of the fourth transistor M4, the second end of the fourth transistor M4 is the source of the fourth transistor M4, and the third end of the fourth transistor M4 is the drain of the fourth transistor M4. The first end of the fifth transistor M5 is the gate of the fifth transistor M5, the second end of the fifth transistor M5 is the source of the fifth transistor M5, and the third end of the fifth transistor M5 is the drain of the fifth transistor M5.

[0107] Specifically, the gate of the fourth transistor M4 is connected to the drain of the fourth transistor M4 and the gate of the fifth transistor M5 respectively. The source of the fourth transistor M4 is electrically connected to the external voltage VDD. The drain of the fourth transistor M4 is also electrically connected to the drain of the second transistor M2 and the first end of the second constant current source I2 respectively. The source of the fifth transistor M5 is electrically connected to the external voltage VDD. The drain of the fifth transistor M5 is electrically connected to the first end of the current output circuit 40.

[0108] It should be noted that the drain of the fourth transistor M4 is the first end of the current mirror circuit 30, the sources of the fourth transistor M4 and the fifth transistor M5 are both the second end of the current mirror circuit 30, and the drain of the fifth transistor M5 is the third end of the current mirror circuit 30.

[0109] It should be noted that when the high-side power transistor M9 is turned on, that is, when the control signal RST is a low-level signal, the current I5 flowing through the fifth transistor M5 satisfies Equation (4):

[0110]

[0111] In Equation (4), I2 represents the current output by the second constant current source I2, that is, the second current generated by the second current generation circuit.

[0112] In this embodiment, whether the high-side power transistor M9 is turned on or off, the fourth transistor M4 and the fifth transistor M5 are both in the on state. When the high-side power transistor M9 is turned off, that is, when the control signal RST is a high-level signal, the current mirror circuit 30 is used to mirror the second current generated by the second current generation circuit 20 to the first end of the current output circuit 40. When the high-side power transistor M9 is turned on, that is, when the control signal RST is a low-level signal, the current mirror circuit 30 is used to superimpose the first current generated by the first current generation circuit 10 and the second current generated by the second current generation circuit 20 to obtain a third current, and mirror the third current to the first end of the current output circuit 40.

[0113] As Figure 3 shown, in some embodiments, the current output circuit 40 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a second capacitor C2, and a second resistor R2.

[0114] The first end and the third end of the sixth transistor M6 are both electrically connected to the first end of the second capacitor C2, and the second end of the sixth transistor M6 is electrically connected to the third end of the eighth transistor M8.

[0115] The first end of the eighth transistor M8 is used to receive the control signal RST, and the second end of the eighth transistor M8 is grounded.

[0116] The first end of the seventh transistor M7 is electrically connected to the first end of the second capacitor C2, the second end of the seventh transistor M7 is connected to the first end of the second resistor R2, the third end of the seventh transistor M7 is electrically connected to the control circuit, and the second end of the second resistor R2 is grounded.

[0117] The first end of the second capacitor C2 is also electrically connected to the third end of the current mirror circuit 30, and the second end of the second capacitor C2 is grounded.

[0118] Among them, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all NMOS transistors.

[0119] In this embodiment, the first end of the sixth transistor M6 is the gate of the sixth transistor M6, the second end of the sixth transistor M6 is the source of the sixth transistor M6, and the third end of the sixth transistor M6 is the drain of the sixth transistor M6. The first end of the seventh transistor M7 is the gate of the seventh transistor M7, the second end of the seventh transistor M7 is the source of the seventh transistor M7, and the third end of the seventh transistor M7 is the drain of the seventh transistor M7. The first end of the eighth transistor M8 is the gate of the eighth transistor M8, the second end of the eighth transistor M8 is the source of the eighth transistor M8, and the third end of the eighth transistor M8 is the drain of the eighth transistor M8.

[0120] Specifically, the gate of the eighth transistor M8 is used to access the control signal RST, the source of the eighth transistor M8 is grounded, the drain of the eighth transistor M8 is electrically connected to the source of the sixth transistor M6, and both the gate and the drain of the sixth transistor M6 are electrically connected to the first end of the second capacitor C2.

[0121] The gate of the seventh transistor M7 is electrically connected to the first end of the second capacitor C2, the source of the seventh transistor M7 is electrically connected to the first end of the second resistor R1, and the drain of the seventh transistor M7 is electrically connected to the control circuit.

[0122] It should be noted that the first end of the second capacitor C2 is the first end of the current output circuit 40, the gate of the eighth transistor M8 is the second end of the current output circuit 40, and the drain of the seventh transistor M7 is the third end of the current output circuit 40.

[0123] As Figure 3 shown, in some embodiments, when the high-side power transistor M9 is turned off, the control signal RST sent by the control circuit 50 is a high-level signal, the sixth transistor M6 and the eighth transistor M8 are both turned on, the seventh transistor M7 is turned off, and the current output circuit 40 is used to reset the second capacitor C2. The voltage of the second capacitor C2 after reset is the gate-source voltage of the sixth transistor M6.

[0124] When the control signal RST is a high-level signal, the sixth transistor M6 and the eighth transistor M8 are controlled to be turned on, and the seventh transistor M7 is controlled to be turned off. At this time, the sixth transistor M6 operates in the saturation region, the eighth transistor M8 operates in the deep linear region, and the drain voltage of the eighth transistor M8 is approximately equal to the source voltage of the eighth transistor M8; in the current output circuit 40, the sixth transistor M6 is connected in parallel with the second capacitor C2, and the sixth transistor M6 resets the second capacitor C2 so that the voltage across the second capacitor C2 is equal to the gate-source voltage of the sixth transistor M6. The current output circuit 40 does not output a ramp compensation current to the control circuit 50.

[0125] It should be noted that when the seventh transistor M7 is controlled to be turned off, the gate-source voltage of the seventh transistor M7 approaches the conduction threshold voltage of the seventh transistor M7, so that when the seventh transistor M7 needs to be turned on subsequently, the seventh transistor M7 can be quickly turned on.

[0126] When the control signal RST is a low-level signal, the sixth transistor M6 and the eighth transistor M8 are both turned off, the seventh transistor M7 is turned on, and the current output circuit 40 generates a ramp compensation current I_SLOPE based on the third current and outputs the ramp compensation current ISLOPE to the control circuit 50.

[0127] When the control signal RST is a low-level signal, the sixth transistor M6 and the eighth transistor M8 are controlled to be turned off, and the seventh transistor M7 is controlled to be turned on. At this time, since the gate-source voltage of the seventh transistor M7 approaches the conduction voltage of the seventh transistor M7 when the seventh transistor M7 is controlled to be turned off, when the control signal RST switches from a high-level signal to a low-level signal, the seventh transistor M7 can be quickly turned on and generate a ramp compensation current I_SLOPE based on the third current.

[0128] In this embodiment, when the high-side power transistor M9 is turned on, that is, when the control signal RST is a low-level signal, the current I5 (the third current) flowing through the fifth transistor M5 charges the second capacitor C2. At this time, the gate voltage V of the seventh transistor M7 G7 satisfies formula (5):

[0129]

[0130] In formula (5), V GS6 represents the gate-source voltage of the sixth transistor M6. C2 represents the resistance value of the second capacitor C2.

[0131] It should be noted that since the gate-source voltage V of the sixth transistor M6 GS6 is approximately equal to the gate-source voltage V of the seventh transistor M7 GS7 the ramp compensation current I_SLOPE output by the seventh transistor M7 satisfies formula (6):

[0132]

[0133] In formula (6), V S7 represents the source voltage of the seventh transistor M7.

[0134] It should be noted that based on the calculation formula of I_SLOPE in the above formula (6), by taking the derivative of the time of the slope compensation current I_SLOPE, the slope MSLOPE of the slope compensation circuit can be obtained, and the slope MSLOPE of the slope compensation circuit satisfies formula (7):

[0135]

[0136] In formula (7), the slope MSLOPE of the slope compensation circuit includes a variable that changes with the conduction time T of the high-side power transistor M9 on and a constant that remains unchanged.

[0137] It should be noted that in the DC-DC converter, when the input current signal ICOMP (the signal after superimposing the slope compensation current I_SLOPE and the inductor current sampling signal IL_SENS) is consistent with the inductor current peak signal IPEAK, the slope compensation current I_SLOPE has an effect.

[0138] The present application provides a slope compensation circuit, including a first current generation circuit, a second current generation circuit, a current mirror circuit, and a current output circuit. When the high-side power transistor is turned on, the control circuit sends a low-level signal. The first current generation circuit generates a first current that changes with the conduction time of the high-side power transistor. The second current generation circuit generates a constant second current. The current mirror circuit superimposes the first current and the second current to obtain a third current, and mirrors the third current to the current output circuit. The current output circuit is used to generate a slope compensation current based on the third current and output the slope compensation current to the control circuit. In the present application, since the first current changes dynamically with the duty cycle of the DC-DC converter and the second current remains constant, the slope compensation current generated based on the first current and the second current also changes dynamically with the duty cycle of the DC-DC converter. Under high duty cycle conditions, the first current gradually increases as the conduction time of the high-side power transistor increases, and the compensation slope of the slope compensation current also increases accordingly, which can effectively suppress the occurrence of subharmonic oscillations, improve the stability and anti-noise ability of the system, and reduce the output voltage ripple; under low duty cycle conditions, the first current is small, but due to the superimposing effect of the constant second current, the compensation slope of the slope compensation current still remains within a reasonable range, effectively avoiding the over-compensation and the increase in output voltage ripple caused by the traditional fixed slope compensation circuit, facilitating the guarantee of the dynamic response ability and control accuracy of the system, and improving the overall performance of the DC-DC converter.

[0139] It should be noted that in the related art, due to process corner differences, there may be slight performance deviations in components of different batches during the manufacturing process (such as the deviation between the actual value and the designed value of resistors and capacitors), and these deviations may affect the performance of the DC-DC converter. In addition, the characteristics of electronic components (such as inductance and resistance) change significantly with temperature. Under high-temperature conditions, the impedance of circuit components increases, which may lead to a slowdown in the system response speed; under low-temperature conditions, the performance of components is unstable, which may cause problems such as insufficient compensation. Therefore, when the duty cycle of the DC-DC converter is within the range of 50% to 55%, in order to ensure system stability and performance, ramp compensation still needs to be performed through a ramp compensation circuit.

[0140] The compensation slope of the ramp compensation current generated by the ramp compensation circuit provided in this application gradually increases as the on-time of the high-side power transistor increases, can adapt to the change of the duty cycle of the DC-DC converter, suppress sub-harmonic oscillation, eliminates the limitations brought by the fixed compensation slope, and optimizes the output voltage quality and anti-noise ability of the DC-DC converter. In addition, the ramp compensation circuit provided in this application can adapt to the situation where the duty cycle is small but still requires ramp compensation under extreme process corner and temperature change conditions, and has a wide application range.

[0141] The ramp compensation circuit provided in this application has a simple structure, does not require complex digital operations or additional control logic, reduces the circuit design and manufacturing costs, reduces the consumption of hardware resources, and has low power consumption.

[0142] An embodiment of this application also provides a DC-DC converter, which includes a control circuit, a bridge circuit, and a ramp compensation circuit provided in any of the above embodiments.

[0143] Among them, the first end of the control circuit is electrically connected to the first end of the ramp compensation circuit, and the second end of the control circuit is electrically connected to the first end of the bridge circuit; the ramp compensation circuit transmits a ramp compensation current to the control circuit, and the control circuit controls the bridge circuit to output a set output voltage according to the ramp compensation current.

[0144] It should be noted that the bridge circuit can be a half-bridge circuit, a full-bridge circuit, or other circuits applying peak current mode, and this embodiment does not make specific limitations on this.

[0145] For example, as Figure 1 shown, the control circuit in the DC-DC converter includes a current comparator CMP and a controller. At this time, the non-inverting input terminal (the first end of the control circuit) of the current comparator CMP in the control circuit is electrically connected to the first end of the ramp compensation circuit, the output terminal of the current comparator CMP is electrically connected to the first end of the controller in the control circuit, and the second end (the second end of the control circuit) of the controller is electrically connected to the first end of the bridge circuit.

[0146] An embodiment of the present application further provides a chip, which integrates the ramp compensation circuit provided in any of the above embodiments.

[0147] An embodiment of the present application further provides a chip, which integrates the DC-DC converter provided in the present application.

[0148] An embodiment of the present application further provides an electronic device, including: the chip provided in the foregoing embodiment.

[0149] An embodiment of the present application further provides an electronic device, including: the DC-DC converter provided in the foregoing embodiment, and the DC-DC converter includes the ramp compensation circuit provided in the present application.

[0150] Finally, it should be noted that: the above embodiments are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A slope compensation circuit, applied to a DC-DC converter, wherein the DC-DC converter comprises a control circuit and a high-side power transistor, characterized in that: The slope compensation circuit includes a first current generating circuit, a second current generating circuit, a current mirror circuit and a current output circuit; A first end of the first current generating circuit is electrically connected to an external voltage, a second end of the first current generating circuit is used to access a control signal sent by the control circuit, and a third end of the first current generating circuit is electrically connected to the first end of the current mirror circuit; A first end of the second current generating circuit is electrically connected to a first end of the current mirror circuit, and a second end of the second current generating circuit is grounded; The second end of the current mirror circuit is electrically connected to the external voltage, the third end of the current mirror circuit is electrically connected to the first end of the current output circuit, the second end of the current output circuit is used to receive the control signal, and the third end of the current output circuit is electrically connected to the control circuit; When the high-side power transistor is turned on, the control signal sent by the control circuit is a low-level signal, the first current generating circuit is used to generate a first current, and the first current changes with the conduction time of the high-side power transistor; the second current generating circuit is used to generate a constant second current; the current mirror circuit is used to superimpose the first current and the second current to obtain a third current, and mirror the third current to the first end of the current output circuit; The current output circuit is used to generate a slope compensation current based on the third current, and the slope compensation current is output to the control circuit.

2. The circuit according to claim 1, characterized in that The first current generating circuit includes a first constant current source, a first transistor, a second transistor, a third transistor, a first capacitor and a first resistor; A first end of the first constant current source is electrically connected to the external voltage, and a second end of the first constant current source is electrically connected to a first end of the first transistor, a third end of the first transistor, a first end of the first capacitor, and a first end of the second transistor, respectively; The second end of the first transistor is electrically connected to the third end of the third transistor, the first end of the third transistor is used to access the control signal, and the second end of the third transistor is grounded; The second end of the second transistor is electrically connected to the first end of the first resistor, and the third end of the second transistor is electrically connected to the first end of the current mirror circuit; The second end of the first resistor and the second end of the first capacitor are both grounded.

3. The circuit according to claim 2, characterized in that When the high-side power transistor is turned off, the control signal sent by the control circuit is a high-level signal, the first transistor and the third transistor are both turned on, the second transistor is turned off, the first current generating circuit is used to reset the first capacitor, and the voltage of the first capacitor after reset is the gate-source voltage of the first transistor; When the control signal is a low level signal, the first transistor and the third transistor are both turned off, the second transistor is turned on, and the first current generated by the first current generating circuit is proportional to the turn-on time of the high-side power transistor.

4. The circuit according to claim 1, characterized in that The second current generating circuit comprises a second constant current source; A first end of the second constant current source is electrically connected to a first end of the current mirror circuit, and a second end of the second constant current source is grounded.

5. The circuit according to claim 1, characterized in that The current mirror circuit includes a fourth transistor and a fifth transistor; The first end of the fourth transistor is electrically connected to the third end of the fourth transistor and the first end of the fifth transistor respectively, the second end of the fourth transistor is electrically connected to the external voltage, and the third end of the fourth transistor is electrically connected to the third end of the first current generating circuit and the first end of the second current generating circuit respectively; The second end of the fifth transistor is electrically connected to the external voltage, and the third end of the fifth transistor is electrically connected to the first end of the current output circuit.

6. The circuit according to claim 1, characterized in that The current output circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor and a second resistor; The first end and the third end of the sixth transistor are both electrically connected to the first end of the second capacitor, and the second end of the sixth transistor is electrically connected to the third end of the eighth transistor; The first terminal of the eighth transistor is used to access the control signal, and the second terminal of the eighth transistor is grounded; The first end of the seventh transistor is electrically connected to the first end of the second capacitor, the second end of the seventh transistor is connected to the first end of the second resistor, the third end of the seventh transistor is electrically connected to the control circuit, and the second end of the second resistor is grounded; The first end of the second capacitor is also electrically connected to the third end of the current mirror circuit, and the second end of the second capacitor is grounded.

7. The circuit according to claim 6, characterized in that When the high-side power transistor is turned off, the control signal sent by the control circuit is a high-level signal, the sixth transistor and the eighth transistor are both turned on, the seventh transistor is turned off, and the current output circuit is used to reset the second capacitor, and the voltage of the second capacitor after reset is the gate-source voltage of the sixth transistor; When the control signal is a low level signal, the sixth transistor and the eighth transistor are both turned off, the seventh transistor is turned on, and the slope compensation current output by the current output circuit is related to the first current and the second current.

8. A DC-DC converter, characterized in that: include: A control circuit and a bridge circuit, and a slope compensation circuit as claimed in any one of claims 1 to 7; The first end of the control circuit is electrically connected to the first end of the slope compensation circuit, and the second end of the control circuit is electrically connected to the first end of the bridge circuit; The slope compensation circuit transmits a slope compensation current to the control circuit, and the control circuit controls the bridge circuit to output a set output voltage according to the slope compensation current.

9. A chip, characterized in that: include: The slope compensation circuit according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: The DC-DC converter according to claim 8, or the chip according to claim 9.

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