Attenuator with extended attenuation range

Abstract

The invention relates to an attenuator with an extended attenuation range. In one aspect, an apparatus includes a first amplifier coupled to a first node of a receiver signal processing path, the first amplifier to receive and amplify a radio frequency (RF) signal; a first resistive attenuator coupled to the first node, the first resistive attenuator being programmable to reduce a level of the RF signal; a second amplifier coupled in parallel with the first amplifier, the second amplifier for receiving and amplifying the RF signal; and a second attenuator coupled between the first node and the second amplifier, the second attenuator being programmable to reduce a level of the RF signal.

Description

BACKGROUND OF THE INVENTION

[0001] Most of the state-of-the-art wireless chips today support several standards and thus include multiple transceivers operating in dual (or more) bands. When implementing such a chip in a device with a single antenna, a front-end duplexer and transmit / receive (T / R) switches are used. Such circuits require strict input terminal impedance matching (small reflection coefficient, |S11|) at the interface.

[0002] On the other hand, the receiver circuits within a wireless chip can experience a wide range of signal power levels from desired or undesired signals, forcing the use of radio frequency (RF) attenuators to scale the signal level as desired. These on-chip attenuators can adversely affect impedance matching and suffer from an undesirable trade-off among attenuation range, linearity, noise, and device reliability. SUMMARY OF THE INVENTION

[0003] In one aspect, a device includes: a first amplifier coupled to a first node of a receiver signal processing path, the first amplifier for receiving and amplifying a radio frequency (RF) signal; a first resistive attenuator coupled to the first node, the first resistive attenuator programmable to reduce the level of the RF signal; a second amplifier coupled in parallel with the first amplifier, the second amplifier for receiving and amplifying the RF signal; and a second attenuator coupled between the first node and the second amplifier, the second attenuator programmable to reduce the level of the RF signal.

[0004] In an implementation, the device further includes a controller for controlling a first attenuation level of the first attenuator and for controlling a second attenuation level of the second attenuator. The controller can be configured to control the first attenuation level and the second attenuation level at least in part based on a gain level of the first amplifier and a gain level of the second amplifier. The controller can control the gain level of the first amplifier, the gain level of the second amplifier, the first attenuation level, and the second attenuation level according to a predetermined order. In one implementation, the controller is to control the gain level of the first amplifier, the gain level of the second amplifier, the first attenuation level, and the second attenuation level according to a predetermined order to maintain the return loss below a threshold level. The predetermined order can be to first control the gain level of the first amplifier, second control the first attenuation level, third control the gain level of the second amplifier, and fourth control the second attenuation level.

[0005] In an implementation: the first resistive attenuator includes a first programmable resistor coupled between the first node and a reference voltage node; and the second attenuator includes: a first resistor coupled between the first node and an input terminal of the second amplifier; and a second programmable resistor coupled between the input terminal of the second amplifier and the reference voltage node.

[0006] In another implementation, the second attenuator includes: a first capacitor coupled between a first node and an input of a second amplifier; and a first programmable capacitor coupled between the input of the second amplifier and a reference voltage node.

[0007] In an embodiment, the device further includes: a third amplifier coupled in parallel with the first amplifier, the third amplifier for receiving and amplifying an RF signal; and a third attenuator coupled between the second attenuator and the third amplifier, the third attenuator for reducing the level of the RF signal. The second attenuator can be a programmable resistive attenuator, and the third attenuator can be a programmable capacitive attenuator.

[0008] In an implementation, the device further includes: a third amplifier coupled in parallel with the first amplifier, the third amplifier for receiving and amplifying an RF signal; and a third attenuator coupled between the first node and the third amplifier, the third attenuator for reducing the level of the RF signal. The first resistive attenuator and the second attenuator can be located away from the receiver signal processing path. The first resistive attenuator and the second attenuator can provide an attenuation range of at least 20 decibels and enable the reflection coefficient of the receiver to be less than approximately -10 decibels.

[0009] In another aspect, a method includes: determining, in a receiver, a signal level associated with an RF signal received in the receiver; at least partially based on the signal level associated with the RF signal, first controlling a gain of a first amplifier coupled along a receiver signal processing path of the receiver, the first amplifier for receiving and amplifying the RF signal, and thereafter controlling a gain of a first resistive attenuator coupled to an input of the first amplifier until the first amplifier and the first resistive attenuator are turned off; and thereafter, controlling a gain of a second attenuator coupled between the input of the first amplifier and an input of a second amplifier coupled in parallel with the first amplifier, and thereafter controlling a gain of the second amplifier.

[0010] In an implementation, the method further includes controlling a gain of a lower frequency gain control circuit coupled along the receiver signal processing path downstream of the first amplifier before controlling the gain of the first amplifier. The method can further include iteratively controlling the gain of the first amplifier and controlling the gain of the first resistive attenuator until the gain of the first amplifier is exhausted. The method can further include: when the signal level associated with the RF signal exceeds a second level greater than a first level, controlling the gain of the second attenuator, and thereafter controlling the gain of the second amplifier.

[0011] In yet another aspect, a wireless device includes: an antenna for receiving and transmitting RF signals of at least a first frequency band and a second frequency band; a switching circuit coupled to the antenna; a matching network circuit coupled to the switching circuit to provide impedance matching; and a multi-band transceiver coupled to the matching network circuit to process RF signals of at least the first frequency band and the second frequency band.

[0012] The multi-band transceiver may include a first receiver having: a first amplifier adapted along a first receiver signal processing path between a first node and a second node, the first amplifier for receiving and amplifying a first RF signal of the first frequency band; a first resistive attenuator coupled between the first node and a reference voltage node, the first resistive attenuator programmable to reduce the level of the first RF signal of the first frequency band; a second amplifier coupled in parallel with the first amplifier between the first node and the second node, the second amplifier for receiving and amplifying the first RF signal of the first frequency band; and a first capacitive attenuator coupled in parallel with the first resistive attenuator between the first node and the reference voltage node, the first capacitive attenuator further coupled to an input of the second amplifier, the second capacitive attenuator programmable to reduce the level of the first RF signal of the first frequency band.

[0013] In an implementation, the wireless device further includes a controller for controlling a first attenuation level of the first resistive attenuator and a second attenuation level of the first capacitive attenuator at least partially based on a signal level of the first RF signal of the first frequency band. The controller may be configured to first back off the gain of the first resistive attenuator and the first amplifier, and thereafter back off the gain of the first capacitive attenuator and the second amplifier, wherein the first amplifier has a greater gain than the second amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram of a device according to an embodiment.

[0015] Figure 2 is a block diagram of a receiver according to an embodiment.

[0016] Figure 3A is a schematic diagram of a resistive attenuator according to an embodiment;

[0017] Figure 3B is a schematic diagram of a secondary low noise amplifier according to an embodiment.

[0018] Figure 3C is a plot of reflection coefficient with varying levels of secondary resistive attenuation according to an embodiment.

[0019] Figure 4A is a schematic diagram of a capacitive attenuator according to an embodiment;

[0020] Figure 4B Schematic diagram of a secondary low-noise amplifier according to an embodiment.

[0021] Figure 4C Illustration of reflection coefficient with varying levels of secondary capacitive attenuator according to an embodiment.

[0022] Figure 5A Schematic diagram of a combined resistive and capacitive attenuator according to an embodiment.

[0023] Figure 5B Illustration of reflection coefficient with varying levels of secondary resistive and capacitive attenuators according to an embodiment.

[0024] Figure 6 Schematic diagram illustrating another implementation of a controllable attenuator according to an embodiment;

[0025] Figure 7 Flowchart of a method according to an embodiment.

[0026] Figure 8 Block diagram of a representative integrated circuit incorporating an embodiment.

[0027] Figure 9 High-level diagram of a network according to an embodiment. Detailed Description

[0028] In various embodiments, a controllable RF attenuator is provided that offers a wide attenuation range (e.g., at least 20 decibels (dB) and up to 30 dB) while maintaining a low impedance mismatch, which implies a small reflection coefficient across the wide attenuation range without sacrificing linearity, noise, and / or active device reliability.

[0029] More specifically, embodiments use a resistive attenuator and (optionally) a capacitive attenuator to provide this wide attenuation range while maintaining a low impedance mismatch. To achieve the desired properties, at least the programmable portion of the attenuator is positioned away from the signal processing path of the receiver, reducing concerns regarding linearity, noise, and active device reliability since there are no switches in the signal processing path.

[0030] Now referring to Figure 1 , a block diagram of a device according to an embodiment is shown. As Figure 1 shown, device 100 can be any type of wireless device, such as an Internet of Things (IoT) device, a smart phone, a tablet, a laptop computer, or any other device with wireless capabilities. Device 100 is shown at a high level to illustrate an implementation in which multiple transceivers operate in different frequency bands. Thus, there is common and separate circuitry, implying the need for good impedance matching.

[0031] Specifically, as Figure 1As shown, device 100 is a dual - band wireless device capable of operating in different frequency bands (e.g., 2.4 gigahertz (GHz) and / or 5 GHz bands). To this end, a single antenna 105 is configured to receive and transmit RF signals of different frequency bands. Antenna 105 is coupled to a duplexer 110. Duplexer 110 is configured to provide frequency separation and isolation and selectively route incoming RF signals of different frequency bands to appropriate circuits. Specifically as shown, incoming RF signals of the first frequency band are provided to the first switch 1201, while incoming RF signals of the second frequency band are provided to the second switch 1202. Switch 120 is configured to perform transmit and receive switching for a given signal processing path.

[0032] In the transmit direction, duplexer 110 receives outgoing RF signals of different frequency bands and provides them to antenna 105. Although there are two similarly configured signal paths (and in other cases there may be additional such paths), for ease of discussion, the components of the first signal path 1151 are discussed. It is understood that similar components exist in the second signal path 1152.

[0033] Regarding the first signal path 1151, switch 120 is coupled to a corresponding matching network 125 in the transmit and receive directions respectively T1,R1 , said matching network 125 T1,R1 having a matching circuit for impedance matching between the switch 120 and the corresponding pins of the transceiver 150. As Figure 1 shown in the embodiment of, transceiver 150 is implemented as a multi - band transceiver, including transmitter and receiver circuits for each of multiple frequency bands. Note that in an embodiment, transceiver 150 may be implemented on a single semiconductor die of an integrated circuit (IC), where each pin is an external interconnect of the IC. In such a case, it is understood that each such pin may be coupled to a corresponding pad on the die via a bond wire or other conductive element (not shown for ease of illustration in Figure 1 ).

[0034] In Figure 1 the high - level shown, transceiver 150 is formed by a pair of transmitters 155 T1,T2 and a pair of receivers 155 R1,R2 It is understood that transceiver 150 may also include control circuitry for configuring the transmitter and receiver to operate appropriately in a selected frequency band and for providing a control interface to additional circuitry of device 100.

[0035] It is understood that additional matching network circuitry may exist within each of the transmitter and receiver of transceiver 150, the details of which are further discussed herein. Using as Figure 1Implementations with multi-band operation require low impedance mismatch (meaning small reflection coefficient |S11|) across all of the duplexer 110, switch 120, matching network 125, and the chip input / output interface to enable the desired quality factor. To this end, the matching circuit within transceiver 150 can provide such good impedance matching (i.e., low impedance mismatch) across varying operating frequency bands, as will be described herein. Although illustrated at this high level in the Figure 1 embodiment, it is understood that many variations and alternatives are possible. That is, the impedance matching techniques described herein can be implemented in other device configurations, particularly where multi-band operation is desired.

[0036] Now referring to Figure 2 , a block diagram of a receiver according to an embodiment is shown. As Figure 2 shown, receiver 200 can be a given one of a plurality of receivers present within a multi-band transceiver and can thus be implemented using on-chip circuitry. As shown, an incoming RF signal (RFin) is provided via input terminal pin 205 to a matching network 210 that further includes passive gain components. In an embodiment, matching network 210 can be implemented using one or more inductors and capacitors.

[0037] The RF signal is then provided to an attenuator circuit formed by a programmable resistor attenuator (Ratt1) 215 and a programmable capacitor attenuator 220 to achieve impedance matching across a wide frequency range. The attenuator circuit is configured to reduce the input RF signal level provided to the remainder of the signal processing path when a large signal level is present. In this way, the downstream linearity requirements are relaxed such that the signal processing path can operate reliably with large desired power and / or blocker power. Additionally, the attenuator circuit controls the signal level to reduce or avoid signal chain saturation (or clipping) up to very large signal levels.

[0038] As Figure 2 shown, resistor attenuator Ratt1 is implemented via a programmable resistor, and attenuator 220 is implemented via a capacitive attenuator having a fixed capacitor C1 and a programmable capacitor C2.

[0039] The resistive attenuator and attenuator 220 operate to attenuate an incoming RF signal based on the power level of the RF signal as may be required. The resulting RF signal is provided to a corresponding low-noise amplifier (LNA) 23012. In various embodiments, the LNA 2301 can be a controllable main path amplifier. In one implementation, LNA programmability can be achieved with multiple equal-weight slices combined with finer binary-weighted slices. For example, the LNA 2301 can be implemented with equal-weight slices (e.g., each of 4x strength), and the LNA 2302 can be implemented with binary-weighted slices (e.g., one 2x and one 1x strength). Depending on the implementation, the LNA 230 can be a current-mode low-noise transconductance amplifier (LNTA) or a voltage-mode LNA. As used herein, unless otherwise specifically stated, the terms "low-noise amplifier" and "LNA" cover both current-mode LNTAs and voltage-mode LNAs.

[0040] The resulting amplified signal from the LNA 230 is coupled to the mixer 240 via a coupling capacitor CC. As Figure 2 shown in the embodiment of, the mixer 240 is implemented as a quadrature mixer to down-convert the incoming RF signal to a lower frequency signal, e.g., an intermediate frequency (IF) or baseband (zero IF) complex signal provided to corresponding quadrature signal paths (i.e., in-phase (I) path and quadrature phase (Q) path).

[0041] Each path includes a transimpedance amplifier (TIA) 250 that converts the current signal to a voltage signal I,Q . The IF signal of the complex path is in turn provided to corresponding filters and amplifiers, more specifically a low-pass filter (LPF) and a programmable gain amplifier (PGA) 260 I,Q . The resulting filtered and amplified IF signal is in turn provided to a digitizer, which is implemented as an analog-to-digital converter (ADC) 270 I,Q . Although shown at this high level in the embodiment of, many variations and alternatives are possible. For example, while Figure 2 the embodiment of illustrates the details of a capacitive attenuator on the secondary branch, in other implementations, there can be a resistive attenuator or a combined resistive-capacitive attenuator. Figure 2

[0042] Now referring to Figure 3A Figure 3A , a schematic diagram of a resistive attenuator according to an embodiment is shown. As Figure 3A shown in, the circuit 300 is part of a receiver including an LNA, implemented as a primary LNA 3301 and a secondary LNA 3302. Although two branches are shown in this illustration, it is understood that in other embodiments, there can be additional branches. Additionally, Figure 3AShows a high level with a single programmable amplifier on each branch. However, it is understood that each of these LNAs 330 can be implemented using a plurality of slices that can be programmably enabled or disabled.

[0043] Still referring to Figure 3A , a first resistive attenuator 310 is coupled between a primary signal path coupled to the input of LNA 3301 and a reference voltage node (e.g., a ground node). The value of the programmable resistor 310 can be controlled depending on the desired attenuation level. Depending on the implementation, the programmability of the resistor 310 can be controlled by a thermometer, binary, radix, or other weighted scheme (or a combination thereof). For example, in one implementation, the programmable resistor 310 can be implemented with a first plurality of thermometer-weighted resistors and a second plurality of binary-weighted resistors. It is understood that each resistor can be controlled by a controllable switch, which can be implemented as a ground-referred metal oxide semiconductor field effect transistor (MOSFET).

[0044] The gain of the primary path including LNA 3301 is given by:

[0045] The reflection coefficient S in dB 11,dB is further given by:

[0046] where R' s is the source impedance related to the LNA input.

[0047] As further illustrated, a second resistive attenuator 320 is coupled between a primary signal path node 305 and a secondary LNA 3302. As illustrated, the resistive attenuator 320 includes a fixed resistor R1 coupled in series to the input of LNA 3302 and a programmable resistor R2 coupled between the input of LNA 3302 and the reference voltage node. The value of the programmable resistor R2 can be controlled depending on the desired attenuation level. The programmable resistor R2 can be implemented similar to the programmable resistor 310 discussed above.

[0048] This arrangement with a secondary branch having a resistive attenuator 320 and a secondary LNA 330 maintains improved matching across a wider gain range. More specifically, this configuration provides an L-network attenuator with R1, which can achieve a low reflection coefficient (S11) across a wider adjustment range of R2. In fact, compared to the primary LNA 3301, the secondary LNA 3302 can be a lower-intensity amplifier. In Figure 3A this implementation, this secondary branch can have a gain given by:

[0049] The reflection coefficient is given by the following equation:

[0050] Figure 3B Further details of the secondary LNA 3302 are illustrated. As shown, the LNA 3302 can be implemented with parallel slices. In the illustrated embodiment, these parallel slices can be implemented as binary weighted amplifiers, namely 2x amplifier slices 3321 and 1x amplifier slices 3322. Of course, additional binary weighted slices can be present in other embodiments. And other coding schemes can exist, such as thermometer weighted slices.

[0051] Now referring to Figure 3C , a plot of the reflection coefficient S11 (in dB) is shown for varying primary and secondary resistor attenuator levels. Initially, Ratt1 is engaged while meeting the S11 < -10 dB requirement. At this point in time, further reducing Ratt1 will violate the S11 requirement. For additional attenuation, Ratt1 and LNA 3301 are also turned off, and Ratt2 along with the LNA 3302 branch is engaged. However, it is also generally possible to freeze Ratt1 without turning it off and continue to use Ratt2 to reduce the gain. Note that whenever Ratt2 is engaged, LNA 3301 is disabled. In this case, the minimum impedance mismatch occurs, where the gain rollback is approximately 10 dB. Although the embodiments are not limited in this regard, this gain rollback can occur when the values of the resistor attenuator arrangement in Figure 3A are in the range of approximately 20 dB.

[0052] In one embodiment, the curve in Figure 3C can be implemented in operation through the control of programmable attenuators, where initially the first resistor attenuator 310 and the LNA 3301 gain slices are backed off while still meeting the S11 requirement. Thereafter, the components of the secondary branch (with the secondary resistor attenuator 320 and LNA 3302) are backed off (where the components of the primary branch are turned off and the primary branch is bypassed). Thus, in this example, when Ratt2 and the secondary LNA 3302 are engaged, the primary LNA 3301 is bypassed (turned off together with Ratt1). However, in other embodiments, an attenuation arrangement is possible where Ratt1 can remain on (to provide some attenuation) when LNA 3301 is disconnected.

[0053] Now referring to Figure 4A , a schematic diagram of a capacitive attenuator according to an embodiment is shown. As Figure 4AAs shown, circuit 400 is part of a receiver including an LNA, implemented as a primary LNA 4301 and a secondary LNA 4302 (of course, in other embodiments, additional branches may exist). Similar to the above Figure 3A Each LNA 430 can be implemented with multiple slices that can be programmably enabled or disabled.

[0054] Still referring to Figure 4A , a resistive attenuator 410 is coupled between the primary signal path and the reference voltage node. The value of the programmable resistor 410 can be controlled depending on the desired attenuation level.

[0055] As further illustrated, a capacitive attenuator 420 is coupled between the primary signal path node 405 and the secondary LNA 4302. The capacitive attenuator 420 includes a fixed capacitor C1 serially coupled to the input of the LNA 4302 and a programmable capacitor C2 coupled between the input to the LNA 4302 and the reference voltage node. The value of the programmable capacitor C2 can be controlled depending on the desired attenuation level. Depending on the implementation, the programmability of the capacitor C2 can be controlled by a thermometer, binary, radix, or other weighted scheme (or a combination thereof). It is understood that each capacitor can be controlled with a controllable switch circuit. To ensure that unconnected capacitors do not float, this switch circuit can be implemented with a pair of complementary MOSFETs (with a common coupled gate terminal). In this way, when unconnected, the capacitor is coupled to a well-defined voltage using a high-resistance switch (e.g., implemented with a PMOS device and a resistor). The capacitor is then connected using a low-resistance switch (e.g., implemented with an NMOS device).

[0056] In Figure 4A this implementation, the secondary branch can have a gain given by:

[0057] The reflection coefficient S in dB 11 is again given by:

[0058] Using this configuration, the secondary branch with the capacitive attenuator 420 and the LNA 4302 maintains improved matching across a wider gain range. More specifically, the L-network attenuator with C1 and C2 provides improved S11 across a wide gain range. In an embodiment, the LNA 4302 is a lower-intensity LNA compared to the LNA 4301. Therefore, the input capacitance of the LNA 4302 is small, allowing small values of C1 and C2 to be used for the capacitive attenuator.

[0059] In one implementation, initially, the resistive attenuator 410 and the LNA 4301 gain slices are backed off within a range where the return loss remains below a specified limit. Then, the attenuation level of the resistive attenuator 410 is frozen and the gain of the secondary branch is backed off (with the LNA 4301 disconnected). Compared with the Figure 3A implementation, this implementation can have a better gain-backoff noise trade-off (since there is no noise figure degradation from a capacitive attenuator), and it can have a smaller impact on linearity degradation.

[0060] Figure 4B FIG. illustrates further details of the secondary LNA 4302. As shown, the LNA 4302 can be implemented with parallel slices (i.e., binary weighted amplifier slices 432 1,2 ). In other implementations, there can be additional binary or other weighted slices.

[0061] Now referring to Figure 4C , a plot is shown that depicts the reflection coefficient S11 with varying levels of the primary resistive attenuator and the secondary capacitive attenuator. The first 4 dB of attenuation is accomplished using the resistive attenuator 410, and the remaining attenuation is accomplished using the capacitive attenuator (while maintaining the attenuation of the attenuator 410 at the 4 dB level). As shown, the minimum reflection loss occurs at a gain-backoff of approximately 2 dB. Although the embodiments are not limited in this regard, this gain-backoff can occur when the value of the capacitive attenuator arrangement in Figure 4A is approximately 12 to 18 dB.

[0062] In other embodiments, there can be additional branches in the receiver signal processing path where controllable resistive and capacitive attenuators are coupled to different paths.

[0063] Now referring to Figure 5A , a schematic diagram of a combined resistive and capacitive attenuator according to an embodiment is shown. As Figure 5A shown, the circuit 500 is part of a receiver that includes an LNA and is implemented as a primary LNA 5301, a secondary LNA 5302, and a tertiary LNA 5303 (of course, in other embodiments, there can be additional branches). As in the above discussion, each LNA 530 can be implemented with multiple slices that can be programmably enabled or disabled.

[0064] Still referring to Figure 5A , a first resistive attenuator 510 is coupled between the primary signal path and a reference voltage node. The value of the first resistive attenuator 510 can be controlled depending on the desired attenuation level.

[0065] As further illustrated, a second resistor attenuator 520 is coupled between the primary signal path node 505 and the secondary LNA 5302. The resistor attenuator 520 includes a fixed resistor R1 serially coupled to the input of the LNA 5302 and a programmable resistor R2 coupled between the input to the LNA 5302 and a reference voltage node. The value of the programmable resistor R2 can be controlled depending on the desired attenuation level.

[0066] Still referring Figure 5A , a capacitor attenuator 525 is coupled between the secondary signal path node 524 and the tertiary LNA 5303. As illustrated, the capacitor attenuator 525 includes a fixed capacitor C1 serially coupled to the input of the LNA 5303 and a programmable capacitor C2 coupled between the input to the LNA 5303 and a reference voltage node. The value of the programmable capacitor C2 can be controlled depending on the desired attenuation level.

[0067] In Figure 5A this implementation, the tertiary branch can have a gain given by:

[0068] The reflection coefficient is in turn given by:

[0069] The secondary and tertiary branches maintain improved matching across a wider gain range. Note that the LNA 530 2,3 can have a lower strength than the LNA 5301. In operation, the resistor attenuator 510 and the LNA 5301 gain slice are depleted during gain backoff. Then, the secondary branch with the resistor attenuator 520 and the LNA 5302 is backed off until S11 reaches a desired low level (where the components of the primary branch are turned off). Finally, the capacitor attenuator 525 and the LNA 5303 are engaged while turning off the LNA 5302 and holding the resistor attenuators 510 and 520 at their desired S11 settings.

[0070] Now referring Figure 5B , a plot of the reflection coefficient S11 is shown for varying levels of primary and secondary resistor and capacitor attenuation.

[0071] Other implementations of the controllable attenuator are possible. Now referring Figure 6 , a schematic diagram is shown illustrating another implementation of a controllable attenuator according to an embodiment. As Figure 6 shown, the combined resistor and capacitor attenuator includes controllable resistor and capacitor paths in parallel. With this arrangement, independent control can exist while optimizing noise and linearity such that both branches can be adjusted simultaneously.

[0072] Specifically, as Figure 6 shown in , the first resistor attenuator 610 is coupled between the primary signal path node 605 and the reference voltage node. The second resistor attenuator 620 is in turn coupled between the primary signal path node 605 and the secondary LNA 6302. The resistor attenuator 620 can be implemented in the same manner as the Figure 3A resistor attenuator 320. Similarly, the capacitor attenuator 625 is coupled between the primary signal path node 605 and the tertiary LNA 6303. The capacitor attenuator 625 can be implemented in the same manner as the Figure 4A capacitor attenuator 420. Although shown at this high level in the Figure 6 embodiment, many variations and alternatives are possible.

[0073] Now referring to Figure 7 , a flowchart of a method according to an embodiment is shown. As Figure 7 shown in , the method 700 is a method for controlling various gain and attenuator elements to enable good reception of incoming RF signals while providing an attenuator configuration with improved impedance matching over a wide range of operating frequencies.

[0074] The method 700 can be performed at least in part by a hardware circuit, such as a controller that executes instructions stored in a non-transitory storage medium. As an example, a receiver can include a controller configured to receive incoming power level information, such as may be obtained from a peak detector at one or more points within the receiver signal processing path (e.g., at RF, IF, and possibly digital locations), and at least partially based on such signal level information, determine appropriate gain settings for gain components, such as for different LNA branches, and appropriate programmable settings for controllable resistors and / or capacitor attenuators as described herein.

[0075] It is understood that Figure 7 shows various gain and attenuator control operations that can be performed based on the signal power level. When the signal level is relatively low, more gain components with higher gain settings are coupled into the receiver signal processing path. As the signal level increases, the gain settings of one or more of these gain components can be updated, for example, by backing off the gain level and / or turning them off. It is also noted that while Figure 7 illustrates specific gain back-off levels and return loss measurements, these values are illustrated for example purposes only.

[0076] As shown, at low signal power levels, the PGA gain can be backed off (block 710). This PGA can be a gain component present in the IF filter circuit and / or in a controllable IF amplifier such as a TIA or PGA. At this low signal level, the reflection coefficient can typically be below -10 dB.

[0077] As shown in blocks 720, 730, and 740, as the signal power level increases, first the primary LNA branch can have its gain backed off, then the resistive attenuator can have its gain backed off, and then additional gain can be backed off within the primary LNA branch. Note that at all of these signal levels, the reflection coefficient can typically be below -10 dB.

[0078] At block 750, as the signal power level further increases, the primary LNA branch can be turned off (while the resistive attenuator can remain on (e.g., at its last backed-off level (e.g., 6 dB in this implementation)), and a gain backing-off process can be performed with respect to the capacitive attenuator. As the signal power level increases, at block 760, the resistive attenuator can again have its gain backed off. At block 760, the 0 - 6 dB Ratt1 gain back-off is complementary to the earlier 6 dB back-off (at block 730).

[0079] Finally, at block 770, at relatively high signal power levels, the secondary and / or tertiary gain branches can have their gains backed off. Note that at such high signal power levels, there may be relaxed input matching. Of course, other values and other orders of attenuator / gain control can occur in other embodiments.

[0080] Now referring Figure 8 , a block diagram of a representative integrated circuit 800 including a dynamically controllable RF attenuator as described herein is shown. In the embodiment shown in Figure 8 , the integrated circuit 800 can be, for example, a dual-mode wireless transceiver that can operate according to one or more wireless protocols (e.g., WLAN and Bluetooth, etc.) or other devices that can be used in various use cases. In one or more embodiments, the circuitry of the integrated circuit 800 shown in Figure 8 can be implemented on a single semiconductor die.

[0081] The integrated circuit 800 can be included in a series of devices including various stations, the devices including smart phones, wearable devices, smart home devices, other consumer devices, or industrial, scientific, and medical (ISM) devices, etc.

[0082] In the illustrated embodiment, integrated circuit 800 includes memory system 810, which in an embodiment may include volatile storage devices such as RAM and non-volatile memory (such as flash memory). As further shown, integrated circuit 800 may also optionally include separate flash memory 890 (or other non-volatile memory). Flash memory 890 may be implemented as a non-transitory storage medium that can store instructions and data. Such non-volatile memory may store instructions, including instructions for identifying conditions that may trigger a change in RF attenuation level, as described herein.

[0083] Memory system 810 is coupled to digital core 820 via bus 850. Digital core 820 may include one or more cores and / or microcontrollers that act as the main processing unit of the integrated circuit. Digital core 820 may in turn be coupled to clock generator 830, which may provide one or more phase-locked loops or other clock generator circuits to generate various clocks for use by the circuits of the IC.

[0084] As further illustrated, IC 800 also includes power circuit 840, which may include one or more voltage regulators. Depending on the particular implementation, additional circuits may optionally be present to provide various functionality and interaction with external devices. Such circuits may include interface circuit 860 and security circuit 870. Interface circuit 860 may provide a LAN or other interface with various off-chip devices, and security circuit 870 may perform wireless security techniques.

[0085] Additionally, as Figure 8 shown, transceiver circuit 880 may be provided to implement transmission and reception of wireless signals according to one or more of local or wide area wireless communication schemes such as Zigbee, Bluetooth, IEEE 802.11, IEEE 802.15.4, cellular communication, etc. As shown, transceiver circuit 880 includes a separate branch of RF attenuator 885 1-n that may be dynamically selected at least in part based on the signal level to provide a desired amount of attenuation while maintaining a small reflection coefficient, as described herein. It is understood that while shown at this high level view, many variations and alternatives are possible.

[0086] Integrated circuits such as those described herein may be implemented in a variety of different devices such as wireless stations, IoT devices, etc. Now referring Figure 9 to Figure 9As shown, network 900 includes various devices, including wireless stations, which include smart devices such as IoT devices, access points, and remote service providers, which may utilize embodiments of dynamic RF attenuator control as described herein.

[0087] In Figure 9 an embodiment, a wireless network 905 exists, for example, in a building having a plurality of wireless devices 910 0-n . As shown, the wireless devices 910 are coupled to an access point 930, which in turn communicates with a remote service provider 960 via a wide area network 950 (such as the Internet). It is understood that while shown at this high level in Figure 9 an embodiment, many variations and alternatives are possible.

[0088] Although the invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate many modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of the invention.

Claims

1. A device comprising: a first amplifier coupled to a first node of a receiver signal processing path, the first amplifier configured to receive and amplify a radio frequency (RF) signal; a first resistive attenuator coupled to the first node, the first resistive attenuator being programmable to reduce a level of the RF signal; a second amplifier coupled in parallel with the first amplifier, the second amplifier configured to receive and amplify the RF signal; as well as A second attenuator is coupled between the first node and the second amplifier, the second attenuator being programmable to reduce the level of the RF signal. 2 . The apparatus of claim 1 , further comprising a controller for controlling a first attenuation level of the first attenuator and controlling a second attenuation level of the second attenuator.

3. The device according to claim 2, wherein: The controller is to control the first attenuation level and the second attenuation level based at least in part on a gain level of the first amplifier and a gain level of the second amplifier.

4. The device according to claim 2, wherein: The controller is to control the gain level of the first amplifier, the gain level of the second amplifier, the first attenuation level, and the second attenuation level according to a predetermined sequence.

5. The device according to claim 4, wherein: The controller is to control the gain level of the first amplifier, the gain level of the second amplifier, the first attenuation level, and the second attenuation level according to the predetermined sequence to maintain the return loss below a threshold level.

6. The device according to claim 4, wherein: The predetermined sequence includes controlling the gain level of the first amplifier first, controlling the first attenuation level second, controlling the gain level of the second amplifier third, and controlling the second attenuation level fourth.

7. The apparatus of claim 1, wherein: The first resistance attenuator comprises: a first programmable resistor coupled between the first node and a reference voltage node; and The second attenuator comprises: a first resistor coupled between the first node and an input terminal of the second amplifier; and A second programmable resistor is coupled between the input of the second amplifier and the reference voltage node.

8. The device according to claim 1, wherein: The second attenuator comprises: a first capacitor coupled between the first node and an input terminal of the second amplifier; and A first programmable capacitor is coupled between the input of the second amplifier and a reference voltage node.

9. The apparatus according to claim 1, further comprising: a third amplifier coupled in parallel with the first amplifier, the third amplifier being configured to receive and amplify the RF signal; as well as A third attenuator is coupled between the second attenuator and the third amplifier, the third attenuator being configured to reduce the level of the RF signal.

10. The device according to claim 9, wherein: The second attenuator comprises a programmable resistive attenuator, and the third attenuator comprises a programmable capacitive attenuator.

11. The device according to claim 1, further comprising: a third amplifier coupled in parallel with the first amplifier, the third amplifier being configured to receive and amplify the RF signal; as well as A third attenuator is coupled between the first node and the third amplifier, the third attenuator being configured to reduce the level of the RF signal.

12. The device according to claim 1, wherein: The first resistive attenuator and the second attenuator are positioned remotely from the receiver signal processing path.

13. The apparatus according to claim 1, wherein: The first resistive attenuator and the second attenuator provide an attenuation range of at least 20 decibels and enable a reflection coefficient of the receiver to be less than approximately -10 decibels.

14. A method comprising: determining, in a receiver, a signal level associated with a radio frequency (RF) signal received in the receiver; Based at least in part on the signal level associated with the RF signal, first controlling a gain of a first amplifier coupled along a receiver signal processing path of the receiver, the first amplifier configured to receive and amplify the RF signal, and thereafter controlling a gain of a first resistive attenuator coupled to an input of the first amplifier until the first amplifier and the first resistive attenuator are turned off; as well as Thereafter, a gain of a second attenuator coupled between the input of the first amplifier and an input of a second amplifier coupled in parallel with the first amplifier is controlled, and thereafter a gain of the second amplifier is controlled.

15. The method of claim 14, further comprising controlling the gain of a lower frequency gain control circuit coupled along the receiver signal processing path downstream of the first amplifier before controlling the gain of the first amplifier. 16 . The method of claim 14 , further comprising iteratively controlling the gain of the first amplifier and controlling the gain of the first resistive attenuator until the gain of the first amplifier is exhausted.

17. The method of claim 14, further comprising controlling the gain of the second attenuator when the signal level associated with the RF signal exceeds a second level greater than the first level, and thereafter controlling the gain of the second amplifier.

18. A wireless device comprising: an antenna for receiving and transmitting radio frequency (RF) signals of at least a first frequency band and a second frequency band; a switching circuit coupled to the antenna; a matching network circuit coupled to the switch circuit to provide impedance matching; as well as a multi-band transceiver coupled to the matching network circuit to process the RF signals of at least the first frequency band and the second frequency band, the multi-band transceiver comprising a first receiver, the first receiver comprising: a first amplifier adapted along a first receiver signal processing path between the first node and the second node, the first amplifier being configured to receive and amplify a first RF signal in the first frequency band; a first resistive attenuator coupled between the first node and a reference voltage node, the first resistive attenuator being programmable to reduce a level of the first RF signal in the first frequency band; a second amplifier coupled in parallel with the first amplifier between the first node and the second node, the second amplifier being configured to receive and amplify the first RF signal of the first frequency band; and A first capacitive attenuator is coupled in parallel with the first resistive attenuator between the first node and the reference voltage node, the first capacitive attenuator is further coupled to an input of the second amplifier, and the second capacitive attenuator is programmable to reduce the level of the first RF signal in the first frequency band.

19. The wireless device of claim 18, further comprising a controller for controlling a first attenuation level of the first resistive attenuator and controlling a second attenuation level of the first capacitive attenuator based at least in part on a signal level of the first RF signal in the first frequency band.

20. The wireless device of claim 19, wherein: The controller is to first back off the gain of the first resistive attenuator and the first amplifier, and thereafter back off the gain of the first capacitive attenuator and the second amplifier, wherein the first amplifier has a greater gain than the second amplifier.

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