Phase-locked loop circuit and control method thereof

Abstract

The invention discloses a phase-locked loop circuit and a control method thereof, and proposes that a filter of the phase-locked loop circuit comprises a first filtering module and a second filtering module, and before the phase-locked loop circuit is locked, a control module bypasses the second filtering module to improve the locking speed; after the phase-locked loop circuit is locked, the control module controls the second filtering module to be connected to the phase-locked loop circuit so as to reduce jitter or reduce the area of the phase-locked loop. Furthermore, the second filtering module is provided with a control unit, so that when the system is insensitive to the output jitter of the phase-locked loop, the control unit controls locking, and when the system is sensitive to the output jitter of the phase-locked loop, the control unit controls open loop, and the influence of the output jitter of the phase-locked loop on the system is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular, to a phase-locked loop circuit and a control method thereof. Background Art

[0002] The traditional charge pump phase-locked loop circuit is as Figure 1 shown, and includes: a prescaler ( / M), a phase frequency detector (PFD), a charge pump circuit (CP), a loop filter (LPF), a voltage controlled oscillator (VCO), a loop divider ( / N), an output divider ( / K), and ( / L).

[0003] As the phase-locked loop circuit is more and more widely used in chips, there is usually one or more phase-locked loop circuits in a chip to provide the clock frequencies required by the chip. As an important module of the phase-locked loop circuit, the loop filter is used to receive the output current from the charge pump and then generate a control voltage for controlling the voltage controlled oscillator. The common implementation method is Figure 1 the combination of a large capacitor and a large resistor as shown, a second-order filter shown in the dashed box. The capacitor C1 is a large capacitor that acts as an integration path, usually in the range of dozens to hundreds of picofarads. The resistor R1 is a large resistor that acts as a proportional path, usually in the range of thousands to tens of thousands of ohms. The capacitor C2 acts as a further filtering function, usually in the range of a few picofarads to dozens of picofarads. Such a filter is not conducive to reducing the area of the phase-locked loop circuit.

[0004] Moreover, although there are some studies on reducing the area of the phase-locked loop circuit in the existing literature, it is difficult to take into account the locking speed. For example, the circuit provided in the patent document WO2021174420 A1 can be used to reduce the area of the phase-locked loop, but it sacrifices the locking speed of the phase-locked loop. Therefore, how to reduce the area of the phase-locked loop to reduce the cost of chip manufacturing, and on this basis, how to reduce the output jitter of the phase-locked loop has become a research difficulty in the current industry. Summary of the Invention

[0005] Based on the above-described problems, the present invention proposes to set the filter to include a first filtering module and a second filtering module. Before the phase-locked loop circuit is locked, the control module bypasses the second filtering module to improve the locking speed; after the phase-locked loop circuit is locked, the control module controls the second filtering module to be connected to the phase-locked loop circuit to reduce jitter or reduce the area of the phase-locked loop. Specifically as follows: In a first aspect, an embodiment of the present invention provides a phase-locked loop circuit, the phase-locked loop circuit includes a filter, and is characterized in that the filter includes: A first filtering module, the first filtering module includes a low-pass filtering circuit; A second filtering module; The control module bypasses the second filtering module before the phase-locked loop circuit is locked to improve the locking speed; after the phase-locked loop circuit is locked, the control module controls the second filtering module to be connected to the phase-locked loop circuit to reduce jitter or reduce the area of the filter.

[0006] In a preferred embodiment, the second filtering module includes a control unit, and the control unit includes a first state and a second state; When the control unit is in the first state, the control unit is used to control the second filtering module to enable low-frequency signals to pass through directly and high-frequency signals to be attenuated; When the control unit is in the second state, it is used to reduce output jitter.

[0007] In a preferred embodiment, the first state is a conducting state and the second state is a non-conducting state.

[0008] In a preferred embodiment, the phase-locked loop circuit further includes a locking detection module, which is used to detect the locking state of the phase-locked loop circuit and output a locking state signal to the control module, and the control module controls the second filtering module according to the locking state signal.

[0009] In a preferred embodiment, the low-pass filter circuit includes any one of a first-order low-pass filter, a second-order low-pass filter, a third-order low-pass filter or a higher-order low-pass filter.

[0010] In a preferred embodiment, the second filtering module includes a first circuit unit and a second circuit unit connected in series, and the control unit is electrically connected between the first circuit unit and the second circuit unit.

[0011] In a preferred embodiment, after the phase-locked loop circuit is locked, the second filtering module is controlled to be connected to the phase-locked loop circuit, and the control unit is controlled to be in the first state to reduce the filter area or reduce the jitter of the phase-locked loop circuit; or the control unit is controlled to be in the second state to reduce output jitter.

[0012] In a preferred embodiment, according to a preset period, the control unit is periodically controlled to be in the first state or the second state.

[0013] In a preferred embodiment, the second filtering module includes a first circuit unit and a second circuit unit connected directly in series.

[0014] In a preferred embodiment, the first circuit unit includes a first capacitor unit and a first resistor unit connected in parallel, and the second circuit unit includes a second capacitor unit.

[0015] In a preferred embodiment, the first circuit unit further includes a second resistor unit, the second resistor unit is connected in series with the first capacitor unit and in parallel with the first resistor unit; and / or, the second circuit unit further includes a third resistor unit, the third resistor unit is connected in series with the second capacitor unit.

[0016] In a preferred embodiment, the control module controls the bypass of the second filtering module by controlling the bypass of the first circuit unit.

[0017] In a preferred embodiment, the control module includes a transmission gate and an inverter. The input terminal and the output terminal of the transmission gate are electrically connected to the first end and the second end of the first resistor unit respectively. The first control terminal of the transmission gate is directly electrically connected to the output terminal of the lock detection module, and the second control terminal of the transmission gate is electrically connected to the output terminal of the lock detection module through the inverter.

[0018] In a second aspect, the embodiment of the present invention further provides a control method for the phase-locked loop circuit based on any one of the foregoing embodiments. The control module controls the bypass of the second filtering module according to the lock state signal output by the lock detection module before the phase-locked loop circuit is locked to achieve the effect of fast locking; after the phase-locked loop circuit is locked, the control module controls the second filtering module to be connected to the phase-locked loop circuit to reduce jitter or reduce the area of the filter.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The present invention proposes to provide a filter including a first filtering module and a second filtering module. By bypassing the second filtering module before the phase-locked loop circuit is locked, the control module can improve the locking speed; after the phase-locked loop circuit is locked, the control module controls the second filtering module to be connected to the phase-locked loop circuit to reduce jitter or reduce the area of the phase-locked loop. Further, it is also proposed that the second filtering module is provided with a control unit to realize that when the system is less sensitive to the output jitter of the phase-locked loop, the control unit controls the loop to close, and when the system is sensitive to the output jitter of the phase-locked loop, the control unit controls the open loop, thereby further reducing the influence of the output jitter of the phase-locked loop on the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings of the present invention form a part of this specification and are used to further understand the present invention. The drawings show embodiments of the present invention and are used together with the specification to illustrate the principles of the present invention.

[0021] Figure 1 It is an example of a conventional phase-locked loop.

[0022] Figure 2a It is a structure diagram of a phase-locked loop according to an embodiment of the present invention.

[0023] Figure 2bDetailed structural diagram of a phase-locked loop according to an embodiment of the present invention.

[0024] Figures 3a - 3c Example of the first filtering module according to an embodiment of the present invention.

[0025] Figure 4a Structural diagram of the second filtering module according to an embodiment of the present invention.

[0026] Figures 4b - 4d Example of the second filtering module according to an embodiment of the present invention.

[0027] Figure 5 Detailed circuit diagram of a phase-locked loop according to a specific embodiment of the present invention.

[0028] Figures 6a - 6b For Figure 5 the equivalent circuit of the detailed circuit of the phase-locked loop based on different controls. Specific embodiments

[0029] The following detailed descriptions are all illustrative and are intended to provide further description of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0030] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention.

[0031] First, the functions of each basic module involved in the existing phase-locked loop are introduced as follows, taking Figure 1 as an example: Prescaler ( / M): Receives a clock signal with a frequency of fref from outside the phase-locked loop and outputs a reference clock signal with a reduced frequency of fref / M suitable for phase-locked loop applications. It is usually implemented in the form of a digital counter, and the value of M can be variable according to application requirements.

[0032] Phase Frequency Detector (PFD): Receives the reference clock signal output from the prescaler ( / M) and the feedback clock signal output from the loop divider ( / N), compares the phase difference between the two, and outputs corresponding up and down signals. If the phase difference between the reference clock and the feedback clock is negative, that is, the reference clock signal lags behind the feedback clock signal, the down signal is high and the up signal is low; if the phase difference between the reference clock and the feedback clock is positive, that is, the reference clock signal leads the feedback clock signal, the up signal is high and the down signal is low; if the reference clock and the feedback clock arrive at the same time, the output up and down signals are both high for a period of time and then both low, and this period of time is usually determined by the delay circuit in the phase frequency detector circuit.

[0033] Charge pump circuit (CP): Receives the up signal and down signal output from the phase frequency detector (PFD). If the up signal is at a high level and the down signal is at a low level, the charge pump circuit (CP) outputs a charging current into the loop filter (LPF), causing the output voltage Vc of the loop filter (LPF) to increase and the frequency of the voltage controlled oscillator (VCO) to increase. If the up signal is at a low level and the down signal is at a high level, the charge pump circuit (CP) extracts a discharging current from the loop filter (LPF), causing the output voltage Vc of the loop filter (LPF) to decrease and the frequency of the voltage controlled oscillator (VCO) to decrease. If the up signal and the down signal are both at a high level, the charging and discharging currents are both turned on. At this time, if there is no mismatch between the charging and discharging currents, the output voltage Vc of the loop filter (LPF) remains unchanged and the output frequency of the voltage controlled oscillator (VCO) remains unchanged. If the up signal and the down signal are both at a low level, the charging and discharging currents are both turned off, then the output voltage Vc of the loop filter (LPF) remains unchanged and the output frequency of the voltage controlled oscillator (VCO) remains unchanged.

[0034] Loop filter (LPF): Figure 1 The loop filter (LPF) shown in it is composed of two capacitors C1, C2 and a resistor R1, receives the current signal output by the charge pump circuit (CP), and converts the current signal into a voltage signal Vc for output to the voltage controlled oscillator (VCO). The voltage controlled oscillator (VCO) changes its output frequency according to the magnitude of Vc.

[0035] Voltage controlled oscillator (VCO): Receives the output voltage Vc from the loop filter (LPF), and outputs a clock signal with a corresponding frequency fout according to the magnitude of Vc.

[0036] Loop divider ( / N): Receives the clock signal output by the voltage controlled oscillator (VCO), and outputs a feedback clock signal with a down-converted frequency of fout / N. It is usually implemented in the form of a digital counter, and the magnitude of N can be variable according to application requirements.

[0037] Output dividers ( / K) and ( / L): Receive the clock signal output by the voltage controlled oscillator (VCO), and output clock signals with down-converted frequencies of fclk1 = fout / K and fclk2 = fout / L, which are provided to the modules outside the phase locked loop that require clock signals. It is usually implemented in the form of a digital counter, and the magnitudes of K and L can be variable according to application requirements. Since the phase locked loop is a negative feedback system, after the phase locked loop is locked, there will be fout / N = fref / M, resulting in fclk1 = N×fref / (K×M), and fclk1 = N×fref / (L×M). By selecting appropriate values of M, N, K, and L, the desired output frequency clock signal can be obtained.

[0038] The PLL example provided by the present invention will be introduced in detail below.

[0039] As Figures 2a - 2b shown, it is a PLL structure diagram according to an embodiment of the present invention. Compared with the existing PLL circuits such as Figure 1 shown, in this embodiment, the filter part is designed. The filter 0 of the PLL circuit includes: a first filter module 1 and a second filter module 2. The PLL circuit further includes a lock detection module 7 and a control module 3.

[0040] Among them, the first filter module 1 may include a low-pass filter circuit; preferably, the first filter module 1 is connected to the output Vc node of the charge pump circuit CP. The low-pass filter circuit included in the first filter module 1 may be a low-pass filter of any order. For example, it may be a first-order low-pass filter, as Figure 3a shown, including an RC series circuit with one end connected to the node Vc and the other end grounded. Specifically, the first-order low-pass filter may include a resistor unit R 11 and a capacitor unit C 11 ; the low-pass filter may also be a second-order low-pass filter, as Figure 3b shown. Compared with the first-order low-pass filter, it further includes a capacitor unit C 21 with one end connected to the node Vc and the other end grounded; the low-pass filter may also be a third-order low-pass filter, as Figure 3c shown. Compared with the second-order low-pass filter, it further includes a resistor unit R 13 and a capacitor unit C 13 . One end of the resistor unit R 13 is connected to the node Vc and the other end is connected to the charge pump current output end. The low-pass filter may also be a higher-order low-pass filter, which will not be elaborated here one by one. It should be noted that R 11 , R 13 respectively represent the total equivalent resistance between two nodes in its circuit, and C 11 , C 21 are the total equivalent capacitances between two nodes respectively, and different implementation forms may be available according to the semiconductor manufacturing process.

[0041] The second filter module 2 is also connected to the output Vc node of the charge pump circuit CP. Preferably, as Figure 4aAs shown, the second filtering module 2 includes a first circuit unit 4, a second circuit unit 6 connected in series, and a control unit 5. The control unit 5 is electrically connected between the first circuit unit 4 and the second circuit unit 6. The control unit 5 includes a first state and a second state. The first state can make the phase-locked loop circuit in a closed-loop state, and the second state can make the phase-locked loop circuit in an open-loop state. The control unit 5 can be a switch. When the switch is in the first state, it is in a conducting state to maintain the phase-locked loop circuit in a closed-loop state. When the switch is in the second state, it is in an off state to maintain the phase-locked loop circuit in an open-loop state. Specifically, when the control unit 5 is in the first state, the control unit 5 is used to control the second filtering module 2 to achieve direct passing of low-frequency signals and attenuation of high-frequency signals. When the control unit 5 is in the second state, it is used to reduce the output jitter of the phase-locked loop circuit.

[0042] Preferably, the second filtering module 2 is preferably as Figure 4b shown. The first circuit unit 4 includes a first capacitor unit C 21 and a first resistor unit R 21 connected in parallel, and the second circuit unit 5 includes a second capacitor unit C 22 . The control unit 5 includes a switch S1. When the switch S1 is conducting, it realizes the effect of direct passing of low-frequency signals from Vc to Vcont and attenuation of high-frequency signals to obtain a small equivalent K VCO . When the switch S1 is off, the phase-locked loop is disconnected, thereby isolating the jitter introduced by the periodic phase discrimination behavior of the frequency discriminator and phase discriminator to reduce the output jitter of the phase-locked loop.

[0043] Preferably, the second filtering module 2 can also be as Figure 4c shown. The first circuit unit 4 further includes a second resistor unit R 22 . The second resistor unit R 22 is connected in series with the first capacitor unit C 21 and is connected in parallel with the first resistor unit R 21 .

[0044] Preferably, the second filtering module 2 can also be as Figure 4d shown. The second circuit unit 5 further includes a third resistor unit R 23 . The third resistor unit R 23 is connected in series with the second capacitor unit C 22 . In addition, the second circuit unit 5 includes a third resistor unit R 23 . At the same time, the first circuit can also include a second resistor unit R 21 connected in series with the first capacitor unit C 22 , and the second resistor unit R 22 is connected in parallel with the first resistor unit R 21 .

[0045] It should be noted that the first resistor unit R 21 , the second resistor unit R 22 , and the third resistor unit R 23 are respectively the total equivalent resistances between two nodes in the circuit. The first capacitor unit C 21 , and the second capacitor unit C 22 are respectively the total equivalent capacitances between two nodes. The capacitor or resistor can have different implementation forms according to the semiconductor manufacturing process. Additionally, in this embodiment, S1 is a switch, such as an NMOS transistor, a PMOS transistor, or a parallel circuit of an NMOS transistor and a PMOS transistor. As a control unit, as long as it can achieve the functions of connection and disconnection, it is also acceptable. In some applications where the switch S1 needs to be always on, the switch S1 can also be replaced by a resistor or a wire.

[0046] Based on the foregoing phase-locked loop circuit, before the phase-locked loop circuit is locked, the control module 3 bypassing the second filtering module 2 can improve the locking speed; after the phase-locked loop circuit is locked, the control module 3 controlling the second filtering module 2 to be connected to the phase-locked loop circuit can reduce jitter or reduce the area of the filter.

[0047] Preferably, the locking detection module 7 is used to detect the locking state of the phase-locked loop circuit and output a locking state signal to the control module 3, and the control module 3 controls the second filtering module 2 according to this locking state signal.

[0048] Preferably, the control module 3 can also control the bypass of the second filtering module 2 by controlling the bypass of the first circuit unit 4.

[0049] The present invention also provides a control method based on the foregoing phase-locked loop circuit. The control module 3, according to the locking state signal output by the locking detection module 7, before the phase-locked loop circuit is locked, controls the second filtering module 2 to be bypassed to achieve the effect of fast locking; after the phase-locked loop circuit is locked, controls the second filtering module 2 to be connected to the phase-locked loop circuit to reduce jitter or reduce the area of the filter. Specifically, before locking, the second filtering module is bypassed (for example: it can be short-circuited), and at this time only the first filtering module 1 functions, and the effect of fast locking can be achieved; after locking, the second filtering module 2 functions and the switch S1 is turned on, and the effect of a small equivalent Kvco (the gain of the voltage-controlled oscillator) can be achieved. At this time, according to the requirements of the application, the obtained small equivalent Kvco can be used to achieve the effect of low area or low jitter.

[0050] Preferably, after the phase-locked loop circuit is locked, the second filtering module 2 is controlled to be connected to the phase-locked loop circuit, and the control unit 5 is controlled to be in the first state to reduce the filter area or reduce the jitter of the phase-locked loop circuit; or the control unit 5 is controlled to be in the second state to reduce the output jitter. Specifically, after the phase-locked loop is locked, the on or off of the switch S1 in the second filtering module can be periodically controlled according to the application scenario. This includes but is not limited to disconnecting S1 in a short period when the system is sensitive to the output jitter of the phase-locked loop, thereby reducing the output jitter and improving the system performance; and closing S1 during the time when the system is less sensitive to the output jitter of the phase-locked loop to achieve normal locking.

[0051] Preferably, the control unit can also be periodically controlled to be in the first state or the second state according to a preset period T, so that the phase-locked loop circuit can match different degrees of output jitter sensitivity according to different preset periods T. Embodiment

[0052] As Figure 5 shown, it is the detailed circuit diagram of the phase-locked loop of a specific embodiment of the present invention. The control module 3 can include a transmission gate PSG and an inverter INV. The input terminal and the output terminal of the transmission gate PSG are electrically connected to the first terminal and the second terminal of the first resistor unit R 21 respectively, and the first terminal and the second terminal refer to the input terminal and the output terminal of the first resistor unit R 21 . The first control terminal of the transmission gate PSG is directly electrically connected to the output terminal of the lock detection module 7, and the second control terminal of the transmission gate PSG is electrically connected to the output terminal of the lock detection module 7 through the inverter INV.

[0053] Compared with Figure 1 the structure of the traditional loop filter used in the phase-locked loop circuit shown, in the phase-locked loop circuit of the embodiment in Appendix Figure 5 , on the basis of the first filtering module, a second filtering module 2 is added to the filter 0 used in the embodiment, that is, a first circuit unit composed of the first resistor unit R 21 and the first capacitor unit C 21 is added, and a second circuit unit composed of the second capacitor unit C 22 is added. In this embodiment, the first circuit unit and the second circuit unit are directly connected in series through a wire. In addition, the phase-locked loop of this embodiment in Appendix Figure 5 also adds a control module 3 for controlling the bypass or connection of the second filtering module to the phase-locked loop circuit, and a lock detection module 7 for detecting whether the loop is locked. In this embodiment, for example, when the phase-locked loop is not locked, the output signal of the lock detection module 7 is low. At this time, the transmission gate PSG is turned on, and Vc and Vcont are short-circuited, that is, the first circuit unit of the second filtering module is bypassed. At this time, the locking speed of the phase-locked loop circuit can be accelerated, and the equivalent circuit at this time is as shown in Figure 6aAs shown, only the capacitor from Vc to ground changes from C2 in the traditional phase-locked loop circuit to C 12 +C 22 . After the phase-locked loop is locked, the output signal of the lock detection module 7 is high. At this time, the transmission gate is disconnected, and the equivalent circuit can be as shown in Figure 6b .

[0054] For easy comparison, first introduce the existing phase-locked loop shown in Figure 1 . The resistance and capacitance values of the second-order loop filter in it are usually determined by the maximum phase margin method. According to this rule, the following relationships (1) to (5) can be obtained: (1) (2) (3) (4) (5) where b is the ratio of the two capacitors C1 and C2. When b = 13, the phase margin is about 60°. w c is the bandwidth of the phase-locked loop, usually about 1 / 10 of the reference clock frequency. w z is the zero point of the open-loop transfer function of the phase-locked loop. K cp and K vco are the gains of the frequency discriminator / phase detector charge pump and the voltage-controlled oscillator respectively, and N is the loop division ratio.

[0055] Next, a detailed analysis will be carried out based on the circuit principle of Figure 6b . The loop gain transfer function of this phase-locked loop can be approximated as Equation (6) at low frequencies: (6) At high frequencies, it can be approximated as Equation (7): (7) where, (8) K cp and K vco are the gains of the frequency discriminator / phase detector charge pump and the voltage-controlled oscillator respectively, N is the loop division ratio, and s is the complex frequency. Compared with the phase-locked loop based on the traditional second-order loop filter structure of Figure 1 , the resistance of the newly added first resistor unit R 21 is in the megohm level (can be realized by polysilicon resistors or diodes), and the capacitance values of the first capacitor unit C 21 and the second capacitor unit C 22 are in the picofarad level. Because the first resistor unit R 21The resistance value will be designed to be several orders of magnitude higher than that of the R1 included in the filter of the traditional phase-locked loop, but the first capacitor unit C 21 and the second capacitor unit C 22 differ from the capacitors C1 and C2 included in the filter of the traditional phase-locked loop by less than two orders of magnitude; therefore, the zero-poles introduced additionally by the second filtering module circuit will be much smaller than those introduced by the traditional second-order filter (R1, C1, C2) itself. Therefore, the newly added modules can make the open-loop transfer function of the phase-locked loop first see the zero-poles introduced by the first resistor unit R 21 , the first capacitor unit C 21 and the second capacitor unit C 22 , and then the zero-poles introduced by the resistor unit R 11 , the capacitor unit C 11 , the capacitor unit C 12 of the low-pass loop filter of the first filtering module. Among them, the low-frequency component of Vc can directly reach Vcont through the first resistor unit R 21 , and the high-frequency component of Vc is divided by the first capacitor unit C 21 , and after attenuation, it reaches Vcont, finally making the equivalent K VCO attenuation of the loop become α times that of the original, where α = C 21 ⁄ (C 21 + C 22 ). Utilizing the characteristic that the equivalent K VCO attenuation becomes α times that of the original, compared with the capacitors C1 and C2 of the traditional loop filter, the capacitor units C 11 , C 12 involved in the first filtering module of this implementation can be reduced to 1 / α times that of the original. In order to ensure that the loop bandwidth and phase margin remain unchanged, it is only necessary to magnify the resistor R1 used in the traditional phase-locked loop to 1 / α times that of the original, that is, set the resistance value of the resistor unit R 11 of the first filtering module to 1 / α times that of R1. Since the capacitor is one of the most area-consuming devices in the integrated circuit, a large capacitor means a large size. Therefore, the reduction of the capacitor described above in this embodiment can significantly reduce the area of the phase-locked loop filter, thereby reducing the area of the phase-locked loop and its manufacturing cost.

[0056] It should be emphasized that the newly added first resistor unit R 21 in this embodiment will be set with a relatively large resistance value. In order to reduce the influence of the large time constant introduced by the large resistance value on the slow voltage establishment, that is, in order to reduce the newly added first resistor unit R 21 , the first capacitor unit C 21 and the second capacitor unit C 22The influence on the voltage of the Vc node and the establishment speed of the voltage of the Vcont node before the phase-locked loop locks. In this embodiment, the locking detection module 7 is used to control the filter 0, so that before locking, although the topological structure of the phase-locked loop is the same as the traditional one, due to the resistance unit R 11 is 1 / α times that of the traditional resistor R1, and the capacitance value of the capacitance unit C 11 is α times that of the capacitance C1 of the traditional structure, which can make the loop bandwidth of the phase-locked loop in this stage higher than that of the traditional structure, so as to achieve the effect of faster locking compared with the traditional structure. The specific reason can be seen from the expression of the bandwidth in formula (5). It can be known that a large R 11 resistance value can bring a large bandwidth, and thus can bring a large locking speed. Qualitatively analyzed from the time domain, the current in the circuit of this embodiment charges and discharges the capacitor. The charging and discharging current remains unchanged, but the capacitor becomes smaller, so the change rate of the voltage becomes higher and can reach the expected value more quickly.

[0057] In addition, the phase-locked loop circuit of this embodiment can also be used to design a phase-locked loop circuit with low output jitter. Using the characteristic that the equivalent K VCO attenuation is 1 / α times that of the original, only compared with the traditional structure, keep the resistance unit R 11 、C 11 、C 12 of the first filter module consistent with the values of R1, C1, and C2 included in the filter of the traditional phase-locked loop circuit. At the same time, increase the phase-locked loop charge pump current to 1 / α times that of the traditional structure, and then it is possible to achieve smaller output jitter while maintaining the same loop bandwidth and phase margin as the traditional structure, and at the same time be able to achieve faster locking.

[0058] In summary, based on the phase-locked loop circuit proposed by the present invention, the phase-locked loop circuit can be designed according to the actual application scenario. Suppose in a first application scenario, the size requirement for the phase-locked loop circuit is relatively high, then design the resistance unit R 11 、C 11 、C 12 of the first filter module of the phase-locked loop circuit for the aforementioned design to reduce the area of the filter and thus reduce the area of the phase-locked loop circuit. If in a second application scenario, the requirement for reducing output jitter is particularly strong, it is possible to choose to keep the resistance unit R 11 、C 11 、C 12 of the first filter module consistent with the values of R1, C1, and C2 included in the filter of the traditional phase-locked loop circuit, and at the same time increase the phase-locked loop charge pump current to 1 / α times that of the traditional structure. Or, regardless of the resistance unit R 11 、C 11 、C 12Whether the values of R1, C1, and C2 included in the filter of the traditional phase-locked loop circuit are kept consistent or not. Further, a second filtering module is provided with a control unit to achieve that when the system is less sensitive to the output jitter of the phase-locked loop, the control unit controls locking, and when the system is sensitive to the output jitter of the phase-locked loop, the control unit controls open-loop, thereby reducing the impact of the output jitter of the phase-locked loop on the system. The setting of this control unit can enable the circuit designed in the aforementioned first application scenario to obtain good low-output-jitter performance. For the circuit designed in the aforementioned second application scenario, it can further reduce the output jitter on the basis of the reduced output jitter, thereby obtaining better low-output-jitter performance.

[0059] The following uses an example to strengthen the description of the phase-locked loop in the attached Figure 5 embodiment. For example, it is desired that the phase-locked loop achieves a bandwidth of 400 kHz and a phase margin of 60°. The following conditions are known: 、 、

[0060] If a phase-locked loop circuit designed with a traditional second-order loop filter as shown in Figure 1 is adopted, generally it is necessary to satisfy: 、 、

[0061] If the structure of this embodiment is adopted, then, for example, it can be designed as: 、 、 、 、 、

[0062] Before the phase-locked loop is locked, the first resistor unit R 21 and the first capacitor unit C 21 are bypassed by the control module 3, and the loop bandwidth can reach 950 kHz and the phase margin is 30°. In this way, it can be used to accelerate the locking of the phase-locked loop. After the phase-locked loop is locked, the control module 3 connects the first resistor unit R 21 and the first capacitor unit C 21 to the phase-locked loop circuit. The first resistor unit R 21 and the first capacitor unit C 21 come into play, making the loop bandwidth 400 kHz and the phase margin 60°.

[0063] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to the present invention. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to the present invention. Such modifications, improvements, and corrections are suggested in the present invention, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of the present invention.

[0064] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, by way of example and not limitation, alternative configurations of the embodiments of the present invention may be regarded as consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A phase-locked loop circuit, the phase-locked loop circuit comprising a filter, characterized in that, The filter includes: A first filtering module, the first filtering module including a low-pass filtering circuit; A second filtering module; A control module. Before the phase-locked loop circuit is locked, the control module bypasses the second filtering module to improve the locking speed; after the phase-locked loop circuit is locked, the control module controls the second filtering module to be connected to the phase-locked loop circuit to reduce jitter or reduce the area of the filter.

2. The phase-locked loop circuit according to claim 1, characterized in that, The second filtering module includes a control unit, and the control unit includes a first state and a second state; When the control unit is in the first state, the control unit is used to control the second filtering module to enable direct passage of low-frequency signals and attenuation of high-frequency signals; When the control unit is in the second state, it is used to reduce output jitter.

3. The phase-locked loop circuit according to claim 2, characterized in that, The first state is a conducting state, and the second state is a non-conducting state.

4. The phase-locked loop circuit according to claim 1, characterized in that, The phase-locked loop circuit further includes a locking detection module, which is used to detect the locking state of the phase-locked loop circuit and output a locking state signal to the control module, and the control module controls the second filtering module according to the locking state signal.

5. The phase-locked loop circuit according to claim 1, characterized in that, The low-pass filtering circuit includes any one of a first-order low-pass filter, a second-order low-pass filter, a third-order low-pass filter, or a higher-order low-pass filter.

6. The phase-locked loop circuit according to claim 2, characterized in that, The second filtering module includes a first circuit unit and a second circuit unit connected in series, and the control unit is electrically connected between the first circuit unit and the second circuit unit.

7. The phase-locked loop circuit according to claim 6, characterized in that, After the phase-locked loop circuit is locked, control the second filtering module to be connected to the phase-locked loop circuit, and control the control unit to be in the first state to reduce the area of the filter or reduce the jitter of the phase-locked loop circuit; or control the control unit to be in the second state to reduce output jitter.

8. The phase-locked loop circuit according to claim 7, characterized in that, According to a preset period, periodically control the control unit to be in the first state or the second state.

9. The phase-locked loop circuit according to claim 1, characterized in that, The second filtering module includes a first circuit unit and a second circuit unit connected directly in series.

10. The phase-locked loop circuit according to claim 6 or 9, characterized in that, The first circuit unit includes a first capacitor unit and a first resistor unit connected in parallel, and the second circuit unit includes a second capacitor unit.

11. The phase-locked loop circuit according to claim 10, characterized in that, The first circuit unit further includes a second resistor unit, the second resistor unit is connected in series with the first capacitor unit and in parallel with the first resistor unit; and / or, the second circuit unit further includes a third resistor unit, the third resistor unit is connected in series with the second capacitor unit.

12. The phase-locked loop circuit according to claim 6, characterized in that, The control module controls the bypass of the second filtering module by controlling the bypass of the first circuit unit.

13. The phase-locked loop circuit according to claim 12, characterized in that, The control module includes a transmission gate and an inverter. The input terminal and the output terminal of the transmission gate are electrically connected to the first end and the second end of the first resistor unit respectively. The first control terminal of the transmission gate is directly electrically connected to the output terminal of the locking detection module, and the second control terminal of the transmission gate is electrically connected to the output terminal of the locking detection module through the inverter.

14. A control method for a phase-locked loop circuit according to any one of claims 1 to 13, characterized in that, The control module, according to the locking state signal output by the locking detection module, controls the bypass of the second filtering module before the phase-locked loop circuit is locked to achieve the effect of fast locking; After the phase-locked loop circuit is locked, control the second filtering module to be connected to the phase-locked loop circuit to reduce jitter or reduce the area of the filter.

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