Connecting circuit board for testing and preparation method thereof

Abstract

The invention discloses a connecting circuit board for testing and a preparation method thereof. The preparation method comprises the following steps: providing a printed circuit board; the printed circuit board is processed, the circuit board with the plating layer boss is prepared, and the height of the plating layer of the circuit board with the plating layer boss is larger than that of the ink layer on the circuit board with the plating layer boss. By controlling the height of the plating layer to be greater than the height of the ink layer, a plating layer boss structure is formed, so that the bonding pad of the multi-layer organic carrier plate can be in contact with the probe more conveniently, and therefore, scrappage caused by pricking due to the fact that the probe is in contact with the bonding pad for many times is reduced, and the durability is improved. The original processing flow is changed, appearance processing is carried out before nickel-palladium-gold processing, a printed circuit board is milled into small boards, and the area of the circuit board is reduced to reduce the reaction activity of a plating bath, so that a bonding pad is smoother.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit test boards, and in particular to a connecting circuit board for testing and a preparation method thereof. Background Art

[0002] Multi-layer organic substrates (MLOs) are commonly used in the field of integrated circuit (IC) testing. MLO boards usually have the characteristics of small pitch, small pads, and fine lines. The pad size is generally below 150 microns, and most of them are 100 microns. The upper surface of the MLO board is connected to the probe, and the lower surface is connected to the IC test board, playing the role of signal transmission and testing. It is a key component of the probe and the IC test board, which not only improves the accuracy and efficiency of testing, but also facilitates the debugging and troubleshooting of the circuit.

[0003] During the use of the MLO, it will come into contact with the probe multiple times, and abnormal problems such as poor probe contact often occur. Most of the reasons are caused by pad scratches. Since the surface of the pad is lower than the surface of the solder mask layer, it is inconvenient for the probe to contact it, and strong pressure is required to make full contact. To improve this defect, it is necessary to find a way to increase the height of the pad so that it is higher than the solder mask surface. During use, the probe can easily contact the pad, reducing the risk of probe scratching, improving durability, and reducing the scrapping of the MLO during use. The nickel thickness can be increased, but there will be a problem with the flatness of the pad. Summary of the Invention

[0004] An embodiment of the present invention provides a connecting circuit board for testing and a preparation method thereof to solve the problems of poor contact between the probe and the pad, easy scratching of the pad, poor durability, and poor flatness.

[0005] To achieve the above object, in one embodiment, a preparation method of a connecting circuit board for testing is provided, including: Providing a printed circuit board; Processing the printed circuit board to obtain a circuit board with plating bosses, and the height of the plating of the circuit board with plating bosses is greater than the height of the solder mask layer on the circuit board with plating bosses.

[0006] In one embodiment, processing the printed circuit board to obtain a circuit board with plating bosses includes: Performing solder mask treatment on the printed circuit board to form a solder mask layer, obtaining a printed circuit board with a solder mask layer; Performing pre-treatment for immersion gold on the printed circuit board with a solder mask layer to obtain a printed circuit board after pre-treatment for immersion gold; Performing nickel-palladium-gold treatment on the printed circuit board after pre-treatment for immersion gold to form a plating layer, obtaining a printed circuit board with plating bosses, and the printed circuit board with plating bosses is the connecting circuit board for testing.

[0007] In one embodiment, a solder mask treatment is performed on the printed circuit board by screen printing to control the thickness of the ink layer within a first set thickness range.

[0008] In one embodiment, after obtaining a printed circuit board with an ink layer, it further includes: detecting the thickness of the ink layer, and when the thickness of the ink layer exceeds the first set thickness range, performing a plasma roughening treatment on the ink layer to control the thickness of the ink layer within the first set thickness range.

[0009] In one embodiment, after obtaining a printed circuit board after electroless gold pretreatment, it further includes: performing shape processing on the printed circuit board after electroless gold pretreatment to obtain a milled small board, so as to reduce the area of the printed circuit board during the nickel-palladium-gold treatment.

[0010] In one embodiment, after controlling the thickness of the ink layer within a first set thickness range, when performing nickel-palladium-gold treatment on the circuit board after electroless gold pretreatment, controlling the time range of the nickel-palladium-gold treatment to be within 5000 - 5500 seconds enables the coating thickness to be within a second set thickness range.

[0011] In one embodiment, there is provided a connection circuit board for testing, which is characterized in that it includes: a substrate, a circuit layer is provided on the substrate, an ink layer is provided between the circuit layers, a coating boss is provided on the circuit layer, and the thickness of the coating boss is greater than the thickness of the ink layer.

[0012] In one embodiment, a first contact area for connecting a probe is provided on the coating boss provided on the upper surface of the circuit layer on the substrate.

[0013] In one embodiment, a second contact area for connecting an integrated circuit test board is provided on the coating boss provided on the lower surface of the circuit layer on the substrate.

[0014] In one embodiment, the first set thickness range is 0 - 15 microns, the second set thickness range is 10 - 20 microns, and the second set thickness range is greater than the first set thickness range.

[0015] The above-mentioned connection circuit board for testing and its manufacturing method control the height of the coating on the printed circuit board to be greater than the height of the ink layer through the manufacturing method, forming a coating boss structure, making it more convenient for the probe to contact the pads of the multi-layer organic carrier board. Therefore, it reduces the scrapping caused by the pinholes resulting from the probe contacting the pads multiple times, and improves the durability of the multi-layer organic carrier board (MLO). Description of the Drawings

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 is a flowchart of the preparation method in an embodiment of the present invention; Figure 2 is a schematic diagram of a printed circuit board in an embodiment of the present invention; Figure 3 is a schematic diagram of a circuit board with a plating boss in an embodiment of the present invention; Figure 4 is a schematic diagram of forming an ink layer by solder mask treatment in an embodiment of the present invention; Figure 5 is a schematic diagram before the small board milling process in an embodiment of the present invention; Figure 6 is a schematic diagram after the small board milling process in an embodiment of the present invention.

[0018] Reference numerals: 1 is a circuit printed board, 11 is a circuit layer, 12 is a dielectric material or a multi-layer core board, 2 is an ink layer, and 3 is a plating layer. Detailed implementation manners

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0020] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or portion discussed below may be denoted as the second element, component, region, layer or portion.

[0022] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0024] To fully understand the present invention, detailed structures and steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other embodiments.

[0025] In one embodiment, a method for preparing a connection circuit board for testing is provided, including: S101, providing a printed circuit board; Among them, the provided printed circuit board 1 is as Figure 2 shown. The printed circuit board 1 is composed of a circuit layer 11 and a dielectric material or a multi-layer core board 12. The circuit layer 11 is a copper layer, responsible for the transmission of current, having high thermal conductivity and good electrical conductivity, capable of effectively transmitting current and helping to dissipate heat, and maintaining the stable operating temperature of electronic components. The dielectric material or multi-layer core board 12 mainly plays a role of insulation and support.

[0026] S102, processing on the printed circuit board to obtain a circuit board with a plated bump, and the height of the plating layer of the circuit board with the plated bump is greater than the height of the solder mask layer on the circuit board with the plated bump.

[0027] Among them, as Figure 3 shown, the height of the plating layer 3 is greater than the height of the solder mask layer 2, so that a plated bump is formed on the circuit board, and a circuit board with a plated bump is obtained.

[0028] In the preparation method of this embodiment, by making the height of the plating layer on the circuit board greater than the height of the solder mask layer, a plated bump is formed. Compared with the original circuit board where the plating layer is lower than the solder mask layer, the circuit board with the plated bump is more convenient to contact with the probe. Therefore, it can reduce the damage to the pads caused by pressing the probe forcefully against the pads, thereby improving the durability of the circuit board and reducing the scrapping of the circuit board caused by pad damage.

[0029] In one embodiment, in the above step S102, that is, processing on the printed circuit board to obtain a circuit board with a plated bump, includes: S201, performing solder mask treatment on the printed circuit board to form a solder mask layer, and obtaining a printed circuit board with a solder mask layer; Among them, as Figure 4 shown, after the solder mask treatment, a solder mask layer 2 is formed. The solder mask layer 2 can block the flow of current on the circuit board, protecting the stability and reliability of the circuit, especially for high-density integrated circuit boards. In addition, the solder mask layer 2 has excellent antioxidant and anti-corrosion properties, can effectively prevent the circuit board from being affected by moisture, rust and corrosion, can well protect the circuit board, and extend the service life of the circuit board. The solder mask layer 2 has high insulation performance, can improve the insulation level of the circuit board, reduce the mutual interference and crosstalk between circuit boards. Especially in high-frequency, high-speed and high-precision circuits, the insulation performance of the solder mask layer 2 has an important impact on the operation stability and signal transmission quality of the circuit. In addition, the solder mask layer 2 can also provide a certain aesthetic effect while protecting the circuit board from mechanical damage.

[0030] S202. Perform pre-treatment for electroless gold plating on the printed circuit board with an ink layer to obtain a printed circuit board after pre-treatment for electroless gold plating. Among them, the pre-treatment for electroless gold plating can effectively remove dirt, oxides and other impurities on the surface of the circuit board, ensure the cleanliness and electrical performance of the circuit board, improve the heat dissipation performance of components, and can also form tiny concave and convex textures on the circuit board to increase its roughness, improve adhesion and increase friction, so as to facilitate the subsequent preparation steps. The specific operation of the pre-treatment for electroless gold plating is sandblasting, but when performing the pre-treatment for electroless gold plating here, the grinding brush should be turned off during the sandblasting process.

[0031] S203. Perform nickel-palladium-gold treatment on the printed circuit board after pre-treatment for electroless gold plating to form a plating boss, and obtain a printed circuit board with a plating boss. The printed circuit board with a plating boss is the connection circuit board for testing.

[0032] Among them, nickel-palladium-gold treatment refers to first plating a layer of nickel on the circuit layer (copper layer) 11 through a redox reaction, then plating a layer of palladium on the nickel through a redox reaction, and finally plating a layer of gold on the palladium through a displacement reaction. The palladium layer in nickel-palladium-gold treatment serves as a barrier layer to prevent the mutual migration between nickel and gold, avoid the occurrence of black nickel phenomenon, ensure the long-term reliability of the circuit, and its durability and stability are good, which can reduce maintenance and replacement costs and has high cost-effectiveness. Nickel-palladium-gold treatment does not use harmful chemical substances, meets environmental protection standards, and has less impact on the human body and the environment. When performing nickel-palladium-gold treatment, the circuit board is placed in a plating tank, and there is bath solution in the plating tank to form a plating layer. As Figure 3 shown, the height of the plating layer 3 should be greater than the height of the ink layer 2 to form a plating boss and obtain a circuit board with a plating boss.

[0033] In one embodiment, a solder mask treatment is performed on the printed circuit board by means of screen printing to control the thickness of the ink layer within a first set thickness range.

[0034] Among them, during the solder mask treatment, screen printing with a large mesh count is used. The mesh count of the screen refers to the number of holes in the screen per inch, and 1 inch = 2.54 cm. For example, 150 mesh means there are 150 mesh holes per inch. Screen printing, also known as silk screen printing, is a printing process. Its basic principle is to use some mesh holes of the screen to penetrate the paste and some mesh holes not to penetrate the paste for printing. Usually during printing, the paste is poured at one end of the screen, and a squeegee applies a certain pressure on the screen and moves towards the other end of the screen at the same time, so that the paste is extruded from the mesh holes of the graphic part onto the circuit board during the movement. Generally, a screen with a screen T number of 77T or more can effectively control the thickness of the ink layer 2 within a first set thickness range, where the screen T number refers to the number of mesh holes per square centimeter. For example, 77T = 196 mesh. As Figure 4As shown, when performing solder mask treatment, the thickness of the solder mask layer 2 needs to be controlled within a first set thickness range to facilitate subsequent steps.

[0035] In one embodiment, after obtaining a printed circuit board with a solder mask layer, it further includes: detecting the thickness of the solder mask layer, and when the thickness of the solder mask layer exceeds the first set thickness range, performing plasma roughening treatment on the solder mask layer to control the thickness of the solder mask layer within the first set thickness range.

[0036] Among them, as Figure 4 shown, after obtaining a printed circuit board with a solder mask layer 2, it is also necessary to detect the thickness of the solder mask layer 2 to see if it is within the first set thickness range. If it is within the first set thickness range, the next preparation step is carried out, which is to perform pre-treatment for immersion gold on the printed circuit board with the solder mask layer 2; if it is not within the first set thickness range, plasma roughening treatment is required to control the thickness of the solder mask layer 2 to be within the first set thickness range. The core principle of plasma roughening treatment is that high-energy particles in the plasma undergo physical and chemical reactions with the material surface, thereby changing the microscopic structure and chemical properties of the material surface. In this embodiment, the purpose of plasma roughening is to make the thickness of the solder mask layer 2 meet the first set thickness range.

[0037] In one embodiment, after obtaining a printed circuit board after pre-treatment for immersion gold, it further includes: performing shape processing on the printed circuit board after pre-treatment for immersion gold to obtain a milled small board, so as to reduce the area of the printed circuit board during the nickel-palladium-gold treatment.

[0038] Among them, when milling the small board, the shape and size of the circuit board will be changed. As Figure 5 shown, the original processing size of the circuit board is 406 * 458 millimeters (mm). As Figure 6 shown, the size after milling the small board is 110 * 127 millimeters (mm). When milling the small board, start the machine tool and perform milling processing according to a preset program, including rough machining and finish machining, to ensure dimensional accuracy and surface finish. The main function of milling the small board is to reduce the plating area, thereby reducing the reaction activity of the bath solution in the plating tank, and enabling the pads to be flatter during the nickel-palladium-gold treatment.

[0039] In one embodiment, after controlling the thickness of the solder mask layer within the first set thickness range, when performing nickel-palladium-gold treatment on the circuit board after pre-treatment for immersion gold, controlling the time range of the nickel-palladium-gold treatment to be 5000 - 5500 seconds makes the thickness of the plating layer within a second set thickness range.

[0040] Among them, when performing nickel-palladium-gold treatment, the circuit board after milling small boards is placed in a plating tank, and the nickel thickness is controlled by increasing the soaking time of the small boards in the nickel tank. When the nickel plating time is controlled within 5000 - 5500 seconds, the thickness of the plating layer 3 reaches the second set thickness range. Since the second set thickness is greater than the first set thickness, as Figure 3 shown, at this time, the thickness of the plating layer 3 is higher than the thickness of the solder mask layer 2, forming a plating protrusion. The nickel plating time within 5000 - 5500 seconds here is only for the circuit board in this embodiment.

[0041] Optionally, since different PCB circuit boards require different nickel plating times, for small circuit boards with a thickness of less than 100 microns, nickel-palladium-gold processing is optimal. For other types of circuit boards, plating protrusions can also be formed through processing methods such as electroless nickel immersion gold treatment, pattern electroplating nickel treatment, and electroplating gold nickel treatment.

[0042] Among them, in the electroless nickel immersion gold treatment, palladium is displaced on the surface of copper through a chemical reaction, and then a nickel-phosphorus alloy layer is electrolessly plated on the basis of the palladium core, and then a layer of gold is plated on the surface of nickel through a displacement reaction; the pattern electroplating nickel treatment is a process of plating a layer of metallic nickel on a specific pattern area (such as copper traces on a circuit board) using the principle of electrochemistry. This treatment can enhance the hardness, wear resistance, corrosion resistance, and electrical conductivity of the object surface, thereby improving the overall performance and service life of the object; the electroplating gold nickel treatment is to cover a layer of nickel on the surface of a metal or some non-metals by using electrolysis or chemical reactions. In some cases, in order to further enhance the performance or aesthetics of the plating layer, a layer of gold may also be plated on top of the nickel layer. Appropriate treatment methods can be selected according to different circuit boards to form plating protrusions, all of which are within the protection scope of the present invention.

[0043] In one embodiment, a connection circuit board for testing is provided, including: a substrate, a circuit layer is provided on the substrate, a solder mask layer is provided between the circuit layers, and a plating protrusion is provided on the circuit layer, and the thickness of the plating protrusion is greater than the thickness of the solder mask layer.

[0044] Among them, as Figure 3 shown, the substrate is the printed circuit board 1, a circuit layer 11 is provided on the substrate 1, the circuit layer 11 is a copper layer, the substrate 1 further includes a dielectric material or a multi-layer core board 12, a solder mask layer 2 is provided between the circuit layers 11, and a plating layer 3 is provided on the circuit layer 11, and the height of the plating layer 3 is greater than the height of the solder mask layer 2, forming a plating protrusion.

[0045] For the connection circuit board used in the test of this embodiment, by setting the height of the plating layer on the circuit layer to be greater than the height of the solder mask layer on the circuit board, a plating boss is formed. Compared with the original circuit board where the plating layer is lower than the solder mask layer, the circuit board with the plating boss is more convenient to contact with the probe. Therefore, it can reduce the damage to the pads caused by pressing hard on the contact pads, thereby improving the durability of the circuit board and reducing the scrapping caused by pad damage.

[0046] In one embodiment, a first contact area for connecting the probe is provided on the plating boss provided on the upper surface of the circuit layer on the substrate.

[0047] Among them, the first contact area is used to contact the probe. The plating boss makes the height of the pad greater than the height of the solder mask layer, which can greatly reduce the phenomenon of poor contact due to the original pad surface being lower than the solder mask layer surface, enabling the probe to easily contact the pad. During use, the risk of the pad being damaged by the probe is reduced, thereby improving durability and reducing the scrapping of the test board.

[0048] In one embodiment, a second contact area for connecting the integrated circuit test board is provided on the plating boss provided on the lower surface of the circuit layer on the substrate.

[0049] Among them, the second contact area is used to connect with the integrated circuit test board (IC test board). The IC test board is mainly used to ensure the quality and performance of the integrated circuit (IC). During the product production process, if there is a problem with the main board, the IC test board can help detect whether it is a problem with the main board itself or the IC, and can also be used to screen out defective ICs, saving time and labor costs. The IC test board also supports the convenient replacement of chips, reducing the test time and workload and improving efficiency.

[0050] In one embodiment, the first set thickness range is 0 - 15 microns, the second set thickness range is 10 - 20 microns, and the second set thickness range is greater than the first set thickness range.

[0051] Among them, the first set thickness range is the thickness of the solder mask layer, and the second set thickness range is the thickness of the plating layer. The solder mask layer is obtained through solder mask treatment. If the thickness of the solder mask layer after solder mask treatment does not reach within the range of 0 - 15 microns, plasma roughening treatment is performed to make the thickness of the solder mask layer within 0 - 15 microns. The plating layer is obtained through nickel-palladium-gold treatment. During nickel-palladium-gold treatment, the circuit board is placed in the plating tank, and the height of the plating layer is controlled by controlling the reaction time between the bath solution and the circuit board, so that the height of the plating layer is within 10 - 20 microns, 5 - 10 microns higher than the thickness of the solder mask layer, forming a plating boss.

[0052] In this embodiment, by setting the height of the plating layer on the printed circuit board to be greater than the height of the ink layer, a plating boss structure is formed, making the pads of the multi-layer organic carrier board more convenient to contact with the probes. Therefore, the scrap caused by the puncture damage due to the probes contacting the pads multiple times is reduced, and the durability of the multi-layer organic carrier board (MLO) is improved.

[0053] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for preparing a connection circuit board for testing, characterized in that: include: Providing a printed circuit board; The printed circuit board is processed to prepare a circuit board with plated bosses, wherein the height of the plated layer of the circuit board with plated bosses is greater than the height of the ink layer on the circuit board with plated bosses.

2. The preparation method according to claim 1, characterized in that: Processing on the printed circuit board to prepare a circuit board with a plated boss comprises: Performing solder resist treatment on the printed circuit board to form an ink layer, thereby obtaining a printed circuit board having an ink layer; Performing a gold pretreatment on the printed circuit board having the ink layer to obtain a printed circuit board after the gold pretreatment; The printed circuit board after the gold pretreatment is subjected to nickel-palladium-gold treatment to form a plating layer, thereby obtaining a printed circuit board with a plating boss, and the printed circuit board with the plating boss is the connecting circuit board for the test.

3. The preparation method according to claim 2, characterized in that: The solder resist process is performed on the printed circuit board by screen printing to control the thickness of the ink layer to be within a first set thickness range.

4. The preparation method according to claim 3, characterized in that: After obtaining a printed circuit board with an ink layer, the method further includes: detecting the thickness of the ink layer, and when the thickness of the ink layer exceeds the first set thickness range, performing plasma roughening treatment on the ink layer to control the thickness of the ink layer to be within the first set thickness range.

5. The preparation method according to claim 2, characterized in that: After obtaining the printed circuit board after the gold pretreatment, the method further includes: performing shape processing on the printed circuit board after the gold pretreatment to obtain a milled board to reduce the area of ​​the printed circuit board during the nickel-palladium-gold treatment.

6. The preparation method according to claim 3, characterized in that: After controlling the thickness of the ink layer within the first set thickness range, when the circuit board after the gold pre-treatment is subjected to nickel-palladium-gold treatment, the time range of the nickel-palladium-gold treatment is controlled to be 5000-5500 seconds, so that the thickness of the coating is within the second set thickness range.

7. A connection circuit board for testing, characterized in that: include: A substrate is provided with a circuit layer on the substrate, an ink layer is provided between the circuit layers, a plating boss is provided on the circuit layer, and the thickness of the plating boss is greater than the thickness of the ink layer.

8. The circuit board according to claim 7, characterized in that: A first contact area for connecting a probe is arranged on a plating boss arranged on the upper surface of the circuit layer on the substrate.

9. The circuit board according to claim 7, characterized in that: A second contact area for connecting to an integrated circuit test board is arranged on a plating boss arranged on the lower surface of the circuit layer on the substrate.

10. The preparation method according to claim 6, characterized in that: The first set thickness range is 0-15 microns, the second set thickness range is 10-20 microns, and the second set thickness range is greater than the first set thickness range.

Images