PCB impedance compensation design method, device and equipment and storage medium

Abstract

The embodiment of the invention discloses a PCB impedance compensation design method and device, equipment and a storage medium. The method comprises the steps that the impedance line width and the line spacing of each line layer in a PCB are acquired; determining the maximum film compensation amount and the minimum film spacing of the compensation design under the circuit layer thickness corresponding to each circuit layer in the PCB; performing first compensation on the film compensation value of each circuit layer in the PCB according to the maximum film compensation amount; and performing second compensation on the film compensation value of the line layer of which the actual distance of the impedance line does not meet the compensation condition in each line layer of the PCB. According to the invention, the effect of improving the impedance design yield is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board design and manufacturing, and particularly relates to a PCB impedance compensation design method, device, equipment and storage medium. Background Art

[0002] In the impedance formation process of a PCB, a protective film is covered on a copper clad laminate (CCL). The pattern of a negative film (film) is transferred to the surface of the CCL through exposure. The unexposed pattern is removed through development, and the copper surface of the unexposed part of the pattern is removed through etching. At this time, a circuit loop with a single-layer conduction design is formed on the surface of the CCL. Finally, the protective film of the exposed part is removed by stripping to obtain an etched core board.

[0003] The existing compensation scheme is to adjust the line width, line spacing, copper thickness, etc. during pattern design, or to adjust relevant process parameters during etching. Due to the existence of side etching / over etching in the etching process, when it is necessary to obtain a graphic circuit with a small difference between the upper and lower bottom surfaces, it is necessary to protect the size of the pattern slightly larger than the target pattern, that is, etching compensation.

[0004] Figure 1 It is a schematic diagram of the etching compensation of a PCB board. Theoretically, graphic compensation can make the line width / spacing design of the target line reach different positions on the board surface under the same etching end point design. In fact, affected by aspects such as the resolution ability of the protective film, the resolution ability of the exposure machine, the etching line potion and the etching time, the compensation cannot be increased without limit, and the film spacing cannot be made infinitely small. Therefore, for impedance lines with a small film spacing and line width, the prior art cannot achieve the corresponding impedance adjustment. Summary of the Invention

[0005] The present invention provides a PCB impedance compensation design method, device, equipment and storage medium to solve the problem that impedance lines with small film spacing and line width cannot be adjusted during the design process of a PCB board.

[0006] According to one aspect of the present invention, a PCB impedance compensation design method is provided, including:

[0007] Obtaining the impedance line width and line spacing of each circuit layer in a PCB board;

[0008] Confirming the maximum compensation amount of the film and the minimum film spacing for compensation design under the corresponding circuit layer thickness of each circuit layer in the PCB board;

[0009] Performing a first additional compensation on the film compensation value of each circuit layer in the PCB board according to the maximum compensation amount of the film;

[0010] Perform a second addition to the film compensation value of the circuit layer in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions.

[0011] Optionally, performing a second addition to the film compensation value of the circuit layer in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions includes:

[0012] After the first addition is performed on the film compensation values of each circuit layer of the PCB, perform a second addition to the film compensation value of the circuit layer where the difference between the actual spacing of the impedance lines and the maximum film compensation amount is less than or equal to the minimum film spacing.

[0013] Optionally, the addition amount for performing a second addition to the film compensation value of the circuit layer in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions satisfies the following relationship:

[0014] L = (b - (Sn - a)) * c

[0015] Where L is the addition amount for performing a second addition to the film compensation value of the circuit layer in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions, b - (Sn - a) > 0, b is the minimum film spacing, Sn is the signal line spacing, a is the maximum film compensation amount, and c is the addition amount coefficient.

[0016] Optionally, the value range of the addition amount coefficient is 0.5 to 1.0.

[0017] Optionally, after performing a second addition to the film compensation value of the circuit layer in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions, the film compensation value of the circuit layer in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions satisfies the following relationship:

[0018] M = (b - (Sn - a)) * c + a / 2 + (Sn - b) / 2

[0019] Where M is the film compensation value of the circuit layer in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions.

[0020] Optionally, after performing a second addition to the film compensation value of the circuit layer in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions, it further includes:

[0021] Copy the impedance line layer of the circuit layer after the second addition to the original layer;

[0022] Check the open - short circuit electrical property of the circuit layer after the second addition.

[0023] Optionally, after checking the open - short circuit electrical property of the circuit layer after the second addition, it further includes:

[0024] Each circuit layer of the graphical PCB board.

[0025] According to another aspect of the present invention, there is provided a PCB impedance compensation design device, including:

[0026] A parameter acquisition module for acquiring the impedance line width and line spacing of each circuit layer in the PCB board;

[0027] A parameter confirmation module for confirming the maximum compensation amount of the film and the minimum film spacing for compensation design corresponding to the thickness of each circuit layer in the PCB board;

[0028] A first compensation adding module for performing a first compensation addition to the film compensation value of each circuit layer in the PCB board according to the maximum compensation amount of the film;

[0029] A second compensation adding module for performing a second compensation addition to the film compensation value of the circuit layer in each circuit layer of the PCB board where the actual line spacing of the impedance line does not meet the compensation condition.

[0030] According to another aspect of the present invention, there is also provided an electronic device, including:

[0031] At least one processor; and

[0032] A memory communicatively connected to the at least one processor; wherein,

[0033] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the PCB impedance compensation design method described in any embodiment of the present invention.

[0034] According to another aspect of the present invention, there is also provided a computer-readable storage medium storing computer instructions for causing a processor to execute the PCB impedance compensation design method described in any embodiment of the present invention when executed.

[0035] In the technical solution of the embodiment of the present invention, by obtaining the impedance line width and line spacing of each circuit layer in the PCB board, the maximum compensation amount of the film for compensation design and the minimum film spacing corresponding to the thickness of each circuit layer in the PCB board are confirmed. The film compensation value of each circuit layer in the PCB board is first supplemented according to the maximum compensation amount of the film, so that the impedance of each circuit layer remains consistent within a certain range. The film compensation value of the circuit layer in which the actual line spacing of the impedance line in each circuit layer of the PCB board does not meet the compensation condition is secondarily supplemented. For impedance lines with a small film spacing and line width, additional compensation is used to ensure that these lines reach the required impedance value, thereby improving the overall performance of the PCB board. Through the first supplementation and the second supplementation, the film compensation value can be adjusted more precisely, so that the rework and scrap rates caused by impedance mismatch of each circuit layer are reduced, the production efficiency and product quality of the PCB board are improved, and the yield of impedance design is improved accordingly.

[0036] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 It is a schematic diagram of the etching compensation of the PCB board;

[0039] Figure 2 It is a flowchart of a PCB impedance compensation design method provided by an embodiment of the present invention;

[0040] Figure 3 It is a schematic diagram of the maximum film compensation amount and the minimum film spacing of the PCB board;

[0041] Figure 4 It is a flowchart of another PCB impedance compensation design method provided by an embodiment of the present invention;

[0042] Figure 5 It is a schematic diagram of each manufacturing parameter of the PCB board;

[0043] Figure 6 It is a flowchart of another PCB impedance compensation design method provided by an embodiment of the present invention;

[0044] Figure 7It is a schematic diagram of the modules of a PCB impedance compensation design device provided by an embodiment of the present invention;

[0045] Figure 8 It is a schematic diagram of the structure of an electronic device for a PCB impedance compensation design method provided by an embodiment of the present invention. Detailed implementation manners

[0046] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0048] Embodiment 1

[0049] Figure 2 It is a flowchart of a PCB impedance compensation design method provided by an embodiment of the present invention. This embodiment is applicable to the situation of impedance compensation in the PCB board design process. As Figure 2 shown, the method includes:

[0050] S110. Obtain the impedance line widths and line spacings of each circuit layer in the PCB board.

[0051] Among them, the impedance line width refers to the width of the impedance line in each circuit layer. The line spacing refers to the distance between adjacent impedance lines.

[0052] Specifically, use a distance measurement tool or software to scan or measure the PCB board to obtain the width of the impedance line in each circuit layer and the distance between adjacent impedance lines.

[0053] S120. Confirm the maximum compensation amount of the film and the minimum film spacing for the compensation design corresponding to each circuit layer thickness in the PCB board.

[0054] Among them, Figure 3 is a schematic diagram of the maximum compensation amount of the PCB film and the minimum film spacing. As Figure 3 shown, the maximum compensation amount of the film refers to the amount of adjusting the line width or line spacing to change the impedance. The minimum film spacing refers to the minimum safe distance between adjacent lines to avoid short circuits or open circuits during the PCB manufacturing process.

[0055] Specifically, according to the manufacturing requirements and impedance characteristics of the PCB, determine the amount of adjusting the line width or line spacing to change the impedance required for each circuit layer at different thicknesses and the minimum safe distance allowed between adjacent lines.

[0056] S130. Perform the first addition and compensation on the film compensation values of each circuit layer in the PCB according to the maximum compensation amount of the film.

[0057] Among them, the first addition and compensation is a preliminary adjustment process aimed at adjusting the impedance value to within a range close to the target value.

[0058] Specifically, perform a preliminary adjustment on the film compensation values of each circuit layer in the PCB by modifying the line width or line spacing to approach the target impedance value. Exemplarily, for a line where Sn - a > b, perform the first addition and compensation on the film compensation values of each circuit layer in the PCB; where Sn is the signal line spacing, a is the maximum compensation amount of the film, and b is the minimum film spacing.

[0059] S140. Perform the second addition and compensation on the film compensation values of the circuit layers in each circuit layer of the PCB where the actual spacing of the impedance lines does not meet the compensation conditions.

[0060] Among them, the compensation condition means that the difference between the actual spacing of the impedance lines and the maximum compensation amount of the film is greater than the minimum film spacing. The second addition and compensation is for the circuit layers that still do not meet the compensation conditions after the preliminary adjustment.

[0061] Specifically, check the PCB after the preliminary adjustment to determine whether there are circuit layers where the actual spacing of the impedance lines does not meet the condition that the difference between the actual spacing of the impedance lines and the maximum compensation amount of the film is greater than the minimum film spacing. If there are circuit layers where the actual spacing of the impedance lines does not meet the compensation conditions, then perform further adjustment on the film compensation values of these circuit layers.

[0062] In the technical solution of the embodiment of the present invention, by obtaining the impedance line widths and line spacings of each circuit layer in the PCB board, the maximum compensation amount of the film and the minimum film spacing for compensation design corresponding to the thickness of each circuit layer in the PCB board are confirmed. The first addition is performed on the film compensation values of each circuit layer in the PCB board according to the maximum compensation amount of the film, so that the impedance of each circuit layer remains consistent within a certain range. The second addition is performed on the film compensation values of the circuit layers in which the actual line spacing of the impedance lines in each circuit layer of the PCB board does not meet the compensation conditions. For impedance lines with a small film spacing and line width, additional compensation is used to ensure that these lines reach the required impedance value, thereby improving the overall performance of the PCB board. Through the first addition and the second addition, the film compensation value can be adjusted more precisely, so that the rework and scrap rates caused by impedance mismatch of each circuit layer are reduced, the production efficiency and product quality of the PCB board are improved, and the effect of improving the yield of impedance design is achieved.

[0063] Embodiment 2

[0064] Figure 4 is a flowchart of another PCB impedance compensation design method provided by the embodiment of the present invention. This embodiment is also applicable to the case of impedance compensation in the PCB board design process. As Figure 4 shown, the method includes:

[0065] S210. Obtain the impedance line widths and line spacings of each circuit layer in the PCB board.

[0066] S220. Confirm the maximum compensation amount of the film and the minimum film spacing for compensation design corresponding to the thickness of each circuit layer in the PCB board.

[0067] S230. Perform the first addition on the film compensation values of each circuit layer in the PCB board according to the maximum compensation amount of the film.

[0068] S240. After the first addition is performed on the film compensation values of each circuit layer in the PCB board, perform the second addition on the film compensation values of the circuit layers in which the difference between the actual line spacing of the impedance lines and the maximum compensation amount of the film is less than or equal to the minimum film spacing.

[0069] Specifically, check the PCB board after preliminary adjustment, and check the difference between the actual line spacing of the impedance lines of each circuit layer and the maximum compensation amount of the film. If the difference is less than or equal to the minimum film spacing, perform the second addition on the film compensation value of this circuit layer. The second addition is to compensate for those circuit layers that still cannot meet the impedance requirements after the first addition. By further adjusting the film compensation value, it can be ensured that the impedance characteristics of these circuit layers are closer to the target value.

[0070] In the technical solution of the embodiment of the present invention, by obtaining the impedance line widths and line spacings of each circuit layer in the PCB board, the maximum compensation amount of the film and the minimum film spacing for compensation design corresponding to the thickness of each circuit layer in the PCB board are confirmed. The film compensation values of each circuit layer in the PCB board are first supplemented according to the maximum compensation amount of the film, so that the impedances of each circuit layer are kept consistent within a certain range. After the film compensation values of each circuit layer in the PCB board are first supplemented, the film compensation values of the circuit layers where the difference between the actual line spacing of the impedance line and the maximum compensation amount of the film is less than or equal to the minimum film spacing are secondarily supplemented. For impedance lines with relatively small film spacings and line widths, additional compensation is used to ensure that these lines reach the required impedance values, thereby improving the overall performance of the PCB board. Through the first supplementation and the second supplementation, the film compensation values can be adjusted more precisely, reducing the rework and scrap rates of each circuit layer caused by impedance mismatch, improving the production efficiency and product quality of the PCB board, and thus achieving the effect of improving the yield of impedance design.

[0071] Figure 5 are schematic diagrams of various manufacturing parameters of the PCB board. As Figure 5 shown, on the basis of the above embodiments, the supplementation amount for secondarily supplementing the film compensation values of the circuit layers in each circuit layer of the PCB board where the actual line spacing of the impedance line does not meet the compensation conditions satisfies the following relationship:

[0072] L = (b - (Sn - a)) * c

[0073] Wherein, L is the supplementation amount for secondarily supplementing the film compensation values of the circuit layers in each circuit layer of the PCB board where the actual line spacing of the impedance line does not meet the compensation conditions, b - (Sn - a) > 0, b is the minimum film spacing, Sn is the signal line spacing, a is the maximum compensation amount of the film, and c is the supplementation amount coefficient.

[0074] Specifically, the part of (b - (Sn - a)) in the formula first calculates a difference. This difference reflects the difference between the minimum film spacing b and the difference between the signal line spacing Sn minus the maximum compensation amount of the film a. This difference can be understood as how much additional compensation is required to meet the requirements of the minimum film spacing under the given number of circuit layers and the maximum compensation amount. Then, this difference is multiplied by the supplementation amount coefficient c to obtain the final supplementation amount L. The introduction of the supplementation amount coefficient c enables the supplementation amount to be adjusted according to the actual situation to meet different design requirements and manufacturing conditions. By introducing a specific calculation formula, this method can more accurately determine the supplementation amount of the second supplementation, thereby more precisely adjusting the film compensation values, reducing the rework and scrap rates of each circuit layer caused by impedance mismatch, improving the production efficiency and product quality, and thus achieving the effect of improving the yield of impedance design.

[0075] Optionally, the value range of the additional compensation coefficient is 0.5 to 1.0.

[0076] Specifically, the introduction of the additional compensation coefficient c makes the method have a certain flexibility and can be adjusted according to different design requirements and manufacturing conditions. Exemplarily, in this embodiment, the value of the additional compensation coefficient c is 0.7.

[0077] Optionally, after performing a second additional compensation on the film compensation value of the line layers in each line layer of the PCB board where the actual spacing of the impedance lines does not meet the compensation conditions, the film compensation value of the line layers in each line layer of the PCB board where the actual spacing of the impedance lines does not meet the compensation conditions satisfies the following relationship:

[0078] M = (b - (Sn - a)) * c + a / 2 + (Sn - b) / 2

[0079] Where, M is the film compensation value of the line layers in each line layer of the PCB board where the actual spacing of the impedance lines does not meet the compensation conditions.

[0080] Specifically, the PCB impedance compensation design method of the present invention adjusts the film compensation value of the line layers that do not meet the compensation conditions through specific formula calculations. This method can ensure that the spacing of the impedance lines in each line layer of the PCB board meets the design requirements, thereby improving the yield rate of the PCB board.

[0081] Embodiment III

[0082] Figure 6 is a flowchart of another PCB impedance compensation design method provided by the embodiments of the present invention. This embodiment is also applicable to the impedance compensation situation in the PCB board design process. As Figure 6 shown, the method includes:

[0083] S310. Obtain the impedance line widths and line spacings of each line layer in the PCB board.

[0084] S320. Confirm the maximum film compensation amount and the minimum film spacing for the compensation design corresponding to the thickness of each line layer in the PCB board.

[0085] S330. Perform a first additional compensation on the film compensation value of each line layer in the PCB board according to the maximum film compensation amount.

[0086] S340. Perform a second additional compensation on the film compensation value of the line layers in each line layer of the PCB board where the actual spacing of the impedance lines does not meet the compensation conditions.

[0087] S350. Copy the impedance line layer of the line layer after the second additional compensation to the original layer.

[0088] S360. Check the open - short circuit electrical properties of the line layer after the second additional compensation.

[0089] S370, each circuit layer of the graphical PCB board.

[0090] Specifically, use a distance measurement tool or software to scan or measure the PCB board to obtain the width of the impedance lines in each circuit layer and the distance between adjacent impedance lines. According to the manufacturing requirements and impedance characteristics of the PCB board, determine the amount of line width or line spacing adjustment required for each circuit layer at different thicknesses to change the impedance and the minimum safe distance allowed between adjacent lines. Initially adjust the film compensation value of each circuit layer in the PCB board by modifying the line width or line spacing to approach the target impedance value. Inspect the PCB board after the initial adjustment to determine if there are any circuit layers where the actual spacing of the impedance lines does not meet the condition that the difference between the actual spacing of the impedance lines and the maximum film compensation amount is greater than the minimum film spacing. If there are circuit layers where the actual spacing of the impedance lines does not meet the compensation condition, perform a second additional compensation on the film compensation value of these circuit layers. After completing all necessary compensation adjustments, copy the impedance line layer of the circuit layers after the second additional compensation back to the original layer, and perform an open / short test on the circuit layers after the compensation adjustment. If the open / short electrical property does not change, perform graphicalization on each circuit layer of the PCB board, and then perform PCB manufacturing processes such as exposure, development, and etching.

[0091] The technical solution of the embodiment of the present invention, by obtaining the impedance line width and line spacing of each circuit layer in the PCB board, confirming the maximum film compensation amount and the minimum film spacing for compensation design corresponding to each circuit layer thickness in the PCB board, performing a first additional compensation on the film compensation value of each circuit layer in the PCB board according to the maximum film compensation amount, enables the impedance of each circuit layer to be consistent within a certain range. Perform a second additional compensation on the film compensation value of the circuit layers in each circuit layer of the PCB board where the actual spacing of the impedance lines does not meet the compensation condition. For impedance lines with a small film spacing and line width, ensure that these lines reach the required impedance value through additional compensation, thereby improving the overall performance of the PCB board. After completing all necessary compensation adjustments, copy the impedance line layer of the circuit layers after the second additional compensation back to the original layer, and perform an open / short test on the circuit layers after the compensation adjustment to ensure that no open or short problems are introduced during the compensation adjustment process, which can reduce manufacturing errors, improve the yield and reliability of the PCB board. If the open / short electrical property does not change, perform graphicalization on each circuit layer of the PCB board, and then perform PCB manufacturing processes such as exposure, development, and etching, making the production more efficient and orderly. Through the first additional compensation and the second additional compensation, the film compensation value can be adjusted more precisely, reducing the rework and scrap rate caused by impedance mismatch in each circuit layer, improving the production efficiency and product quality of the PCB board, and thus achieving the effect of improving the yield of impedance design.

[0092] Embodiment 4

[0093] Figure 7 It is a schematic diagram of the modules of a PCB impedance compensation design device provided by an embodiment of the present invention; as Figure 7 shown, the PCB impedance compensation design device includes:

[0094] A parameter acquisition module 610, configured to acquire the impedance line width and line spacing of each circuit layer in the PCB board;

[0095] A parameter confirmation module 620, configured to confirm the maximum film compensation amount and the minimum film spacing for compensation design corresponding to the thickness of each circuit layer in the PCB board;

[0096] A first compensation addition module 630, configured to perform a first compensation addition on the film compensation value of each circuit layer in the PCB board according to the maximum film compensation amount;

[0097] A second compensation addition module 640, configured to perform a second compensation addition on the film compensation value of the circuit layers in each circuit layer of the PCB board where the actual line spacing of the impedance lines does not meet the compensation conditions.

[0098] The technical solution of this embodiment obtains the impedance line width and line spacing of each circuit layer in the PCB board through the parameter acquisition module; confirms the maximum film compensation amount and the minimum film spacing for compensation design corresponding to the thickness of each circuit layer in the PCB board through the parameter confirmation module; performs a first compensation addition on the film compensation value of each circuit layer in the PCB board according to the maximum film compensation amount through the first compensation addition module; and performs a second compensation addition on the film compensation value of the circuit layers in each circuit layer of the PCB board where the actual line spacing of the impedance lines does not meet the compensation conditions through the second compensation addition module. For impedance lines with a small film spacing and line width, additional compensation is used to ensure that these lines reach the required impedance value, thereby improving the overall performance of the PCB board. Through the first compensation addition and the second compensation addition, the film compensation value can be adjusted more precisely, reducing the rework and scrap rates caused by impedance mismatch in each circuit layer, improving the production efficiency and product quality of the PCB board, and thus achieving the effect of improving the yield of impedance design.

[0099] Optionally, the second compensation addition module 640 includes:

[0100] A second compensation addition unit, configured to perform a second compensation addition on the film compensation value of the circuit layers where the difference between the actual line spacing of the impedance lines and the maximum film compensation amount is less than or equal to the minimum film spacing after the first compensation addition is performed on the film compensation value of each circuit layer in the PCB board.

[0101] A PCB impedance compensation design device provided by an embodiment of the present invention can execute a PCB impedance compensation design method provided by any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method.

[0102] Embodiment Five

[0103] Figure 8 This is a schematic structural diagram of an electronic device for the PCB impedance compensation design method provided by an embodiment of the present invention. Refer to Figure 8 , the electronic device for the PCB impedance compensation design method includes: The electronic device 70 includes at least one processor 71 and a memory communicatively connected to the at least one processor 71, such as a read-only memory (ROM) 72, a random access memory (RAM) 73, etc. Among them, the memory stores a computer program executable by the at least one processor. The processor 71 can execute various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 72 or the computer program loaded from the storage unit 78 into the random access memory (RAM) 73. In the RAM 73, various programs and data required for the operation of the electronic device 70 can also be stored. The processor 71, the ROM 72, and the RAM 73 are connected to each other through a bus 74. The input / output (I / O) interface 75 is also connected to the bus 74.

[0104] Multiple components in the electronic device 70 are connected to the I / O interface 75, including: an input unit 76, such as a keyboard, a mouse, etc.; an output unit 77, such as various types of displays, speakers, etc.; a storage unit 78, such as a disk, an optical disc, etc.; and a communication unit 79, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 79 allows the electronic device 70 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0105] The processor 71 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 71 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 71 executes the various methods and processes described above, such as the PCB impedance compensation design method.

[0106] In some embodiments, the PCB impedance compensation design method can be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 78. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 70 via the ROM 72 and / or the communication unit 79. When the computer program is loaded into the RAM 73 and executed by the processor 71, one or more steps of the PCB impedance compensation design method described above can be performed. Alternatively, in other embodiments, the processor 71 can be configured to execute the PCB impedance compensation design method by any other suitable means (e.g., by means of firmware).

[0107] The various implementations of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0108] The computer programs for implementing the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer programs are executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer programs can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0109] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0110] To provide for interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0111] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0112] A computing system may include a client and a server. The client and the server are generally far from each other and usually interact via a communication network. The relationship between the client and the server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, and solves the defects of large management difficulty and weak business scalability existing in traditional physical hosts and VPS services.

[0113] The computer device provided above can be used to execute the PCB impedance compensation design method provided in any of the above embodiments, and has corresponding functions and beneficial effects.

[0114] It should be understood that various forms of processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0115] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A PCB impedance compensation design method, characterized in that: include: Get the impedance line width and line spacing of each line layer in the PCB board; Confirm the maximum film compensation amount and the minimum film spacing of the compensation design under the corresponding circuit layer thickness of each circuit layer in the PCB board; Performing a first additional compensation on the film compensation value of each circuit layer in the PCB board according to the maximum film compensation amount; A second supplement is performed on the film compensation value of the circuit layer whose actual impedance line spacing in each circuit layer of the PCB board does not meet the compensation condition.

2. The PCB impedance compensation design method according to claim 1, characterized in that: Performing a second supplement to the film compensation value of the circuit layer whose actual impedance line spacing in each circuit layer of the PCB does not meet the compensation condition comprises: After the film compensation value of each circuit layer in the PCB board is supplemented for the first time, the film compensation value of the circuit layer whose difference between the actual spacing of the impedance line and the maximum film compensation amount is less than or equal to the minimum film spacing is supplemented for the second time.

3. The PCB impedance compensation design method according to claim 1, characterized in that: The second compensation amount for the film compensation value of the circuit layer whose actual impedance line spacing in each circuit layer of the PCB does not meet the compensation condition satisfies the following relationship: L=(b-(Sn-a))*c Among them, L is the second compensation amount for the film compensation value of the circuit layer whose actual impedance line spacing in each circuit layer of the PCB board does not meet the compensation conditions, b-(Sn-a)>0, b is the minimum film spacing, Sn is the signal line spacing, a is the maximum film compensation amount, and c is the compensation coefficient.

4. The PCB impedance compensation design method according to claim 3, characterized in that: The value range of the additional compensation coefficient is 0.5 to 1.

0.

5. The PCB impedance compensation design method according to claim 3, characterized in that: After the second supplement is performed on the film compensation value of the circuit layer whose actual spacing of impedance lines in each circuit layer of the PCB board does not meet the compensation conditions, the film compensation value of the circuit layer whose actual spacing of impedance lines in each circuit layer of the PCB board does not meet the compensation conditions satisfies the following relationship: M=(b-(Sn-a))*c+a / 2+(Sn-b) / 2 Wherein, M is the film compensation value for the circuit layer whose actual spacing of impedance lines in each circuit layer of the PCB board does not meet the compensation condition.

6. The PCB impedance compensation design method according to claim 1, characterized in that: After performing a second supplement to the film compensation value of the circuit layer whose actual impedance line spacing in each circuit layer of the PCB does not meet the compensation condition, the method further includes: Copy the impedance line layer of the circuit layer after the second patching to the original layer; Check the open and short circuit electrical properties of the circuit layer after the second patching.

7. The PCB impedance compensation design method according to claim 6, characterized in that: After checking the open and short circuit electrical properties of the circuit layer after the second supplementation, the following steps are also included: Each circuit layer of the PCB board is patterned.

8. A PCB impedance compensation design device, characterized in that: include: The parameter acquisition module is used to obtain the impedance line width and line spacing of each line layer in the PCB board; A parameter confirmation module, used to confirm the maximum film compensation amount and the minimum film spacing of the compensation design under the corresponding circuit layer thickness of each circuit layer in the PCB board; A first supplementing module, used for performing a first supplement to the film compensation value of each circuit layer in the PCB board according to the maximum film compensation amount; The second supplementing module is used to perform a second supplement on the film compensation value of the circuit layer whose actual impedance line spacing in each circuit layer of the PCB board does not meet the compensation condition.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the PCB impedance compensation design method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the PCB impedance compensation design method according to any one of claims 1 to 7 when executed.

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