Semiconductor memory device

Abstract

A semiconductor memory device includes a conductive line elongated in a first direction, a superlattice layer disposed on the conductive line, a plurality of channel regions spaced apart from each other in the first direction on the superlattice layer and each connected to the conductive line, a back gate electrode elongated in a second direction between the first channel region and a second channel region, and a pair of word lines disposed between the second channel region and the third channel region. The superlattice layer includes a first superlattice layer having a plurality of first oxide layers and a plurality of first compound layers alternately stacked with each other. The superlattice layer further includes a second superlattice layer having a plurality of second oxide layers and a plurality of second compound layers alternately stacked with each other.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor. Background Art

[0002] Most semiconductor devices include transistors. For example, in a memory device such as a dynamic random access memory (DRAM), a memory cell includes a cell transistor.

[0003] Since memory devices constantly require improvements in integration and performance, transistor manufacturing technology faces physical limitations. For example, as the size of the memory cell decreases, the size of the transistor decreases, which inevitably shortens the channel length of the transistor. When the channel length of the transistor decreases, the characteristics of the memory device deteriorate due to various problems such as a decrease in data retention characteristics.

[0004] Recently, a vertical channel transistor has been proposed. The vertical channel transistor (VCT) includes a pillar in which a vertical channel is formed. Summary of the Invention

[0005] The present disclosure provides a semiconductor memory device having a reduced process cost and improved electrical reliability by preventing degradation of a capacitor.

[0006] In addition, the features and advantages of the present disclosure are not limited to those described above, and other features and advantages will be clearly understood by those skilled in the art from the following description.

[0007] The present disclosure provides a semiconductor memory device as described below.

[0008] According to an aspect of the present disclosure, there is provided a semiconductor memory device including: a conductive wire extending in a first horizontal direction; a superlattice layer provided on the conductive wire; a plurality of channel regions arranged on the superlattice layer to be spaced apart from each other in the first horizontal direction and configured to be respectively connected to the conductive wire; a back gate electrode extending in a second horizontal direction between a first channel region and a second channel region and spaced apart from the conductive wire in a vertical direction, the first channel region and the second channel region being selected from the plurality of channel regions and adjacent to each other, the second horizontal direction being perpendicular to the first horizontal direction; and a pair of word lines arranged between the second channel region and a third channel region and spaced apart from each other in the first horizontal direction, the second channel region and the third channel region being selected from the plurality of channel regions and adjacent to each other, wherein the superlattice layer includes a first superlattice layer and a second superlattice layer, the first superlattice layer being formed by alternately stacking a plurality of first oxide layers and a plurality of first compound layers, and the second superlattice layer being formed by alternately stacking a plurality of second oxide layers and a plurality of second compound layers.

[0009] According to another aspect of the present disclosure, there is provided a semiconductor memory device including: a conductive wire extending in a first horizontal direction; a superlattice layer provided on the conductive wire; a plurality of channel regions arranged at positions spaced apart from the conductive wire in a vertical direction and spaced apart from each other in the first horizontal direction; a plurality of contact plugs spaced apart from the conductive wire in the vertical direction with the plurality of channel regions therebetween; a back gate electrode extending in a second horizontal direction between a first channel region and a second channel region and spaced apart from the conductive wire in the vertical direction, the first channel region and the second channel region being selected from the plurality of channel regions and adjacent to each other, the second horizontal direction being perpendicular to the first horizontal direction; a back gate dielectric film disposed between the back gate electrode and the second channel region and contacting each of the back gate electrode and the second channel region; a word line spaced apart from the back gate electrode in the first horizontal direction with the second channel region therebetween; and a gate dielectric film disposed between the word line and the second channel region and contacting each of the word line and the second channel region, wherein the superlattice layer has a structure in which a plurality of oxide layers and a plurality of compound layers are alternately stacked.

[0010] According to another aspect of the present disclosure, there is provided a semiconductor memory device including: a plurality of conductive wires extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a plurality of contact plugs disposed at positions spaced apart from the plurality of conductive wires in a vertical direction; a plurality of channel regions disposed between the plurality of conductive wires and the plurality of contact plugs, each channel region including one end spaced apart from the plurality of conductive wires in the vertical direction and the other end connected to one contact plug selected from the plurality of contact plugs; a plurality of back gate electrodes extending in the second horizontal direction between the plurality of conductive wires and the plurality of contact plugs and spaced apart from each other in the first horizontal direction; a plurality of back gate dielectric films respectively contacting the plurality of back gate electrodes; a plurality of word lines extending in the second horizontal direction between the plurality of conductive wires and the plurality of contact plugs; a plurality of gate dielectric films respectively contacting the plurality of word lines; and a superlattice layer disposed between the plurality of channel regions and the plurality of conductive wires, wherein the superlattice layer has a structure in which a plurality of oxide layers and a plurality of compound layers are alternately stacked, and the plurality of compound layers include materials selected from silicon phosphide (SiP), silicon arsenide (SiAs), and combinations thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Implementations of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a plan layout diagram showing some elements of a semiconductor memory device according to some implementations;

[0013] Figure 2 is along Figure 1A cross-sectional view taken along line X1-X1' in

[0014] Figure 3A and Figure 3B is an enlarged cross-sectional view of the area indicated by "EX" in Figure 2 ; and

[0015] Figures 4A to 18B is a diagram for describing a method of manufacturing a semiconductor memory device according to some implementations in accordance with a process sequence, where Figure 4A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 12A , Figure 15A , Figure 16A and Figure 18A are plan layout diagrams showing some elements for describing a method of manufacturing a semiconductor memory device according to a process sequence, Figure 4B , Figure 5 , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11 , Figure 12B , Figure 13 , Figure 14 , Figure 15B , Figure 16B , Figure 17 and Figure 18B are cross-sectional views of the area corresponding to line X1-X1' in Figure 1 . DETAILED DESCRIPTION

[0016] Hereinafter, implementations will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements, and redundant descriptions thereof are omitted.

[0017] Since the implementations can be modified in various ways, specific implementations are shown in the drawings and described in detail in the detailed description. However, this is not intended to limit the scope to the specific implementations, and should be understood to include all transformations, equivalents, and alternatives included in the disclosed spirit and technical scope. When determining that the detailed description of the related art may obscure this point, its detailed description is omitted.

[0018] Figure 1 is a plan layout diagram showing some elements of a semiconductor memory device 100 according to some implementations. Figure 2 is a cross-sectional view taken along Figure 1 line X1-X1' in Figure 3A andFigure 3B is an enlarged cross-sectional view of the region indicated by "EX" in Figure 2 .

[0019] First, referring to Figure 1 and Figure 2 , the semiconductor memory device 100 includes a plurality of conductive lines BL that extend or stretch in a first horizontal direction (X direction) and are repeatedly arranged at intervals from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). In the semiconductor memory device 100, each of the plurality of conductive lines BL may constitute a bit line.

[0020] A plurality of channel regions CHL may be respectively provided on the plurality of conductive lines BL, and a plurality of contact plugs 130 may be provided on the plurality of channel regions CHL. The plurality of channel regions CHL may be repeatedly arranged at intervals from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction) between the plurality of conductive lines BL and the plurality of contact plugs 130. Each of the plurality of channel regions CHL may have one end spaced apart from the plurality of conductive lines BL in a vertical direction (Z direction) and the other end connected to one contact plug 130 selected from the plurality of contact plugs 130. The plurality of channel regions CHL may be physically spaced apart from the conductive lines BL respectively and may each be in contact with one contact plug 130.

[0021] Each of the plurality of conductive lines BL may include doped polysilicon, metal, conductive metal nitride, or any combination thereof. For example, each of the plurality of conductive lines BL may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), ruthenium (Ru), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), ruthenium titanium nitride (RuTiN), or any combination thereof.

[0022] The plurality of contact plugs 130 may be spaced apart from the plurality of conductive lines BL in a vertical direction (Z direction) with a plurality of channel regions CHL therebetween. The plurality of contact plugs 130 may be arranged in a matrix arrangement in the first horizontal direction (X direction) and the second horizontal direction (Y direction) to be spaced apart from each other. The plurality of contact plugs 130 may be respectively connected to the plurality of channel regions CHL.

[0023] Each of the plurality of contact plugs 130 may include metal, conductive metal nitride, metal silicide, doped polysilicon, or any combination thereof. For example, each of the plurality of contact plugs 130 may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, titanium silicide (TiSi), titanium silicon nitride (TiSiN), tungsten silicide (WSi), tungsten silicon nitride (WSiN), tantalum silicide (TaSi), tantalum silicon nitride (TaSiN), ruthenium titanium nitride (RuTiN), cobalt silicide (CoSi), nickel silicide (NiSi), doped polysilicon, or any combination thereof. In some implementations, as Figure 2 shown, each of the plurality of contact plugs 130 includes a first conductive pattern 132, a second conductive pattern 134, and a third conductive pattern 136 sequentially stacked on a respective one of the plurality of channel regions CHL. For example, the first conductive pattern 132 may include doped polysilicon, the second conductive pattern 134 may include metal silicide, and the third conductive pattern 136 may include metal, but the present disclosure is not limited thereto.

[0024] As Figure 1 shown, the plurality of channel regions CHL may include a first set of channel regions CHL and a second set of channel regions CHL. The first set of channel regions CHL are arranged in rows in a first horizontal direction (X direction) and are spaced apart from each other in the first horizontal direction (X direction). The second set of channel regions CHL are arranged in rows in a second horizontal direction (Y direction) and are spaced apart from each other in the second horizontal direction (Y direction). Each of the plurality of contact plugs 130 may be disposed on a channel region CHL selected from the plurality of channel regions CHL. Each of the plurality of contact plugs 130 may pass through the interlayer insulating film 138 and may contact the selected one of the channel regions CHL. The interlayer insulating film 138 may include a silicon oxide film, a silicon nitride film, or a combination thereof.

[0025] Here, terms such as "first", "second", and "third" are used to describe various elements, but these terms are not intended to limit the elements. These terms are only used to distinguish one element from another, and unless specifically stated to the contrary, the first element may be the second element or the third element. For example, without departing from the scope of the various implementations described below, the first channel region may be referred to as the second channel region or the third channel region. Similarly, the second channel region or the third channel region may be referred to as the first channel region. Each of the first channel region, the second channel region, and the third channel region is a channel region, but the first channel region, the second channel region, and the third channel region are not necessarily the same channel region.

[0026] In some implementations, each of the plurality of channel regions CHL may include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. In other implementations, each of the plurality of channel regions CHL may include at least one of germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some implementations, the channel region CHL may include a conductive region, an impurity-doped well, or an impurity-doped structure.

[0027] A plurality of back gate electrodes BG and a plurality of word lines WL may be disposed on each of the plurality of conductive lines BL. Each of the plurality of back gate electrodes BG and the plurality of word lines WL may extend in a second horizontal direction (Y direction) between the plurality of conductive lines BL and the plurality of contact plugs 130. The plurality of back gate electrodes BG and the plurality of word lines WL may be spaced apart from each other in a first horizontal direction (X direction).

[0028] Among the plurality of back gate electrodes BG and the plurality of word lines WL arranged in rows in a first horizontal direction (X direction) on one conductive line BL, one back gate electrode BG and a pair of word lines WL may be alternately arranged with each other, and the one back gate electrode BG and the pair of word lines WL may be spaced apart from each other with one of the plurality of second sets of channel regions CHL therebetween. In other words, the plurality of word lines WL may be arranged such that a pair of adjacent word lines WL are arranged between two corresponding back gate electrodes BG among the plurality of back gate electrodes BG. The tops of the pair of word lines WL may be spaced apart from each other in the first horizontal direction (X direction).

[0029] Each of the plurality of back gate electrodes BG may include a metal, a conductive metal nitride, doped polycrystalline silicon, or any combination thereof. For example, each of the plurality of back gate electrodes BG may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, doped polycrystalline silicon, or any combination thereof, but is not limited thereto. Each of the plurality of word lines WL may include a metal, a conductive metal nitride, or any combination thereof. For example, each of the plurality of word lines WL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, or any combination thereof, but is not limited thereto.

[0030] Each of the plurality of back gate electrodes BG may extend in a second horizontal direction (Y direction) between two channel regions CHL adjacent to each other in a first horizontal direction (X direction). Each of the plurality of back gate electrodes BG may be disposed at a position spaced apart from each of the conductive line BL and the plurality of contact plugs 130 in a vertical direction (Z direction).

[0031] The semiconductor memory device 100 includes a plurality of back gate dielectric films 152 covering a plurality of back gate electrodes BG. Each of the plurality of back gate dielectric films 152 may be located between one back gate electrode BG and a channel region CHL adjacent to the one back gate electrode BG. Each of the plurality of back gate dielectric films 152 may be in contact with an adjacent back gate electrode BG and an adjacent channel region CHL.

[0032] Between a pair of adjacent channel regions CHL, a first capping insulating pattern 158 may be disposed between the back gate electrode BG and the plurality of contact plugs 130. The first capping insulating pattern 158 and the back gate electrode BG may be arranged to overlap each other in a vertical direction (Z direction). The first capping insulating pattern 158 may include a silicon oxide film, a silicon nitride film, or a combination thereof.

[0033] Each of the plurality of word lines WL may be disposed at a position spaced apart from each of the conductive lines BL and the plurality of contact plugs 130 in a vertical direction (Z direction). A pair of word lines WL may be disposed between two corresponding back gate electrodes BG among the plurality of back gate electrodes BG in a first horizontal direction (X direction). The pair of word lines WL may be spaced apart from an adjacent back gate electrode BG in the first horizontal direction (X direction), with a set of a plurality of second sets of channel regions CHL therebetween.

[0034] As Figure 2 shown, a first superlattice layer 103 and a second superlattice layer 105 may be located between the plurality of channel regions CHL and the conductive lines BL. The first superlattice layer 103 and the second superlattice layer 105 may be used as direct contact plugs. The first superlattice layer 103 and the second superlattice layer 105 may also be used as an etch stop film during a manufacturing process for the second superlattice layer 105 at a later time.

[0035] The first superlattice layer 103 includes a first oxide layer 103a and a first compound layer 103b. In some implementations, the first oxide layer 103a may include silicon oxide. In some implementations, the first oxide layer 103a may include silicon dioxide (SiO2). In some implementations, the concentration of oxygen atoms in the first oxide layer 103a may be in the range of about 10 17 / cm 3 to about 10 22 / cm 3 In some implementations, the first compound layer 103b may include silicon phosphide (SiP). In some implementations, the concentration of phosphorus in the first compound layer 103b may be in the range of about 10 16 / cm 3 to about 10 22 / cm 3within a range. In some implementations, the number of superlattices in the first superlattice layer 103 formed by the first oxide layer 103a and the first compound layer 103b can be in the range of 1 to 100.

[0036] The second superlattice layer 105 includes a second oxide layer 105a and a second compound layer 105b. In some implementations, the second oxide layer 105a can include silicon oxide. In some implementations, the second oxide layer 105a can include SiO2. In some implementations, the concentration of oxygen atoms in the second oxide layer 105a can be about 10 17 / cm 3 to about 10 22 / cm 3 within a range. In some implementations, the second compound layer 105b can include silicon arsenide (SiAs). In some implementations, the concentration of arsenic in the second compound layer 105b can be about 10 16 / cm 3 to about 10 22 / cm 3 within a range. In some implementations, the number of superlattices in the second superlattice layer 105 formed by the second oxide layer 105a and the second compound layer 105b can be in the range of 1 to 100.

[0037] In some implementations, the sum of the thicknesses of the first superlattice layer 103 and the second superlattice layer 105 can be in the range of about 1 nm to about 100 nm. In Figure 2 the first compound layer 103b and the second compound layer 105b respectively include phosphorus (P) and arsenic (As). However, the present disclosure is not limited thereto, and the compound layer can include other p-type dopants such as antimony (Sb).

[0038] The spacer insulating pattern 124 can be disposed between a pair of word lines WL, and the pair of word lines WL are disposed between a pair of adjacent channel regions CHL. The first buried insulating pattern 126 can be disposed between the pair of word lines WL and the plurality of contact plugs 130. The word lines WL and the first buried insulating pattern 126 can be disposed to overlap each other in the vertical direction (Z direction) between a pair of adjacent channel regions CHL. The pair of word lines WL can be spaced apart from the plurality of contact plugs 130 in the vertical direction (Z direction) with the first buried insulating pattern 126 therebetween.

[0039] Each of the spacer insulating pattern 124 and the first buried insulating pattern 126 may include a silicon oxide film, a silicon nitride film, or any combination thereof. In some implementations, the spacer insulating pattern 124 and the first buried insulating pattern 126 may include the same or similar materials to each other. In other implementations, the spacer insulating pattern 124 and the first buried insulating pattern 126 may include different materials from each other.

[0040] The gate dielectric film 120 may be located between each of the plurality of word lines WL and the adjacent channel region CHL, and contact each of the plurality of word lines WL and the adjacent channel region CHL. A pair of gate dielectric films 120 may be arranged between a pair of adjacent channel regions CHL, and a pair of word lines WL may be arranged between the pair of gate dielectric films 120. Each of the pair of gate dielectric films 120 may include one end spaced apart from the conductive line BL and the other end contacting one contact plug 130 selected from the plurality of contact plugs 130.

[0041] The metal silicide film 164 may be located between the first and second superlattice layers 103 and 105 and the conductive line BL. The metal silicide film 164 may include TiSi, WSi, TaSi, CoSi, NiSi, or any combination thereof, but is not limited thereto.

[0042] In some implementations, each of the gate dielectric film 120 and the back gate dielectric film 152 may include a silicon oxide film, a high-k dielectric film, or any combination thereof. The high-k dielectric film may refer to a film having a higher dielectric constant than the silicon oxide film. In some implementations, each of the gate dielectric film 120 and the back gate dielectric film 152 may include at least one material selected from silicon oxide, hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth iron oxide (BFO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). The plurality of back gate electrodes BG, the plurality of word lines WL, the plurality of channel regions CHL, the plurality of back gate dielectric films 152, and the plurality of gate dielectric films 120 arranged between the plurality of conductive lines BL and the plurality of contact plugs 130 may form a plurality of vertical channel transistors. The back gate dielectric film 152 and the gate dielectric film 120 may contact the second superlattice layer 105.

[0043] AsFigure 1 and Figure 2 As shown in Figure 2 , the capacitor structure 140 may be disposed on the plurality of contact plugs 130 and the interlayer insulating film 138. The capacitor structure 140 includes a plurality of lower electrodes 142, a capacitor dielectric film 144, and an upper electrode 146. The capacitor dielectric film 144 conformally covers the surface of each of the plurality of lower electrodes 142, and the upper electrode 146 covers the plurality of lower electrodes 142 with the capacitor dielectric film 144 therebetween. Each of the plurality of lower electrodes 142 may be connected to the channel region CHL through one contact plug 130 selected from the plurality of contact plugs 130. The third conductive pattern 136 included in each of the plurality of contact plugs 130 may be used as a landing pad for contacting one lower electrode 142 selected from the plurality of lower electrodes 142.

[0044] Figure 3A and Figure 3B are enlarged cross-sectional views of the region indicated by "EX" in Figure 2 . Figure 3A The semiconductor memory device 100a in Figure 3B and the semiconductor memory device 100b in Figure 2 differ from the semiconductor memory device 100 in Figure 2 only in terms of the first superlattice layer 103 and the second superlattice layer 105 (see Figure 2 ), and the remaining elements are the same. Therefore, the illustration and description of the same elements are omitted, and the differences are mainly described below.

[0045] Different from the semiconductor memory device 100 in Figure 2 where the second superlattice layer 105 is disposed on the first superlattice layer 103, Figure 3A the semiconductor memory device 100a in Figure 3A only includes the second superlattice layer 105. The second superlattice layer 105 may include a structure in which a second oxide layer 105a and a second compound layer 105b are alternately stacked. In some implementations, the second oxide layer 105a may contain silicon oxide. In some implementations, the concentration of oxygen atoms in the second oxide layer 105a may be in the range of about 10 17 / cm 3 to about 10 22 / cm 3 . In some implementations, the second compound layer 105b may contain SiAs. In some implementations, the concentration of arsenic in the second compound layer 105b may be in the range of about 10 16 / cm 3 to about 10 22 / cm 3 . In some implementations, the number of superlattices in the second superlattice layer 105 formed by the second oxide layer 105a and the second compound layer 105b may be in the range of 1 to 100.

[0046] Figure 3B The semiconductor memory device 100b in [description] only includes the first superlattice layer 103. The first superlattice layer 103 may include a structure in which a first oxide layer 103a and a first compound layer 103b are alternately stacked. In some implementations, the first oxide layer 103a may contain silicon oxide. In some implementations, the concentration of oxygen atoms in the first oxide layer 103a may be in the range of about 10 17 / cm 3 to about 10 22 / cm 3 In some implementations, the first compound layer 103b may contain SiP. In some implementations, the concentration of phosphorus in the first compound layer 103b may be in the range of about 10 16 / cm 3 to about 10 22 / cm 3 In some implementations, the number of superlattices in the first superlattice layer 103 formed by the first oxide layer 103a and the first compound layer 103b may be in the range of 1 to 100.

[0047] Figures 4A to 18B is a diagram for describing a method of manufacturing a semiconductor memory device according to some implementations in accordance with a process sequence. More specifically, Figure 4A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 12A , Figure 15A , Figure 16A and Figure 18A are plan layout diagrams showing some elements in accordance with a process sequence for describing a method of manufacturing a semiconductor memory device. Figure 4B , Figure 5 , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11 , Figure 12B , Figure 13 , Figure 14 , Figure 15B , Figure 16B , Figure 17 and Figure 18B are cross-sectional views of regions corresponding to the line X1-X1' in Figure 1 in accordance with a process sequence. Refer to Figures 4A to 18B to describe an example of a method of manufacturing the semiconductor memory device 100 shown in Figure 1 and Figure 2 InFigures 4A to 18B In Figure 1 and Figure 2 the same reference numerals as those in the accompanying drawings denote the same components, and redundant descriptions thereof are omitted herein.

[0048] Referring to Figure 4A and Figure 4B , a substrate structure including a substrate 102, a first superlattice layer 103, a second superlattice layer 105, and an active layer 106 can be fabricated.

[0049] The substrate 102 can be a silicon substrate. The first superlattice layer 103 can have a structure in which a first oxide layer 103a and a first compound layer 103b are stacked in sequence. The second superlattice layer 105 can have a structure in which a second oxide layer 105a and a second compound layer 105b are stacked in sequence. The active layer 106 can include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some implementations, the active layer 106 can include an impurity-doped well or an impurity-doped structure.

[0050] A mask pattern MP1 can be formed on the active layer 106 of the substrate structure. The mask pattern MP1 can include a silicon nitride film. In some implementations, an oxide film can be located between the active layer 106 and the mask pattern MP1.

[0051] The mask pattern MP1 can be used as an etching mask for etching some regions of the substrate structure and forming a plurality of first trenches T1. The plurality of first trenches T1 can be formed to penetrate a part of the first and second superlattice layers 103 and 105 and the active layer 106 in the vertical direction (Z direction) and extend in the second horizontal direction (Y direction).

[0052] Referring to Figure 5 , in Figure 4A and Figure 4B of the product, a back gate dielectric film 152 that conformally covers the inner walls of the plurality of first trenches T1 and the surfaces of each mask pattern MP1 and a back gate conductive layer BGL that fills the plurality of first trenches T1 on the back gate dielectric film 152 can be formed. The material of the back gate conductive layer BGL is substantially the same as the material described above for the back gate electrode BG.

[0053] Referring to Figure 6A and Figure 6B , in Figure 5 of the product, the back gate conductive layer BGL can be etched back to form a plurality of back gate electrodes BG in the plurality of first trenches T1, the upper spaces of each of the plurality of first trenches T1 can be filled with a first capping insulating pattern 158, and the product thus obtained can be planarized to expose the upper surface of the mask pattern MP1.

[0054] Referring to Figure 7A and Figure 7B , the mask pattern MP1 can be removed from the products of Figure 6A and Figure 6B to expose the active layer 106 around the plurality of first capping insulating patterns 158 and the plurality of back gate dielectric films 152.

[0055] Referring to Figure 8A and Figure 8B , a plurality of spacer layers SPL can be formed to cover partial regions of each of the plurality of first capping insulating patterns 158 and the plurality of back gate dielectric films 152 and partial regions of the active layer 106 existing therearound. Each of the plurality of spacer layers SPL can include a silicon oxide film. The plurality of spacer layers SPL can include a first group of spacer layers SPL and a second group of spacer layers SPL. The first group of spacer layers SPL are arranged in rows in a first horizontal direction (X direction) and are spaced apart from each other in the first horizontal direction (X direction), and the second group of spacer layers SPL are arranged in rows in a second horizontal direction (Y direction) and are spaced apart from each other in the second horizontal direction (Y direction).

[0056] Referring to Figure 9A and Figure 9B , the plurality of spacer layers SPL can be re-etched to form a plurality of spacers SP covering opposite sidewalls in the first horizontal direction (X direction) of each of the plurality of structures, and the plurality of structures include the first capping insulating patterns 158 and the back gate dielectric films 152. Some regions of the upper surface of the active layer 106 adjacent to the structures can be covered by the plurality of spacers SP.

[0057] Referring to Figure 10A and Figure 10B , the active layer 106 can be etched by using the plurality of first capping insulating patterns 158, the plurality of back gate dielectric films 152, and the plurality of spacers SP as etching masks to form a plurality of second trenches T2. As a result, portions of the active layer 106 existing under the plurality of spacers SP can be retained as a plurality of channel regions CHL. During the process of etching the active layer 106, a portion of the second superlattice layer 105 can be etched due to over-etching, such that a plurality of recessed regions 105R connected to the plurality of second trenches T2 can be formed on the upper surface of the second superlattice layer 105.

[0058] Referring to Figure 11 , in forming a conformal coverage of Figure 10A and Figure 10BAfter forming a gate dielectric film 120 of the product and forming a conductive layer covering the gate dielectric film 120, a part of the conductive layer can be etched in the second trench T2 and the recessed area 105R of the second superlattice layer 105 to form a preliminary word line PWL that conformally covers the gate dielectric film 120. Thereafter, a spacer insulating pattern 124 can be formed to fill the upper space of the preliminary word line PWL. The spacer insulating pattern 124 can be formed to fill the second trench T2 and the recessed area 105R on the preliminary word line PWL and cover the upper surface of the preliminary word line PWL. The material of the conductive layer is the same as that of the word line WL described above.

[0059] Referring to Figure 12A and Figure 12B , in Figure 11 of the product, the spacer insulating pattern 124 can be etched back to remove the upper part of the spacer insulating pattern 124, thereby exposing a part of the preliminary word line PWL, and the exposed part of the preliminary word line PWL can be etched to form a plurality of word lines WL.

[0060] Referring to Figure 13 , a first buried insulating film 126L covering Figure 12A and Figure 12B of the product can be formed. The material of the first buried insulating film 126L can be the same as that of the first buried insulating pattern 126 described above.

[0061] Referring to Figure 14 , in Figure 13 of the product, a planarization process can be performed on the exposed upper surface of the first buried insulating film 126L to expose a plurality of channel regions CHL, and a first buried insulating pattern 126 can be formed from the first buried insulating film 126L. After exposing the plurality of channel regions CHL, the height of the uppermost part of each of the first capping insulating pattern 158 and the gate dielectric film 120 in Figure 13 of the product can be reduced.

[0062] Referring to Figure 15A and Figure 15B , in Figure 14 of the product, a plurality of contact plugs 130 can be formed on the plurality of channel regions CHL, and an interlayer insulating film 138 can be formed to fill the space between the corresponding contact plugs 130 among the plurality of contact plugs 130.

[0063] Referring to Figure 16A and Figure 16B , a capacitor structure 140 connected to the plurality of contact plugs 130 can be formed on Figure 15A and Figure 15B of the product.

[0064] Referring to Figure 17 , by Figure 16Aand Figure 16B The product of Figure 16B is flipped to be upside down in the vertical direction (Z direction). The substrate 102 can be face up in the vertical direction (Z direction), and the grinding process and the wet etching process can be sequentially performed on the exposed back surface of the substrate 102 until the first superlattice layer 103 is exposed. The first superlattice layer 103 and the second superlattice layer 105 can be used as direct contact plugs later. By forming the first superlattice layer 103 and the second superlattice layer 105 used as direct contact plugs before forming the capacitor structure 140, different from forming the direct contact plugs after forming the capacitor structure 140, the process can be performed in the range of 430 °C or lower. Therefore, there is less concern that the semiconductor memory device including other components will be damaged by heat.

[0065] Referring to Figure 18A and Figure 18B , in Figure 17 the product of Figure 17 , a metal silicide film 164 and a conductive line BL covering the exposed surface of the first superlattice layer 103 can be formed, so that Figure 1 and Figure 2 the semiconductor memory device 100 shown in Figure 2 can be manufactured.

[0066] Figure 3A The semiconductor memory device 100a shown in Figure 3A can be obtained by performing the process of Figures 5 to 18B after forming the second superlattice layer 105. The second superlattice layer 105 is obtained by alternately stacking only the second oxide layer 105a and the second compound layer 105b on the substrate 102 without the first superlattice layer 103 in the process of Figure 4A and Figure 4B . Figure 3B The semiconductor memory device 100b shown in Figure 3B can be obtained by performing the process of Figures 5 to 18B after forming the first superlattice layer 103. The first superlattice layer 103 is obtained by alternately stacking only the first oxide layer 103a and the first compound layer 103b on the substrate 102 without the second superlattice layer 105 in the process of Figure 4A and Figure 4B .

[0067] ​​​​​​​​​​​​Although the present disclosure contains many specific implementation details, these details should not be construed as limitations on the scope that may be claimed. Certain features described in the context of separate implementations in the present disclosure may also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination in multiple implementations. In addition, although the features may be described above as acting in certain combinations, one or more features from a combination may in some cases be deleted from the combination, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0068] Although the present disclosure has been specifically shown and described with reference to implementations thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0069] This application claims priority to Korean Patent Application No. 10-2023-0187521, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: A conductive line extending in a first direction; A superlattice layer is arranged on the conductive line; a plurality of channel regions spaced apart from each other in the first direction on the superlattice layer and each connected to the conductive line; a back gate electrode extending in a second direction between a first channel region and a second channel region of the plurality of channel regions, the first channel region and the second channel region being adjacent to each other, wherein the back gate electrode is spaced apart from the conductive line in a third direction, and wherein the second direction is perpendicular to the first direction; and a pair of word lines arranged between the second channel region and the third channel region of the plurality of channel regions, the second channel region and the third channel region being adjacent to each other, wherein top ends of the pair of word lines are spaced apart from each other in the first direction, Wherein, the superlattice layer includes a first superlattice layer, the first superlattice layer includes a plurality of first oxide layers and a plurality of first compound layers stacked alternately with each other, and wherein, the superlattice layer further includes a second superlattice layer, the second superlattice layer includes a plurality of second oxide layers and a plurality of second compound layers stacked alternately with each other.

2. The semiconductor memory device according to claim 1, wherein: The second superlattice layer is disposed on the first superlattice layer.

3. The semiconductor memory device according to claim 1, wherein: The first compound layer includes silicon phosphide (SiP), and the second compound layer includes silicon arsenide (SiAs).

4. The semiconductor memory device according to claim 1, wherein: The superlattice layer has a thickness in the third direction in a range from about 1 nm to about 100 nm.

5. The semiconductor memory device according to claim 1, wherein: The concentration of oxygen (O) atoms included in each of the first oxide layer and the second oxide layer is about 10 17 / cm 3 to about 10 22 / cm 3 within the range.

6. The semiconductor memory device according to claim 1, wherein The concentration of phosphorus (P) included in the first compound layer is about 10 16 / cm 3 to about 10 22 / cm 3 within the range.

7. The semiconductor memory device according to claim 1, wherein: The concentration of arsenic (As) included in the second compound layer is about 10 16 / cm 3 to about 10 22 / cm 3 within the range.

8. The semiconductor memory device according to claim 1, wherein: The first oxide layer and the second oxide layer include the same material. 9 . The semiconductor memory device according to claim 1 , further comprising a metal silicide film between the superlattice layer and the conductive line.

10. The semiconductor memory device according to claim 1, further comprising a plurality of contact plugs spaced apart from the conductive line in the third direction, wherein The plurality of channel regions are respectively arranged between the plurality of contact plugs and the conductive line, and wherein each of the plurality of contact plugs is in contact with a corresponding channel region of the plurality of channel regions, and The back gate electrode has a first end surface facing the plurality of contact plugs and a second end surface facing the superlattice layer and the conductive line.

11. The semiconductor memory device according to claim 1, further comprising: a back-gate dielectric film, located between the second channel region and the back-gate electrode; as well as a gate dielectric film located between the second channel region and a first word line of the pair of word lines that is closer to the second channel region, Wherein, the back gate dielectric film and the gate dielectric film are in contact with the superlattice layer.

12. A semiconductor memory device comprising: A conductive line extending in a first direction; A superlattice layer is arranged on the conductive line; a plurality of channel regions spaced apart from each other in the first direction, wherein the plurality of channel regions are spaced apart from the conductive line in a third direction; a plurality of contact plugs spaced apart from the conductive line in the third direction, wherein the plurality of channel regions are respectively arranged between the plurality of contact plugs and the conductive line; a back gate electrode extending in a second direction between a first channel region and a second channel region of the plurality of channel regions, the first channel region and the second channel region being adjacent to each other, wherein the back gate electrode is spaced apart from the conductive line in the third direction, and wherein the second direction is perpendicular to the first direction; a back-gate dielectric film disposed between the back-gate electrode and the second channel region and contacting each of the back-gate electrode and the second channel region; a word line spaced apart from the back gate electrode in the first direction, wherein the second channel region is arranged between the word line and the back gate electrode; and a gate dielectric film disposed between the word line and the second channel region and contacting each of the word line and the second channel region, The superlattice layer has a structure in which a plurality of oxide layers and a plurality of compound layers are alternately stacked.

13. The semiconductor memory device according to claim 12, wherein: The plurality of compound layers include silicon phosphide (SiP), and the concentration of phosphorus (P) included in the plurality of compound layers is about 10 16 / cm 3 to about 10 22 / cm 3 within the range.

14. The semiconductor memory device according to claim 12, wherein: The plurality of compound layers include silicon arsenide (SiAs), and the concentration of arsenic (As) included in the plurality of compound layers is about 10 16 / cm 3 to about 10 22 / cm 3 within the range.

15. The semiconductor memory device according to claim 12, wherein: The superlattice layer has a thickness in the third direction in a range from about 1 nm to about 100 nm.

16. The semiconductor memory device according to claim 12, wherein: The concentration of oxygen atoms included in the plurality of oxide layers is about 10 17 / cm 3 to about 10 22 / cm 3 within the range. 17 . The semiconductor memory device according to claim 12 , further comprising a metal silicide film between the superlattice layer and the conductive line.

18. A semiconductor memory device comprising: a plurality of conductive lines extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction; a plurality of contact plugs spaced apart from the plurality of conductive lines in a third direction; a plurality of channel regions, respectively arranged between the plurality of conductive lines and the plurality of contact plugs, wherein each of the plurality of channel regions includes an end portion spaced apart from the plurality of conductive lines in the third direction and connected to a corresponding contact plug of the plurality of contact plugs; a plurality of back gate electrodes extending in the second direction between the plurality of conductive lines and the plurality of contact plugs and spaced apart from each other in the first direction; A plurality of back-gate dielectric films, respectively contacting the plurality of back-gate electrodes; a plurality of word lines extending in the second direction between the plurality of conductive lines and the plurality of contact plugs; a plurality of gate dielectric films, respectively contacting the plurality of word lines; and a superlattice layer disposed between the plurality of channel regions and the plurality of conductive lines, The superlattice layer has a structure in which a plurality of oxide layers and a plurality of compound layers are alternately stacked, and The plurality of compound layers include a material selected from silicon phosphide (SiP), silicon arsenide (SiAs), and a combination of SiP and SiAs.

19. The semiconductor memory device according to claim 18, wherein: The superlattice layer has a thickness in the third direction in a range from about 1 nm to about 100 nm.

20. The semiconductor memory device according to claim 18, wherein The concentration of oxygen atoms included in the plurality of oxide layers is about 10 17 / cm 3 to about 10 22 / cm 3 within the range.

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