Three-dimensional stacked chip and manufacturing method thereof

Abstract

The invention discloses a three-dimensional stacked chip and a manufacturing method thereof. The three-dimensional stacked chip comprises a substrate, a first storage module and a logic module, the first storage module and the logic module are sequentially stacked on the substrate, and the first storage module is arranged between the logic module and the substrate; one side of the first storage module is in conductive connection with the logic module, and the other side of the first storage module is in conductive connection with the substrate, so that the logic module can perform data interaction with the first storage module and perform signal interaction with the outside by virtue of the first storage module and the substrate. The influence of heat generated by the logic module on the storage module is avoided, the power consumption tolerance of the logic module is remarkably improved, the logic module can provide enough supporting strength in the whole technological process, and the situation of structural damage is avoided while an additional supporting structure is omitted.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and more specifically, relates to a three-dimensional stacked chip and a manufacturing method thereof. Background Art

[0002] With the explosion of large language models in AI applications, artificial intelligence software has put forward higher requirements for the chip design industry. Traditional chip architectures and supporting memories are far from meeting the requirements of large language models for large bandwidth and high capacity. In order to meet the needs of the explosive development of AI, it is necessary to accelerate the research and development of new chip architectures and new storage technologies. Summary of the Invention

[0003] In view of the above defects or improvement requirements of the prior art, the present invention provides a three-dimensional stacked chip and a manufacturing method thereof, which avoid the influence of heat generated by the logic module on the storage module, significantly improve the power consumption tolerance of the logic module, and the logic module can provide sufficient support strength during the entire process, eliminating the need for an additional support structure and avoiding structural damage.

[0004] To achieve the above object, according to one aspect of the present invention, a three-dimensional stacked chip is provided, including a substrate, a first storage module, and a logic module; the first storage module and the logic module are stacked on the substrate in sequence, and the first storage module is disposed between the logic module and the substrate; one side of the first storage module forms an electrical connection with the logic module, and the other side of the first storage module forms an electrical connection with the substrate, so that the logic module can perform data interaction with the first storage module and communicate with the outside through the first storage module and the substrate.

[0005] In some embodiments, the above three-dimensional stacked chip further includes one or more stacked second storage modules, and the one or more stacked second storage modules are disposed between the first storage module and the logic module to form a storage module stacked structure with the first storage module; one side of each second storage module forms an electrical connection with the adjacent first storage module or other second storage modules on the same side, and the other side of each second storage module forms an electrical connection with the adjacent logic module or other second storage modules on the same side, so that the logic module can perform data interaction with the first storage module and the one or more stacked second storage modules and communicate with the outside through the storage module stacked structure and the substrate.

[0006] In some embodiments, the logic module includes a plurality of stacked sub-logic modules, and adjacent surfaces of the plurality of stacked sub-logic modules form an electrical connection.

[0007] In some embodiments, the logic module is connected to the power supply through the storage module stacked structure and grounded through the side opposite to the storage module stacked structure.

[0008] In some embodiments, the logic module is connected through the memory module stack structure, and the power supply is connected through the side opposite to the memory module stack structure.

[0009] In some embodiments, the logic module is connected to the power supply and ground through the side opposite to the memory module stack structure.

[0010] In some embodiments, the logic module is connected to the power supply and ground through the memory module stack structure.

[0011] In some embodiments, the first memory module includes a first substrate and a first interconnect layer disposed on one side of the first substrate, the logic module includes a second substrate and a second interconnect layer disposed on one side of the second substrate, and each second memory module includes a third substrate and a third interconnect layer and a fourth interconnect layer disposed on both sides of the third substrate respectively; the first interconnect layer of the first memory module is bonded to the fourth interconnect layer of the adjacent second memory module, the second interconnect layer of the logic module is bonded to the third interconnect layer of the adjacent second memory module, the fourth interconnect layer of each second memory module is bonded to the first interconnect layer of the adjacent first memory module on the same side or the third interconnect layer of other second memory modules, and the third interconnect layer of each second memory module is bonded to the second interconnect layer of the adjacent logic module on the same side or the fourth interconnect layer of other second memory modules.

[0012] In some embodiments, the first memory module includes a plurality of first through-silicon vias penetrating the first substrate, and each second memory module includes a plurality of second through-silicon vias penetrating the third substrate; the first interconnect layer, the second interconnect layer, the third interconnect layer, and the fourth interconnect layer each include an insulating layer and a conductive structure formed in the insulating layer; through the conductive structure and the first through-silicon vias and the second through-silicon vias, the logic module forms a conductive connection with the first memory module and one or more second memory modules, and forms a conductive path in the memory module stack structure.

[0013] In some embodiments, the above three-dimensional stacked chip further includes a heat dissipation module, and the heat dissipation module is disposed on the logic module.

[0014] In some embodiments, the above three-dimensional stacked chip further includes an external circuit, the external circuit is disposed on the substrate, and the other side of the first memory module forms a conductive connection with the external circuit through the substrate.

[0015] In some embodiments, the above three-dimensional stacked chip further includes a silicon interposer and an external circuit, the silicon interposer is disposed between the first memory module and the substrate, the external circuit is disposed on the silicon interposer, and the other side of the first memory module forms a conductive connection with the external circuit through the silicon interposer and the substrate.

[0016] According to another aspect of the present invention, there is provided a method for manufacturing a three-dimensional stacked chip, including:

[0017] Forming a first storage structure;

[0018] Forming a logic module;

[0019] Forming a plurality of second storage structures;

[0020] Forming a first stacked structure with the logic module and the plurality of second storage structures, wherein the first stacked structure includes the logic module and a plurality of second storage modules stacked on the logic module in sequence, and the second storage modules are obtained by processing the second storage structures;

[0021] Forming a second stacked structure with the first storage structure and the first stacked structure, wherein the second stacked structure includes the logic module and a plurality of second storage modules and a first storage module stacked on the logic module in sequence, and the first storage module is obtained by processing the first storage structure;

[0022] Inverting the second stacked structure and connecting the first storage module to the substrate.

[0023] In some embodiments, forming the first storage structure includes: forming a first storage device and a first interconnect layer on a first substrate; forming the logic module includes: forming a logic device and a second interconnect layer on a second substrate; forming the second storage structure includes: forming a second storage device and a third interconnect layer on a third substrate.

[0024] In some embodiments, forming the first stacked structure includes:

[0025] Combining the second storage structure and the logic module;

[0026] Processing the combined second storage structure to obtain a second storage module;

[0027] Combining the next second storage structure and the second storage module, and processing the combined next second storage structure to obtain the next second storage module.

[0028] In some embodiments, combining the second storage structure and the logic module includes:

[0029] Inverting the second storage structure, aligning the third interconnect layer and the second interconnect layer;

[0030] Combining the second storage structure and the logic module such that the second storage structure and the logic module form a conductive connection through the third interconnect layer and the second interconnect layer.

[0031] In some embodiments, processing the combined second storage structure to obtain a second storage module includes:

[0032] Thin the third substrate of the second storage structure to form a through-silicon via penetrating the thinned third substrate;

[0033] Form a fourth interconnect layer on the thinned third substrate.

[0034] In some embodiments, forming the second stacked structure includes:

[0035] Combine the first storage structure and the second storage module;

[0036] Process the combined first storage structure to obtain a first storage module.

[0037] In some embodiments, processing the combined first storage structure to obtain a first storage module includes: thinning the first substrate of the first storage structure to form a through-silicon via penetrating the thinned first substrate.

[0038] In some embodiments, the method for manufacturing the above three-dimensional stacked chip further includes: arranging a heat dissipation module on the logic module.

[0039] Generally speaking, compared with the prior art by the above technical solutions conceived by the present invention, the following beneficial effects are achieved: The storage module stacked structure is arranged between the logic module and the substrate, such that the logic module is arranged above the storage module stacked structure, which provides great convenience for the heat dissipation of the logic module. The logic module is closer to the heat dissipation module than the storage module stacked structure, avoiding the influence of the heat generated by the logic module on the storage module and significantly improving the power consumption tolerance of the logic module. In addition, the logic module connects to the power supply and ground and interacts with the outside through the storage module stacked structure. Therefore, there is no need to thin the substrate forming the logic module, and the logic module can provide sufficient support strength throughout the process, saving an additional support structure while avoiding the occurrence of structural damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic structural diagram of a three-dimensional stacked chip;

[0041] Figure 2 is a schematic structural diagram of a three-dimensional stacked chip according to an embodiment of the present invention;

[0042] Figure 3 is a schematic structural diagram of a three-dimensional stacked chip according to another embodiment of the present invention;

[0043] Figure 4 is a schematic structural diagram of a three-dimensional stacked chip according to another embodiment of the present invention;

[0044] Figures 5A - 5H is a schematic diagram of the method for manufacturing a three-dimensional stacked chip according to an embodiment of the present invention;

[0045] Figure 6 It is a schematic diagram of the manufacturing process of the three-dimensional stacked chip according to the embodiment of the present invention. Detailed implementation manners

[0046] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary in nature rather than restrictive.

[0047] Stacking the storage module and the logic module in multiple layers can multiply the bandwidth and capacity of the system, so it can fully meet the requirements of large language models. Figure 1 A solution for a three-dimensional stacked chip is given.

[0048] As Figure 1 shown, a logic module 103 and multiple storage modules 105 are sequentially stacked on a substrate 101. The storage module 105 is disposed above the logic module 103, and the logic module 103 is disposed between the storage module 105 and the substrate 101. On the one hand, it is convenient to provide appropriate power and ground for the logic module 103, and on the other hand, it is convenient for the logic module 103 to transfer data to the outside. At the same time, since a large amount of heat is generated when the logic module 103 operates, this part of the heat is mainly dissipated upward through the side where the storage module 105 is located, and the storage module 105 is very sensitive to heat, and the multi-layer stacked storage module 105 further restricts the heat dissipation. Especially when the logic module 103 operates at high power consumption, this stacking method will cause a serious heat accumulation effect, greatly reducing the power consumption tolerance of the logic module 103. Therefore, Figure 1 The three-dimensional stacked chip shown cannot meet the requirements of large language models for the power consumption and computing power of the logic module.

[0049] In order to improve the power consumption tolerance of the logic module and reduce the adverse effects of heat accumulation on the storage module, it is necessary to Figure 1 make further improvements to the three-dimensional stacked chip shown.

[0050] As Figure 2As shown, the three-dimensional stacked chip according to an embodiment of the present invention includes a substrate 201, a first storage module 203, one or more second storage modules 207, and a logic module 205. The first storage module 203, one or more second storage modules 207, and the logic module 205 are stacked on the substrate 201 in sequence. The first storage module 203 and one or more second storage modules 207 form a storage module stacked structure. The logic module 205 is disposed on the storage module stacked structure, and the storage module stacked structure is disposed between the substrate 201 and the logic module 205.

[0051] One side of the first storage module 203 forms an electrical connection with an adjacent second storage module 207, and the other side of the first storage module 203 forms an electrical connection with the substrate 201. One side of the logic module 205 forms an electrical connection with an adjacent second storage module 207. When one side of the second storage module 207 is adjacent to other second storage modules 207, one side of the second storage module 207 forms an electrical connection with the adjacent second storage module 207; when both sides of the second storage module 207 are adjacent to other second storage modules 207, both sides of the second storage module 207 form electrical connections with other second storage modules 207.

[0052] Further, the logic module 205 forms an electrical connection with the first storage module 203 and one or more second storage modules 207, enabling the logic module 205 to perform data interaction with the first storage module 203 and one or more second storage modules 207. Specifically, the first storage module 203 and one or more second storage modules 207 are mainly used to provide and store the data required by the logic module 205, supporting the logic module 205 to complete corresponding tasks. In some embodiments, one or more of the first storage module 203 and one or more second storage modules 207 can also implement a small amount of logic control functions, that is, one or more of these storage modules are a combination of a storage medium and a logic medium, and this combination may be a one-dimensional structure, a two-dimensional structure, or a three-dimensional structure. In some embodiments, the functions that the logic module 205 can implement include one or more of arithmetic operation, control, interface, and data processing.

[0053] The logic module 205 forms a conductive connection with the first storage module 203 and one or more second storage modules 207, thereby forming a conductive path in the storage module stack structure, enabling the logic module 205 to interact with the outside world through the storage module stack structure. In some embodiments, the logic module 205 is connected to the power supply through the storage module stack structure and is grounded through the side opposite to the storage module stack structure; in some embodiments, the logic module 205 is grounded through the storage module stack structure and is connected to the power supply through the side opposite to the storage module stack structure; in some embodiments, the logic module 205 is connected to the power supply and the ground through the side opposite to the storage module stack structure; in some embodiments, the logic module 205 is connected to the power supply and the ground through the storage module stack structure.

[0054] In some embodiments, the logic module 205 includes a plurality of stacked sub-logic modules, and adjacent surfaces of the plurality of stacked sub-logic modules form a conductive connection. In some embodiments, the sub-logic module closer to the storage module stack structure has lower power, and the sub-logic module farther from the storage module stack structure has higher power, which helps to dissipate the heat of the sub-logic module with higher power and reduce the impact of heat on the storage module.

[0055] In some embodiments, one or more second storage modules 207 can be omitted, and the storage module stack structure is replaced by the first storage module 203. That is, one side of the first storage module 203 forms a conductive connection with the logic module 205, and the other side of the first storage module 203 forms a conductive connection with the substrate 201. The above solution of placing the logic module on top of the storage module still applies to the case of only one storage module.

[0056] In some embodiments, the above-described manner of forming the conductive connection includes one or more of hybrid bonding connection and conductive bump connection. In some embodiments, the first storage module 203 may be directly or indirectly disposed on the substrate 201, and one or more second storage modules 207 as a whole may also be directly or indirectly disposed on the first storage module 203, and the logic module 205 may also be directly or indirectly disposed on one or more second storage modules 207. In some embodiments, adjacent means closest proximity, which can be either directly adjacent or indirectly adjacent. For example, when there are no other second storage modules 207 or other structures between two adjacent second storage modules 207, they are directly adjacent; when there are no other second storage modules 207 between two adjacent second storage modules 207 but there are other structures, they are indirectly adjacent; the second storage module 207 adjacent to the first storage module 203 refers to the second storage module 207 closest to the first storage module 203; the second storage module 207 adjacent to the logic module 205 refers to the second storage module 207 closest to the logic module 205.

[0057] In some embodiments, an external circuit (such as a GPU / CPU) is also disposed on the substrate 201. The external circuit and the first storage module 203 are connected through an external interface and the substrate 201, and the substrate 201 is then connected to a circuit board through external pins (not shown in the figure). In some embodiments, the logic module 205 is connected to power and ground through a storage module stack structure and the substrate 201. Further, the logic module 205 obtains working instructions from the outside (external circuit) through the substrate 201 and via the storage module stack structure, completes corresponding work, and transmits the processing result via the storage module stack structure and through the substrate 201 (transmitted to the external circuit).

[0058] In some embodiments, a silicon interposer is disposed between the first storage module 203 and the substrate 201 to provide high-density electrical connections using the silicon interposer. An external circuit (such as a GPU / CPU) is also disposed on the silicon interposer. The external circuit and the first storage module 203 are connected through an external interface and the silicon interposer, and the silicon interposer is then connected to the substrate 201 through an external interface to the external pins, and finally connected to a circuit board through the external pins (not shown in the figure). In some embodiments, the logic module 205 is connected to power and ground through a storage module stack structure and the silicon interposer. Further, the logic module 205 obtains working instructions from the outside (external circuit) through the silicon interposer (or through the silicon interposer and the substrate 201) and via the storage module stack structure, completes corresponding work, and transmits the processing result via the storage module stack structure and through the silicon interposer (or through the silicon interposer and the substrate 201) (transmitted to the external circuit).

[0059] In some embodiments, the substrate 201 is made of one or several of silicon, silicon germanium, germanium, silicon-on-insulator (SOI) film, and organic materials. In some embodiments, the first storage module 203 is Flash, RRAM, DRAM, MRAM, or SRAM, and the second storage module 207 is Flash, RRAM, DRAM, MRAM, or SRAM.

[0060] Figure 2 The structure shown facilitates heat dissipation of the logic module 205 through the side opposite to the storage module stack structure by disposing the logic module 205 on top of the storage module stack structure, avoiding heat accumulation caused by blocked heat conduction in both the upper and lower directions of the logic module when the logic module is between the storage module stack structure and the substrate, and significantly reducing the impact of the heat generated by the logic module on the storage module.

[0061] As Figure 3 shown, a heat dissipation module 301 is disposed on the logic module 205. The heat dissipation module 301 can ensure that a large amount of heat generated by the logic module 205 during high-power operation is dissipated in a timely manner, and thus can significantly improve the power consumption tolerance of the logic module. In some embodiments, the heat dissipation module 301 can be directly or indirectly disposed on the logic module 205. Generally speaking, the positional relationship among the storage module stack structure, the logic module 205, and the heat dissipation module 301 only needs to satisfy that the high-power logic module 205 is closer to the top heat dissipation module 301 than the storage module stack structure. In some embodiments, the heat dissipation module 301 is connected to the logic module 205 through an intermediate material layer with a good thermal conductivity coefficient.

[0062] Further, as Figure 4 shown, the three-dimensional stacked chip includes three second storage modules 207. The first storage module 203 includes a first substrate and a first interconnect layer 401 disposed on one side of the first substrate. The logic module 205 includes a second substrate and a second interconnect layer 402 disposed on one side of the second substrate. Each second storage module 207 includes a third substrate and a third interconnect layer 403 and a fourth interconnect layer 404 disposed on both sides of the third substrate. The first interconnect layer 401 of the first storage module 203 is bonded to the fourth interconnect layer 404 of the adjacent second storage module 207, and the second interconnect layer 402 of the logic module 205 is bonded to the third interconnect layer 403 of the adjacent second storage module 207.

[0063] When one side of the second storage module 207 is adjacent to other second storage modules 207, the third interconnect layer 403 of the second storage module 207 is bonded to the fourth interconnect layer 404 of the adjacent other second storage module 207, or the fourth interconnect layer 401 of the second storage module 207 is bonded to the third interconnect layer 403 of the adjacent other second storage module 207. When both sides of the second storage module 207 are adjacent to other second storage modules 207, the third interconnect layer 403 of the second storage module 207 is bonded to the fourth interconnect layer 404 of the other second storage module 207 adjacent to one side, and the fourth interconnect layer 404 of the second storage module 207 is bonded to the third interconnect layer 403 of the other second storage module 207 adjacent to the other side.

[0064] In some embodiments, when one or more second storage modules 207 are removed and only the first storage module 203 remains, the first interconnect layer 401 of the first storage module 203 is bonded to the second interconnect layer 402 of the logic module 205.

[0065] In some embodiments, the first interconnect layer 401 includes an insulating layer and a conductive structure formed in the insulating layer; the second interconnect layer 402 includes an insulating layer and a conductive structure formed in the insulating layer; the third interconnect layer 403 includes an insulating layer and a conductive structure formed in the insulating layer; the fourth interconnect layer 404 includes an insulating layer and a conductive structure formed in the insulating layer. In some embodiments, the bonded connection means that the insulating layers at the interface of the two interconnect layers form a chemical bond, and the conductive structures at the interface of the two interconnect layers undergo physical interdiffusion, thereby forming a bonding interface between the interconnect layers.

[0066] The storage module stack structure further includes a plurality of Through Silicon Vias (TSVs). Specifically, the first storage module 203 includes a plurality of first silicon vias 405 penetrating the first substrate, and each second storage module 207 includes a plurality of second silicon vias 407 penetrating the third substrate. In some embodiments, forming the first silicon via includes forming a hole structure penetrating the first substrate and filling the hole structure with an insulating material and a conductive material; forming the second silicon via includes forming a hole structure penetrating the third substrate and filling the hole structure with an insulating material and a conductive material.

[0067] Through the conductive structures in the first to fourth interconnect layers and the first and second silicon vias, the logic module 205 forms a conductive connection with the first storage module 203 and one or more second storage modules 207, and forms a conductive path in the storage module stack structure, so that the logic module 205 can perform data interaction with the first storage module 203 and one or more second storage modules 207, and can connect to the power supply and ground through the storage module stack structure and perform signal interaction with the outside.

[0068] Figures 5A - 5H is a schematic diagram of a method for manufacturing a three-dimensional stacked chip according to an embodiment of the present invention, Figure 6 and is a flowchart of an exemplary method 600 for manufacturing a three-dimensional stacked chip. First, in combination with Figures 5A - 5C , the formation processes of the first storage structure, the logic module, and the second storage structure required for manufacturing the three-dimensional stacked chip will be described.

[0069] Forming the first storage structure includes: forming a first storage device and a first interconnect layer on a first substrate. As Figure 5A shown, a first storage device is formed on the first substrate 501, and then a first interconnect layer 503 is formed on the first storage device. The first interconnect layer 503 includes an insulating layer 505 and a plurality of conductive structures 507 formed in the insulating layer 505. Obviously, the surface where the first interconnect layer 503 is located is the front face of the first storage structure, and the surface opposite to the first interconnect layer 503 is the back face of the first storage structure. In some embodiments, in addition to the storage function, the first storage device can also implement a small amount of logic control functions.

[0070] Forming the logic module includes: forming a logic device and a second interconnect layer on a second substrate. As Figure 5B shown, a logic device is formed on the second substrate 509, and then a second interconnect layer 511 is formed on the logic device. The second interconnect layer 511 includes an insulating layer 513 and a plurality of conductive structures 515 formed in the insulating layer 513. Obviously, the surface where the second interconnect layer 511 is located is the front face of the logic module, and the surface opposite to the second interconnect layer 511 is the back face of the logic module. In some embodiments, the functions that the logic device can implement include one or more of arithmetic operation, control, interface, and data processing.

[0071] In a manner similar to that for forming the first storage structure, one or more (e.g., 3) second storage structures are formed. Specifically, a second storage device and a third interconnect layer are formed on a third substrate to form the second storage structure. As Figure 5C shown, a second storage device is formed on the third substrate 519, and then a third interconnect layer 521 is formed on the second storage device. The third interconnect layer 521 includes an insulating layer 523 and a plurality of conductive structures 525 formed in the insulating layer 523. Obviously, the surface where the third interconnect layer 521 is located is the front face of the second storage structure, and the surface opposite to the third interconnect layer 521 is the back face of the second storage structure. In some embodiments, in addition to the storage function, one or more second storage devices can also implement a small amount of logic control functions.

[0072] The exemplary method 600 begins at operation 601, as Figure 6As shown, invert the second storage structure, align the third interconnect layer and the second interconnect layer, and combine the second storage structure and the logic module, such that the second storage structure and the logic module form a conductive connection through the third interconnect layer and the second interconnect layer. As Figure 5D As shown, the second storage structure 526 and the logic module 527 are combined in a face-to-face manner to form a bonding interface 528. Specifically, forming the bonding interface 528 includes: causing the insulating layer 523 in the third interconnect layer 521 and the insulating layer 513 in the second interconnect layer 511 to form a chemical bond at the interface, and causing the conductive structure 525 in the third interconnect layer 521 and the conductive structure 515 in the second interconnect layer 511 to physically diffuse at the interface.

[0073] The example method 600 continues with operation 603, as Figure 6 As shown, thin the third substrate of the second storage structure, form a through-silicon via penetrating the thinned third substrate, form a fourth interconnect layer on the thinned third substrate, and form a second storage module. As Figure 5E As shown, thin the third substrate 519 of the second storage structure 526 to obtain a thinned substrate 529, form a through-silicon via 531 penetrating the substrate 529, further form a fourth interconnect layer 533 on the substrate 529, and then form a second storage module 534. The fourth interconnect layer 533 includes an insulating layer 535 and a plurality of conductive structures 537 formed in the insulating layer 535. Obviously, the surface where the fourth interconnect layer 533 is located is the back of the second storage module 534.

[0074] In some embodiments, the insulating layer in the first to fourth interconnect layers is one or more layers of insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the formation process of the conductive structures in the first to fourth interconnect layers includes: first forming an opening in the insulating layer, and then filling the required opening with a conductor material. In some embodiments, the conductor material for manufacturing the conductive structures includes but is not limited to tungsten, cobalt, copper, aluminum, doped silicon, silicide, or a combination of the above materials. In some embodiments, filling the opening with a conductor material can be performed using ALD, CVD, PVD, and / or other suitable methods.

[0075] The example method 600 continues with operation 605, as Figure 6 As shown, in a manner similar to operations 601 and 603, stack more second storage modules on the second storage module in sequence to obtain a first stacked structure including a logic module and a plurality of second storage modules. As Figure 5FAs shown, the second storage module 536 and the second storage module 538 are successively stacked on the second storage module 534. The second storage module 536 and the second storage module 534 are combined in a face-to-back manner to form a bonding interface 540. Specifically, the third interconnect layer 542 of the second storage module 536 is bonded to the fourth interconnect layer 533 of the second storage module 534. The second storage module 538 and the second storage module 536 are combined in a face-to-back manner to form a bonding interface 544. Specifically, the third interconnect layer 548 of the second storage module 538 is bonded to the fourth interconnect layer 546 of the second storage module 536. Similar to the second storage module 534, through-silicon vias 552 penetrating the substrate 550 are formed in the second storage module 536, and through-silicon vias 556 penetrating the substrate 554 are formed in the second storage module 538.

[0076] The exemplary method 600 continues with operation 607, as Figure 6 shown, the first storage structure is inverted, the first interconnect layer and the fourth interconnect layer are aligned, and the first storage structure and the second storage module are combined such that the first storage structure and the second storage module form an electrical connection through the first interconnect layer and the fourth interconnect layer. As Figure 5G shown, the first storage structure 558 and the second storage module 538 are combined in a face-to-back manner to form a bonding interface 560. Specifically, the first interconnect layer 503 of the first storage structure 558 is bonded to the fourth interconnect layer 562 of the second storage module 538.

[0077] The exemplary method 600 continues with operation 609, as Figure 6 shown, the first substrate of the first storage structure is thinned, through-silicon vias penetrating the thinned first substrate are formed, and then a first storage module is formed, obtaining a second stacked structure including a logic module, a plurality of second storage modules, and the first storage module. The second stacked structure is inverted, and an electrical connection is formed between the back surface of the first storage module and the substrate. As Figure 5H shown, the first substrate 501 of the first storage structure 558 is thinned to obtain a thinned substrate 560, through-silicon vias 562 penetrating the substrate 560 are formed, and then a first storage module 564 is formed. The entire stacked structure is inverted, and an electrical connection is formed between the back surface of the first storage module 564 and the substrate 566 through conductive bumps 568. The other side of the substrate 566 is further connected to a circuit board through conductive bumps.

[0078] In some embodiments, the first storage module further includes an interconnect layer formed on its back surface, and the first storage module forms an electrical connection with the substrate by means of this interconnect layer.

[0079] In some embodiments, an external circuit is further disposed on the substrate 566, and the external circuit forms an electrical connection with the first storage module 564 through a conductive structure in the substrate 566.

[0080] In some embodiments, a silicon interposer is introduced. The back surface of the first storage module 564 forms an electrical connection with the silicon interposer, the silicon interposer and the substrate form an electrical connection through conductive bumps, and the other side of the substrate is connected to a circuit board through conductive bumps. In some embodiments, an external circuit is further disposed on the silicon interposer, and the external circuit forms an electrical connection with the first storage module 564 through conductive structures in the silicon interposer and the substrate.

[0081] Furthermore, the back surface of the logic module 527 does not transmit electrical signals, so it is not necessary to thin the second substrate 509 of the logic module 527. Therefore, during the process of thinning the substrates of the first storage structure and the second storage structure, and during the process of connecting the first storage module 564 to the substrate or the silicon interposer, the second substrate 509 can provide sufficient support strength to avoid structural damage.

[0082] In some embodiments, a heat dissipation module is disposed on the back surface of the logic module 527, so that a large amount of heat generated by the logic module 527 during high-power operation can be easily dissipated. In some embodiments, the second substrate 509 of the logic module 527 is bonded to the heat dissipation module through a spacer layer with a good thermal conductivity coefficient.

[0083] In the above method, the step of forming one or more second storage structures can be omitted. Correspondingly, the first storage structure is inverted, and the first storage structure and the logic module are combined so that the first storage structure and the logic module form an electrical connection through the first interconnection layer and the second interconnection layer.

[0084] It should be noted that the above method for manufacturing the three-dimensional stacked chip is merely exemplary and should not be used to limit the present invention. The step content and / or order in the above method can be adjusted according to actual needs to obtain the same or similar technical effects. For example, the processes of forming the first storage structure and forming the logic module are independent of each other and there is no sequence requirement. In addition, the step of combining the second storage structure and the logic module can be performed after the manufacturing of the first storage structure is completed, or can be performed before the manufacturing of the first storage structure is completed.

[0085] In the present invention, a stacked structure of a storage module is disposed between a logic module and a substrate, such that the logic module is disposed above the stacked structure of the storage module, which provides great convenience for the heat dissipation of the logic module. The logic module is closer to the heat dissipation module than the stacked structure of the storage module, avoiding the influence of the heat generated by the logic module on the storage module and significantly improving the power consumption tolerance of the logic module. In addition, the logic module is connected to the power supply and ground and interacts with the outside world through the stacked structure of the storage module. Therefore, there is no need to thin the substrate forming the logic module, and the logic module can provide sufficient support strength throughout the process, saving an additional support structure and avoiding the occurrence of structural damage.

[0086] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0087] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0088] Any process or method description shown in the flowchart or described in other ways herein may be understood to represent a module, segment, or portion of code including one or more (two or more) executable instructions for implementing a specific logical function or process. And the scope of the preferred embodiments of the present application includes additional implementations, where the functions may be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed.

[0089] The logic and / or steps represented in the flowchart or described in other ways herein, for example, may be considered as a sequenced list of executable instructions for implementing a logical function and may be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in combination with these instruction execution systems, apparatus, or devices.

[0090] It should be understood that each part of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the method in the above embodiments can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0091] In addition, each functional unit in various embodiments of the present application can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium can be a read-only memory, a magnetic disk, an optical disc, etc.

[0092] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various changes or substitutions, and these should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A three-dimensional stacked chip, characterized in that: It includes a substrate, a first storage module and a logic module; the first storage module and the logic module are stacked on the substrate in sequence, and the first storage module is arranged between the logic module and the substrate; one side of the first storage module forms a conductive connection with the logic module, and the other side of the first storage module forms a conductive connection with the substrate, so that the logic module can exchange data with the first storage module, and exchange signals with the outside world through the first storage module and the substrate.

2. The three-dimensional stacked chip according to claim 1, characterized in that: It also includes one or more stacked second storage modules, which are arranged between the first storage module and the logic module to form a storage module stacking structure with the first storage module; one side of each of the second storage modules forms a conductive connection with the first storage module or other second storage modules adjacent to the same side, and the other side of each of the second storage modules forms a conductive connection with the logic module or other second storage modules adjacent to the same side, so that the logic module can exchange data with the first storage module and the one or more stacked second storage modules, and exchange signals with the outside world via the storage module stacking structure and the substrate.

3. The three-dimensional stacked chip according to claim 2, characterized in that: The logic module includes a plurality of stacked sub-logic modules, and adjacent surfaces of the plurality of stacked sub-logic modules form an electrically conductive connection.

4. The three-dimensional stacked chip according to claim 2, characterized in that: The logic module is connected to a power source via the memory module stacking structure, and is connected to a ground via a side opposite to the memory module stacking structure.

5. The three-dimensional stacked chip according to claim 2, characterized in that: The logic module is connected to the ground via the memory module stacking structure, and is connected to a power source via a side opposite to the memory module stacking structure.

6. The three-dimensional stacked chip according to claim 2, characterized in that: The logic module is connected to power and ground via a side opposite to the memory module stacking structure.

7. The three-dimensional stacked chip according to claim 2, characterized in that: The logic module is connected to power and ground via the storage module stacking structure.

8. The three-dimensional stacked chip according to claim 7, characterized in that: The first storage module includes a first substrate and a first interconnection layer arranged on one side of the first substrate, the logic module includes a second substrate and a second interconnection layer arranged on one side of the second substrate, and each of the second storage modules includes a third substrate and a third interconnection layer and a fourth interconnection layer respectively arranged on both sides of the third substrate; the first interconnection layer of the first storage module is bonded to the fourth interconnection layer of the adjacent second storage module, the second interconnection layer of the logic module is bonded to the third interconnection layer of the adjacent second storage module, the fourth interconnection layer of each of the second storage modules is bonded to the first interconnection layer of the first storage module adjacent to the same side or the third interconnection layer of other second storage modules, and the third interconnection layer of each of the second storage modules is bonded to the second interconnection layer of the logic module adjacent to the same side or the fourth interconnection layer of other second storage modules.

9. The three-dimensional stacked chip according to claim 8, characterized in that: The first storage module includes a plurality of first through silicon vias penetrating the first substrate, and each of the second storage modules includes a plurality of second through silicon vias penetrating the third substrate; the first interconnection layer, the second interconnection layer, the third interconnection layer and the fourth interconnection layer all include an insulating layer and a conductive structure formed in the insulating layer; through the conductive structure and the first through silicon vias and the second through silicon vias, the logic module forms a conductive connection with the first storage module and the one or more second storage modules, and forms a conductive path in the storage module stacking structure.

10. The three-dimensional stacked chip according to any one of claims 1 to 9, characterized in that: It also includes a heat dissipation module, which is arranged on the logic module.

11. The three-dimensional stacked chip according to any one of claims 1 to 9, characterized in that: It also includes an external circuit, which is arranged on the substrate, and the other side of the first storage module is conductively connected to the external circuit through the substrate.

12. The three-dimensional stacked chip according to any one of claims 1 to 9, characterized in that: It also includes a silicon interposer and an external circuit, wherein the silicon interposer is arranged between the first storage module and the substrate, the external circuit is arranged on the silicon interposer, and the other side of the first storage module forms a conductive connection with the external circuit through the silicon interposer and the substrate.

13. A method for manufacturing a three-dimensional stacked chip, characterized in that: include: forming a first storage structure; Forming logical modules; forming a plurality of second storage structures; Using a logic module and a plurality of second storage structures to form a first stacking structure, wherein the first stacking structure includes a logic module and a plurality of second storage modules sequentially stacked on the logic module, and the second storage modules are obtained by processing the second storage structures; Using the first storage structure and the first stacking structure to form a second stacking structure, wherein the second stacking structure includes a logic module and a plurality of second storage modules and the first storage module stacked sequentially on the logic module, and the first storage module is obtained by processing the first storage structure; The second stacking structure is inverted to connect the first storage module to the substrate.

14. The method for manufacturing a three-dimensional stacked chip according to claim 13, characterized in that: Forming a first storage structure includes: forming a first storage device and a first interconnection layer on a first substrate; forming a logic module includes: forming a logic device and a second interconnection layer on a second substrate; forming a second storage structure includes: forming a second storage device and a third interconnection layer on a third substrate.

15. The method for manufacturing a three-dimensional stacked chip according to claim 14, characterized in that: Forming a first stacking structure includes: combining the second storage structure and the logic module; Processing the combined second storage structure to obtain a second storage module; The next second storage structure is combined with the second storage module, and the combined next second storage structure is processed to obtain the next second storage module.

16. The method for manufacturing a three-dimensional stacked chip according to claim 15, characterized in that: Combining the second storage structure and the logic module includes: inverting the second storage structure to align the third interconnect layer with the second interconnect layer; The second storage structure and the logic module are combined so that the second storage structure and the logic module form a conductive connection through the third interconnect layer and the second interconnect layer.

17. The method for manufacturing a three-dimensional stacked chip according to claim 16, wherein: The combined second storage structure is processed to obtain a second storage module including: Thinning the third substrate of the second storage structure to form a through silicon via penetrating the thinned third substrate; A fourth interconnection layer is formed on the thinned third substrate.

18. The method for manufacturing a three-dimensional stacked chip according to claim 17, characterized in that: Forming a second stacking structure includes: combining a first storage structure and a second storage module; The combined first storage structure is processed to obtain a first storage module.

19. The method for manufacturing a three-dimensional stacked chip according to claim 18, characterized in that: Processing the combined first storage structure to obtain the first storage module includes: thinning the first substrate of the first storage structure to form a through silicon via penetrating the thinned first substrate.

20. The method for manufacturing a three-dimensional stacked chip according to any one of claims 13 to 19, characterized in that: Also includes: A heat dissipation module is provided on the logic module.

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