Groove type silicon carbide MOSFET device and construction method

Abstract

The invention relates to the technical field of semiconductor devices, and provides a groove type silicon carbide MOSFET device and a construction method. The device comprises a substrate, an epitaxial layer and a grid electrode. The epitaxial layer comprises a bottom screen junction and a side screen junction, and the bottom of the side screen junction is connected with the bottom screen junction in a staggered mode to form grid staggering. The epitaxial layer is provided with a groove, the connecting position of the side wall and the bottom of the groove is in an arc shape, the bottom of the groove is sunken in the bottom screen junction, and the groove is located between the side screen junctions. Through a three-dimensional grid shielding system formed by the bottom screen junction and the side screen junction, surrounding type shielding can be formed on the gate region below the bottom and the side wall of the groove, the peak electric field intensity borne by the gate oxide layer under high voltage is dispersed and reduced to the maximum extent, and the voltage endurance capability and the gate oxide reliability of the device are remarkably improved.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and in particular, to a trench-type silicon carbide metal oxide semiconductor field effect transistor (MOSFET) device and a fabrication method thereof. Background Art

[0002] Silicon carbide (SiC) materials have been widely used in the field of power electronics, especially in high-voltage devices, due to their excellent high-temperature, high-frequency, and high-power characteristics. As one of the core devices, MOSFETs have attracted much attention due to their high switching speed and low on-resistance. Currently, SiC MOSFETs are mainly divided into planar-gate and trench-gate structures. The planar-gate structure has a simple process and high reliability, but there is a junction field-effect transistor (JFET) effect, resulting in a relatively large on-resistance; the trench-gate structure eliminates the region with JFET effect through a vertical channel, significantly improving the channel mobility and reducing the on-resistance, but the problem of concentrated gate oxide electric field at the bottom of the trench seriously affects the reliability of the device.

[0003] To solve the above problems, the industry usually adopts various means to optimize the performance of trench-type MOSFETs. For example, improving the gate oxide growth process to improve the quality of the gate oxide, or introducing a specific doping region on the sidewall of the trench to improve the electric field distribution. In addition, it also includes optimizing the trench geometry, such as adjusting the sidewall angle or adopting a round-bottom design, and introducing P+ implantation in the source region and other methods to alleviate the problem of electric field concentration. Although these methods can improve the device performance to a certain extent, there are still certain limitations.

[0004] Specifically, it is difficult for the conventional means in the related art to simultaneously achieve the goals of reducing the electric field concentration at the bottom of the trench and optimizing the on-resistance. Especially when the gate oxide electric field at the bottom of the trench is too high, the long-term reliability of the device is seriously threatened, which further limits its further promotion in high-voltage and high-temperature application scenarios. Summary of the Invention

[0005] In order to more effectively reduce the electric field concentration at the bottom of the trench and optimize the on-resistance, this application provides a trench-type silicon carbide MOSFET device and a fabrication method thereof.

[0006] On the one hand, this application provides a trench-type silicon carbide MOSFET device, adopting the following technical solution: A trench-type silicon carbide MOSFET device includes: A substrate with an epitaxial layer, the epitaxial layer including an interlaced bottom screen junction and side screen junction formed by an implantation process, the bottom screen junction sinking below the upper surface of the epitaxial layer, the sinking depth of the bottom screen junction starting from the epitaxial layer being greater than the depth of the trench; the side screen junction being continuously formed in the epitaxial layer, the side screen junction extending to the upper surface of the epitaxial layer, the bottom of the side screen junction intersecting with the bottom screen junction in an interlaced manner to form a grid interlace; the epitaxial layer being provided with a trench, the connection between the side wall and the bottom of the trench being arc-shaped, the bottom of the trench being recessed below the bottom screen junction, and the trench being located between the side screen junctions. A gate, disposed within the trench.

[0007] Adopting the above technical solution, the three-dimensional grid shielding system formed by the bottom screen junction and side screen junction formed by the implantation process can form an enclosed shielding for the gate region under the bottom and side walls of the trench, maximizing the dispersion and reduction of the peak electric field intensity borne by the gate oxide layer under high voltage, and significantly improving the breakdown voltage capability and gate oxide reliability of the device. And by making the connection between the side wall and the bottom be arc-shaped, the existence of sharp corners is avoided, which helps to make the electric field distribution in the trench bottom corner region more gentle, further reducing the electric field concentration in this region, and jointly enhancing the reliability of the gate oxide layer with the screen junction structure.

[0008] Optionally, the substrate and the epitaxial layer have a first type of impurity, and the bottom screen junction and the side screen junction have a second type of impurity, wherein the first type of impurity and the second type of impurity have opposite polarities.

[0009] Adopting the above technical solution, the semiconductor doping type configuration necessary for the operation of the device is clarified, enabling the PN junction formed by the bottom screen junction and side screen junction (second type of impurity, such as P-type) and the epitaxial layer (first type of impurity, such as N-type) to generate a depletion layer under reverse bias, thereby effectively modulating the electric field distribution in the epitaxial layer and realizing the electric field shielding function for the trench region.

[0010] Optionally, the epitaxial layer further includes: A body layer, located within the epitaxial layer, the body layer having a second type of impurity; An epitaxial bottom layer, located below the body layer and the bottom screen junction; A first doping layer, located on the body layer, the first doping layer having a first type of impurity; A second doping layer, located on the first doping layer, the second doping layer having a first type of impurity, wherein the doping concentration of the second doping layer is higher than that of the first doping layer; Wherein, the body layer, the first doping layer and the second doping layer fill the gap between the side screen junction and the gate.

[0011] With the above technical solution, a vertical MOSFET active structure including a body layer, a first doped layer (such as an N-drift / source extension), and a second doped layer (N+ source) is constructed within the region defined by the side screen junction, ensuring the on-function of the device and placing the active region within the protection of the side screen junction, which helps to form a clearly defined conduction path while achieving the shielding effect.

[0012] Optionally, the trench-type silicon carbide MOSFET device further includes: An interlayer dielectric layer located above the gate, the second doped layer, and the side screen junction, wherein the interlayer dielectric layer has contact holes that expose a part of the surface of the second doped layer around the side screen junction; A metal silicide layer located on the side screen junction and a part of the surface of the second doped layer at the contact holes; A metal conductive layer located on the interlayer dielectric layer and the metal silicide layer; A passivation layer located on the metal conductive layer; A buffer protection layer located on the passivation layer; A metal backplane connected to the back surface of the substrate through an ohmic contact layer.

[0013] With the above technical solution, by setting up structures such as an interlayer dielectric layer, contact holes, a metal silicide layer, a metal conductive layer, a passivation layer, a buffer protection layer, as well as back ohmic contacts and a metal backplane, the electrode lead-out, interlayer isolation, surface protection, and back connection of the device are completed. Among them, the metal silicide layer reduces the source contact resistance, the passivation layer and the buffer protection layer improve the environmental tolerance and mechanical reliability of the device, and the back low-resistance contact and metallization structure ensure an efficient drain current path and heat dissipation, thus constituting a complete, reliable, and easy-to-package power device.

[0014] Optionally, the gate is filled in the trench, and there is a gate oxide layer between the inner wall of the trench and the gate.

[0015] With the above technical solution, setting the gate oxide layer provides necessary electrical insulation between the gate and the inner wall of the trench, enabling the gate to control the formation and turn-off of the surface channel of the body layer through the electric field effect across the insulating layer, which is the core structure for realizing the switching function of the MOSFET.

[0016] On the other hand, a method for constructing a trench-type silicon carbide MOSFET device is provided, including: Providing a substrate with an epitaxial layer, on the upper surface of which a trench region, a side screen region parallel to each other, and a bottom screen region staggered with the trench region are defined; Align with the bottom screen area, and form a bottom screen junction in the epitaxial layer in a sinking manner. The bottom screen junction sinks below the upper surface of the epitaxial layer, and the sinking depth is greater than the trench depth. Align with the side screen area, and form a side screen junction in the epitaxial layer in a longitudinally continuous extension manner. The side screen junction continuously extends to the upper surface of the epitaxial layer. The bottom of the side screen junction intersects with the bottom screen junction in a staggered manner to form a grid intersection. Align with the trench area, and open a trench in the epitaxial layer. An arc shape is formed at the connection of the side wall and the bottom of the trench. The bottom of the trench is recessed below the bottom screen junction, and the trench is located between the side screen junctions. Set a gate in the trench.

[0017] Adopting the above technical solution, by precisely defining the bottom screen area, the side screen area and the trench area, and processing in a specific order (first forming a grid of staggered deep bottom screen junctions and side screen junctions, and then opening trenches therein), a trench-type silicon carbide MOSFET with a three-dimensional grid shielding structure can be reliably manufactured, ensuring the precise relative position between the shielding structure and the trench, thereby realizing the high-reliability advantages brought by the device structure.

[0018] Optionally, a main body area parallel to the side screen area is further defined on the upper surface of the epitaxial layer, and the trench area is located in the main body area. Among them, before opening the trench, align with the main body area, and sequentially form a body layer and a first doping layer in the epitaxial layer in a sinking manner, and form a second doping layer in the epitaxial layer in a longitudinally continuous extension manner. The body layer sinks below the upper surface of the epitaxial layer. The lower surface of the body layer is flush with the upper surface of the bottom screen junction. The lower surface of the first doping layer is flush with the upper surface of the body layer. The lower surface of the second doping layer is flush with the upper surface of the first doping layer, and the second doping layer extends to the upper surface of the epitaxial layer.

[0019] Adopting the above technical solution, before the trench is formed, by pre-forming a body layer, a first doping layer and a second doping layer with clear structures and precise positions in the main body area, the difficulty of manufacturing a complex active area in a narrow space after the subsequent trench is formed is simplified, which helps to improve the consistency and controllability of the device structure parameters and ensures the stability of the device performance.

[0020] Optionally, align with the bottom screen area, and inject a second type of impurity through an ion implantation process to form a bottom screen junction. The ion implantation process includes a channel implantation process or a high-energy implantation process. Align with the side screen area, and inject a second type of impurity through an ion implantation process to form a side screen junction. Align with the main body area, and inject a second type of impurity through an ion implantation process to form a body layer. Align with the main body region, and inject impurities of the first type through an ion implantation process or a diffusion process to sequentially form a first doped layer and a second doped layer; Activate the impurities of the first type and the impurities of the second type through a heat treatment process.

[0021] Adopting the above technical solution, using mature and controllable semiconductor manufacturing technologies such as ion implantation, diffusion, and heat treatment activation, various required doped regions (screen junctions, body layers, doped layers) can be precisely formed, ensuring the designability and repeatability of the device structure parameters. In particular, high-energy implantation or channel implantation can effectively form a deeply buried bottom screen junction, and the heat activation step is the key to ensuring the function of the dopant and repairing implantation damage, thus ensuring the normal electrical function of the device.

[0022] Optionally, when aligning with the bottom screen region and injecting impurities of the second type through an ion implantation process to form a bottom screen junction, also align with the side screen region and inject impurities of the second type within a first depth range; When aligning with the side screen region and injecting impurities of the second type through an ion implantation process to form a side screen junction, inject impurities of the second type at a depth outside the first depth range; Alternatively, when aligning with the bottom screen region and injecting impurities of the second type through an ion implantation process to form a bottom screen junction, also align with the side screen region and inject impurities of the second type within a second depth range, where the depth of the second depth range is greater than the depth of the first depth range; When aligning with the side screen region and injecting impurities of the second type through an ion implantation process to form a side screen junction, inject impurities of the second type at a depth outside the second depth range.

[0023] Adopting the above technical solution, a process integration method combining bottom screen junction implantation with partial implantation (shallow or deep) of the side screen junction is proposed. By simultaneously performing partial doping of multiple regions using a mask in the same step, the number of ion implantation times can be effectively reduced, thereby simplifying the manufacturing process, reducing process complexity and production costs, and improving production efficiency.

[0024] Optionally, the method further includes: Form an interlayer dielectric layer on the gate, the second doped layer, and the side screen junction; Form a contact hole in the interlayer dielectric layer to expose at least a part of the second doped layer located around the side screen junction; Form a metal silicide layer at the contact hole; Successively form a metal conductive layer, a passivation layer, and a buffer protection layer on the interlayer dielectric layer and the metal silicide layer; Thin the substrate, and successively form an ohmic contact layer and a metal backplane on the back surface of the substrate.

[0025] By adopting the above technical solution, the backend manufacturing process of the device is completed through steps of depositing interlayer dielectric, etching contact holes, forming silicide, depositing and patterning metal, depositing a protective layer, and processing the back surface, achieving effective electrical connection and necessary protection for the internal device units, forming a complete external electrode, and finally obtaining a trench-type silicon carbide MOSFET chip with perfect functions, reliable performance, and suitable for packaging and application.

[0026] In summary, the present application includes at least one of the following beneficial technical effects: 1. Through the three-dimensional grid shielding system formed by the bottom screen junction and the side screen structure, it is possible to form an encircling shield for the gate region under the bottom and side walls of the trench, maximizing the dispersion and reduction of the peak electric field intensity borne by the gate oxide layer under high voltage, significantly improving the breakdown voltage and gate oxide reliability of the device. And by making the connection between the side wall and the bottom in an arc shape, the existence of sharp corners is avoided, which helps to make the electric field distribution in the trench bottom corner region smoother, further reducing the electric field concentration in this region, and jointly enhancing the reliability of the gate oxide layer with the screen junction structure; 2. By precisely defining the bottom screen region, side screen region, and trench region and processing them in a specific order (first forming an interlaced grid of deep bottom screen junctions and side screen junctions, and then opening trenches therein), it is possible to reliably manufacture a trench-type silicon carbide MOSFET with a three-dimensional grid shielding structure, ensuring the precise relative position between the shielding structure and the trench, thereby realizing the high-reliability advantage brought by the device structure; 3. A process integration method of combining the bottom screen junction implantation with partial implantation (shallow or deep) of the side screen junction is proposed. By simultaneously completing the partial doping of multiple regions using a mask in the same step, the number of ion implantations can be effectively reduced, thereby simplifying the manufacturing process, reducing the process complexity and production cost, and improving the production efficiency. Description of the Drawings

[0027] Figure 1 is a schematic structural diagram of a planar-type silicon carbide MOSFET device in the related art; Figure 2 is a schematic structural diagram of a trench-type silicon carbide MOSFET device in the related art; Figure 3 is Figure 2 the electric field schematic diagram of the trench-type silicon carbide MOSFET device in Figure 4 is a schematic structural diagram of another trench-type silicon carbide MOSFET device in the related art; Figure 5 is a schematic diagram of the surface of the epitaxial layer of the trench-type silicon carbide MOSFET device in Embodiment 1 of the present application; Figure 6 is a cross-sectional view of the trench-type silicon carbide MOSFET device according to an embodiment of the present application, where Figure 6 a is a cross-sectional view along Figure 5 the A-A line in Figure 6 b is a cross-sectional view along Figure 5 the B-B line in Figure 6 c is a cross-sectional view along Figure 5 the C-C line in; Figure 7 is a schematic flow chart of the manufacturing method of the trench-type silicon carbide MOSFET device according to Embodiment 2 of the present application; Figure 8 is a cross-sectional view of the structure after performing Figure 7 the step S1 in, where Figure 8 a is a cross-sectional view along Figure 5 the A-A line in Figure 8 b is a cross-sectional view along Figure 5 the B-B line in; Figure 9 is a cross-sectional view of the structure after performing Figure 7 the step S2 of, where Figure 9 a is a cross-sectional view along Figure 5 the A-A line in Figure 9 b is a cross-sectional view along Figure 5 the C-C line in; Figure 10 is a cross-sectional view of the structure along the C-C line after performing Figure 7 the step S3 of Figure 5 in; Figure 11 is a cross-sectional view of the structure along the C-C line after performing Figure 7 the step S4 of Figure 5 in; Figure 12 is a cross-sectional view of the structure after performing Figure 7 the step S5 of, where Figure 12 a is a cross-sectional view along Figure 5 the A-A line in Figure 12 b is a cross-sectional view along Figure 5 the B-B line in Figure 12 c is a cross-sectional view along Figure 5 the C-C line in; Figure 13 is a cross-sectional view of the structure along the C-C line after performing Figure 7 the step S6 of Figure 5 in; Figure 14 is a cross-sectional view of the structure along the C-C line after performing Figure 7 the step S7 of Figure 5 in; Figure 15It is the cross-sectional view along the C-C line of the structure after step S8 of executing Figure 7 ; Figure 5 The cross-sectional view along the C-C line of the structure after step S9 of executing Figure 16 It is the cross-sectional view along the C-C line of the structure after step S10 of executing Figure 7 ; Figure 5 The cross-sectional view along the C-C line of the structure after step 11 of executing Figure 17 It is the cross-sectional view along the C-C line of the structure after step S10 of executing Figure 7 ; Figure 5 The cross-sectional view along the C-C line of the structure after step 11 of executing Figure 18 It is the cross-sectional view along the C-C line of the structure after step S10 of executing Figure 7 ; Figure 5 The cross-sectional view along the C-C line of the structure after step 11 of executing Figure 19 It is the schematic flow chart of the manufacturing method of the trench-type silicon carbide MOSFET device according to Embodiment 3 of the present application; Figure 20 It is the cross-sectional view of the structure after step S1 of executing Figure 19 ; wherein Figure 20 a is the cross-sectional view along the A-A line of Figure 5 ; Figure 20 b is the cross-sectional view along the B-B line of Figure 5 ; Figure 20 c is the cross-sectional view along the D-D line of Figure 5 ; Figure 21 It is the cross-sectional view of the structure after step S2 of executing Figure 19 ; wherein Figure 21 a is the cross-sectional view along the A-A line of Figure 5 ; Figure 21 b is the cross-sectional view along the C-C line of Figure 5 ; Figure 22 It is the schematic flow chart of the manufacturing method of the trench-type silicon carbide MOSFET device according to Embodiment 4 of the present application; Figure 23 It is the cross-sectional view of the structure after step S1 of executing Figure 22 ; wherein Figure 23 a is the cross-sectional view along the A-A line of Figure 5 ; Figure 23 b is the cross-sectional view along the B-B line of Figure 5 ; Figure 23 c is the cross-sectional view along the D-D line of Figure 23 a; Figure 24 It is the cross-sectional view of the structure after step S2 of executing Figure 22 ; Figure 24 a is the cross-sectional view along the A-A line of Figure 5 ; Figure 24b is a cross-sectional view along the Figure 5 C-C line of Figure 5 .

[0028] Description of reference numerals: 110, Drain; 120, N-type substrate; 130, N-type drift region; 131, JEFT region; 140, P-type base region; 141, channel; 150, gate; 160, source; 170, N-type doped region of source region; 180, trench; 190, P-type shielding region of source region; 10, substrate; 20, epitaxial layer; 20a, main body region; 20b, side shielding region; 20c, trench region; 20d, bottom shielding region; 21, bottom epitaxial layer; 22, bottom shielding junction; 23, side shielding junction; 23a, first depth range; 23b, second depth range; 24, body layer; 25, first doped layer; 26, second doped layer; 27, trench; 30, gate; 31, gate oxide layer; 40, interlayer dielectric layer; 41, contact hole; 50, metal silicide layer; 61, metal conductive layer; 62, passivation layer; 63, buffer protection layer; 64, metal backplane; 70, mask; 71, mask opening; 80, protection layer. Detailed description of the specific implementation

[0029] The following is combined with Figure 1 - Figure 24 to further elaborate on this application in detail.

[0030] Figure 1 is a schematic structural diagram of a planar silicon carbide MOSFET device in the related art. Referring to Figure 1 , this planar silicon carbide MOSFET device includes: Drain 110, N-type substrate (N+ Substrate) 120, N-type drift region (N-Drift Region) 130, P-type base region (P-Base) 140, Gate 150, Source 160, and N-type doped region of source region (N+) 170.

[0031] The gate 150 is located on the N-type drift region 130 and the P-type base region 140, and a channel (Channel) 141 is formed at the P-type base region 140 below the gate 150. When an appropriate voltage is applied to the gate 150, the channel 141 forms a conductive path, allowing electrons to flow from the source 160 to the N-type drift region 130 and finally to the drain 110.

[0032] However, a JEFT region 131 is formed at the N-type drift region 130 of the two P-type base regions 140, and the current flowing from the channel 141 to the drain 110 will pass through the JEFT region 131. Since the depletion layers formed by the P-type base regions 140 on both sides of the JEFT region 131 will expand towards the JEFT region 131, a pinch-off effect similar to that of a junction field-effect transistor (JFET) will be generated on the current path of the JEFT region 131, thereby increasing the on-resistance of the device.

[0033] Figure 2 is a schematic structural diagram of a trench-type silicon carbide MOSFET device in the related art. Refer to Figure 2 This trench-type silicon carbide MOSFET device includes: a drain 110, an N-type substrate 120, an N-type drift region 130, a P-type base region 140, a gate 150, a source 160, a source region N-type doping region 170, and a trench 180, wherein the main body of the gate 150 is located in the trench 180.

[0034] Compared with Figure 1 the planar-type silicon carbide MOSFET device in, the channel 141 of this trench-type silicon carbide MOSFET device is formed near the side wall of the trench 180. When an appropriate voltage is applied to the gate 150, a conductive path is formed along the side wall of the trench 180 in the P-type base region 140, and electrons flow from the source 160 to the N-type drift region 130 through this conductive path and finally flow to the drain 110. Since the current directly enters the underlying N-type drift region 130 from the trench 180, the JFET effect in the planar-type silicon carbide MOSFET device can be basically eliminated, which helps to achieve a lower on-resistance.

[0035] However, the trench-type silicon carbide MOSFET device also brings other problems. Figure 3 is Figure 2 a schematic diagram of the electric field of the trench-type silicon carbide MOSFET device in. Refer to Figure 3 At this time, the electric field at the bottom and corners of the trench 180 is prone to concentration, which will affect the reliability of the gate oxide.

[0036] Figure 4 is a schematic structural diagram of another trench-type silicon carbide MOSFET device in the related art. Refer to Figure 4 This trench-type silicon carbide MOSFET device includes a drain 110, an N-type substrate 120, an N-type drift region 130, a P-type base region 140, a gate 150, a source 160, a source region N-type doping region 170, a trench 180, and a source region P-type shielding region 190, wherein the source region P-type shielding region 190 is located on the side of the trench 180.

[0037] Compared to Figure 2 The trench-type silicon carbide MOSFET device in the present invention is also provided with a source region P-type shielding region 190 located on the side of the trench 180. The source region P-type shielding region 190 can play a shielding role on the side of the trench 180. By expanding the depletion layer and adjusting the electric field distribution, the electric field concentration at the bottom and corners of the trench 180 can be reduced, thereby improving the reliability of the gate oxide.

[0038] However, the source region P-type shielding region 190 is mainly located on the side of the trench 180. Although they can indirectly alleviate the bottom electric field by affecting the electric field distribution, they are not the most effective for electric field shielding in the area directly below the trench 180, and the highest electric field peak often appears at the bottom corner of the trench 180.

[0039] In response to the above-mentioned problems in the related art, on the one hand, an embodiment of the present application discloses a trench silicon carbide MOSFET device.

[0040] Example 1 Figure 5 It is a surface schematic diagram of the epitaxial layer of the trench silicon carbide MOSFET device of Example 1 of the present application. Figure 6 is a cross-sectional view of a trench silicon carbide MOSFET device according to Embodiment 1 of the present application, wherein: Figure 6 a is along Figure 5 The cross-sectional view along the AA line. Figure 6 b is along Figure 5 The cross-sectional view of the BB line. Figure 6 c is along Figure 5 Sectional view of the CC line. Figure 6 The trench silicon carbide MOSFET device includes a substrate (Substrate) 10, an epitaxial layer (Epi) 20, a gate (Poly) 30, an interlayer dielectric layer (Inter-Layer Dielectric, ILD) 40, a metal silicide layer (Silicide) 50, a metal conductive layer 61, a passivation layer 62, a buffer protection layer 63, an ohmic contact layer (not shown in the figure) and a metal back plate 64, wherein the epitaxial layer 20 includes an epitaxial bottom layer 21, a bottom screen junction (P+) 22, a side screen junction (Source P+) 23, a body layer (P Body) 24, a first doped layer (N-) 25 and a second doped region (N+) 26, and the epitaxial layer 20 is provided with a trench (Trench) 27.

[0041] The epitaxial layer 20 is located on the substrate 10, and the material of the epitaxial layer 20 includes but is not limited to SiC. The doping types of the substrate 10 and the epitaxial layer 20 can be N-type or P-type. In this embodiment, the epitaxial layer 20 is taken as an example of N-type for illustration. It is easy to understand that when the epitaxial layer 20 is P-type, all corresponding doping types need to be changed to the opposite types.

[0042] The epitaxial bottom layer 21 is located under the bottom screen junction 22 and the body layer 24.

[0043] The bottom screen junction 22 sinks below the upper surface of the epitaxial layer 20, and the sinking depth of the bottom screen junction 22 starting from the epitaxial layer 20 is greater than the depth of the trench 27; the side screen junction 23 is continuously formed in the epitaxial layer 20, the side screen junction 23 extends to the upper surface of the epitaxial layer 20, and the bottom of the side screen junction 23 intersects with the bottom screen junction 22 in a staggered manner to form a grid stagger. The bottom screen junction 22 and the side screen junction 23 have P-type impurities.

[0044] The epitaxial layer 20 is provided with a trench 27, the bottom of the trench 27 is recessed below the bottom screen junction 22, and the trench 27 is located between the side screen junctions 23.

[0045] The trench 27 is filled with polysilicon to form a gate 30, and there is a gate oxide layer (Gate Oxide, GOX) 12 between the gate 30 and the inner wall of the trench 27.

[0046] The bottom surface of the trench 27 can be a plane or a curved surface. The inclination angle between the side wall of the trench 27 and the trench 27 is 80 - 91°. Preferably, the inclination angle between the side wall of the trench 27 and the trench 27 is 86°. The connecting part between the bottom surface of the trench 27 and the side wall of the trench 27 can be arc-shaped.

[0047] The body layer 24 is located in the epitaxial layer 20 and has P-type impurities. The first doped layer 25 is located on the body layer 24 and has N-type impurities. The second doped layer 26, located on the first doped layer 25, has N-type impurities, and finally forms an N+N-P type structure. Among them, the doping concentration of the second doped layer 26 is higher than that of the first doped layer 25.

[0048] Among them, the body layer 24, the first doped layer 25 and the second doped layer 26 are filled in the gap between the side screen junction 23 and the gate 30.

[0049] The interlayer dielectric layer 40 covers the gate 30, the second doped layer 26 and the side screen junction 23. The material of the interlayer dielectric layer 40 can be silicon dioxide (SiO2) and / or silicon nitride (SiN).

[0050] A contact hole (CONT) 41 is formed on the interlayer dielectric layer 40 to expose at least a part of the second doped layer 26 around the side screen junction 23. The metal silicide layer 50 is located on the surface of at least a part of the side screen junction 23 and the second doped layer 26 at the contact hole 41.

[0051] The metal conductive layer 61 is located on the metal silicide layer 50 and the interlayer dielectric layer 40, forming the source electrode of the trench-type silicon carbide MOSFET device. The material of the metal conductive layer 61 can be Al, Cu, Al / Cu alloy (such as AlSi alloy, AlCu alloy, and AlSiCu alloy), or a laminated combination of the above materials.

[0052] The passivation layer 62 is located on the metal conductive layer 61. The material of the passivation layer 62 can be silicon dioxide (SiO2), silicon nitride (SiN), or a combination of them. The thickness of the passivation layer 62 can be 0.1 - 20 um.

[0053] The buffer protection layer 63 is located on the passivation layer 62. The material of the buffer protection layer 63 can be polyimide (PI), polyamide, polybenzoxazole (PBO), or a combination of them. The thickness of the buffer protection layer 63 can be 1 - 50 um, preferably 10 - 15 um.

[0054] The thickness of the substrate 10 is 80 - 250 um, preferably 150 - 200 um.

[0055] The metal backplane 64 is connected to the substrate through an ohmic contact layer, forming the drain electrode of the trench-type silicon carbide MOSFET device. The material of the metal backplane 64 can be Ti, Ni, Ag, Pd, Au, and their alloys or combinations.

[0056] The implementation principle of Embodiment 1 of this application is as follows: Through the three-dimensional grid shielding system composed of the bottom screen junction and the side screen junction, an enclosed shielding can be formed for the gate region at the bottom of the trench and below the sidewall, dispersing and reducing the peak electric field intensity borne by the gate oxide layer under high voltage to the greatest extent, and significantly improving the breakdown voltage and gate oxide reliability of the device.

[0057] On the other hand, this application embodiment also discloses a method for constructing a trench-type silicon carbide MOSFET device.

[0058] Embodiment 2 Figure 7 is a schematic flow chart of the construction method of the trench-type silicon carbide MOSFET device in Embodiment 2 of this application. Refer toFigure 7 , the method comprising: S1. Provide a substrate 10 having an epitaxial layer 20, wherein the upper surface of the epitaxial layer 20 is defined with a main region 20a and a side screen region 20b parallel to each other, a groove region 20c located in the main region 20a and parallel to the side screen region 20b, and a bottom screen region 20d interlaced with the groove region 20c, and inject P-type impurities into the bottom screen region 20d to form a bottom screen junction 22 in the epitaxial layer 20 in a deposition manner, and the bottom screen junction 22 sinks to the upper surface of the epitaxial layer 20, and the sinking depth is greater than the groove depth.

[0059] S2. Inject P-type impurities into the side screen area 20b to form a side screen junction 23 in the epitaxial layer 20 in a longitudinally continuous extension manner. The side screen junction 23 extends continuously to the upper surface of the epitaxial layer 20. The bottom of the side screen junction 23 is staggered with the bottom screen junction 22 to form a grid staggered.

[0060] S3. Align the main region 20a with the injection of P-type impurities to form a body layer 24 in the epitaxial layer 20 by deposition. The body layer 24 is sunk to the upper surface of the epitaxial layer 20 , and the lower surface of the body layer 24 is flush with the upper surface of the bottom screen junction 22 .

[0061] S4. N-type impurities are injected into the main region 20a to sequentially form a first doping layer 25 and a second doping layer 26, wherein the lower surface of the first doping layer 25 is flush with the upper surface of the body layer 24, the lower surface of the second doping layer 26 is flush with the upper surface of the first doping layer 25, and the second doping layer 26 extends to the upper surface of the epitaxial layer 20, wherein the doping concentration of the first doping layer 25 is lower than the doping concentration of the second doping layer 26.

[0062] S5. Align the groove area 20c and open a groove 27 in the epitaxial layer 20, wherein an arc shape is formed at the connection between the side wall and the bottom of the groove 27, the bottom of the groove 27 is recessed in the bottom screen junction 22, and the groove 27 is located between the side screen junctions 23.

[0063] S6. Activate the implanted N-type impurities and P-type impurities through a high temperature annealing process.

[0064] S7 . Form a gate oxide layer 31 on the inner wall of the trench 27 .

[0065] S8 , filling the trench 27 with polysilicon to form a gate 30 .

[0066] S9. Form an interlayer dielectric layer 40 on the surface of the wafer.

[0067] S10. Form a contact hole 41 in the interlayer dielectric layer 40 to expose at least a part of the second doped layer 26 around the side screen junction 23.

[0068] S11. Form a metal silicide layer 50 at the contact hole 41.

[0069] S12. Sequentially form a metal conductive layer 61, a passivation layer 62, and a buffer protection layer 63 on the wafer, thin the substrate 10, and sequentially form an ohmic contact layer and a metal backplane 64 on the back surface of the substrate 10.

[0070] The following specifically describes each step of the method.

[0071] Figure 8 is the cross-sectional view of the structure after performing Figure 7 step S1, where Figure 8 a is the cross-sectional view along the Figure 5 A-A line in Figure 8 b is the cross-sectional view along the Figure 5 B-B line in Figure 8 . Referring to Figure 8 , in step S1, a substrate 10 with an epitaxial layer 20 is provided. The upper surface of the epitaxial layer 20 is defined with a main body region 20a and a side screen region 20b that are parallel to each other, a trench region 20c located in the main body region 20a and parallel to the side screen region 20b, and a bottom screen region 20d that intersects with the trench region 20c. P-type impurities are implanted by aligning with the bottom screen region 20d, and a bottom screen junction 22 is formed in the epitaxial layer 20 in a deposition manner. The bottom screen junction 22 sinks below the upper surface of the epitaxial layer 20, and the sinking depth is greater than the trench depth.

[0072] Among them, a mask 70 is formed on the surface of the epitaxial layer 20. A mask opening 71 corresponding to the shape and position of the bottom screen region 20d is formed on the mask 70 by photolithography. By aligning with the bottom screen region 20d, P-type impurities are implanted through an ion implantation process, and a bottom screen junction 22 is formed in the epitaxial layer 20 in a deposition manner, and the mask 70 is removed. The ion implantation process can be a channeling implantation process or a high-energy implantation process.

[0073] When P-type impurities (such as boron ions or aluminum ions) are implanted, the ion beam will bombard the entire surface of the epitaxial layer 20. However, only at the mask opening 71 can the ions pass through and enter the underlying epitaxial layer 20. In the region covered by the mask 70, the ions will be blocked outside. By precisely controlling the energy of the implanted ions, the ions can penetrate the surface of the epitaxial layer 20 and finally stop below the predetermined position for forming the trench 27 in the epitaxial layer 20.

[0074] The materials of the substrate 10 and the epitaxial layer 20 include, but are not limited to, SiC. The doping types of the substrate 10 and the epitaxial layer 20 can be N-type or P-type. In this embodiment, the epitaxial layer 20 is taken as an example of N-type for illustration. It is easy to understand that when the epitaxial layer 20 is P-type, all corresponding doping types need to be changed to the opposite types.

[0075] Figure 9 is the cross-sectional view of the structure after performing Figure 7 step S2, where Figure 9 a is the cross-sectional view along the Figure 5 A-A line in Figure 9 b is the cross-sectional view along the Figure 5 C-C line in Figure 9 Referring to Figure 9 , in step S2, P-type impurities are injected into the side screen region 20b, and a side screen junction 23 is formed in the epitaxial layer 20 in a longitudinally continuous extension manner. The side screen junction 23 continuously extends to the upper surface of the epitaxial layer 20. The bottom of the side screen junction 23 intersects with the bottom screen junction 22 in a staggered manner to form a grid stagger.

[0076] Wherein, a mask is formed on the surface of the epitaxial layer 20, a mask opening corresponding to the shape and position of the side screen region 20b is formed on the mask through photolithography, P-type impurities are injected through an ion implantation process to form the side screen junction 23 in the epitaxial layer 20, and the mask is removed.

[0077] Figure 10 is the cross-sectional view of the structure along the Figure 7 C-C line after performing Figure 5 step S3. Referring to Figure 10 , in step S3, P-type impurities are injected into the main body region 20a, and a body layer 24 is formed in the epitaxial layer 20 in a sedimentation manner. The body layer 24 sinks below the upper surface of the epitaxial layer 20, and the lower surface of the body layer 24 is flush with the upper surface of the bottom screen junction 22.

[0078] Figure 11 is the cross-sectional view of the structure along the Figure 7 C-C line after performing Figure 5 step S4. Referring to Figure 11, in step S4, N-type impurities are implanted into the main body region 20a to successively form a first doped layer 25 and a second doped layer 26. The lower surface of the first doped layer 25 is flush with the upper surface of the body layer 24, the lower surface of the second doped layer 26 is flush with the upper surface of the first doped layer 25, and the second doped layer 26 extends to the upper surface of the epitaxial layer 20, wherein the doping concentration of the first doped layer 25 is lower than that of the second doped layer 26. Among them, N-type impurities can be implanted into the surface of the epitaxial layer 20 through an ion implantation process or a diffusion process to finally form an N+N-P type structure.

[0079] Figure 12 is a cross-sectional view of the structure after performing Figure 7 step S5, wherein Figure 12 a is a cross-sectional view along the Figure 5 A-A line in Figure 12 b is a cross-sectional view along the Figure 5 B-B line in Figure 12 c is a cross-sectional view along the Figure 5 C-C line in Figure 12 . Referring to

[0080]

[0081] Figure 13 Figure 7 is a cross-sectional view of the structure after performing Figure 5 step S6 along the Figure 13 C-C line in . Referring to

[0082] In the previous steps, P-type and N-type impurities were implanted into the lattice of the epitaxial layer 20 through ion implantation. However, at this time, most of these impurity atoms are in interstitial positions and do not replace lattice atoms, so they do not have electrical activity (that is, they cannot effectively provide holes or electrons). This step uses high-temperature annealing (high-temperature activation) to provide energy to make the implanted impurity atoms migrate to the substitution positions of the lattice, thereby becoming electrically active and capable of changing the conductivity type and conductivity of the semiconductor to form the required P region and N region.

[0083] During high-temperature activation, the semiconductor surface may decompose, volatilize (e.g., Si atoms sublime), or become rough. Therefore, it is necessary to cover a protective layer (Capping Layer) 80 before activation to prevent the surface from being damaged at high temperature, and then remove the protective layer 80 after the high-temperature activation is completed. Among them, the material of the protective layer 80 can be materials such as photoresist (PR), sputter carbon (Sputter C), aluminum nitride (AlN), etc. The temperature of high-temperature activation can be 1400 - 2100 °C, preferably 1700 - 1800 °C.

[0084] Figure 14 Is the structure after step S7 of Figure 7 along the Figure 5 C-C line in Figure 14 Refer to

[0085] Among them, first, the surface of the wafer is oxidized at high temperature to form a sacrificial oxide layer (Sacrificial Oxide, SAC OX) on the inner wall of the trench 27 to eliminate the damaged layer or contamination left on the semiconductor structure surface due to previous processes (such as surface residues or damage after trench etching and ion implantation), and then remove the sacrificial oxide layer. Here, the term "wafer" refers to the whole semiconductor structure formed after performing the foregoing steps.

[0086] Furthermore, a gate oxide layer 31 is formed on the inner wall of the trench 27 through processes such as thermal oxidation or chemical vapor deposition (CVD).

[0087] Figure 15 Is the structure after step S8 of Figure 7 along the Figure 5 C-C line in Figure 15 Refer to

[0088] Figure 16 Is the structure after step S9 of Figure 7 along the Figure 5 C-C line in Figure 16, in step S9, an interlayer dielectric layer 40 is formed on the surface of the wafer. Among them, the interlayer dielectric layer 40 covers the gate 30, the second doped layer 26, and the sidewall junction 23. The material of the interlayer dielectric layer 40 can be silicon dioxide (SiO2) and / or silicon nitride (SiN).

[0089] Figure 17 is the structure after performing Figure 7 step S10 along the Figure 5 C-C line in Figure 17 , in step S10, a contact hole (CONT) 41 is formed on the interlayer dielectric layer 40 to expose at least a part of the second doped layer 26 located around the sidewall junction 23.

[0090] Among them, a mask 70 is formed on the surface of the interlayer dielectric layer 40, a mask opening 71 corresponding to the position of the sidewall junction 23 is formed on the mask 70 by photolithography, the interlayer dielectric layer 40 located at the mask opening is etched away, and a part of the sidewall junction 23 and the second doped layer 26 located there is continuously etched to form the contact hole 41, and then the mask 70 is removed. The etching depth of the sidewall junction 23 and the second doped layer 26 can be 30 - 40 angstroms.

[0091] Figure 18 is the structure after performing Figure 7 step 11 along the Figure 5 C-C line in Figure 18 , in step S11, a metal silicide layer 50 is formed at the contact hole 41. Among them, a metal layer (such as Ti, Ni, Co) is deposited on the surface of the wafer (including the surface of the sidewall junction 23, the second doped layer 26, and the surrounding interlayer dielectric layer 40 exposed at the contact hole 41); the deposited metal reacts with the silicon of the sidewall junction 23 and the second doped layer 26 at high temperature to form the metal silicide layer 50, and at this time, the deposited metal does not react with the interlayer dielectric layer 40; finally, the deposited metal located on the interlayer dielectric layer 40 that has not reacted is removed.

[0092] Figure 6 is a cross-sectional view of the trench-type silicon carbide MOSFET device according to Embodiment 1 of the present application, where Figure 6 a is a cross-sectional view along the Figure 5 A-A line in Figure 6 b is a cross-sectional view along the Figure 5 B-B line in Figure 6 c is a cross-sectional view along the Figure 5 C-C line in

[0093] Refer toFigure 6 In step S12, a metal conductive layer 61, a passivation layer 62, and a buffer protection layer 63 are sequentially formed on the wafer. The substrate 10 is thinned, and an ohmic contact layer and a metal backplane 64 are sequentially formed on the back surface of the substrate 10 to form the trench-type silicon carbide MOSFET device.

[0094] Among them, the metal conductive layer 61 is located on the metal silicide layer 50 and the interlayer dielectric layer 40, constituting the source electrode of the trench-type silicon carbide MOSFET device. The material of the metal conductive layer 61 can be Al, Cu, an Al / Cu alloy (such as an AlSi alloy, an AlCu alloy, and an AlSiCu alloy), or a laminated combination of the above materials.

[0095] The passivation layer 62 is located on the metal conductive layer 61. The material of the passivation layer 62 can be silicon dioxide (SiO2), silicon nitride (SiN), or a combination thereof. The thickness of the passivation layer 62 can be 0.1 - 20 um.

[0096] The buffer protection layer 63 is located on the passivation layer 62. The materials of the buffer protection layer 63 include but are not limited to polyimide (PI), polyamide, polybenzoxazole (PBO), and combinations thereof. The thickness of the buffer protection layer 63 can be 1 - 50 um, preferably 10 - 15 um.

[0097] The thickness of the thinned substrate 10 is 80 - 250 um, preferably 150 - 200 um.

[0098] The metal backplane 64 is connected to the substrate through the ohmic contact layer, constituting the drain electrode of the trench-type silicon carbide MOSFET device. The material of the metal backplane 64 can be Ti, Ni, Ag, Pd, Au, and their alloys or combinations.

[0099] The implementation principle of Example 2 is as follows: The bottom screen area, side screen area, and trench area are precisely defined, and processing is carried out in a specific order (first forming an interleaved deep bottom screen combined with a side screen junction grid, and then opening trenches therein), so that a trench-type silicon carbide MOSFET with a three-dimensional grid shielding structure can be reliably manufactured, ensuring the precise relative position between the shielding structure and the trench, and realizing the high-reliability advantages brought by the device structure.

[0100] Example 3 Figure 19 is a schematic flowchart of the manufacturing method of the trench-type silicon carbide MOSFET device according to Embodiment 3 of the present application. Referring to Figure 19 , the differences between this embodiment and Embodiment 2 lie in steps S1 and S2.

[0101] Figure 20 is a cross-sectional view of the structure after performing the steps in Figure 19 , where Figure 20 a is a cross-sectional view along the A-A line of Figure 5 , Figure 20 b is a cross-sectional view along the B-B line of Figure 5 . Figure 20 c is a cross-sectional view along the D-D line of Figure 5 . Referring to Figure 20 , in step S1, P-type impurities are implanted while aligning the bottom screen region 20d to form a bottom screen junction 22 in the epitaxial layer 20, and at the same time, P-type impurities are implanted while aligning the side screen region 20b within the first depth range 23a.

[0102] Figure 21 is a cross-sectional view of the structure after performing the steps in Figure 19 , where Figure 21 a is a cross-sectional view along the A-A line of Figure 5 , Figure 21 b is a cross-sectional view along the C-C line of Figure 5 . Referring to Figure 21 , in step S2, P-type impurities are implanted while aligning the side screen region 20b at a depth outside the first depth range 23a to form a side screen junction 23 in the epitaxial layer 20.

[0103] In this embodiment, the process of implanting P-type impurities at the depth of the first depth range 23a is omitted in step S2, which can simplify the process steps. The remaining steps and the finally formed device of this embodiment are the same as those of Embodiment 2, and will not be elaborated here.

[0104] The implementation principle of Embodiment 3 is: by combining the bottom screen junction implantation with the shallow implantation of the side screen junction, and by using a mask plate to simultaneously complete the partial doping of multiple regions in the same step, the number of ion implantations can be effectively reduced, thereby simplifying the manufacturing process, reducing the process complexity and production cost, and improving the production efficiency.

[0105] Embodiment 4 Figure 22 is a schematic flow chart of the manufacturing method of the trench-type silicon carbide MOSFET device according to Embodiment 4 of the present application. Referring to Figure 22 , the difference between this embodiment and Embodiment 2 lies in step S1 and step S2.

[0106] Figure 23 is a cross-sectional view of the structure after performing the steps in Figure 22 , where Figure 23 a is a cross-sectional view along the A-A line of Figure 5 , Figure 23 b is a cross-sectional view along the B-B line of Figure 5 .Figure 23 c is a cross-sectional view along Figure 23 the D-D line of a. Refer to Figure 23 , in step S1, P-type impurities are implanted into the bottom screen region 20d to form a bottom screen junction 22 in the epitaxial layer 20, and at the same time, P-type impurities are implanted into the side screen region 20b within a second depth range 23b, and the depth of the second depth range 23b is greater than the depth of the first depth range 23a.

[0107] Figure 24 is to execute Figure 22 a cross-sectional view of the structure after step S2 in Figure 24 a is a cross-sectional view along Figure 5 the A-A line of Figure 24 b is a cross-sectional view along Figure 5 the C-C line of Figure 24 , in step S2, P-type impurities are implanted into the side screen region 20b at a depth outside the second depth range 23b to form a side screen junction 23 in the epitaxial layer 20.

[0108] In this embodiment, the process of implanting P-type impurities at the depth of the second depth range 23b is omitted in step S2, which can simplify the process steps. The remaining steps and the finally formed device in this embodiment are the same as those in Embodiment 2, and will not be described in detail here.

[0109] The implementation principle of Embodiment 4 is: combining the implantation of the bottom screen junction with the deep implantation of the side screen junction, and by using a mask plate to simultaneously complete the partial doping of multiple regions in the same step, the number of ion implantations can be effectively reduced, thereby simplifying the manufacturing process, reducing the process complexity and production cost, and improving the production efficiency.

[0110] The above are all preferred embodiments of the present application. The protection scope of the present application is not limited by this. Therefore, all equivalent changes made according to the structure, shape, and principle of the present application should be covered within the protection scope of the present application.

Claims

1. A trench silicon carbide MOSFET device, characterized in that: include: A substrate (10) having an epitaxial layer (20), wherein the epitaxial layer (20) comprises a bottom screen junction (22) and a side screen junction (23) which are interlaced and connected to each other and formed by an implantation process, wherein the bottom screen junction (22) is sunken to the upper surface of the epitaxial layer (20), and the sinking depth of the bottom screen junction (22) starting from the epitaxial layer (20) is greater than the depth of the groove (27); and the side screen junction (23) is continuously formed on the epitaxial layer (20). The side screen junction (23) extends to the upper surface of the epitaxial layer (20), and the bottom of the side screen junction (23) is staggered with the bottom screen junction (22) to form a grid staggered structure; the epitaxial layer (20) is provided with a groove (27), the connection between the side wall and the bottom of the groove (27) forms an arc shape, the bottom of the groove (27) is recessed in the bottom screen junction (22), and the groove (27) is located between the side screen junctions (23); A gate (30) is arranged in the groove (27).

2. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The substrate (10) and the epitaxial layer (20) have first type impurities, and the bottom screen junction (22) and the side screen junction (23) have second type impurities, wherein the first type impurities have opposite polarities to the second type impurities.

3. The trench silicon carbide MOSFET device according to claim 2, characterized in that: The epitaxial layer (20) further comprises: A body layer (24) located in the epitaxial layer (20), wherein the body layer (24) has second type impurities; An epitaxial bottom layer (21) located below the body layer (24) and the bottom screen junction (22); A first doping layer (25) located on the body layer (24), the first doping layer (25) having a first type of impurities; a second doping layer (26), located on the first doping layer (25), the second doping layer (26) having a first type of impurities, wherein the doping concentration of the second doping layer (26) is higher than the doping concentration of the first doping layer (25); The body layer (24), the first doping layer (25) and the second doping layer (26) are filled in the gap between the side screen junction (23) and the gate (30).

4. The trench silicon carbide MOSFET device according to claim 3, characterized in that: Also includes: an interlayer dielectric layer (40) located above the gate (30), the second doped layer (26) and the side screen junction (23), wherein the interlayer dielectric layer (40) has a contact hole (41), and the contact hole (41) exposes a portion of the surface of the second doped layer (26) located around the side screen junction (23); A metal silicide layer (50) is located at the contact hole (41) on a portion of the surface of the side screen junction (23) and the second doped layer (26).

5. The trench silicon carbide MOSFET device according to claim 4, characterized in that: Also includes: A metal conductive layer (61) located on the interlayer dielectric layer (40) and the metal silicide layer (50); A passivation layer (62) located on the metal conductive layer (61); A buffer protection layer (63), located on the passivation layer (62); A metal back plate (64) is connected to the back side of the substrate (10) via an ohmic contact layer.

6. The trench silicon carbide MOSFET device according to claim 1, characterized in that: The gate (30) is filled in the trench (27), and a gate oxide layer (31) is provided between the inner wall of the trench (27) and the gate (30).

7. A method for constructing a trench silicon carbide MOSFET device, characterized in that: include: Providing a substrate (10) having an epitaxial layer (20), wherein the upper surface of the epitaxial layer (20) is defined with a groove region (20c) and a side screen region (20b) parallel to each other, and a bottom screen region (20d) interlaced with the groove region (20c); Aligning the bottom screen region (20d), forming a bottom screen junction (22) in the epitaxial layer (20) in a sinking manner, wherein the bottom screen junction (22) is sunk to the upper surface of the epitaxial layer (20), and the sinking depth is greater than the groove depth; Aligning the side screen area (20b), forming a side screen junction (23) in the epitaxial layer (20) in a longitudinally continuous extending manner, wherein the side screen junction (23) continuously extends to the upper surface of the epitaxial layer (20), and the bottom of the side screen junction (23) is staggered with the bottom screen junction (22) to form a grid staggered; Aligning the groove area (20c), opening a groove (27) in the epitaxial layer (20), wherein a circular arc is formed at the connection between the side wall and the bottom of the groove (27), the bottom of the groove (27) is recessed in the bottom screen junction (22), and the groove (27) is located between the side screen junctions (23); A gate (30) is arranged in the trench (27).

8. The construction method according to claim 7, characterized in that: The upper surface of the epitaxial layer (20) is further defined with a main body region (20a) parallel to the side screen region (20b), and the groove region (20c) is located in the main body region (20a), wherein before the groove (27) is formed, the main body region (20a) is aligned, and a body layer (24) and a first doped layer (25) are sequentially formed in the epitaxial layer (20) by a deposition method, and a second doped layer (26) is formed in the epitaxial layer (20) by a longitudinal continuous extension method, wherein the body layer (24) is sunk to the upper surface of the epitaxial layer (20), the lower surface of the body layer (24) is flush with the upper surface of the bottom screen junction (22), the lower surface of the first doped layer (25) is flush with the upper surface of the body layer (24), the lower surface of the second doped layer (26) is flush with the upper surface of the first doped layer (25), and the second doped layer (26) extends to the upper surface of the epitaxial layer (20); wherein, aligning the bottom screen region (20d), implanting second type impurities through an ion implantation process to form a bottom screen junction (22), wherein the ion implantation process includes a channel implantation process or a high energy implantation process; Aligning the side screen region (20b), and implanting second type impurities through an ion implantation process to form a side screen junction (23); Aligning the main body region (20a), and implanting second type impurities through an ion implantation process to form a body layer (24); Aligning the main region (20a), and injecting first type impurities through an ion implantation process or a diffusion process, so as to sequentially form a first doping layer (25) and a second doping layer (26); The first type impurities and the second type impurities are activated through a thermal treatment process.

9. The construction method according to claim 8, characterized in that: Also includes: forming an interlayer dielectric layer (40) on the gate (30), the second doped layer (26) and the side screen junction (23); forming a contact hole (41) in the interlayer dielectric layer (40) to expose a portion of the second doped layer (26) located around the side screen junction (23); forming a metal silicide layer (50) at the contact hole (41); Sequentially forming a metal conductive layer (61), a passivation layer (62) and a buffer protection layer (63) on the interlayer dielectric layer (40) and the metal silicide layer (50); The substrate (10) is thinned, and an ohmic contact layer and a metal back plate (64) are sequentially formed on the back side of the substrate (10).

10. The construction method according to claim 8, characterized in that: When aligning the bottom screen region (20d) and implanting the second type of impurities through an ion implantation process to form a bottom screen junction (22), also aligning the side screen region (20b) and implanting the second type of impurities within a first depth range (23a); When aligning the side screen region (20b) and implanting the second type of impurities through an ion implantation process to form a side screen junction (23), the second type of impurities are implanted at a depth outside the first depth range (23a); Alternatively, when aiming at the bottom screen region (20d) and implanting the second type of impurities through an ion implantation process to form a bottom screen junction (22), the side screen region (20b) is also aimed at and the second type of impurities are implanted within a second depth range (23b), the depth of the second depth range (23b) being greater than the depth of the first depth range (23a); When aligning the side screen region (20b) and implanting the second type of impurities through an ion implantation process to form a side screen junction (23), the second type of impurities are implanted at a depth outside the second depth range (23b).

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