A multi-finger GGNMOS structure

Abstract

The present invention discloses a multi-finger GGNMOS structure, which includes a P-type well doped well region disposed on a substrate, multiple strip-shaped N-type doped active regions, a P-type heavily doped active region, and multiple annular polysilicon gates; the multiple strip-shaped N-type doped active regions are spaced apart and disposed in the P-type well doped well region; the P-type heavily doped active region surrounds the multiple strip-shaped N-type doped active regions in an annular shape; two longitudinal sides of each annular polysilicon gate are located between corresponding two strip-shaped N-type doped active regions, and a connection region is provided in the middle between the two longitudinal sides of each annular polysilicon gate, and a position for connecting a metal contact hole is provided on the connection region, so that the surface potential on the P-type well doped well region and at the position of the connection metal contact hole is clamped to be close to the ground potential. The present invention can reduce the effective substrate resistance at the middle position, making the conduction difficulty of the middle finger approach the conduction difficulty of the edge finger, and solving the problem of uneven conduction in the multi-finger GGNMOS structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and in particular to a multi-finger GGNMOS structure. Background Art

[0002] Multi-finger GGNMOS is a design that integrates multiple NMOS transistor cells in parallel within the same device structure. By splitting the gate and drain / source regions, a single wide-channel NMOS transistor is divided into multiple narrow-channel parallel cells (called fingers), forming multiple fingers in parallel. Multi-finger GGNMOS reduces the current density of a single finger through the parallel connection, preventing local overheating failure and improving overall ESD (electrostatic discharge) robustness.

[0003] However, during an ESD event, the multi-finger GGNMOS may experience uneven conduction, that is, one of the fingers in the multi-finger GGNMOS may turn on prematurely (for example, the middle finger requires only a smaller current to turn on due to the larger substrate resistance, causing the middle finger to be turned on prematurely), resulting in current concentration and reducing the protection capability of the multi-finger GGNMOS.

[0004] Based on this, a new technical solution is needed. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a multi-finger GGNMOS structure to at least solve the problem that a finger in the existing multi-finger GGNMOS structure is turned on prematurely, thereby reducing the protection capability of the multi-finger GGNMOS structure.

[0006] The embodiments of the present invention provide the following technical solutions:

[0007] An embodiment of the present invention provides a multi-finger GGNMOS structure, including:

[0008] A P-type well doping type well region is provided on the substrate;

[0009] A plurality of strip-shaped N-type doping type active regions, wherein the plurality of strip-shaped N-type doping type active regions are arranged at intervals in the P-type well doping type well region;

[0010] A P-type heavily doped active region, the P-type heavily doped active region is arranged in the P-type well doping type well region and surrounds the multiple strip-shaped N-type doping type active regions in a ring shape, and the P-type heavily doped active region and the multiple strip-shaped N-type doping type active regions are isolated from each other;

[0011] Multiple annular polysilicon gates are spaced apart on the P-type well-doped well region, and two longitudinal sides of each of the multiple annular polysilicon gates are located between two corresponding strip-shaped N-type doped active regions. A connection region is provided in the middle between the two longitudinal sides of each of the annular polysilicon gates, and a position for connecting a metal contact hole is provided on the connection region so that the surface potential on the P-type well-doped well region and at the position of the metal contact hole is clamped to be close to the ground potential. Among them, the metal contact hole is a conductive channel between the annular polysilicon gate and the metal layer.

[0012] Further, the multiple strip-shaped N-type doped active regions are surrounded by an annular N-type doped active region, and the annular N-type doped active region is provided in the P-type well-doped well region;

[0013] Two transverse sides of the annular polysilicon gate are located between the annular N-type doped active region and the corresponding strip-shaped N-type doped active region.

[0014] Further, the connection region is a strip-shaped structure, and its two ends extend to the two longitudinal sides of the annular polysilicon gate.

[0015] Further, there are multiple connection regions, which are spaced apart in the middle of the annular polysilicon gate.

[0016] Further, the connection region is at least one of a circular, figure-eight, or square structure to increase the position and area of the position for connecting the metal contact hole provided on the connection region.

[0017] Further, the position for connecting the metal contact hole on the connection region is electrically connected to the ground voltage.

[0018] Further, an STI isolation region is also provided in the P-type well-doped well region, and the STI isolation region is correspondingly provided with the connection region.

[0019] Further, the P-type heavily doped active region and the multiple strip-shaped N-type doped active regions are isolated by STI.

[0020] Further, the periphery of the P-type heavily doped active region is isolated from the substrate by an STI region.

[0021] Further, the substrate is a P-type substrate.

[0022] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the embodiments of the present invention at least include:

[0023] A multi-finger GGNMOS structure of the present invention adopts an annular polysilicon gate structure and sets the position of the metal contact hole connected to the polysilicon gate at the middle position of the polysilicon gate structure, thereby clamping the substrate surface potential at the middle position close to the ground potential, further enabling the hole current to flow more concentratedly towards the substrate contact point instead of lateral diffusion, and finally reducing the effective substrate resistance at the middle position, making the NPN at the middle position require a larger current to be turned on, increasing the conduction difficulty of the middle finger, and making the conduction difficulty of the middle finger approach that of the edge finger to improve its conduction uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is a top view of a multi-finger GGNMOS structure according to an embodiment of the present invention;

[0026] Figure 2 is Figure 1 a cross-sectional view of AA' in

[0027] Figure 3 is Figure 1 a cross-sectional view of BB' in

[0028] The reference numerals of the present invention are as follows:

[0029] 10. Substrate; 20. P-type well doped region; 30. Strip-shaped N-type doped active region; 40. P-type heavily doped active region; 50. Annular polysilicon gate; 51. Connection region; 52. Position of the connection metal contact hole; 60. Metal contact hole; 70. Annular N-type doped active region. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The embodiments of the present application will be described in detail below with reference to the drawings.

[0031] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0032] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0033] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application schematically. The diagrams only show the components related to the present application and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0034] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0035] As the process size continues to shrink, the operating speed of CMOS chips increases, but the electrostatic discharge (ESD) ability of the devices decreases accordingly. Therefore, on-chip ESD protection devices need to be integrated into the chips. Commercial ICs usually require a human body model (HBM) ESD withstand voltage of 2 kV and a machine model (MM) ESD withstand voltage of 200 V. To optimize the ESD performance, the traditional method uses a gate-grounded NMOS (GGNMOS) with a multi-finger layout to reduce the area occupation.

[0036] However, in a multi-finger GGNMOS structure, due to the uneven distribution of substrate resistance, the parasitic NPN transistor in the central finger (with a higher base resistance) will trigger first, resulting in the ESD current being discharged only through a local area, causing non-uniform conduction and reducing the ESD robustness.

[0037] Figures 1-3 Disclosed is a multi-finger GGNMOS structure (gate-grounded NMOS) claimed in the present application, wherein Figure 2 is the basic unit structure for GGNMOS to achieve its ESD function. Its main structure is a MOSFET, where the source, gate, and substrate are commonly grounded at potential (T2), and the drain is connected to a high potential (T1). When an ESD high-voltage pulse is applied at T1, the N+ (N-type heavily doped active region) / Pwell (P-type well-doped type well region 20) will first undergo avalanche breakdown, generating a large number of electron-hole pairs and forming an avalanche current. Among them, the holes will flow through the Pwell, through the P+ (P-type heavily doped active region 40) to the T2 terminal. Due to the parasitic resistance existing in the Pwell itself, a potential difference will be generated between the Pwell and the T1 terminal. When the potential is higher than 0.7V, the Pwell and the N+ at the T2 source terminal conduct, and at the same time, the NPN is turned on. At this time, the drift current will replace the avalanche current, and more holes will rush into T1. The conduction mechanism causes the bias voltage to maintain the same current to decrease significantly, and the device exhibits a negative resistance characteristic. When the voltage decreases and the current increases, the current in the device is basically provided by the drift current, and the negative resistance characteristic ends. As the voltage and current increase, when a certain value is reached, the entire device undergoes secondary breakdown, and at this time, the critical burnout point of the device is reached.

[0038] In a multi-finger GGNMOS structure, the parasitic base resistance of the NPN at the edge position of the structure is lower. From the above principle analysis, it can be seen that when an ESD pulse is generated, it requires a lower voltage to undergo avalanche breakdown. When the ESD voltage gradually increases, the avalanche breakdown occurs at the middle position. Due to the larger parasitic base resistance of the NPN at the middle position of the structure (R1 + R2 + R3 + R4..; R5 + R6 + R7 + R8..), its NPN is more likely to be turned on (specifically: after the avalanche current is generated at the edge, the avalanche current flows to the NPN at the middle position. Due to the larger base resistance at the middle position, a larger potential difference is generated across the base resistance at the middle position, making its NPN more likely to reach 0.7V, that is, more likely to be turned on). Subsequently, the voltage at the middle position is quickly clamped to the holding voltage, resulting in the inability to turn on the edge position. Macroscopically, this causes a situation of non-uniform current distribution in the multi-finger NMOS structure where the edge undergoes avalanche breakdown first, and then drives the NPN at the middle position to turn on.

[0039] In view of this, the inventors conducted in-depth research and improvement exploration on the flow direction of avalanche current, hole current and the effective capacitance of substrate 10, and found that: when the surface potential of substrate 10 in the middle position is clamped to close to the ground potential, the hole current generated by the avalanche current is more concentrated to flow to the contact point of substrate 10 rather than diffusing laterally, which can effectively reduce the effective substrate resistance, so that a higher avalanche current is required at the middle position to make its NPN turn on, and the avalanche current required for the GGNMOS parasitic NPN to turn on in the middle position is closer to the edge position, thereby enhancing its conduction uniformity.

[0040] Based on this, this specification proposes a solution: Figure 1 As shown, a multi-finger GGNMOS structure of the present invention provides a connection region 51 on a ring-shaped polysilicon gate 50 and plans a location 52 for connecting to a metal contact hole on the connection region 51. When the ring-shaped polysilicon gate 50 is connected to ground potential through the metal contact hole 60, the substrate surface potential at the center of the ring-shaped polysilicon gate 50 is clamped to a voltage close to ground. This allows the hole current generated by the avalanche current to flow more concentratedly toward the contact point on the substrate 10 rather than diffusing laterally. By optimizing the current path, the present invention can effectively reduce the effective substrate resistance at the center, thereby requiring a higher avalanche current to turn on the NPN transistor at the center. This allows the avalanche current required to turn on the parasitic NPN transistor at the center of the GGNMOS to be closer to that at the edge, thereby enhancing conduction uniformity.

[0041] The following describes the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0042] like Figures 1-3As shown in the figure, a multi-finger GGNMOS structure provided by an embodiment of the present invention includes a P-type well-doped well region 20, multiple strip-shaped N-type doped active regions 30, a P-type heavily doped active region 40, and multiple annular polysilicon gates 50 disposed on a substrate 10. Among them, the multiple strip-shaped N-type doped active regions 30 are spaced apart and disposed within the P-type well-doped well region 20; the P-type heavily doped active region 40 is disposed within the P-type well-doped well region 20 and surrounds the multiple strip-shaped N-type doped active regions 30 in a ring shape. The P-type heavily doped active region 40 and the multiple strip-shaped N-type doped active regions 30 are isolated from each other; the multiple annular polysilicon gates 50 are spaced apart and disposed on the P-type well-doped well region 20. Two longitudinal sides of each annular polysilicon gate 50 are located between two corresponding strip-shaped N-type doped active regions 30. A connection region 51 is provided in the middle between the two longitudinal sides of each annular polysilicon gate 50, and a position 52 for connecting a metal contact hole is provided on the connection region 51, so that the surface potential on the P-type well-doped well region 20 and at the position 52 of the metal contact hole is clamped to be close to the ground potential. Wherein, the metal contact hole is a conductive channel between the annular polysilicon gate and the metal layer.

[0043] Among them, the two longitudinal sides of the annular polysilicon gate 50 are: the two longer sides when the annular polysilicon gate 50 is a square frame structure; or the two longer sides when the annular polysilicon gate 50 is an irregular frame structure.

[0044] For example, when the annular polysilicon gate 50 is rectangular, the two longitudinal sides are two longer opposite sides.

[0045] Among them, the metal contact hole is usually used in a semiconductor device as a conductive channel for connecting a metal layer and a semiconductor material or a doped region. For example, in a MOS transistor, the metal contact holes of the source and drain are used to connect the metal layer and the source-drain regions.

[0046] Among them, the main structure of the GGNMOS is a MOSFET, and its substrate 10 is a P-type substrate.

[0047] Among them, the P-type well-doped well region 20 is used to provide controllable substrate doping and optimize the current distribution.

[0048] Among them, the strip-shaped N-type doped active regions 30 are formed in the implantation region of the P-type well-doped well region 20 and are used to form a multi-finger structure to improve the current-carrying capacity.

[0049] Among them, the tops of the strip-shaped N-type doped active regions 30 are flush with the top of the P-type well-doped well region 20.

[0050] Preferably, the multiple strip-shaped N-type doped active regions 30 are spaced apart and uniformly disposed.

[0051] Among them, the P-type heavily doped active region 40 is formed in the implantation region of the P-type well-doped well region 20, which is used to reduce the substrate resistance and improve the hole current discharge.

[0052] Among them, the P-type heavily doped active region 40 is in a ring structure, such as a square frame structure, and the top of the P-type heavily doped active region 40 is flush with the top of the P-type well-doped well region 20.

[0053] Among them, the ring-shaped polysilicon gate 50 and the connection region 51 are used to clamp the substrate potential through the metal contact hole 60 to ensure uniform conduction of multiple fingers.

[0054] Among them, the ring-shaped polysilicon gate 50 is formed on the top surface of the P-type well-doped well region 20.

[0055] The improvement of this application mainly lies in that a connection region 51 is provided at the middle position of the polysilicon gate, and a position 52 for connecting the metal contact hole is provided on the connection region 51, and the surface potential of the corresponding substrate 10 at this position is clamped to be close to the ground potential, so that the effective substrate resistance of the middle part approaches that of the edge part, enabling the middle finger (middle gate finger) and the edge finger (edge gate finger) of the multi-finger GGNMOS to approach simultaneous turn-on, thereby increasing the conduction uniformity of the multi-finger GGNMOS, and solving the problem of non-uniform conduction of the existing GGNMOS due to non-uniform substrate resistance distribution.

[0056] Furthermore, multiple strip-shaped N-type doped active regions 30 are surrounded by a ring-shaped N-type doped active region 70, and the ring-shaped N-type doped active region 70 is disposed in the P-type well-doped well region 20; the two horizontal sides of the ring-shaped polysilicon gate 50 are located between the ring-shaped N-type doped active region 70 and the corresponding strip-shaped N-type doped active region 30.

[0057] The ring-shaped N-type doped active region 70 surrounding the strip-shaped N-type doped active region 30 can force the current to be evenly distributed and avoid the edge effect, and the horizontal sides of the polysilicon gate are located between the ring-shaped N-type doped active region 70 and the strip-shaped N-type doped active region 30, which can also enhance the gate control ability and improve the ESD robustness, solving the problem that the connection positions at both ends of the existing polysilicon gate structure are set as metal contact holes, resulting in the inability to fully utilize both ends.

[0058] Preferably, the connection region 51 is in a strip structure, and its two ends extend to the two vertical sides of the ring-shaped polysilicon gate 50 to enhance the substrate 10 potential control.

[0059] Among them, extending the strip-shaped connection region 51 to the vertical side of the polysilicon gate expands the contact area, reduces the substrate resistance, and can effectively improve the clamping effect.

[0060] Furthermore, there are multiple connection regions 51, which are spaced apart in the middle of the annular polysilicon gate 50 to perform multi-point clamping to ensure uniform distribution of the potential of the substrate 10, thereby solving the problem that a single connection region 51 may not be able to fully balance the potential of the substrate 10.

[0061] In some of the embodiments, the connection area 51 is at least one of a circular, an eight-shaped, and a square structure to increase the position 52 and area of the connection metal contact hole set on the connection area 51 to solve the problem that a single shape may limit process flexibility or contact area.

[0062] By setting the connection region 51 to have different shapes, the flexibility of the layout of the metal contact hole 60 can be increased, and the current discharge capability can be improved.

[0063] Furthermore, the position 52 connected to the metal contact hole on the connection area 51 is electrically connected to the ground voltage to force the potential of the substrate 10 to be stable and ensure uniform triggering.

[0064] Furthermore, an STI isolation region is provided in the P-type well doping type well region 20. The STI isolation region is provided corresponding to the connection region 51 to optimize device reliability, solve the problem that the connection region 51 may affect the electrical characteristics of adjacent devices, prevent leakage or latch-up effects, and improve ESD robustness.

[0065] Furthermore, the P-type heavily doped active region 40 and the plurality of strip-shaped N-type doped active regions 30 are isolated by STI to ensure electrical isolation, avoid abnormal conduction, and solve the problem of leakage or parasitic effects that may be caused by direct contact.

[0066] Furthermore, the periphery of the P-type heavily doped active region 40 is isolated from the substrate 10 by the STI region to prevent current diffusion in the substrate 10, optimize ESD performance, and avoid the problem that the P-type heavily doped region may affect the overall potential of the substrate 10.

[0067] This invention addresses the uneven conduction problem of conventional GGNMOS devices through a potential clamping design involving a ring-shaped polysilicon gate 50 and substrate 10. Furthermore, optimizations such as STI isolation, multi-shaped connection regions 51, and a ring-shaped N-type region layout improve ESD performance and process flexibility. The core innovation lies in the active control of the substrate 10 potential, ensuring uniform triggering and efficient current discharge.

[0068] The present invention forms a GGNMOS structure by surrounding the left and right edge positions (lateral sides) of the polysilicon gate structure with polysilicon gates, thereby making full use of the layout area and improving area utilization.

[0069] The advantages of the present invention are as follows: it has an annular GGNMOS effective structure; the position of the metal contact hole connected to the polysilicon gate is placed in the central area, saving the occupied area and solving the problem that the position of the metal contact hole connected to the polysilicon gate on both sides occupies more positions; the middle position is replaced by the position of the metal contact hole connected to the polysilicon gate, alleviating the premature turn-on of the middle NPN and making the discharge of GGNMOS more uniform.

[0070] In this specification, for the same or similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the partial descriptions of the system embodiments.

[0071] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A multi-finger GGNMOS structure, characterized in that, Comprising: A P-type well doped well region disposed on a substrate; A plurality of strip-shaped N-type doped active regions, the plurality of strip-shaped N-type doped active regions being spaced apart and disposed within the P-type well doped well region; A P-type heavily doped active region, the P-type heavily doped active region being disposed within the P-type well doped well region and surrounding the plurality of strip-shaped N-type doped active regions in a ring shape, the P-type heavily doped active region and the plurality of strip-shaped N-type doped active regions being isolated from each other; A plurality of ring-shaped polysilicon gates, the plurality of ring-shaped polysilicon gates being spaced apart and disposed on the P-type well doped well region, and two longitudinal sides of each ring-shaped polysilicon gate being located between corresponding two strip-shaped N-type doped active regions, and a connection region being provided in the middle between the two longitudinal sides of each ring-shaped polysilicon gate, and a position for connecting a metal contact hole being provided on the connection region, so that the surface potential on the P-type well doped well region and at the position of the connection metal contact hole is clamped to be close to the ground potential, wherein the metal contact hole is a conductive channel between the ring-shaped polysilicon gate and a metal layer.

2. The multi-finger GGNMOS structure according to claim 1, wherein The plurality of strip-shaped N-type doped active regions are surrounded by a ring-shaped N-type doped active region, and the ring-shaped N-type doped active region is disposed within the P-type well doped well region; Two transverse sides of the ring-shaped polysilicon gate are located between the ring-shaped N-type doped active region and the corresponding strip-shaped N-type doped active region.

3. The multi-finger GGNMOS structure according to claim 1, characterized in that, The connection region is in a strip structure, and its two ends extend to the two longitudinal sides of the ring-shaped polysilicon gate.

4. The multi-finger GGNMOS structure according to claim 3, characterized in that, There are a plurality of the connection regions, and they are spaced apart and disposed in the middle of the ring-shaped polysilicon gate.

5. The multi-finger GGNMOS structure according to claim 1, characterized in that The connection region is at least one of a circular shape, an eight-shaped shape, and a square shape to increase the position and area of the position for connecting the metal contact hole provided on the connection region.

6. The multi-finger GGNMOS structure according to claim 1, characterized in that, The position of the connection metal contact hole on the connection region is electrically connected to the ground voltage.

7. The multi-finger GGNMOS structure according to claim 1, wherein An STI isolation region is further provided within the P-type well doped well region, and the STI isolation region is correspondingly disposed with the connection region.

8. The multi-finger GGNMOS structure according to claim 1, wherein The P-type heavily doped active region and the plurality of strip-shaped N-type doped active regions are isolated by STI.

9. The multi-finger GGNMOS structure according to claim 1, wherein The periphery of the P-type heavily doped active region is isolated from the substrate by an STI region.

10. The multi-finger GGNMOS structure according to claim 1, wherein The substrate is a P-type substrate.

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