A uniformly turned-on GGNMOS structure

Abstract

The present invention discloses a uniformly turned-on GGNMOS structure, comprising a P-type well-doped well region, an annular P-type heavily doped active region, an annular N-type heavily doped active region, an N-type well-doped well region, a strip-shaped N-type heavily doped active region, an annular polysilicon gate, and an intermediate P-type heavily doped active region. The annular P-type heavily doped active region is implanted at the edge of the P-type well-doped well region; the annular N-type heavily doped active region is located inside the P-type heavily doped active region and is isolated from the P-type heavily doped active region; the Nwell is annular and located between the substrate and the annular N-type heavily doped active region; multiple strip-shaped N-type heavily doped active regions are surrounded by the annular N-type heavily doped active region; and each intermediate P-type heavily doped active region is implanted into the middle of the strip-shaped N-type heavily doped active region. The GGNMOS structure of the present invention can easily break down to generate an avalanche current and can quickly enter a uniformly turned-on state, solving the problem of uneven conduction of existing multi-finger GGNMOS.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and in particular to a uniformly turned-on GGNMOS structure. Background Art

[0002] Electrostatic discharge (ESD) is one of the main causes of integrated circuit failure, especially in deep submicron and nanometer processes. The destructive effects of ESD models such as HBM (Human Body Model), CDM (Charged Device Model), and MM (Machine Model) are particularly prominent. Currently, ESD protection designs must meet the requirements of high current discharge efficiency, fast response, and effective clamping voltage. GGNMOS is widely used due to its CMOS process compatibility and excellent discharge capabilities.

[0003] In the prior art, when a high-voltage ESD pulse is applied to a GGNMOS, the device's edge regions, due to their lower parasitic base resistance, trigger avalanche breakdown first. As the resulting avalanche current propagates toward the central region, the higher parasitic resistance in the central region creates a significant potential difference, causing the central parasitic bipolar transistor (NPN) to turn on prematurely. At this point, the voltage in the central region is quickly clamped to the holding voltage, preventing the edge regions from generating sufficient trigger voltage, ultimately leading to a current concentration effect. This manifests itself macroscopically as avalanche breakdown of the edge finger structure, with only the central NPN remaining conductive, while the overall device's current discharge capacity is underutilized.

[0004] Based on this, a new technical solution is needed. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a uniformly turned-on GGNMOS structure to at least solve the problem of uneven conduction of the existing multi-finger GGNMOS.

[0006] The embodiments of the present invention provide the following technical solutions:

[0007] An embodiment of the present invention provides a uniformly turned-on GGNMOS structure, comprising:

[0008] A P-type well doping type well region formed on the substrate;

[0009] an annular P-type heavily doped active region, wherein the annular P-type heavily doped active region is implanted into the edge of the P-type well doping type well region;

[0010] an annular N-type heavily doped active region, wherein the annular N-type heavily doped active region is implanted at the edge of the P-type well-doped well region, is located inside the annular P-type heavily doped active region, and is isolated from the annular P-type heavily doped active region;

[0011] An N-type well-doped well region is implanted into the P-type well-doped well region in a ring shape and is located between the substrate and the ring-shaped N-type heavily doped active region;

[0012] a plurality of strip-shaped N-type heavily doped active regions, wherein the plurality of strip-shaped N-type heavily doped active regions are implanted into the P-type well-doping type well region at intervals and are surrounded by the annular N-type heavily doped active region, and the annular N-type heavily doped active region and the plurality of strip-shaped N-type heavily doped active regions are isolated from each other;

[0013] A plurality of annular polysilicon gates, wherein the plurality of annular polysilicon gates are spaced apart and formed at the top of the P-type well doping type well region, and the two longitudinal sides of each of the annular polysilicon gates are correspondingly located between two adjacent strip-shaped N-type heavily doped active regions;

[0014] A plurality of intermediate P-type heavily doped active regions are formed, each of which is implanted into the middle of the strip-shaped N-type heavily doped active region surrounded by the annular polysilicon gate and is isolated from the strip-shaped N-type heavily doped active region.

[0015] Furthermore, the width of the annular N-type heavily doped active region is smaller than the width of the N-type well-doped well region.

[0016] Furthermore, the middle P-type heavily doped active region is grounded via a metal contact hole.

[0017] Furthermore, the middle P-type heavily doped active region is isolated from the strip-shaped N-type heavily doped active region by an annular STI region.

[0018] Furthermore, the annular STI region extends into the P-type well doping type well region.

[0019] Furthermore, a plurality of the intermediate P-type heavily doped active regions are implanted into the middle of the strip-shaped N-type heavily doped active region surrounded by the polysilicon gate, and the plurality of the intermediate P-type heavily doped active regions are arranged at intervals.

[0020] Furthermore, the annular P-type heavily doped active region is isolated from the annular N-type heavily doped active region by an STI region.

[0021] Furthermore, the annular P-type heavily doped active region is isolated from the substrate by an STI region.

[0022] Furthermore, the annular N-type heavily doped active region is isolated from the plurality of strip-shaped N-type heavily doped active regions by an STI region.

[0023] Furthermore, two lateral sides of the annular polysilicon gate are provided with positions for connecting metal contact holes, and the two lateral sides are located on the STI region between the annular N-type heavily doped active region and the plurality of strip-shaped N-type heavily doped active regions.

[0024] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0025] The present invention provides a gate-grounded NMOS structure. By implanting a P-type heavily doped active region into an N-type heavily doped active region surrounded by each annular polysilicon gate and grounding the P-type heavily doped active region, the parasitic resistance from the base region to the ground of a parasitic NPN located in the middle of the GGNMOS can be reduced, and the avalanche current required for the parasitic NPN located in the middle to turn on can be increased, so that the parasitic NPN located in the middle of the GGNMOS requires a higher voltage to turn on.

[0026] Then, an N-type well-doped well region is added between the annular N-type heavily doped active region at the edge and the substrate to increase the base resistance of the parasitic NPN at the edge of the GGNMOS, so that the parasitic NPN at the edge can be turned on with a smaller avalanche current. Finally, by turning on the parasitic NPN at the edge in advance and delaying the turn-on of the parasitic NPN in the middle, the NPN turn-on in the GGNMOS can be made more uniform.

[0027] Finally, adding a P-type heavily doped active region in the middle position can also make up for the problem that adding an N-type well-doped well region at the edge position makes it difficult for the reverse junction to break down and turn on, so that the overall structure can break down more easily to generate avalanche current and can quickly enter a uniformly turned-on state. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 A top view of a gate-grounded NMOS structure according to an embodiment of the present invention;

[0030] Figure 2 for Figure 1 Cross-sectional view of AA';

[0031] Figure 3 for Figure 1 Cross-section of middle BB';

[0032] Figure 4 for Figure 1 Cross-sectional view of CC'.

[0033] The accompanying drawings of the present invention are as follows:

[0034] 10. P-type well-doping type well region; 20. Annular P-type heavily doped active region; 30. Annular N-type heavily doped active region; 40. N-type well-doping type well region; 50. Strip-shaped N-type heavily doped active region; 60. Annular polysilicon gate; 70. Middle P-type heavily doped active region; 80. STI region; 90. Metal contact hole. DETAILED DESCRIPTION

[0035] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0036] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0037] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0038] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0039] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples, however, one skilled in the art will appreciate that the examples can be practiced without these specific details.

[0040] As technology advances, device dimensions continue to shrink along with the diffusion of silicide to increase the operating speed of CMOS chips. However, with advanced CMOS technology, device electrostatic discharge (ESD) capabilities weaken, necessitating the inclusion of on-chip ESD protection devices. To achieve ideal ESD robustness in CMOS integrated circuits, on-chip ESD protection devices are typically designed with larger device dimensions and traditionally drawn using a multi-finger layout to reduce the total silicon footprint.

[0041] In a multi-finger gate-grounded NMOS (GGNMOS) circuit surrounded by a P+ guard ring, due to the varying substrate resistances at various locations within the multi-finger GGNMOS circuit, the parasitic npn BJT on the middle finger (with its higher base-substrate resistance) triggers faster than the other fingers under ESD stress. Once the middle finger triggers, the ESD overstress voltage is clamped to its holding voltage. Consequently, the ESD current discharges only through the localized center region, causing uneven conduction. As the current gradually increases, the channel region in the center generates significant heat, eventually burning out, reducing the overall current discharge efficiency of the structure.

[0042] Specifically, in existing multi-finger GGNMOS ESD structures, when a high-voltage ESD pulse is applied to T1, its N+ (N-type heavily doped active region) / Pwell (P-type well-doped well region) first experiences avalanche breakdown, generating an avalanche current. Holes then flow through Pwell, through the P+ (P-type heavily doped active region), and to T2. Due to the parasitic resistance of Pwell, a potential difference is generated between Pwell and T1. When the potential exceeds 0.7V, Pwell and the N+ at T2 conduct forward, turning on the NPN (reflected on TLP as Vt1 and It1). At this point, the drift current replaces the avalanche current, and more holes flow into T1. The conductive mechanism significantly reduces the bias voltage required to maintain the same current, causing the device to exhibit negative resistance. As the voltage decreases and the current increases, the current in the device is primarily provided by the drift current, and the negative resistance ends. As the voltage and current increase, the entire device undergoes secondary breakdown, reaching its critical burnout point.

[0043] In a multi-finger GGNMOS structure, the base parasitic resistance of the NPNs at the edges of the structure is low. Based on the principle analysis above, when an ESD pulse is generated, a lower voltage is required to trigger avalanche breakdown. However, as the ESD voltage gradually increases, avalanche breakdown occurs at the center. Because the NPNs in the center have larger parasitic base resistances (R1+R2+R3, R4+R5+R6), their NPNs are more likely to turn on. Subsequently, the voltage in the center quickly clamps to the holding voltage, preventing the edges from turning on. Macroscopically, this results in a multi-finger NMOS structure with avalanche breakdown at the edges first, followed by an uneven current distribution that drives the NPNs in the center to turn on.

[0044] More specifically, after the edge of the structure is broken down by avalanche, the avalanche current generated by it flows toward the middle position. The base resistance of the parasitic NPN in the middle position is larger, resulting in a larger potential difference at the base NPN in the middle position, causing the potential difference at the base NPN in the middle position to reach 0.7V earlier, and ultimately causing the parasitic NPN in the middle position to be turned on first.

[0045] In view of this, the inventors conducted in-depth research and improvement exploration on the avalanche current, base resistance and turn-on time of the parasitic NPN in the GGNMOS structure, and found that: after the avalanche current is generated at the edge of the GGNMOS, if the base resistance of the parasitic NPN in the middle position of the GGNMOS structure is reduced, the turn-on time of the parasitic NPN in the middle position can be delayed; if the base resistance of the parasitic NPN at the edge position of the GGNMOS structure is increased, the turn-on time of the parasitic NPN at the edge position can be advanced, thereby making the turn-on of the GGNMOS structure more uniform.

[0046] Based on this, this specification proposes a solution: Figure 1 As shown, a uniformly turned-on GGNMOS structure of the present invention adopts a ring-shaped polysilicon gate structure, which makes the area efficiency of NMOS higher, thereby improving the overall current discharge capability;

[0047] By adding a P-type heavily doped active region in the middle position of each finger of the multi-finger gate-grounded NMOS and grounding the P-type heavily doped active region, the base region of the parasitic NPN of the GGNMOS (gate-grounded NMOS) can be connected to the ground through the middle position of each finger structure, thereby reducing the parasitic resistance from the base region of the middle parasitic NPN to the ground, so that the parasitic NPN in the middle position requires a higher current or voltage to be turned on, causing the middle position of the finger structure to be turned on with a delayed hysteresis or causing the middle finger structure to be turned on with a delayed hysteresis;

[0048] Furthermore, by implanting an N-type well-doped well region 40 between the annular N-type heavily doped active region 30 and the substrate, the path from the parasitic NPN base region at the edge of each finger unit to the surrounding P-type heavily doped active region is greatly increased, thereby increasing the base resistance of the edge parasitic NPN, so that the edge parasitic NPN can be turned on under a smaller avalanche current, thereby turning on the parasitic NPN of the edge structure in advance, and making the parasitic NPN of the edge structure and the parasitic NPN of the middle structure turn on more evenly;

[0049] Finally, adding a P-type heavily doped active area in the middle position can also make up for the problem that the reverse junction is difficult to break down and turn on due to the addition of an N-type well-doped well region 40 at the edge position, so that the overall structure can easily break down to generate avalanche current and can quickly enter a uniformly turned-on state.

[0050] The following describes the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0051] like Figures 1 to 4 As shown, the present invention provides a uniformly turned-on GGNMOS structure, comprising a P-type well-doped type well region 10, an annular P-type heavily doped active region 20, an annular N-type heavily doped active region 30, an N-type well-doped type well region 40, a plurality of strip-shaped N-type heavily doped active regions 50, a plurality of annular polysilicon gates 60, and a plurality of intermediate P-type heavily doped active regions 70 formed on a substrate. The annular P-type heavily doped active region 20 is implanted at the edge of the P-type well-doped type well region 10; the annular N-type heavily doped active region 30 is implanted at the edge of the P-type well-doped type well region 10, and is located on the inner side of the P-type heavily doped active region, and is isolated from the P-type heavily doped active region; the N-type well-doped type well region 40 is implanted in the P-type well-doped type well region 10 in an annular shape, and is located between the substrate and the annular N-type heavily doped active region 30; a plurality of strip-shaped N-type heavily doped active regions 50 are implanted in the P-type well-doped type well region 10 at intervals, and are The annular N-type heavily doped active area 30 is surrounded, and the annular N-type heavily doped active area 30 and the multiple strip-shaped N-type heavily doped active areas 50 are isolated and arranged; multiple annular polysilicon gates 60 are formed at intervals at the top of the P-type well-doped type well area 10, and the two longitudinal sides of each annular polysilicon gate 60 are correspondingly located between the two adjacent N-type heavily doped active areas 50; each intermediate P-type heavily doped active area 70 is correspondingly implanted into the middle of the strip-shaped N-type heavily doped active area 50 surrounded by an annular polysilicon gate 60, and is isolated and arranged from the strip-shaped N-type heavily doped active area 50.

[0052] The substrate is a P-type substrate, and a P-type well doping type well region 10 is formed on the substrate by ion implantation or the like.

[0053] like Figures 2 and 3As shown, the various parts of the present application are electrically connected to port T2 and port T1, and the electrical connection method is basically the same as the existing connection method, and the intermediate P-type heavily doped active area 70 in the present application is grounded through port T2 to be grounded through the metal contact hole 90, directly reducing the intermediate NPN base resistance and accurately controlling the turn-on voltage.

[0054] Among them, Figures 2 and 3 A schematic diagram of the parasitic NPN and an equivalent diagram of the base resistor are also shown.

[0055] The annular P-type heavily doped active region 20 and the annular N-type heavily doped active region 30 are located at the edge of the P-type well, and can form a low-resistance path.

[0056] Adding an N-type well-doping type well region 40 between the annular N-type heavily doped active region 30 and the substrate can increase the edge parasitic resistance, forcing the parasitic NPN base resistance in the edge and middle regions to be balanced.

[0057] The N-type well doping type well region 40 is also an annular structure, and its extending direction is the same as the extending direction of the annular N-type heavily doped active region 30 .

[0058] Among them, after the middle P-type heavily doped active region 70 is grounded, it can reduce the middle NPN base resistance, increase the turn-on voltage threshold of the middle region, and avoid premature clamping.

[0059] The strip-shaped N-type heavily doped active region 50 and the annular polysilicon gate 60 are used to improve area utilization, enhance the drift current path, and accelerate uniform conduction.

[0060] Among them, the annular P-type heavily doped active area 20, the annular N-type heavily doped active area 30, the N-type well-doped type well area 40 / the strip-shaped N-type heavily doped active area 50, and the middle P-type heavily doped active area 70 can all be implanted into the P-type well-doped type well area 10 by ion implantation or the like.

[0061] The present invention optimizes the parasitic resistance distribution and achieves uniform turn-on of multi-finger GGNMOS through the layout of the annular polysilicon gate 60, the middle P-type heavily doped active region 70 and the N-type well-doped well region 40, thereby solving the problem of the existing GGNMOS structure in which the middle region is preferentially turned on, the current is unevenly distributed, and the discharge efficiency is reduced due to the difference in parasitic base resistance during ESD events.

[0062] Furthermore, the width of the annular N-type heavily doped active area 30 is smaller than the width of the N-type well doping type well area 40 to ensure that the N-type well doping type well area 40 covers the annular N-type heavily doped active area 30, extending the parasitic base path to further improve the edge resistance.

[0063] Among them, by setting the width of the annular N-type heavily doped active area 30 to be smaller than the width of the N-type well doping type region, the N-type well is extended outward, thereby increasing the base path length (R7, R8, etc.), balancing the edge and middle resistance differences, and solving the problem that insufficient N-type well width may lead to insufficient edge resistance adjustment.

[0064] Furthermore, the middle P-type heavily doped active area 70 is isolated from the strip-shaped N-type heavily doped active area 50 by the annular STI region 80 to block direct contact between the middle P-type heavily doped active area 70 and the strip-shaped N-type heavily doped active area 50, thereby ensuring electrical isolation, avoiding leakage or premature conduction, preventing carrier diffusion, and maintaining structural stability.

[0065] Furthermore, the annular STI region 80 extends into the P-type well doping type well region 10 to evenly distribute the electric field, avoid local breakdown, and reduce the risk of hot spot effect.

[0066] Furthermore, a plurality of intermediate P-type heavily doped active regions 70 are implanted in the middle of the strip-shaped N-type heavily doped active region 50 surrounded by the polysilicon gate, and the plurality of intermediate P-type heavily doped active regions 70 are arranged at intervals to enhance the local base resistance adjustment capability.

[0067] Among them, by setting up multiple intermediate P-type heavily doped active areas 70, multi-point grounding can be used to disperse the current path and further balance the parasitic resistance distribution to solve the problem that a single intermediate P-type heavily doped active area 70 may not be able to fully cover the strip-shaped N-type heavily doped active area 50.

[0068] Furthermore, the annular P-type heavily doped active region 20 is isolated from the annular N-type heavily doped active region 30 by the STI region 80 , so as to eliminate unintended conduction paths and avoid reverse leakage or premature triggering.

[0069] Furthermore, the annular P-type heavily doped active region 20 is isolated from the substrate by the STI region 80 to improve noise immunity and block substrate coupling effects.

[0070] The width of the STI region 80 is greater than the width of the annular P-type heavily doped active region 20 .

[0071] Furthermore, the annular N-type heavily doped active region 30 is isolated by the STI region 80 and the plurality of strip-shaped N-type heavily doped active regions 50 to ensure that current flows along the designed path, optimize discharge efficiency, and avoid current path confusion.

[0072] Among them, STI can force current to pass through the channel region controlled by the polysilicon gate, thereby enhancing current controllability.

[0073] Furthermore, positions for connecting metal contact holes 90 are provided on the two lateral sides of the annular polysilicon gate 60, and the two lateral sides are located on the STI region 80 between the annular N-type heavily doped active area 30 and the multiple strip-shaped N-type heavily doped active areas 50, which are used to reduce contact resistance fluctuations. By being set in the STI region 80, it is also possible to ensure that the metal contact resistance is consistent and avoid local current concentration.

[0074] The present invention reduces the intermediate base resistance by grounding the intermediate P-type heavily doped active region 70, and simultaneously introduces the N-type well-doped well region 40 to increase the edge base resistance, forcing the multi-finger structure of the GGNMOS to be uniformly turned on. In addition, the layout of the annular polysilicon gate 60 and the strip-shaped N-type heavily doped region improves the area utilization, enhances the current discharge capability, and achieves a fast response, uniform conduction, and high robustness protection effect under ESD time.

[0075] This structure utilizes a ring-shaped polysilicon gate structure to achieve higher area utilization efficiency for the grounded gate NMOS, improving overall current discharge capability. By adding a heavily doped P-type active region in the center of a single cell structure (each finger) and connecting it to ground via metal contact 90, the base of the parasitic NPN structure in the center of the GGNMOS is connected to GND through the center of the cell structure. This reduces the parasitic resistance from the center NPN base to GND, requiring a higher voltage to turn on the center NPN. Simultaneously, the introduction of Nwells around the structure significantly increases the path from the center NPN base to the surrounding heavily doped P-type active regions, increasing their parasitic resistance (R7+R1+…; R8+R6+…), making it easier for the NPN to turn on.

[0076] In addition, since the resistance of R7 and R8 is much larger than the Pwell resistor, the parasitic NPN of the surrounding edge GGNMOS and the internal GGNMOS are turned on more evenly.

[0077] Finally, the P-type heavily doped active region added in the middle position can make up for the disadvantage that the reverse junction is more difficult to break down and turn on due to the addition of Nwell at the edge position, so that the structure can both break down more easily to generate avalanche current and quickly enter a uniform on state.

[0078] In this specification, references to the same or similar parts between the various embodiments can be made to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0079] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A uniformly turned-on GGNMOS structure, characterized in that: include: A P-type well doping type well region formed on the substrate; an annular P-type heavily doped active region, wherein the annular P-type heavily doped active region is implanted into the edge of the P-type well doping type well region; an annular N-type heavily doped active region, wherein the annular N-type heavily doped active region is implanted at the edge of the P-type well-doped well region, is located inside the annular P-type heavily doped active region, and is isolated from the annular P-type heavily doped active region; An N-type well-doped well region is implanted into the P-type well-doped well region in a ring shape and is located between the substrate and the ring-shaped N-type heavily doped active region; a plurality of strip-shaped N-type heavily doped active regions, wherein the plurality of strip-shaped N-type heavily doped active regions are implanted into the P-type well-doping type well region at intervals and are surrounded by the annular N-type heavily doped active region, and the annular N-type heavily doped active region and the plurality of strip-shaped N-type heavily doped active regions are isolated from each other; A plurality of annular polysilicon gates, wherein the plurality of annular polysilicon gates are spaced apart and formed at the top of the P-type well doping type well region, and the two longitudinal sides of each of the annular polysilicon gates are correspondingly located between two adjacent strip-shaped N-type heavily doped active regions; Multiple intermediate P-type heavily doped active regions are provided, each of the intermediate P-type heavily doped active regions is implanted into the middle portion of the strip-shaped N-type heavily doped active region surrounded by the annular polysilicon gate, and is isolated from the strip-shaped N-type heavily doped active region. The intermediate P-type heavily doped active region is grounded through a metal contact hole to reduce the parasitic resistance from the intermediate parasitic NPN base region to the ground.

2. The uniformly turned-on GGNMOS structure according to claim 1, wherein: The width of the annular N-type heavily doped active region is smaller than the width of the N-type well-doped well region.

3. The uniformly turned-on GGNMOS structure according to claim 1, wherein: The middle P-type heavily doped active region is isolated from the strip-shaped N-type heavily doped active region by the annular STI region.

4. The uniformly turned-on GGNMOS structure according to claim 3, wherein: The annular STI region extends into the P-type well doping type well region.

5. The uniformly turned-on GGNMOS structure according to any one of claims 1, 3, and 4, characterized in that: A plurality of the intermediate P-type heavily doped active regions are implanted into the middle of the strip-shaped N-type heavily doped active region surrounded by the polysilicon gate, and the plurality of the intermediate P-type heavily doped active regions are arranged at intervals.

6. The uniformly turned-on GGNMOS structure according to claim 1, wherein: The annular P-type heavily doped active region is isolated from the annular N-type heavily doped active region by an STI region.

7. The uniformly turned-on GGNMOS structure according to claim 1, wherein: The annular P-type heavily doped active region is isolated from the substrate by an STI region.

8. The uniformly turned-on GGNMOS structure according to claim 1, wherein: The annular N-type heavily doped active region is isolated from the plurality of strip-shaped N-type heavily doped active regions by the STI region.

9. The uniformly turned-on GGNMOS structure according to claim 8, characterized in that: Positions for connecting metal contact holes are provided on two lateral sides of the annular polysilicon gate, and the two lateral sides are located on the STI region between the annular N-type heavily doped active region and the plurality of strip-shaped N-type heavily doped active regions.

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