Chip packaging structure and light-emitting device

Abstract

The invention relates to a chip packaging structure and a light-emitting device. The chip packaging structure comprises a packaging body, a chip body and a through hole penetrating through the chip body, the packaging body comprises a packaging assembly, a first electrode layer and a second electrode layer, the chip body comprises an N-type semiconductor, a light-emitting layer, a P-type semiconductor and a reflecting layer which are stacked in sequence, the chip body is provided with a first conducting layer and a second conducting layer, and the first conducting layer and the second conducting layer are arranged on the packaging assembly. The through holes comprise a first through hole penetrating through the first area and a second through hole penetrating through the second area, and the first area and the second area are separated from each other; the packaging assembly is electrically connected with the second electrode layer and the power supply, the first electrode layer is electrically connected with the first conductive layer, the second electrode layer is electrically connected with the second conductive layer, the N-type semiconductor, the first conductive layer and the second conductive layer form a conductive path through the through holes, and the light emitting layer emits light based on the conductive path. By adopting the structure, the light emitting flexibility of the LED chip can be improved by arranging the first region and the second region which are independently conducted in the chip packaging structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a chip packaging structure and a light-emitting device. Background Art

[0002] With the continuous development of technology, the LED (Light Emitting Diode) chip packaging technology is in continuous iteration. LED light-emitting devices based on the LED chip packaging structure are widely used in various industries, such as automotive headlights, commercial lighting, street lighting, stage lighting, projectors, and mobile lighting.

[0003] Currently, lighting LEDs or COB LEDs (Chip On Board Light Emitting Diodes) and other light-emitting devices are usually composed of LED chips and LED packages, and most are single or multiple identical or different LED chips fixed on a packaging base to achieve a single-color LED light source, a multi-color LED light source, or a COB light source module. However, during the process of adjusting the light source of the light-emitting device, due to limitations such as the stability of the adjustment mechanism and the design of the light source module, it is difficult for the light-emitting device to switch the light source freely. Therefore, the current LED chips have poor light-emitting flexibility. Summary of the Invention

[0004] Based on this, in view of the above technical problems, it is necessary to provide a chip packaging structure and a light-emitting device that can improve the light-emitting flexibility of LED chips by providing a first region and a second region that are independently conducted under different through-holes with different current conduction capabilities in the chip packaging structure.

[0005] In a first aspect, the present application provides a chip packaging structure. The chip packaging structure includes a package body, a chip body, and through-holes that penetrate the chip body. Among them, the package body includes a packaging component, a first electrode layer located on the backlight side of the chip body, and a second electrode layer located on the opposite side of the backlight side of the chip body. The chip body includes an N-type semiconductor, a light-emitting layer, a P-type semiconductor, and a reflective layer stacked in sequence. A first conductive layer and a second conductive layer are oppositely arranged on the light-emitting side of the chip body. The through-holes include first through-holes that penetrate the first region of the reflective layer and second through-holes that penetrate the second region of the reflective layer, and the first region and the second region are separated from each other. Among them,

[0006] The encapsulation component is electrically connected to the second electrode layer and the power supply respectively. The first electrode layer is electrically connected to the first conductive layer, and the second electrode layer is electrically connected to the second conductive layer. The N-type semiconductor forms a conductive path with the first conductive layer and the second conductive layer respectively through the through holes, and light is emitted from the light-emitting layer based on the conductive path. Among them, the first current flowing through the first region is conducted through the first through hole, and the second current flowing through the second region is conducted through the second through hole. The magnitudes of the first current and the second current are different.

[0007] In one embodiment, the second region is all the regions surrounding the first region on the reflective layer except the first region. The first conductive layer includes a plurality of first electrode units, and the second conductive layer includes a plurality of second electrode units. The plurality of first electrode units and the plurality of second electrode units are symmetrically distributed on the reflective layer based on the central position of the reflective layer.

[0008] In one embodiment, the symmetrical distribution modes of the plurality of first electrode units and the plurality of second electrode units include one of the following:

[0009] The plurality of first electrode units and the plurality of second electrode units are matrix-symmetrically distributed on the reflective layer based on the central position of the reflective layer; the plurality of first electrode units and the plurality of second electrode units are stagger-symmetrically distributed on the reflective layer based on the central position of the reflective layer; the plurality of first electrode units and the plurality of second electrode units are spiral-symmetrically distributed on the reflective layer based on the central position of the reflective layer; the plurality of first electrode units and the plurality of second electrode units are mixed-symmetrically distributed on the reflective layer based on the central position of the reflective layer.

[0010] In one embodiment, the first electrode layer and the second electrode layer are electrically connected by a copper wire, and the first electrode layer is electrically connected to the plurality of first electrode units and the plurality of second electrode units respectively by a gold wire.

[0011] In one embodiment, the multiple first electrode units include a first electrode, a second electrode, and a third electrode, the multiple second electrode units include a fourth electrode, a fifth electrode, and a sixth electrode, the first electrode layer includes a first positive electrode, a second positive electrode, a third positive electrode, and a fourth positive electrode, the second electrode layer includes a first negative electrode, a second negative electrode, a third negative electrode, and a fourth negative electrode, the first positive electrode is electrically connected to the first negative electrode, the second positive electrode is electrically connected to the second negative electrode, the third positive electrode is electrically connected to the third negative electrode, the fourth positive electrode is electrically connected to the fourth negative electrode, the first positive electrode is electrically connected to the second electrode, the second positive electrode is respectively electrically connected to the first electrode and the third electrode, the third positive electrode is electrically connected to the fifth electrode, and the fourth positive electrode is respectively electrically connected to the fourth electrode and the sixth electrode.

[0012] In one embodiment, the first area of the first region is less than or equal to the second area of the second region, and the ratio of the area between the first area and the second area is , Satisfying: .

[0013] In one embodiment, the first current of the first through hole is greater than the second current of the second through hole, and the shapes of the first through hole and the second through hole are the same.

[0014] In one embodiment, the chip package structure includes one of the following:

[0015] The hole density of the first through hole is greater than the hole density of the second through hole; the number of the first through holes is greater than the number of the second through holes; the number of the first through holes is the same as the number of the second through holes, and the aperture of the first through hole is greater than the aperture of the second through hole.

[0016] In one embodiment, a conduction region is provided on the first electrode layer, and the chip body is welded to the central position of the conduction region.

[0017] In a second aspect, the present application further provides a method for manufacturing a chip packaging structure for manufacturing the chip packaging structure as described in the first aspect above. The method includes: disposing a packaging component, a first electrode layer on the backlight side of the chip body, and a second electrode layer on the side opposite to the backlight side of the chip body in the package. The chip body includes an N-type semiconductor, a light-emitting layer, a P-type semiconductor, and a reflective layer stacked in sequence, and a first conductive layer and a second conductive layer are oppositely disposed on the light-emitting side of the chip body. A first through hole penetrating through the first region of the reflective layer and a second through hole penetrating through the reflective layer are provided in the chip body, and the first region and the second region are separated from each other. Wherein, the packaging component is electrically connected to the second electrode layer and a power supply respectively, the first electrode layer is electrically connected to the first conductive layer, the second electrode layer is electrically connected to the second conductive layer, the N-type semiconductor forms a conductive path with the first conductive layer and the second conductive layer through the through holes respectively, and light is emitted from the light-emitting layer based on the conductive path. Among them, a first current flowing through the first region is conducted through the first through hole, a second current flowing through the second region is conducted through the second through hole, and the magnitudes of the first current and the second current are different.

[0018] In a third aspect, the present application further provides a light-emitting device, including a light-emitting component and the chip packaging structure as described in the first aspect above. The chip packaging structure is welded to the light-emitting component through the second electrode layer.

[0019] The above-mentioned chip packaging structure and light-emitting device are jointly composed of a packaging body, a chip body, and a through-hole that penetrates the chip body. Among them, the packaging body includes a packaging component, a first electrode layer located on the backlight side of the chip body, and a second electrode layer located on the opposite side of the backlight side of the chip body. The chip body includes an N-type semiconductor, a light-emitting layer, a P-type semiconductor, and a reflective layer stacked in sequence. A first conductive layer and a second conductive layer are oppositely arranged on the light-emitting side of the chip body. The through-hole includes a first through-hole that penetrates the first region of the reflective layer and a second through-hole that penetrates the second region of the reflective layer. The first region and the second region are separated from each other. Among them, since the packaging component is respectively connected to the second electrode layer and the power supply, and the first electrode layer is electrically connected to the first conductive layer, and the second electrode layer is electrically connected to the second conductive layer, a conductive path is formed between the N-type semiconductor and the first conductive layer through the through-hole, and light is emitted from the light-emitting layer based on the conductive path. Among them, the first current flowing through the first region is conducted through the first through-hole, and the second current flowing through the second region is conducted through the second through-hole. The magnitudes of the first current and the second current are different. That is, the current of the conduction circuit passes through different through-holes that penetrate the chip and is transmitted between the N-type semiconductor, the light-emitting layer, the P-type semiconductor, and the reflective layer of the chip body. Specifically, the first current of the conduction circuit sequentially flows through the power supply, the second electrode layer, the P-type semiconductor, the light-emitting layer, and the N-type semiconductor, and then flows through the first through-hole to the first conductive layer and the first electrode layer, thereby forming a current loop. The second current of the conduction circuit sequentially flows through the power supply, the second electrode layer, the P-type semiconductor, the light-emitting layer, and the N-type semiconductor, and then flows through the second through-hole to the second conductive layer and the second electrode layer. Furthermore, it allows the current of the conductive path to pass through different current channels provided by the first through-hole and the second through-hole, enabling the first region and the second region of the reflective layer to emit light independently, thereby achieving the purpose of the partition dimming function of the chip packaging structure. At the same time, since the first region and the second region are separated from each other, the first current flowing through the first region and the second current flowing through the second region do not interfere with each other. Therefore, by setting different first through-holes and second through-holes in the chip packaging structure and transmitting different first currents and second currents on the conductive path through different through-holes, it is possible to enable different light-emitting regions of the LED light-emitting device to emit light independently, rather than the LED light-emitting device can only emit light uniformly, or by setting an adjustment mechanism and designing multiple light source modules for light source adjustment. Therefore, it overcomes the technical defect that it is difficult for the light-emitting device to freely switch the light source due to factors such as the stability of the adjustment mechanism and the design of the light source module, and improves the light-emitting flexibility of the LED chip. Description of the Drawings

[0020] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the accompanying drawings required in the description of the embodiments of the present application or related technologies. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a schematic structural diagram of a chip packaging structure in an embodiment;

[0022] Figure 2 It is a general schematic diagram of a chip packaging structure in an embodiment;

[0023] Figure 3 It is a schematic diagram of a reflective layer after a through hole penetrates the reflective layer in an embodiment;

[0024] Figure 4 It is a schematic diagram of the distribution of multiple first electrode units and multiple second electrode units in an embodiment;

[0025] Figure 5 It is a design schematic diagram of a first electrode layer and a second electrode layer in an embodiment;

[0026] Figure 6 It is an exploded schematic diagram of a chip packaging structure in an embodiment. Detailed implementation manners

[0027] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the following further details the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] First of all, it should be understood that LED lighting devices applying LED chip packaging technology have been widely used in the fields of solid-state lighting, display, and mobile lighting, etc., due to their advantages such as high luminous efficiency, long service life, and high working environmental friendliness. Traditional LED chip packaging technologies mainly include DIP (Dual In-line Package), SMD (Surface Mounted Device), and COB (Chip On Board), etc. For lighting LEDs or COB LEDs, they are usually composed of LED chips and LED packages. Usually, at least one identical or different LED chip is fixed on the packaging base to realize a single-color LED light source, a multi-color LED light source, or a COB light source module. Among them, the multi-color LED light source or the COB light source module can meet different color temperature or color requirements in the case of a single light source, but neither can achieve the light source switching of the product on the light source, such as high and low beam switching, etc. In the mobile lighting market, there are usually the following two types for the realization of high and low beam switching: 1) One type is that a single LED completes the switching by adjusting the position of the lens; 2) The other type is to use two independent groups of LEDs on a larger light-emitting surface, for example, using one group of LEDs to generate high beam and using another group of LEDs to generate low beam. However, both of the above two switching methods have their own defects. The former uses a single LED to achieve high and low beam switching by adjusting the position of the lens, which has problems with the reliability of the adjustment mechanism and the waterproofness of the product, and is prone to color difference problems such as blue light leakage and yellow light leakage during the adjustment process. To sum up, it can be seen that the current lighting device is difficult to freely switch the light source. Therefore, there is an urgent need for a chip packaging structure that can improve the lighting flexibility of LED chips.

[0029] In one embodiment, as Figure 1As shown, a chip packaging structure is provided. The chip packaging structure includes a chip body 11, a packaging body 12, and a through hole 13 that penetrates the chip body 11. Among them, the packaging body 12 includes a packaging component 121, a first electrode layer 122 located on the backlight side of the chip body 11, and a second electrode layer 123 located on the opposite side of the backlight side of the chip body 11. The chip body 11 includes an N-type semiconductor 110, a light-emitting layer 111, a P-type semiconductor 112, and a reflective layer 113 stacked in sequence. A first conductive layer 1 and a second conductive layer 115 are oppositely arranged on the light-emitting side of the chip body 11. The through hole 13 includes a first through hole 131 that penetrates the first region of the reflective layer 113 and a second through hole 132 that penetrates the second region of the reflective layer 113. The first region and the second region are separated from each other. Among them, the packaging component 121 is electrically connected to the second electrode layer 123 and the power supply respectively. The first electrode layer 122 is electrically connected to the first conductive layer 1, and the second electrode layer 123 is electrically connected to the second conductive layer 115. The N-type semiconductor 110 forms a conductive path with the first conductive layer 1 and the second conductive layer 115 through the through hole 13 respectively, and light is emitted from the light-emitting layer 111 based on the conductive path. Among them, a first current flowing through the first region is conducted through the first through hole 131, and a second current flowing through the second region is conducted through the second through hole 132. The magnitudes of the first current and the second current are different.

[0030] In an implementable manner, the N-type semiconductor 110 is located at the uppermost layer of the chip body 11. The first through hole 131 and the second through hole 132 that penetrate the chip body 11 both penetrate the N-type semiconductor 110 by half. The first through hole 131 that penetrates the chip body 11 sequentially penetrates the light-emitting layer 111, the P-type semiconductor 112, and the reflective layer 113 from top to bottom. The second through hole 132 that penetrates the chip body 11 sequentially penetrates the light-emitting layer 111, the P-type semiconductor 112, and the reflective layer 113 from top to bottom, so as to ensure that the first current flowing through the first region and the second current flowing through the second region can efficiently flow through each component of the chip packaging structure. Among them, the first conductive layer 1 and the second conductive layer 115 are oppositely arranged on the light-emitting side of the chip body 11. It can be understood that the packaging component 121 can be specifically electrically connected to the second electrode layer 123 and the power supply through conductive adhesive respectively. The first electrode layer 122 and the first conductive layer 1 can be specifically electrically connected through electrode contact points. The second electrode layer 123 and the second conductive layer 115 can be specifically electrically connected through electrode contact points. To ensure the formation of a complete current loop, the first electrode layer 122 is also connected to the P-type semiconductor 112 through a conductive material (sidewall metallization). The second electrode layer 122 is also connected to the P-type semiconductor 112 through a conductive material (sidewall metallization). The conductive path includes a first conductive path and a second conductive path. The N-type semiconductor 110 and the first conductive layer 1 form a first conductive path through the first through hole 131. The N-type semiconductor 110 and the second conductive layer 115 form a second conductive path through the second through hole. The path of the first current flowing through the first region starts from the power supply and sequentially flows through the second electrode layer 123, sidewall metallization, P-type semiconductor 112, light-emitting layer 111, N-type semiconductor 110, first through hole 131, first conductive layer 1, and first electrode layer 122. The path of the second current flowing through the second region starts from the power supply and sequentially flows through the second electrode layer 123, sidewall metallization, P-type semiconductor 112, light-emitting layer 111, N-type semiconductor 110, second through hole 132, second conductive layer 115, and second electrode layer 123.

[0031] It should be noted that the chip packaging structure can not only provide physical protection conditions for the LED chip, thereby extending the service life of the LED chip in the working state, but also improve the performance of the chip in terms of integration, maintainability and scalability; the P-N junction formed by the P-type semiconductor and the N-type semiconductor is the essential reason for the LED chip to emit light. When a forward voltage is applied to both ends of the P-N junction through different conductive paths by the power supply, the first conductive path and the second conductive path flow through different current paths to the first electrode layer and the second electrode layer, so that the recombination of forward carriers and negative carriers occurs near the P-N junction. During the recombination process, the excess energy is emitted to the external space in the form of photons, and finally light emission is achieved. Since the magnitudes of the first current and the second current are different, the LED chip can be directly controlled to emit light with different luminous intensities in different regions. For example, in an implementable manner, assuming that the first current is greater than the second current and the lighting device is a dimmable LED ceiling lamp, different independently light-emitting regions designed by the chip packaging structure can meet the lighting needs of users in different scenarios. Specifically, when the user is reading, the first conductive path can be turned on to emit light with a strong luminous intensity in the light-emitting layer, and when the user is resting, the second conductive path can be turned on to emit light with a weak luminous intensity in the light-emitting layer.

[0032] It should be noted that the encapsulation body is a module with specific functions formed by encapsulating the LED chip and its necessary circuits. In the traditional chip packaging structure, the electrodes are usually directly arranged on the light-emitting surface. This causes some light to be blocked due to the emission angle when the light-emitting layer emits light at different emission angles, resulting in light loss problems. Therefore, in this embodiment, the electrodes are divided into a first electrode layer and a second electrode layer. Among them, the first electrode layer is arranged on the backlight side of the chip body, and the second electrode layer is arranged on the side opposite to the backlight side of the chip body. On the one hand, it can avoid the current crowding situation inside the chip. On the other hand, the light path is optimized by adjusting the position of the electrode layer, so as to reduce the scattering and reflection losses of light inside the chip, and finally achieve the purpose of improving the light extraction efficiency of the chip body. The encapsulation component is used to support the integration of the LED chip and its necessary components. For example, in an implementable manner, the first electrode layer is the upper electrode layer, the second electrode layer is the lower electrode layer, and the encapsulation component is a support welding part. The upper electrode layer, the encapsulation component, and the lower electrode layer are stacked in sequence from top to bottom. The support welding part is welded to the circuit board, enabling the chip packaging to be applied to various light-emitting devices. Among them, a positive electrode and a negative electrode are arranged on the first electrode layer, and a positive electrode and a negative electrode are also arranged on the second electrode layer. The number of positive and negative electrodes arranged on the first electrode layer and the second electrode layer can be set based on requirements. For example, in an implementable manner, the first electrode layer is provided with positive electrode 1 and negative electrode 1, and the second electrode layer is provided with positive electrode 2 and negative electrode 2. Among them, positive electrode 1 and positive electrode 2 are correspondingly distributed, negative electrode 1 and negative electrode 2 are correspondingly distributed, positive electrode 1 and negative electrode 1 are connected through a metal connection hole, and positive electrode 2 and negative electrode 2 are connected through a metal connection hole.

[0033] It should be noted that the chip body is the carrier of the integrated circuit. It can be understood that multiple chip layers are stacked inside the chip body due to different manufacturing processes. With the reduction of the chip size and the improvement of the chip integration degree requirements, the wire bonding technology in the traditional chip packaging structure is obviously difficult to meet the high-density and high-speed connection requirements. Therefore, to meet the connection requirements between different chip layers, through holes are drilled in the chip body and filled with metal to obtain through holes that penetrate the chip body. It can be understood that the N-type semiconductor of the chip body and the first conductive layer are connected by the first through hole and the second through hole. Among them, the first current flowing through the first through hole can be less than the second current flowing through the second through hole, and the first current flowing through the first through hole can also be greater than the second current flowing through the second through hole. At the same time, the number and deployment positions of the first through hole and the second through hole are not specifically limited in this embodiment. The shapes of the first through hole and the second through hole can be the same or different. For example, in an implementable manner, both the first through hole and the second through hole can be arranged in an array at a preset interval on each chip layer of the chip body. Among them, when the through hole areas of the first through hole and the second through hole are different, the first through hole and the second through hole will have different current guiding capabilities.

[0034] It can be understood that the structure of the light-emitting layer can specifically be a quantum well, a single heterojunction, and a double heterojunction. The first conductive layer can specifically be an N electrode layer, and the second conductive layer can specifically be a P electrode layer. By relatively disposing the first conductive layer and the second conductive layer on the reflective layer, it can help form an effective current injection channel, enabling electrons and holes to be injected into the light-emitting layer from the N electrode layer and the P electrode layer respectively, thereby realizing the recombination luminescence of carriers. Synchronously, it also reflects the photons that could originally escape or be absorbed on the reflective layer back to the optoelectronic conversion region, thereby enhancing the absorption degree of the light generated by the light-emitting layer in the optoelectronic material, and further enabling the improvement of the optoelectronic conversion efficiency of the LED chip. Among them, the reflective layer can be made of a material with a high reflectivity, and the material with a high reflectivity can specifically be metal materials such as silver and aluminum. For example, in an implementable manner, the P electrode layer is disposed on one side of the reflective layer, and the N electrode layer is disposed on the opposite side of the reflective layer, so that the P electrode layer and the N electrode layer are symmetrically distributed based on the central position of the reflective layer, thereby being able to reduce the local current crowding situation and contribute to the improvement of current uniformity. At the same time, the symmetrically distributed current distribution makes the heat distribution inside the device relatively uniform, thereby improving the reliability and lifespan of the device.

[0035] As an example, an N-type semiconductor, a quantum well, a P-type semiconductor, a reflective layer (with a P electrode layer and an N electrode layer relatively disposed on the reflective layer), an upper electrode layer, a packaging component, and a lower electrode layer are sequentially stacked from top to bottom in a direction perpendicular to the surface of the device substrate. Among them, the N-type semiconductor, the quantum well, the P-type semiconductor, and the reflective layer together constitute the chip body of the chip packaging structure, and the upper electrode layer, the packaging component, and the lower electrode layer together constitute the package body of the chip packaging structure. The chip body, the package body, and the through holes penetrating the chip body together constitute the chip packaging structure. The through holes include a first through hole and a second through hole. Multiple pins are deployed on the packaging component, and the packaging component is connected to the power supply and the second electrode layer through different pins. The first electrode layer is electrically connected to the first conductive layer, and the second electrode layer is electrically connected to the second conductive layer. The N-type semiconductor and the first conductive layer form a first conductive path through the first through hole, and the N-type semiconductor and the second conductive layer form a second conductive path through the second through hole, and luminescence occurs in the light-emitting layer based on the first conductive path and the second conductive path. Among them, the first current flowing through the first region is different from the second current flowing through the second region, and the first region and the second region emit light independently. The first region and the second region can emit light at the same time point or at different time points.

[0036] The chip packaging structure of this embodiment is jointly composed of a package body, a chip body, and a through hole that penetrates the chip body. Among them, the package body includes a packaging component, a first electrode layer located on the backlight side of the chip body, and a second electrode layer located on the opposite side of the backlight side of the chip body. The chip body includes an N-type semiconductor, a light-emitting layer, a P-type semiconductor, and a reflective layer stacked in sequence. A first conductive layer and a second conductive layer are oppositely arranged on the light-emitting side of the chip body. The through hole includes a first through hole that penetrates the first region of the reflective layer and a second through hole that penetrates the second region of the reflective layer. The first region and the second region are separated from each other. Among them, since the packaging component is respectively connected to the second electrode layer and the power supply, and the first electrode layer is electrically connected to the first conductive layer, and the second electrode layer is electrically connected to the second conductive layer, a conductive path is formed between the N-type semiconductor and the first conductive layer through the through hole, and based on the conductive path, light is emitted from the light-emitting layer. Among them, the first current flowing through the first region is conducted through the first through hole, and the second current flowing through the second region is conducted through the second through hole. The magnitudes of the first current and the second current are different. That is, the current of the conduction circuit passes through different through holes that penetrate the chip, and is transmitted between the N-type semiconductor, the light-emitting layer, the P-type semiconductor, and the reflective layer of the chip body. Specifically, the first current of the conduction circuit sequentially flows through the power supply, the second electrode layer, the P-type semiconductor, the light-emitting layer, and the N-type semiconductor, and then flows through the first through hole to the first conductive layer and the first electrode layer, thereby forming a current loop. The second current of the conduction circuit sequentially flows through the power supply, the second electrode layer, the P-type semiconductor, the light-emitting layer, and the N-type semiconductor, and then flows through the second through hole to the second conductive layer and the second electrode layer. Furthermore, it is possible to allow the current of the conductive path to pass through different current channels provided by the first through hole and the second through hole, so that the first region and the second region of the reflective layer emit light independently, thereby achieving the purpose of the partition dimming function of the chip packaging structure. At the same time, since the first region and the second region are separated from each other, the first current flowing through the first region and the second current flowing through the second region do not interfere with each other. Therefore, by providing different first through holes and second through holes in the chip packaging structure, and transmitting different first currents and second currents on the conductive path through different through holes, it is possible to make different light-emitting regions of the LED lighting device emit light independently, rather than the LED lighting device can only emit light uniformly, or by setting an adjustment mechanism and designing multiple light source modules for light source adjustment. Therefore, it overcomes the technical defect that due to the limitations of factors such as the stability of the adjustment mechanism and the design of the light source module, it is difficult for the lighting device to freely switch the light source, and improves the lighting flexibility of the LED chip.

[0037] In an implementable manner, referring to Figure 2 , Figure 2 is a general schematic diagram showing the chip packaging structure. Among them, the chip packaging structure includes two parts: a chip body and a package body.

[0038] In one embodiment, as Figure 3 shown, Figure 3 is a schematic diagram showing the reflective layer after the through-hole penetrates the reflective layer. Among them, the first conductive layer and the second conductive layer are oppositely arranged on the reflective layer 113. The first region and the second region are defined on the reflective layer 113. The first region is penetrated by the first through-hole, and the second region is penetrated by the second through-hole. The second region is all the regions on the reflective layer 113 that surround the first region except the first region. That is, the surface region of the reflective layer 113 is divided into a first region and a second region that are separated from each other. It can be understood that the first conductive layer includes a plurality of first electrode units, and the second conductive layer includes a plurality of second electrode units. The plurality of first electrode units and the plurality of second electrode units are symmetrically distributed on the reflective layer 113 based on the central position of the reflective layer 113.

[0039] In an implementable manner, the first region is a circular region with a radius of R on the reflective layer, and the second region is all the regions on the surface region except the circular region. The plurality of first electrode units are equidistant, the plurality of second electrode units are equidistant, and the plurality of first electrode units and the plurality of second electrode units are symmetrically distributed one by one on the reflective layer based on the central position of the reflective layer.

[0040] It should be noted that the first region and the second region together constitute the surface region of the reflective layer. Specifically, the first region and the second region can be separated from each other by an insulating dielectric layer. Among them, the insulating dielectric layer can specifically be , or etc.; the first region and the second region can also be separated from each other by semiconductor insulation. Among them, the material of the semiconductor insulation groove can be the same as the base material; the plurality of first electrode units can be understood as a plurality of electrode contact points distributed at different positions, and the plurality of second electrode units can be understood as a plurality of electrode contact points distributed at different positions. The specific positions of the plurality of first electrode units and the plurality of second electrode units can be set according to design requirements.

[0041] In one embodiment, the symmetric distribution modes of the plurality of first electrode units and the plurality of second electrode units include one of the following:

[0042] The plurality of first electrode units and the plurality of second electrode units are symmetrically distributed in a matrix on the reflective layer based on the central position of the reflective layer; the plurality of first electrode units and the plurality of second electrode units are symmetrically distributed in a staggered manner on the reflective layer based on the central position of the reflective layer; the plurality of first electrode units and the plurality of second electrode units are symmetrically distributed in a spiral manner on the reflective layer based on the central position of the reflective layer; the plurality of first electrode units and the plurality of second electrode units are symmetrically distributed in a mixed manner on the reflective layer based on the central position of the reflective layer.

[0043] It should be noted that the multiple first electrode units and the multiple second electrode units can be arranged on the reflective layer according to row and column rules to form a mesh structure, thereby presenting a matrix-like symmetrical distribution, wherein the row and column rules can specifically be that all electrode units are symmetrically distributed in the horizontal direction, or that all electrode units are symmetrically distributed in the vertical direction; the multiple first electrode units and the multiple second electrode units can also be arranged alternately on the reflective layer to form a checkerboard symmetrical structure; the multiple first electrode units and the multiple second electrode units can also be arranged in a spiral shape outward with the center position of the reflective layer as the base point to form a symmetrical radiation structure; the multiple first electrode units and the multiple second electrode units can also be distributed on the reflective layer according to a pre-set rule combination to form a complex symmetrical structure.

[0044] In one practicable manner, referring to Figure 4 , Figure 4 The diagram is a distribution diagram of multiple first electrode units and multiple second electrode units, wherein the multiple first electrode units include chip electrode 1, chip electrode 2 and chip electrode 3, the multiple second electrode units include chip electrode 4, chip electrode 5 and chip electrode 6, the first area D1 is a circular light-emitting area, the second area D2 is an area surrounding the first area D1, and the chip electrode 1, chip electrode 2, chip electrode 3, chip electrode 4, chip electrode 5 and chip electrode 6 are symmetrically distributed in a matrix based on the center position of the first area.

[0045] In this embodiment, a plurality of first electrode units and a plurality of second electrode units are arranged on the reflective layer, and they are symmetrically distributed in different symmetrical distribution forms. On the one hand, the symmetrical structure can ensure uniform distribution of the electric field between the electrode unit and the reflective layer. On the other hand, different symmetrical distribution methods can be used to achieve targeted design based on application requirements of different scenarios. Therefore, by setting different types of symmetrical distribution methods of electrode units, the light-emitting flexibility of the LED chip can be further improved.

[0046] In one embodiment, the first electrode layer and the second electrode layer are electrically connected through copper wires, and the first electrode layer is electrically connected to the plurality of first electrode units and the plurality of second electrode units through gold wires.

[0047] It should be noted that for the actual electrical connection scenarios between the first electrode layer and the second electrode layer, the first electrode unit, and the second electrode unit, corresponding wires can be set to achieve electrical connection in combination with the characteristics of different wires. Among them, copper wires have characteristics such as low resistivity and low cost, and are suitable for long-distance and large-current transmission. Gold wires have characteristics such as high conductivity and strong oxidation resistance, and are suitable for large-area connection scenarios. Furthermore, since there is a need to electrically connect the first electrode layer and the second electrode layer with an intervening encapsulation component, therefore, in the case of using copper wires for electrical connection, and since the first conductive layer and the second conductive layer are respectively provided with multiple electrode units, therefore, in the case of using gold wires for electrical connection. For example, in an implementable manner, assume that the encapsulation component includes an encapsulation base and a welding base. Among them, the encapsulation base is used to provide a fixed platform for the components within the package, so that the chip encapsulation base will not shift during the encapsulation process. The welding base is used to weld the chip encapsulation structure and the external circuit board. The first electrode layer is the upper electrode layer, and the second electrode layer is the lower electrode layer. The first electrode layer and the second electrode layer are electrically connected one-to-one through drilling and copper plating of the encapsulation base of the intermediate layer (encapsulation component). Multiple first electrode units and multiple second electrode units are respectively connected to the first electrode layer through gold wire bonding, thereby providing an electrical connection path.

[0048] In this embodiment, for the electrical connection requirements between different electrode layers, different types of wires are set to achieve electrical connection between the electrodes. Therefore, while laying a foundation for improving the lighting flexibility of the LED chip, the practicality of the LED chip is improved.

[0049] In one embodiment, multiple first electrode units include a first electrode, a second electrode, and a third electrode. Multiple second electrode units include a fourth electrode, a fifth electrode, and a sixth electrode. The first electrode layer includes a first positive electrode, a second positive electrode, a third positive electrode, and a fourth positive electrode. The second electrode layer includes a first negative electrode, a second negative electrode, a third negative electrode, and a fourth negative electrode. The first positive electrode is electrically connected to the first negative electrode, the second positive electrode is electrically connected to the second negative electrode, the third positive electrode is electrically connected to the third negative electrode, and the fourth positive electrode is electrically connected to the fourth negative electrode. The first positive electrode is electrically connected to the second electrode, the second positive electrode is respectively electrically connected to the first electrode and the third electrode, the third positive electrode is electrically connected to the fifth electrode, and the fourth positive electrode is respectively electrically connected to the fourth electrode and the sixth electrode.

[0050] It should be noted that to improve the reliability of the circuit, during the design process of the chip encapsulation structure, a redundant design of the current path is carried out to prevent the entire circuit from failing due to a single-point failure. Furthermore, multiple positive electrode contact points are deployed on the first electrode layer, multiple negative electrode contact points are deployed on the second electrode layer, and multiple electrode units are respectively electrically connected to the multiple electrode contact points according to a preset electrical connection method.

[0051] In an implementable manner, referring to Figure 5 ,Figure 5 It is a design schematic diagram showing the first electrode layer and the second electrode layer. Among them, the first electrode layer is the upper electrode layer, and the second electrode layer is the lower electrode layer. The upper electrode layer includes a first positive electrode T1, a second positive electrode T2, a third positive electrode T3, and a fourth positive electrode T4. The lower electrode layer includes a first negative electrode B1, a second negative electrode B2, a third negative electrode B3, and a fourth negative electrode B4. The first positive electrode T1 corresponds to the first negative electrode B1, the second positive electrode T2 corresponds to the second negative electrode B2, the third positive electrode T3 corresponds to the third negative electrode B3, and the fourth positive electrode T4 corresponds to the fourth negative electrode B4. Among them, the multiple first electrode units include a first electrode S1, a second electrode S2, and a third electrode S3. The multiple second electrode units include a fourth electrode S4, a fifth electrode S5, and a sixth electrode S6. Among them, the first electrode S1 and the third electrode S3 are connected to the third positive electrode T2, the second electrode S2 is connected to the first electrode T1, the fourth electrode S4 and the sixth electrode S6 are connected to the second positive electrode T4, and the fifth electrode S5 is connected to the third positive electrode T3, thus jointly realizing the electrical connection function of the chip packaging structure.

[0052] In this embodiment, by setting the electrical connection paths between the first electrode layer and the second electrode layer and the multiple first electrode units and the multiple second electrode units respectively, a foundation is laid for the independent light emission of the first region and the second region. At the same time, through the redundant design of the electrical transmission path, the light emission stability of the LED chip is further improved.

[0053] In one embodiment, the area of the first region of the first region is less than or equal to the area of the second region of the second region, and the area ratio between the area of the first region and the area of the second region is , satisfying: .

[0054] It should be noted that the through holes are provided in different chip layers of the chip body, which will affect the transmission of light to a certain extent due to the area. However, the uniform distribution of current during this process can increase the light intensity. Therefore, there is an area ratio that has a positive effect on the light conversion efficiency of the chip packaging structure. Among them, the area of the first region of the first region is less than or equal to the area of the second region of the second region. Let the area ratio between the area of the first region and the area of the second region be , satisfying: , specifically, can be , , or 1, etc.

[0055] In an implementable manner, the first region is the central region of the emission layer, and the second region is the edge region on the reflective layer except the central region. By defining the ratio of the area of the central region to the edge region, the light-emitting effects of different independent light-emitting regions can be differentiated.

[0056] In one embodiment, the chip packaging structure includes one of the following: the hole density of the first through-hole is greater than that of the second through-hole; the number of the first through-holes is greater than that of the second through-holes; the number of the first through-holes is the same as that of the second through-holes, and the aperture of the first through-hole is greater than that of the second through-hole.

[0057] It should be noted that by further increasing the hole density of the first through-holes in the first region and reducing the hole density of the second through-holes in the second region, the light-emitting effects of different regions of the chip packaging structure can be optimized specifically. For example, in an implementable manner, setting the hole density of the first through-holes in the first region to be greater than that of the second through-holes in the second region can result in higher light conversion efficiency and larger luminous flux, thereby enhancing the floodlight effect of the chip packaging structure. Setting the number of the first through-holes in the first region to be greater than that of the second through-holes in the second region can make the light intensity more concentrated in the first region, thereby achieving the purpose of increasing the light intensity and enhancing the irradiation distance of the chip packaging structure. At the same time, due to the concentrated light intensity in the first region, the heating temperature of the central region of the reflective layer is higher, while the second region has a lower heating temperature due to the weaker light intensity. Therefore, there will be a phenomenon of temperature transfer on the chip body of the chip packaging structure, that is, the second region with a lower temperature assists the first region with a higher temperature in heat dissipation.

[0058] It can be understood that after differentiating the current conduction capabilities of the first region and the second region, in the design of the light-emitting region, by setting the N-electrode via distribution and designing high-density vias in the first region, the current density is increased, resulting in a higher light density in the first region, and finally making the first region have the effect of higher far-light intensity. At the same time, by setting the N-electrode in the second region to have a lower via density, while reducing the current density in the second region, the current utilization rate can be improved, thereby enhancing the light efficiency, and finally making the second region have the effect of higher near-light luminous flux. Since the first region and the second region emit light independently, through the chip packaging structure set in this embodiment, far light and near light can be generated in different light-emitting regions respectively, so the effect of freely switching between far light and near light can be achieved on the light source.

[0059] In one embodiment, the first electrode layer is provided with a conduction region, and the chip body is welded to the central position of the conduction region.

[0060] It should be noted that, to meet the actual application requirements, the conduction region of the first electrode layer and the central welding design of the chip body can be carried out. At the same time, the chip body is welded at the central position of the conduction region, which can make the electric field and current path symmetrical, thereby reducing the parasitic effects brought by the asymmetrical structure.

[0061] In an implementable manner, the first electrode layer is the upper electrode layer, the conduction region can adopt a copper plating design, and the LED chip can be welded to the exact center of the square area in the middle of the top layer of the upper electrode layer.

[0062] In an embodiment, the package body further includes a metal dam. The metal dam and the first electrode layer are located on the same layer. The package assembly includes a package base and a welding base. The first electrode layer, the package base, the second electrode layer, and the welding base are stacked and welded in a first preset direction in sequence.

[0063] It can be understood that the package body can also be provided with a metal dam. The metal dam and the first electrode layer are located on the same layer. The package assembly specifically includes a package base and a welding base. Among them, the first electrode layer, the package base, the second electrode layer, and the welding base are stacked and welded in sequence. Among them, the metal dam is used to improve the stability of the package body. It can be understood that electrical transmission paths for electrically connecting conductive paths are provided inside both the package base and the welding base. For example, in an implementable manner, assuming the first electrode layer is the upper electrode layer and the second electrode layer is the lower electrode layer, the package body is stacked in sequence from top to bottom in a direction perpendicular to the surface of the base, including the upper electrode layer, the package base, the lower electrode layer, and the welding base. Among them, the metal dam is on the same layer as the upper electrode layer, and the welding base is welded to an external circuit board.

[0064] Since the package body is jointly composed of the first electrode layer, the second electrode layer, the package base, the welding base, and the metal dam, it can ensure the stability of the chip packaging structure during the packaging process.

[0065] It can be understood that the chip body can also be provided with a metal bonding layer and a chip base. Among them, the chip base is electrically connected to the first electrode layer, and the first conductive layer is arranged on the metal bonding layer. Among them, the N-type semiconductor, the light-emitting layer, the P-type semiconductor, the reflective layer, and the metal bonding layer are stacked in sequence and then bonded to the chip base through the metal bonding layer. The bottom surface area of the first electrode layer is larger than the bottom surface area of the chip base.

[0066] It should be noted that since the current in the conductive path is transmitted between chip bodies through vias, in order to increase the light intensity, the current flowing through different vias can be converged by using a metal bonding layer. The metal bonding layer can specifically be copper and its alloys or silver and its alloys. The first electrode layer is connected to the chip base. Since welding is required between the first electrode layer and the chip base, the bottom surface area of the first electrode layer can be set to be larger than that of the chip base, facilitating the connection and welding of the circuit.

[0067] For example, in an implementable manner, assuming that the first electrode layer is the upper electrode layer, the first conductive layer is the N electrode layer, and the second conductive layer is the P electrode layer, in the chip packaging structure of this embodiment, the N-type semiconductor, light-emitting layer, P-type semiconductor, reflective layer including the P electrode layer and the N electrode layer, and metal bonding layer of the chip body are stacked in sequence from top to bottom in a direction perpendicular to the surface of the base.

[0068] It can be understood that the encapsulation component can further be provided with a fluorescent layer. The fluorescent layer includes uniformly distributed fluorescent substances. The fluorescent layer is coated on the surface of the N-type semiconductor, and the fluorescent layer and the N-type semiconductor are stacked in sequence. Since after the chip packaging structure is placed in different light-emitting devices, ordinary white light may not meet the user's usage requirements, a fluorescent layer can be provided on the outermost layer of the chip packaging structure. The fluorescent layer is used to absorb the light emitted by the light-emitting layer. The fluorescent layer includes uniformly distributed fluorescent substances. The fluorescent layer is coated on the surface of the N-type semiconductor, and the fluorescent layer and the N-type semiconductor are stacked in sequence. The fluorescent substances uniformly distributed in the fluorescent layer can specifically be fluorescein isothiocyanate, tetramethyl rhodamine, tetramethyl isothiocyanate rhodamine, or phycoerythrin, etc.

[0069] In an implementable manner, with reference to Figure 6 , Figure 6Explosion schematic diagram showing a chip packaging structure, where 101 is a fluorescent layer, 102 is an N-type semiconductor, 103 is a quantum well, 104 is a P-type semiconductor, 105 is a reflective layer, and the P electrode layer and the N electrode layer are both provided on the reflective layer 105, 106 is an insulating layer, 107 is an N electrode layer, 108 is a metal bonding layer, 109 is a chip base, 201 is an upper electrode layer, 202 is a metal dam, 203 is a packaging base, 204 is a lower electrode layer, 205 is a soldering base. Through holes are provided on the chip body formed by the fluorescent layer 101, N-type semiconductor 102, quantum well 103, P-type semiconductor 104, reflective layer 105, insulating layer 106, N electrode layer 107, metal bonding layer 108 and chip base 109, and the through holes penetrate the chip body. The specific penetration form can be: penetrating the quantum well 103, P-type semiconductor 104, reflective layer 105, insulating layer 106, N electrode layer 107 and metal bonding layer 108, and partially penetrating the N-type semiconductor 102. Among them, the through holes can specifically be N-via holes. The chip packaging structure is a chip packaging with non-uniform light emission, which has a first region (central region) and a second region (edge region) that are separated from each other. The area ratio of the first region to the second region is between and 1. The upper electrode layer is provided with a first positive electrode, a second positive electrode, a third positive electrode and a fourth positive electrode. The lower electrode layer is provided with a first negative electrode, a second negative electrode, a third negative electrode and a fourth negative electrode. The first electrode layer is provided with a plurality of first electrode units (a first electrode, a second electrode and a third electrode). The second electrode layer is provided with a plurality of electrode units (a fourth electrode, a fifth electrode and a sixth electrode). The first positive electrode is electrically connected to the first negative electrode, the second positive electrode is electrically connected to the second negative electrode, the third positive electrode is electrically connected to the third negative electrode, and the fourth positive electrode is electrically connected to the fourth negative electrode. The first positive electrode is electrically connected to the second electrode, the second positive electrode is electrically connected to the first electrode and the third electrode respectively, the third positive electrode is electrically connected to the fifth electrode, and the fourth positive electrode is electrically connected to the fourth electrode and the sixth electrode respectively. Among them, the plurality of first electrode units and the plurality of second electrode units can be symmetrically distributed on the reflective layer based on the central position of the reflective layer.

[0070] Since the encapsulation component is respectively connected to the second electrode layer and the power supply, and the first electrode layer is electrically connected to the first conductive layer, and the second electrode layer is electrically connected to the second conductive layer, a conductive path is formed between the N-type semiconductor and the first conductive layer through a through hole, and light is emitted from the light-emitting layer based on the conductive path. Among them, the first current flowing through the first region is conducted through the first through hole, and the second current flowing through the second region is conducted through the second through hole. The magnitudes of the first current and the second current are different. That is, the current of the conduction circuit is transmitted between the N-type semiconductor, the light-emitting layer, the P-type semiconductor, and the reflective layer of the chip body through different through holes penetrating the chip. Specifically, the first current of the conduction circuit sequentially flows through the power supply, the second electrode layer, the P-type semiconductor, the light-emitting layer, and the N-type semiconductor, and then flows through the first through hole to the first conductive layer and the first electrode layer, thereby forming a current loop. The second current of the conduction circuit sequentially flows through the power supply, the second electrode layer, the P-type semiconductor, the light-emitting layer, and the N-type semiconductor, and then flows through the second through hole to the second conductive layer and the second electrode layer. Furthermore, the current of the conductive path is allowed to pass through different current channels provided by the first through hole and the second through hole, so that the first region and the second region of the reflective layer emit light independently, thereby achieving the purpose of the zoning dimming function of the chip packaging structure. At the same time, since the first region and the second region are separated from each other, the first current flowing through the first region and the second current flowing through the second region do not interfere with each other. Therefore, by providing different first through holes and second through holes in the chip packaging structure and transmitting different first currents and second currents on the conductive path through different through holes, the different light-emitting regions of the LED lighting device can emit light independently, rather than the LED lighting device can only emit light uniformly, or by setting an adjustment mechanism and designing multiple light source modules to adjust the light source. Therefore, the technical defect that it is difficult for the lighting device to switch the light source freely due to the limitations of factors such as the stability of the adjustment mechanism and the design of the light source module is overcome, and the lighting flexibility of the LED chip is improved.

[0071] This embodiment provides a lighting device, which includes an LED package body provided in the embodiment of the present invention. The lighting device provided in this embodiment includes, but is not limited to, a lighting device, an optical signal indicating device, a supplementary lighting device, or a backlight device.

[0072] It should be noted that the lighting device includes a lighting component and the chip packaging structure of the above embodiment. In actual application, by welding the encapsulation component of the chip packaging structure to the lamp board component of the lighting device, the control circuit of the lighting device can control the chips of the LEDs on the lamp board component to emit light independently in different zones. Among them, the high-intensity high beam emitted by the first region is located at the very center of the reflective secondary optical system of the lighting device, effectively improving the light intensity and beam effect. The second region is located on the outside and can provide a high-flux effect for low beam lighting, thereby achieving a floodlight effect.

[0073] It should be understood that although the steps in the flowcharts involved in the above embodiments are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order limit for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0074] Those skilled in the art can understand that Figure 6 the structure shown in [the figure] is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the light-emitting device to which the solution of the present application is applied. The specific light-emitting device may include more or fewer components than those shown in the figure, or combine some components, or have a different component arrangement.

[0075] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in the present application.

[0076] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises a packaging body, a chip body and a through hole penetrating the chip body, wherein the packaging body comprises a packaging component, a first electrode layer located on the backlight side of the chip body and a second electrode layer located on the opposite side of the backlight side of the chip body, the chip body comprises an N-type semiconductor, a light-emitting layer, a P-type semiconductor and a reflective layer stacked in sequence, a first conductive layer and a second conductive layer are arranged oppositely on the light-emitting side of the chip body, the through hole comprises a first through hole penetrating a first area of ​​the reflective layer and a second through hole penetrating a second area of ​​the reflective layer, the first area and the second area are separated from each other; wherein, The packaging component is electrically connected to the second electrode layer and the power supply respectively, the first electrode layer is electrically connected to the first conductive layer, the second electrode layer is electrically connected to the second conductive layer, the N-type semiconductor forms a conductive path with the first conductive layer and the second conductive layer respectively through the through holes, and emits light in the light-emitting layer based on the conductive path, wherein a first current flowing through the first region is conducted through the first through holes, and a second current flowing through the second region is conducted through the second through holes, and the first current and the second current have different current sizes.

2. The chip packaging structure according to claim 1, characterized in that: The second area is all areas on the reflective layer except the first area and distributed around the first area, the first conductive layer includes a plurality of first electrode units, the second conductive layer includes a plurality of second electrode units, and the plurality of first electrode units and the plurality of second electrode units are symmetrically distributed on the reflective layer based on the center position of the reflective layer.

3. The chip packaging structure according to claim 2, characterized in that: The symmetrical distribution of the plurality of first electrode units and the plurality of second electrode units includes one of the following: The plurality of first electrode units and the plurality of second electrode units are symmetrically distributed on the reflective layer in a matrix based on a central position of the reflective layer; The plurality of first electrode units and the plurality of second electrode units are distributed on the reflective layer in a staggered and symmetrical manner based on a central position of the reflective layer; The plurality of first electrode units and the plurality of second electrode units are symmetrically distributed on the reflective layer in a spiral manner based on a central position of the reflective layer; The plurality of first electrode units and the plurality of second electrode units are distributed on the reflective layer in a mixed symmetrical manner based on a central position of the reflective layer.

4. The chip packaging structure according to claim 2, characterized in that: The first electrode layer and the second electrode layer are electrically connected through copper wires, and the first electrode layer is electrically connected to the plurality of first electrode units and the plurality of second electrode units through gold wires, respectively.

5. The chip packaging structure according to claim 4, characterized in that: The multiple first electrode units include a first electrode, a second electrode and a third electrode, the multiple second electrode units include a fourth electrode, a fifth electrode and a sixth electrode, the first electrode layer includes a first positive electrode, a second positive electrode, a third positive electrode and a fourth positive electrode, the second electrode layer includes a first negative electrode, a second negative electrode, a third negative electrode and a fourth negative electrode, the first positive electrode is electrically connected to the first negative electrode, the second positive electrode is electrically connected to the second negative electrode, the third positive electrode is electrically connected to the third negative electrode, the fourth positive electrode is electrically connected to the fourth negative electrode, the first positive electrode is electrically connected to the second electrode, the second positive electrode is electrically connected to the first electrode and the third electrode respectively, the third positive electrode is electrically connected to the fifth electrode, and the fourth positive electrode is electrically connected to the fourth electrode and the sixth electrode respectively.

6. The chip packaging structure according to claim 1, characterized in that: The first area of ​​the first area is less than or equal to the second area of ​​the second area, and the area ratio between the first area and the second area is , satisfy: .

7. The chip packaging structure according to claim 1, characterized in that: A first current of the first through hole is greater than a second current of the second through hole, and the first through hole and the second through hole have the same shape.

8. The chip packaging structure according to claim 7, characterized in that: The chip packaging structure includes one of the following: The hole density of the first through-holes is greater than the hole density of the second through-holes; The number of the first through holes is greater than the number of the second through holes; The number of the first through holes is the same as the number of the second through holes, and the diameter of the first through holes is larger than the diameter of the second through holes.

9. The chip packaging structure according to claim 1, characterized in that: The first electrode layer is provided with a conducting area, and the chip body is welded at a central position of the conducting area.

10. A light emitting device, characterized in that: The light-emitting device comprises a light-emitting component and the chip packaging structure according to any one of claims 1 to 9, and the chip packaging structure is welded to the light-emitting component through the second electrode layer.

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