Groove type memory and preparation method thereof
By forming a step-like deep groove on the second dielectric layer of the trench storage capacitor and building an electrode layer and a storage layer therein, the electrical connection problem caused by the small upper electrode area in the prior art is solved, and higher electrical connection performance and production efficiency are achieved.
Patent Information
- Application Number
- CN202311744233.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-19
- Publication Date
- 2025-06-20
AI Technical Summary
The upper electrode area of existing trench storage capacitors is getting smaller and smaller, resulting in the process window of the electrical connection holes becoming smaller and smaller, which is prone to inaccurate alignment and serious over-etching due to problems such as lithography and etching, which can damage the device.
By forming a first trench on the second dielectric layer and forming a sacrificial side wall on its side wall, the second trench with a smaller diameter is continued to be etched by the positioning of the side wall, thereby forming a step-shaped deep groove. A trench storage capacitor structure consisting of a first electrode layer, a storage layer and a second electrode layer is formed in the deep groove.
The area of the second electrode layer is effectively increased, the process window of the second electrical connection structure is expanded, the difficulty of lithography, alignment accuracy and etching process is reduced, the electrical connection performance is improved, the production yield of the memory is improved, and the cost is reduced.
Smart Images
Figure CN120187280A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor memory manufacturing, and particularly to a trench memory and a preparation method thereof. Background Art
[0002] The memory cells of semiconductor memory devices generally include transistors and storage capacitors. When reducing the size of the memory cells in proportion to improve the integration of semiconductor memory devices, the area of the semiconductor substrate occupied by the storage capacitors can be reduced. As a result, the capacitance of a typical storage capacitor with a two-dimensional structure decreases. When the capacitance of the storage capacitor decreases, the signal-to-noise ratio drops. Therefore, to ensure the capacitance of the storage capacitor, the design of the storage capacitor has evolved from a planar capacitor structure to a three-dimensional stacked and / or trench capacitor structure.
[0003] The storage capacitor has a MIM structure with a storage material layer inserted between two adjacent metal layers. The storage capacitor generally consists of upper and lower electrode layers and an intermediate storage layer. The storage performance of the memory is proportional to the effective areas of the storage layer and the electrode layer in the storage capacitor. The storage capacitors in the memory cells have evolved from planar to trench type to adapt to the miniaturization and high integration of existing semiconductor devices. With the further development of miniaturization and high integration, the area of the upper electrode of the existing trench storage capacitor becomes smaller, and the process window of the electrical connection holes of the upper electrode also becomes smaller, making it prone to problems such as alignment and severe over-etching due to lithography, etching, etc., and easily damaging the device. Summary of the Invention
[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a trench memory and a preparation method thereof, which are used to solve the problems in the prior art that the area of the upper electrode of the trench storage capacitor becomes smaller and smaller, resulting in a smaller process window for the electrical connection holes of the upper electrode, and being prone to problems such as alignment and severe over-etching due to lithography, etching, etc., and easily damaging the device.
[0005] To achieve the above object and other related objects, the present invention provides a preparation method of a trench memory, and the preparation method includes:
[0006] Providing a substrate, on which a first dielectric layer is formed, and a first electrical connection structure penetrating the first dielectric layer is formed in the first dielectric layer;
[0007] Sequentially forming a second dielectric layer and a first mask layer on the first dielectric layer;
[0008] Using a photolithography and etching process to etch the first mask layer and the second dielectric layer to form a first trench with a preset depth in the second dielectric layer;
[0009] A second mask layer is formed on the surface of the remaining first mask layer and the surface of the first trench;
[0010] The second mask layer is removed by a dry etching process, and only the second mask layer on the sidewall of the first trench is retained to form a sacrificial sidewall;
[0011] A dry etching process is used to further etch the second dielectric layer on the basis of the first trench to form a second trench penetrating the second dielectric layer, and the second trench exposes the first electrical connection structure, wherein the aperture of the second trench is smaller than that of the first trench;
[0012] A first electrode layer is formed on the second trench;
[0013] The sacrificial sidewall is removed;
[0014] A storage layer and a second electrode layer are sequentially formed in the first trench and the second trench, and the second electrode layer fills the first trench and the second trench;
[0015] A third dielectric layer is formed on the second dielectric layer, and a second electrical connection structure penetrating the third dielectric layer is formed, and the second electrical connection structure is in contact connection with the second electrode layer.
[0016] Optionally, before forming the first electrode layer, an isolation layer is formed on the sidewall of the second trench.
[0017] Further, the material of the second dielectric layer is silicon oxide, the material of the first electrode layer is titanium nitride, and the material of the isolation layer is silicon nitride.
[0018] Further, the materials of the first mask layer and the second mask layer are both amorphous silicon.
[0019] Optionally, the method for forming the first electrode layer includes:
[0020] A first electrode material layer is formed on the surface of the obtained structure;
[0021] A dielectric material is spin-coated to fill the first trench and the second trench until the dielectric material is at a preset thickness on the second dielectric layer;
[0022] The dielectric material is removed by a dry etching process, and only the dielectric material in the second trench is retained;
[0023] The first electrode material layer is removed by a wet etching process, and only the first electrode material layer in the second trench is retained to form the first electrode layer;
[0024] The remaining dielectric material is removed by a dry etching process.
[0025] Further, the dielectric material is BARC or photoresist.
[0026] Optionally, the sacrificial sidewall is removed by wet etching.
[0027] Optionally, the method for forming the storage layer and the second electrode layer includes:
[0028] A storage material layer and a second electrode material layer are sequentially formed on the surface of the obtained structure above;
[0029] A metal filling layer is formed on the surface of the second electrode material layer, and the metal filling layer fills the first trench and the second trench to a preset thickness on the surface of the second electrode material layer located on the second dielectric layer;
[0030] The storage material layer, the second electrode material layer, and the metal filling layer on the surface of the second dielectric layer are removed by a CMP process, so that the remaining storage material layer forms a storage layer, and the remaining second electrode material layer and the metal filling layer form a second electrode layer.
[0031] Further, the material of the second electrode material layer is titanium nitride, and the material of the metal filling layer is tungsten.
[0032] Optionally, the third dielectric layer is a stacked structure of a silicon nitride layer and a silicon oxide layer.
[0033] The present invention also provides a trench memory, which is prepared by using the preparation method of the trench memory described in any one of the above.
[0034] As described above, for the trench memory and its preparation method of the present invention, by first forming a first trench on the second dielectric layer and forming a sacrificial sidewall on the sidewall of the first trench, and then continuing to etch the first trench downward by means of the occupation of the sacrificial sidewall to form a second trench with a smaller diameter, thereby forming a stepped deep trench with a smaller diameter. Subsequently, a trench-type storage capacitor structure composed of a first electrode layer, a storage layer, and a second electrode layer is formed in the stepped deep trench. Since the diameter of the upper first trench of the stepped deep trench is larger than that of the lower second trench, the area of the second electrode layer formed therein is increased, thereby effectively increasing the process window of the second electrical connection structure, reducing the difficulty of processes such as lithography CD (critical dimension), alignment accuracy (overlay), and etching of the second electrical connection structure, improving the electrical connection performance between the second electrode layer and the second electrical connection structure, and thus improving the production yield of the trench memory and reducing the cost. Description of the Drawings
[0035] Figures 1 to 20It shows a schematic cross-sectional structure diagram after each step in the preparation process of the trench-type memory of the present invention.
[0036] Element label description
[0037] 100 First dielectric layer
[0038] 101 First electrical connection structure
[0039] 102 Second dielectric layer
[0040] 103 First mask layer
[0041] 104 First trench
[0042] 105 Second mask layer
[0043] 106 Sacrificial sidewall
[0044] 107 Second trench
[0045] 108 Isolation material layer
[0046] 109 Isolation layer
[0047] 110 First electrode material layer
[0048] 111 Dielectric material
[0049] 112 First electrode layer
[0050] 113 Storage material layer
[0051] 114 Second electrode material layer
[0052] 115 Metal filling layer
[0053] 116 Storage layer
[0054] 117 Second electrode layer
[0055] 118 Third dielectric layer
[0056] 119 Silicon nitride layer
[0057] 120 Silicon oxide layer
[0058] 121 Second electrical connection structure
[0059] 122 Conductive via
[0060] 123 Conductive pad Detailed implementation manner
[0061] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0062] Please refer to Figures 1 to 20 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0063] This embodiment provides a method for manufacturing a trench-type memory, and the manufacturing method includes:
[0064] S1. Provide a substrate, a first dielectric layer is formed on the substrate, and a first electrical connection structure penetrating the first dielectric layer is formed in the first dielectric layer;
[0065] S2. Sequentially form a second dielectric layer and a first mask layer on the first dielectric layer;
[0066] S3. Use a photolithography etching process to etch the first mask layer and the second dielectric layer to form a first trench with a preset depth in the second dielectric layer;
[0067] S4. Form a second mask layer on the surface of the remaining first mask layer and the surface of the first trench;
[0068] S5. Use a dry etching process to remove the second mask layer, and only retain the second mask layer on the sidewall of the first trench to form a sacrificial sidewall;
[0069] S6. Use a dry etching process to continue etching the second dielectric layer on the basis of the first trench to form a second trench penetrating the second dielectric layer, and the second trench exposes the first electrical connection structure, wherein the aperture of the second trench is smaller than the aperture of the first trench;
[0070] S7. Form a first electrode layer on the second trench;
[0071] S8. Remove the sacrificial sidewall;
[0072] S9. Sequentially form a storage layer and a second electrode layer in the first trench and the second trench, and the second electrode layer fills the first trench and the second trench;
[0073] S10. Form a third dielectric layer on the second dielectric layer, and form a second electrical connection structure penetrating the third dielectric layer, and the second electrical connection structure is in contact connection with the second electrode layer.
[0074] The manufacturing method of the trench-type memory of this embodiment forms a first trench on the second dielectric layer first, forms a sacrificial sidewall on the sidewall of the first trench, and then continues to etch the first trench downward by means of the occupation of the sacrificial sidewall to form a second trench with a smaller diameter, so as to form a stepped deep trench with a smaller diameter. Subsequently, a trench-type storage capacitor structure composed of a first electrode layer, a storage layer, and a second electrode layer is formed in the stepped deep trench. Since the diameter of the upper first trench of the stepped deep trench is larger than that of the lower second trench, the area of the second electrode layer formed therein is increased, thereby effectively increasing the process window of the second electrical connection structure, reducing the difficulty of processes such as lithography CD (critical dimension), alignment accuracy (overlay), and etching of the second electrical connection structure, improving the electrical connection performance between the second electrode layer and the second electrical connection structure, and thus improving the production yield of the trench-type memory and reducing costs.
[0075] The manufacturing method of the trench-type memory of this embodiment is applicable to any existing memory suitable for a storage capacitor with a MIM structure, such as ferroelectric memory, phase change memory, resistive random access memory, etc. As long as the storage unit of the memory includes a storage capacitor in the form of MIM, the manufacturing method of the trench-type memory of this embodiment can be used for preparation.
[0076] The following will describe in detail the manufacturing method of the trench-type memory of this embodiment with reference to specific drawings.
[0077] As Figure 1 shown, first perform step S1, provide a substrate, a first dielectric layer 100 is formed on the substrate, and a first electrical connection structure 101 penetrating the first dielectric layer 100 is formed in the first dielectric layer 100.
[0078] It should be noted here that the focus of this embodiment is to manufacture the storage capacitor structure in the trench-type memory, so Figure 1 the specific structure of the substrate is not shown. In practice, the structure of the substrate is designed according to the specific structure of the trench-type memory. It can be a substrate that has completed the manufacturing of functional areas. For example, the circuit design of the source, drain, and gate, the design of the circuit interconnection structure, the design of the isolation structure, etc. have been completed in the substrate. There is no excessive limitation here.
[0079] The substrate can be a single-layer semiconductor structure, such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc.; it can also be a stacked structure, such as a silicon / germanium silicon stack, etc. In this embodiment, the silicon substrate that is used more is taken as an example for description.
[0080] As an example, the method of forming the first electrical connection structure 101 includes: first depositing and forming the first dielectric layer 100 on the substrate. The material of the first dielectric layer 100 may be an oxide material, such as silicon oxide. Then, a through hole is formed in a preset area of the first dielectric layer 100, and the through hole exposes electrical connection structures such as pads in the substrate that need to be electrically connected to a subsequent capacitor. Next, an electrical connection material is deposited on the first dielectric layer 100 to at least fill the through hole. Finally, the electrical connection material is planarized. For example, the electrical connection material is polished using a CMP process to grind away the electrical connection material outside the through hole, thereby obtaining the first electrical connection structure 101.
[0081] As an example, the material of the first electrical connection structure 101 can be any suitable conductive material, such as tungsten, copper, aluminum, platinum, etc. In this embodiment, metal tungsten material is preferably used.
[0082] As Figure 3 shown, then step S2 is performed to sequentially form a second dielectric layer 102 and a first mask layer 103 on the first dielectric layer 100.
[0083] The thickness of the second dielectric layer 102 is selected according to the storage capacitor size requirements of the subsequent formed trench memory.
[0084] The thickness of the first mask layer 103 is set in combination with subsequent processes, generally not exceeding Preferably, the range is
[0086] As a specific example, the method of forming the second dielectric layer 102 and the first mask layer 103 includes: as Figure 2 shown, first form the second dielectric layer 102 on the first dielectric layer 100. For example, the second dielectric layer 102 is formed using a CVD deposition process. The material of the second dielectric layer 102 may be an oxide material, such as silicon oxide. Then, the first mask layer 103 is formed on the second dielectric layer 102. For example, the first mask layer 103 is formed using a CVD deposition process or an ALD deposition process. The material of the first mask layer 103 may be any suitable mask material, such as silicon nitride material, amorphous silicon material, etc. Here, amorphous silicon material is preferably used.
[0087] As Figure 4 shown, then step S3 is performed to etch the first mask layer 103 and the second dielectric layer 102 using a photolithography etching process to form a first trench 104 with a preset depth in the second dielectric layer 102.
[0088] As an example, parameters such as the depth and caliber size of the first groove 104 are set according to device size requirements and process levels, and are not overly restricted here.
[0089] As a specific example, the method for forming the first groove 104 includes: first coating a photoresist layer on the first mask layer 103, exposing and developing it to form a patterned photoresist layer, and the patterned photoresist layer exposes the formation region of the first groove 104; then based on the patterned photoresist layer, using a dry etching process to etch the first mask layer 103 and the second dielectric layer 102 to form the first groove 104. After this step, the first mask layer 103 on the surface of the first dielectric layer 102 is retained, as Figure 4 shown; finally, the patterned photoresist layer is removed.
[0090] As Figure 5 shown, then step S4 is carried out, and a second mask layer 105 is formed on the surface of the remaining first mask layer 103 and the surface of the first groove 104. Since in step S3, the first mask layer 103 on the surface of the first dielectric layer 102 is retained, after the second mask layer 105 is formed in this step, the thickness of the mask layer on the surface of the first dielectric layer 102 is the superposition of the first mask layer 103 and the second mask layer 105, while the thickness of the mask layer on the sidewall and bottom wall of the first groove 104 is only the second mask layer 105, so the thickness of the mask layer in the first groove 104 is less than that in other regions.
[0091] As an example, the second mask layer 105 can be formed by a CVD deposition process or an ALD deposition process. The material of the second mask layer 105 can be any suitable mask material, such as silicon nitride material, amorphous silicon material, etc. Here, it is preferably the same material as the first mask layer 103. For example, when the material of the first mask layer 103 is amorphous silicon material, the material of the second mask layer 105 is also amorphous silicon material.
[0092] As Figure 6 shown, then step S5 is carried out, and the second mask layer 105 is removed by a dry etching process, and only the second mask layer 105 on the sidewall of the first groove 104 is retained to form a sacrificial sidewall 106.
[0093] In this step, since the thickness of the mask layer in the first trench 104 obtained in step S4 is smaller than that in other regions, during the dry etching process of this step, after the second mask layer 105 on the bottom wall of the first trench 104 is completely removed, there will still be a remaining mask layer on the surface of the second dielectric layer 102, thereby achieving the effect of protecting the surface of the second dielectric layer 102 during the dry etching process of this step; in addition, the remaining mask layer on the surface of the second dielectric layer 102 can be removed separately later, or can be removed during the subsequent formation of the second trench.
[0094] As a preferred example, the first mask layer 103 and the second mask layer 105 are made of the same material, for example, both are made of amorphous silicon material, so as to facilitate the implementation of the dry etching process in this step.
[0095] As Figure 7 shown, then step S6 is carried out. A dry etching process is used to continue etching the second dielectric layer 102 on the basis of the first trench 104 to form a second trench 107 that penetrates the second dielectric layer 102, and the second trench 107 exposes the first electrical connection structure 101, wherein the diameter of the second trench 107 is smaller than the diameter of the first trench 104. In this step, since a sacrificial sidewall 106 is formed on the sidewall of the first trench 104, when etching the second dielectric layer 102, the outer sidewall of the sacrificial sidewall 106 is used as the etching diameter, so that the diameter of the formed second trench 107 becomes smaller relative to the first trench 104, that is, the first trench 104 achieves the effect of widening the trench diameter relative to the second trench 107.
[0096] In this step, the remaining mask layer on the surface of the second dielectric layer 102 after step S5 can also be removed together during the dry etching process of forming the second trench 107 in this step. Since the dry etching process has an etching selectivity for materials of different materials, in this step, an etching gas with a high etching selectivity for the remaining mask layer on the surface of the second dielectric layer 102 is selected to etch the second dielectric layer 102. During this process, a slow etching effect will be produced on the remaining mask layer on the surface of the second dielectric layer 102. By controlling the etching parameters, the effect of forming the second trench 107 and removing the remaining mask layer on the surface of the second dielectric layer 102 can be achieved.
[0097] As Figure 14 shown, then step S7 is carried out. A first electrode layer 112 is formed on the second trench 107. Since the second trench 107 exposes the first electrical connection structure 101, the first electrode layer 112 formed on the second trench 107 can achieve contact electrical connection with the first electrical connection structure 101.
[0098] As an example, the material of the first electrode layer 112 can be selected from any material suitable for use as a memory capacitor electrode, such as tungsten, copper, aluminum, titanium nitride, etc. In this embodiment, titanium nitride material is preferably used.
[0099] As a preferred example, as Figure 14 shown, before forming the first electrode 112 layer, there is also a step of forming an isolation layer 109 on the sidewall of the second trench 107. The isolation layer 109 can effectively isolate the first electrode layer 112 from the second dielectric layer 102, so as to prevent impurities contained in the second dielectric layer 102 from reacting with the first electrode layer 112 during subsequent processes, resulting in a decrease in the conductivity of the first electrode layer 112. For example, when the material of the first electrode layer 112 is titanium nitride and the material of the second dielectric layer 102 is silicon oxide, there will be many oxygen-containing dangling bonds in the second dielectric layer 102, which will react with titanium nitride under high-temperature conditions, causing the first electrode layer 112 to denature and resulting in a decrease in electrical performance. Therefore, forming a silicon nitride material isolation layer 109 on the sidewall of the second trench 107 can effectively prevent the first electrode layer 112 from being corroded by the second dielectric layer 102.
[0100] As a specific example, the method of forming the isolation layer 109 includes: as Figure 8 shown, first form an isolation material layer 108 on the surface of the entire structure, including the surface of the second dielectric layer 102, the surface of the first trench 104 and the surface of the second trench 107. For example, the isolation material layer 108 is formed by using a CVD deposition process or an ALD deposition process; as Figure 9 shown, then use a dry etching process to remove the isolation material layer 108 outside the second trench 107, so as to only retain the isolation material layer 108 on the second trench 107, making it form an isolation layer 109. The material of the isolation layer 109 is selected on the principle that it can effectively prevent the second dielectric layer 102 from corroding the first electrode layer 112 and it will not corrode the first electrode layer 112 itself.
[0101] As another specific example, as Figures 10 to 14 shown, the method of forming the first electrode layer 112 includes: as Figure 10 shown, first form a first electrode material layer 110 on the surface of the entire structure, including the surface of the second dielectric layer 102, the surface of the first trench 104 and the surface of the second trench 107. For example, the first electrode material layer 110 can be formed by using a PVD deposition process, a CVD deposition process or an ALD deposition process; as Figure 11As shown, the dielectric material 111 is then spin-coated to fill the first trench 104 and the second trench 107 to a preset thickness of the dielectric material 111 on the second dielectric layer 102. The dielectric material 111 can be BARC, photoresist, etc.; As Figure 12 shown, then the dielectric material 111 is removed by dry etching, and only the dielectric material 111 in the second trench 107 is retained; As Figure 13 shown, then the first electrode material layer 110 is removed by wet etching, and only the first electrode material layer 110 in the second trench 107 is retained to form the first electrode layer 112. The wet etching process causes less damage than the dry etching process and can reduce the damage to the first electrode layer 112 in the second trench 107; As Figure 14 shown, finally, the remaining dielectric material 111 is removed by dry etching.
[0102] As Figure 15 shown, then step S8 is performed to remove the sacrificial sidewall 106.
[0103] As a preferred example, the sacrificial sidewall 106 is removed by wet etching. When the material of the sacrificial sidewall 106 is selected as amorphous silicon and the material of the first electrode layer 112 is selected as titanium nitride, when the sacrificial sidewall 106 made of amorphous silicon material is removed by wet etching, the selected etching solution causes the least damage to the first electrode layer 112 made of titanium nitride material.
[0104] As Figure 18 shown, then step S9 is performed to sequentially form a storage layer 116 and a second electrode layer 117 in the first trench 104 and the second trench 107, and the second electrode layer 117 fills the first trench 104 and the second trench 107.
[0105] The trench-type storage capacitor structure obtained after this step is composed of a first electrode layer 112, a storage layer 116, and a second electrode layer 117. Since the exposed surface of the second electrode layer 117 is formed in the first trench 104 with a larger diameter, the contact surface of the second electrode layer 117 is correspondingly increased.
[0106] As a specific example, as Figures 15 to 18 shown, the method for forming the storage layer 116 and the second electrode layer 117 includes: as Figure 15 and Figure 16As shown in the figure, a storage material layer 113 and a second electrode material layer 114 are sequentially formed on the surface of the above-obtained structure (including the surface of the second dielectric layer 102 and the surfaces of the first trench 104 and the second trench 107). For example, the storage material layer 113 and the second electrode material layer 114 can be formed by PVD deposition process, CVD deposition process or ALD deposition process. The material of the storage material layer 113 is selected according to different types of storage capacitors formed. For example, when it is a ferroelectric storage capacitor, the material of the storage material layer 113 is selected as a ferroelectric material, such as Si-doped HfO, Zr-doped HfO, La-doped HfO, Si-doped HfO, Si-doped HfO, SBT, PZ, etc.; when it is a phase change storage capacitor, the material of the storage material layer 113 is selected as a phase change material, such as GST, SST, etc.; when it is a resistive random access memory (RRAM) storage capacitor, the material of the storage material layer 113 is selected as a resistive material, such as HfO, TiO, etc. The material of the second electrode material layer 114 can be selected as any material suitable for the electrode of the memory capacitor, such as tungsten, copper, aluminum, platinum, and titanium nitride, etc. In this embodiment, titanium nitride material is preferably used; as Figure 17 As shown in the figure, then a metal filling layer 115 is formed on the surface of the second electrode material layer 114. The metal filling layer 115 fills the first trench 104 and the second trench 107 to a preset thickness on the surface of the second electrode material layer 114 located on the second dielectric layer 102. The material of the metal filling layer 115 can be selected as any conductive material suitable for the electrode, such as tungsten or copper. In this embodiment, tungsten is preferably used. The metal filling layer 115 can be formed by CVD deposition process to improve the filling efficiency while ensuring the filling quality; as Figure 18 As shown in the figure, finally, the storage material layer 113, the second electrode material layer 114 and the metal filling layer 115 on the surface of the second dielectric layer 102 are removed by CMP process, so that the remaining storage material layer 113 forms a storage layer 116, and the remaining second electrode material layer 114 and the metal filling layer 115 form a second electrode layer 117. In this example, the second electrode layer 117 is a stacked structure of different conductive materials and is formed by a two-step deposition process; in practice, the second electrode layer 117 can also be a single-layer conductive material structure and is formed by a one-step deposition process.
[0107] As Figure 20 As shown in the figure, finally, step S10 is performed. A third dielectric layer 118 is formed on the second dielectric layer 102, and a second electrical connection structure 121 penetrating the third dielectric layer 118 is formed, and the second electrical connection structure 121 is in contact connection with the second electrode layer 117.
[0108] In this step, since the surface of the second electrode layer 117 is effectively increased, the process window for fabricating the second electrical connection structure 121 can be effectively reduced. The difficulties in processes such as the CD of lithography, alignment accuracy, and etching during the fabrication of the second electrical connection structure 121 can be significantly reduced.
[0109] As an example, the second electrical connection structure 121 includes a conductive via 122 penetrating through the third dielectric layer 118 and a conductive pad 123 formed on the conductive via 122.
[0110] As a specific example, the method for forming the second electrical connection structure 121 includes: as Figure 19 shown, first deposit and form the third dielectric layer 118 on the surface of the second dielectric layer 102. The third dielectric layer 118 can be a single-layer structure or a stacked-layer structure. For example, the third dielectric layer 118 is a stacked-layer structure of a silicon nitride layer 119 and a silicon oxide layer 120. The silicon nitride layer 119 can effectively protect the trench-type storage capacitor below it; then form a through hole in a preset area of the third dielectric layer 118, and this through hole exposes the second electrode layer 117 in the second dielectric layer 102; then fill the through hole with an electrical connection material to form a conductive via 122; finally, form a conductive pad 123 on the surface of the conductive via 122.
[0111] Based on the above method for fabricating a trench-type memory, this embodiment further provides a trench-type memory. It can be fabricated by using the above-mentioned method for fabricating a trench-type memory, but it is not limited thereto. Other feasible fabrication methods can also be used to form this trench-type memory. For the beneficial effects that can be achieved, please refer to the above-mentioned fabrication method and will not be elaborated below. As Figure 20 shown, this trench-type memory includes:
[0112] A first dielectric layer 100, in which a first electrical connection structure 101 penetrating through the first dielectric layer 100 is formed;
[0113] A second dielectric layer 102 formed on the first dielectric layer 100,
[0114] A first trench 104 and a second trench 107 extending from the surface of the second dielectric layer 102 towards the first dielectric layer 100. Among them, the first trench 104 communicates with the second trench 107. The second trench 107 exposes the first electrical connection structure 101, and the diameter of the second trench 107 is smaller than the diameter of the first trench 104;
[0115] A first electrode layer 112 formed on the second trench 107;
[0116] A storage layer 116 and a second electrode layer 117 are sequentially formed in the first trench 104 and the second trench 107, and the second electrode layer 117 fills the first trench 104 and the second trench 107;
[0117] A third dielectric layer 118 is formed on the second dielectric layer 102. A second electrical connection structure 121 penetrating the third dielectric layer 118 is formed in the third dielectric layer 118, and the second electrical connection structure 121 is in contact connection with the second electrode layer 117.
[0118] As an example, an isolation layer 109 is formed between the first electrode layer 112 and the second trench 107.
[0119] In summary, the present invention provides a trench-type memory and a manufacturing method thereof. By first forming a first trench on a second dielectric layer and forming a sacrificial sidewall on the sidewall of the first trench, and then using the occupied position of the sacrificial sidewall to continue etching the first trench downward to form a second trench with a smaller diameter, thereby forming a stepped deep trench with a smaller diameter. Subsequently, a trench-type storage capacitor structure composed of a first electrode layer, a storage layer, and a second electrode layer is formed in the stepped deep trench. Since the diameter of the upper first trench of the stepped deep trench is larger than that of the lower second trench, the area of the second electrode layer formed therein is increased, thereby effectively increasing the process window of the second electrical connection structure, reducing the difficulty of processes such as lithography CD (critical dimension), alignment accuracy (overlay), and etching of the second electrical connection structure, improving the electrical connection performance between the second electrode layer and the second electrical connection structure, and thus improving the production yield of the trench-type memory and reducing costs. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0120] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a trench-type memory, characterized in that, The preparation method includes: providing a substrate, on which a first dielectric layer is formed, and a first electrical connection structure penetrating the first dielectric layer is formed in the first dielectric layer; sequentially forming a second dielectric layer and a first mask layer on the first dielectric layer; etching the first mask layer and the second dielectric layer by a photolithography etching process to form a first trench with a preset depth in the second dielectric layer; forming a second mask layer on the surface of the remaining first mask layer and the surface of the first trench; removing the second mask layer by a dry etching process, and only retaining the second mask layer on the sidewall of the first trench to form a sacrificial sidewall; continuing to etch the second dielectric layer on the basis of the first trench by a dry etching process to form a second trench penetrating the second dielectric layer, and the second trench exposes the first electrical connection structure, wherein the aperture of the second trench is smaller than that of the first trench; forming a first electrode layer on the second trench; removing the sacrificial sidewall; sequentially forming a storage layer and a second electrode layer in the first trench and the second trench, and the second electrode layer fills the first trench and the second trench; forming a third dielectric layer on the second dielectric layer, and forming a second electrical connection structure penetrating the third dielectric layer, and the second electrical connection structure is in contact connection with the second electrode layer.
2. The method for manufacturing a trench-type memory according to claim 1, characterized in that: Before forming the first electrode layer, it further includes forming an isolation layer on the sidewall of the second trench.
3. The method for manufacturing a trench-type memory according to claim 2, characterized in that: The material of the second dielectric layer is silicon oxide, the material of the first electrode layer is titanium nitride, and the material of the isolation layer is silicon nitride.
4. The method for manufacturing a trench-type memory according to any one of claims 1 to 3, characterized in that: The materials of the first mask layer and the second mask layer are both amorphous silicon.
5. The method for manufacturing a trench-type memory according to claim 1, characterized in that, The method for forming the first electrode layer includes: forming a first electrode material layer on the surface of the structure obtained above; spin-coating a dielectric material to fill the first trench and the second trench until the dielectric material is at a preset thickness on the second dielectric layer; removing the dielectric material by a dry etching process, and only retaining the dielectric material in the second trench; removing the first electrode material layer by a wet etching process, and only retaining the first electrode material layer in the second trench to form the first electrode layer; removing the remaining dielectric material by a dry etching process.
6. The method for manufacturing a trench-type memory according to claim 5, characterized in that: The dielectric material is BARC or photoresist.
7. The method for manufacturing a trench-type memory according to claim 1, characterized in that: removing the sacrificial sidewall by a wet etching process.
8. The method for manufacturing a trench-type memory according to claim 1, characterized in that, The method for forming the storage layer and the second electrode layer includes: sequentially forming a storage material layer and a second electrode material layer on the surface of the structure obtained above; forming a metal filling layer on the surface of the second electrode material layer, and the metal filling layer fills the first trench and the second trench until it is at a preset thickness on the surface of the second electrode material layer on the second dielectric layer; removing the storage material layer, the second electrode material layer and the metal filling layer on the surface of the second dielectric layer by a CMP process, so that the remaining storage material layer forms a storage layer, and the remaining second electrode material layer and the metal filling layer form a second electrode layer.
9. The method for manufacturing a trench-type memory according to claim 8, characterized in that: The material of the second electrode material layer is titanium nitride, and the material of the metal filling layer is tungsten.
10. The manufacturing method of the trench-type memory according to claim 1, characterized in that: The third dielectric layer is a stacked structure of a silicon nitride layer and a silicon oxide layer.
11. A trench-type memory, characterized in that It is prepared by using the preparation method of the trench-type memory according to any one of claims 1 to 10.