Solid state relay

Abstract

A solid-state relay (200) includes an oscillation circuit (10), an inductor (20), a rectifier circuit (30), a voltage regulator circuit (40), a charge / discharge circuit (50), and a first MOSFET (61). The oscillation circuit (10) outputs a first signal, the inductor (20) amplifies the first signal and outputs the amplified first signal as a second signal, and the rectification circuit (30) rectifies the second signal and outputs the rectified second signal as a third signal. A voltage stabilizing circuit (40) stabilizes the voltage of the third signal and outputs the voltage as a fourth signal, and a charging / discharging circuit (50) charges or discharges the fourth signal from the gate of the first MOSFET (61). The inductor (20) comprises a first inductor (21) and a second inductor (22), the first signal is input into the first inductor (21), and the second signal is output by the second inductor (22).

Description

Technical Field

[0001] The present disclosure relates to a solid-state relay, and particularly to a magnetic-coupling type solid-state relay. Background Art

[0002] So far, there is known a solid-state relay that uses magnetic coupling between inductors to perform a switching operation corresponding to an input signal for signal transmission (for example, refer to Patent Document 1).

[0003] Patent Document 1: Japanese Patent Laid-Open Gazette No. 2022-070567 Summary of the Invention

[0004] -Technical Problem to be Solved by the Invention-

[0005] However, in a magnetic-coupling type solid-state relay, the output voltage of the inductor sometimes varies due to a load or the like connected to a semiconductor switch included in the output section. If the output voltage of the inductor becomes an overvoltage due to such variation, problems such as a failure of the semiconductor switch that receives the output voltage or an inability to operate stably may occur.

[0006] The present disclosure has been completed to solve the above problems, and an object thereof is to provide a solid-state relay that stabilizes the output voltage of an inductor and improves the operating reliability in a magnetic-coupling type solid-state relay.

[0007] -Technical Solution for Solving the Technical Problem-

[0008] To achieve the above object, the solid-state relay according to the present disclosure includes an oscillation circuit, an inductor, a rectification circuit, a voltage regulation circuit, a charge / discharge circuit, and a first MOSFET. The oscillation circuit outputs a first signal. The inductor amplifies the first signal input from the oscillation circuit and outputs it as a second signal. The rectification circuit rectifies the second signal input from the inductor and outputs it as a third signal. The voltage regulation circuit stabilizes the voltage of the third signal and outputs it as a fourth signal. The charge / discharge circuit charges or discharges the fourth signal. The first MOSFET is input with the fourth signal. The inductor includes a first inductor and a second inductor. The first signal is input from the oscillation circuit to the first inductor, and the second inductor outputs the second signal to the rectification circuit.

[0009] -Effects of the Invention-

[0010] According to the present disclosure, even when an excessive voltage is generated in the inductor, it is possible to suppress the excessive voltage from being input to the output circuit and causing a failure of the first MOSFET. The operation of the first MOSFET can be stabilized. In summary, the operating reliability of the solid-state relay can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a functional block diagram of the solid-state relay according to the first embodiment;

[0012] Figure 2 is a circuit diagram of the solid-state relay;

[0013] Figure 3A is a cross-sectional schematic diagram showing an example of one of the first MOSFETs;

[0014] Figure 3B is a cross-sectional schematic diagram showing another example of the first MOSFET;

[0015] Figure 4A is a schematic diagram showing a set of substrates mounted on the solid-state relay;

[0016] Figure 4B is a schematic diagram showing another set of substrates mounted on the solid-state relay;

[0017] Figure 5A is a schematic diagram showing a set of substrates mounted in the solid-state relay according to Modification 1;

[0018] Figure 5B is a schematic diagram showing another set of substrates mounted in the solid-state relay according to Modification 1;

[0019] Figure 6A is a circuit diagram of the first charge / discharge circuit according to Modification 2;

[0020] Figure 6B is a circuit diagram of the second charge / discharge circuit according to Modification 2;

[0021] Figure 6C is a circuit diagram of the third charge / discharge circuit according to Modification 2;

[0022] Figure 7 is a circuit diagram of the voltage regulation circuit according to Modification 2;

[0023] Figure 8 is a functional block diagram of the solid-state relay according to the second embodiment;

[0024] Figure 9 is a schematic diagram showing a set of substrates mounted on the solid-state relay;

[0025] Figure 10 is a functional block diagram of another solid-state relay according to the second embodiment;

[0026] Figure 11 is a schematic diagram showing another set of substrates mounted on the solid-state relay;

[0027] Figure 12 is a functional block diagram of yet another solid-state relay according to the second embodiment;

[0028] Figure 13 is a schematic diagram showing another set of substrates mounted on the solid-state relay;

[0029] Figure 14A is a circuit diagram of an overcurrent protection circuit;

[0030] Figure 14B is a circuit diagram of an overtemperature protection circuit;

[0031] Figure 15A is a circuit diagram of an overvoltage protection circuit;

[0032] Figure 15B is a circuit diagram of another overvoltage protection circuit;

[0033] Figure 16 is a functional block diagram of a solid-state relay according to the third embodiment;

[0034] Figure 17A is a schematic diagram showing a set of substrates mounted on the solid-state relay;

[0035] Figure 17B is a schematic diagram showing another set of substrates mounted on the solid-state relay;

[0036] Figure 18 is a circuit diagram of a fault detection circuit;

[0037] Figure 19 is a functional block diagram of a solid-state relay according to the fourth embodiment;

[0038] Figure 20 is a circuit diagram of a low-voltage malfunction prevention circuit. Detailed Embodiment

[0039] Hereinafter, embodiments of the present disclosure will be described based on the drawings. It should be noted that the following preferred embodiments are merely examples for essentially explaining the present disclosure, and are not intended to limit the present disclosure, its application objects, or its uses.

[0040] (First Embodiment)

[0041] [Structure of Solid-State Relay]

[0042] Figure 1 is a functional block diagram of a solid-state relay according to a first embodiment. Figure 2 is a circuit diagram of the solid-state relay.

[0043] As Figure 1 shown, the solid-state relay 200 includes first to fourth terminals 1 to 4 and fifth and sixth terminals 5, 6. The solid-state relay 200 also includes an oscillation circuit 10, an inductor 20, a rectifier circuit 30, a voltage regulator circuit 40, a charge / discharge circuit 50, and an output circuit 60 as functional blocks.

[0044] In the solid-state relay 200, an input signal Vin is applied between the first terminal 1 and the second terminal 2 which are respectively input terminals, and an output signal corresponding to the input signal Vin is transmitted between the third terminal 3 and the fourth terminal 4 which are respectively output terminals. Moreover, when a load (not shown) is connected to the third terminal 3 and the fourth terminal 4, the output signal is transmitted to the load. It should be noted that, as described later, each functional block in the solid-state relay 200 may be provided on different substrates. In this case, the fifth and sixth terminals 5, 6 function as input terminals for a fourth signal input to the output circuit 60.

[0045] The oscillation circuit 10 outputs a first signal based on the input signal Vin applied between the first terminal 1 and the second terminal 2. As Figure 2 shown, the oscillation circuit 10 has first to third inverters 11 to 13, a resistor 14, and a capacitor 15. The first to third inverters 11 to 13 are connected in series, and a capacitor 15 is connected in parallel at the connection point of the second inverter 12 and the third inverter 13. Moreover, a resistor 14 is connected in parallel to the output of the third inverter 13.

[0046] When the connection point of the second inverter 12 and the third inverter 13 becomes low potential, the output point of the third inverter 13 becomes high potential. When the current flowing through the resistor 14 charges the capacitor 15, the connection point of the second inverter 12 and the third inverter 13 rises from low potential to high potential. Then, the charge accumulated in the capacitor 15 is discharged via the resistor 14, and the connection point of the second inverter 12 and the third inverter 13 becomes low potential.

[0047] These operations are periodically repeated, and the output signal of the third inverter 13 is output as the first signal. It should be noted that the structure of the oscillation circuit 10 is not particularly limited to Figure 2 the structure shown.

[0048] The inductor 20 amplifies the first signal input from the oscillation circuit 10 and outputs it as a second signal. As Figure 1 , 2As shown, inductor 20 is a transformer having a first inductor 21 and a second inductor 22. A first signal input to the first inductor 21 is output to the second inductor 22 magnetically coupled to the first inductor 21. At this time, the first signal is amplified at a voltage transformation ratio corresponding to the turns ratio of the first inductor 21 and the second inductor 22, and is output as a second signal to the rectifier circuit 30.

[0049] The rectifier circuit 30 rectifies the second signal input from the second inductor 22 of the inductor 20, and outputs it as a third signal. Figure 2 The rectifier circuit 30 shown is composed of a diode 31, but it may have other structures.

[0050] The voltage regulator circuit 40 stabilizes the voltage of the third signal input from the rectifier circuit 30, and outputs it as a fourth signal. Figure 2 The voltage regulator circuit 40 shown is composed of a Zener diode 41 connected in parallel with the rectifier circuit 30, and the voltage value of the fourth signal is clamped by the Zener voltage of the Zener diode 41. It should be noted that the voltage regulator circuit 40 is not particularly limited to Figure 2 the structure shown. This will be described below.

[0051] As Figure 2 shown, the charge and discharge circuit 50 has an NPN bipolar transistor 51, a resistor 52A, and a diode 53. The resistor 52A is connected between the collector and the base of the NPN bipolar transistor 51, and the diode 53 is connected between the base and the emitter of the NPN bipolar transistor 51. Moreover, the collector of the NPN bipolar transistor 51 is connected to the gates of the first MOSFET 61 and the second MOSFET 62, and the emitter is connected to the sources of the first MOSFET 61 and the second MOSFET 62.

[0052] When the fourth signal is input from the voltage regulator circuit 40 to the charge and discharge circuit 50, the collector of the NPN bipolar transistor 51 becomes high potential. However, since the base of the NPN bipolar transistor 51 is at low potential, the base-emitter voltage is almost zero, and the NPN bipolar transistor 51 is turned off (OFF). In this case, due to the current flowing through the resistor 52A, current flows between the gate and the source of the first MOSFET 61 and the second MOSFET 62, and these gates are charged.

[0053] When the input of the fourth signal from the voltage stabilizing circuit 40 stops, the charges accumulated in the gates of the first MOSFET 61 and the second MOSFET 62 are supplied to the base of the NPN bipolar transistor 51, and the NPN bipolar transistor 51 conducts (turns ON). As soon as the NPN bipolar transistor 51 conducts, the charges are taken from the gates of the first MOSFET 61 and the second MOSFET 62 via the NPN bipolar transistor 51, and these gates are discharged. The diode 53 is provided to prevent the current from flowing reversely toward the output circuit 60 when charging the gate and to enhance the extraction of charges from the gate when discharging the gate. It should be noted that the charge and discharge circuit 50 is not particularly limited to Figure 2 the structure shown. This will be described below.

[0054] The output circuit 60 includes a first MOSFET 61 and a second MOSFET 62. The first MOSFET 61 and the second MOSFET 62 are each an N-channel enhancement-mode MOSFET (hereinafter simply referred to as an E-MOSFET). The source of the first MOSFET 61 is connected to the source of the second MOSFET 62. The drain of the first MOSFET 61 is connected to the third terminal 3, and the drain of the second MOSFET 62 is connected to the fourth terminal 4. It should be noted that in the following description, the first MOSFET 61 may sometimes be referred to as the first semiconductor switch 61, and the second MOSFET 62 may sometimes be referred to as the second semiconductor switch 62.

[0055] Figure 3A is a cross-sectional schematic diagram showing an example of the first MOSFET, Figure 3B is a cross-sectional schematic diagram showing another example of the first MOSFET. It should be noted that in the present embodiment, the first MOSFET 61 and the second MOSFET 62 have the same cross-sectional structure. Therefore, Figure 3A 、 3B the cross-sectional structure shown also applies to the second MOSFET 62. It should be noted that in the present embodiment, the first MOSFET 61 and the second MOSFET 62 have the same input and output characteristics.

[0056] Figure 3A The first MOSFET 61 shown in + is a known vertical MOSFET. On the surface of the substrate 70, a gate electrode 74 is provided with a gate oxide film 73 interposed therebetween. Moreover, when viewed from a direction orthogonal to the surface of the substrate 70, a p-type well 71 is formed so as to surround the gate electrode 74. A high-concentration n-type region 72 (n + region 72) is formed on the surface of the substrate 70 inside the p-type well 71. The n Figure 3AIn the example shown, the source electrode 75 is directly formed on the surface of the n + region 72. However, in reality, the source electrode 75 is formed on the surface of an interlayer insulating film (not shown), which is formed on the surface of the substrate 70. The source electrode 75 and the n + region 72 are electrically connected via a contact hole (not shown) passing through the interlayer insulating film.

[0057] The substrate 70 includes an n － region 70a and an n － region 70b provided on the back surface of the n + region 70a. The drain region is composed of the n － region 70a and the n + region 70b. A drain electrode 76 is formed on the back surface of the n + region 70b. That is, Figure 3A in the first MOSFET 61 shown, a gate terminal and a source terminal are provided on the surface of the substrate 70, and a drain terminal is provided on the back surface of the substrate 70. Figure 3A In the first MOSFET 61 shown, a long longitudinal distance for applying a drain voltage can be ensured in the drain region, so high breakdown voltage can be achieved.

[0058] Figure 3B The first MOSFET 61 shown is a known lateral MOSFET. On the surface of the substrate 70, a gate electrode 74 is provided with a gate oxide film 73 interposed therebetween. The substrate 70 is a p-type semiconductor substrate. On both sides of the gate electrode 74, n + regions 72 are formed sandwiching the gate electrode 74. One side is the source region and the other side is the drain region. It should be noted that, Figure 3B in the example shown, the source electrode 75 and the drain electrode 76 are directly formed on the surface of the n + region 72, respectively. However, in reality, as described above, the source electrode 75 is electrically connected to the n + region 72 via a contact hole (not shown) penetrating the interlayer insulating film; the drain electrode 76 is electrically connected to the n + region 72 via a contact hole (not shown) penetrating the interlayer insulating film. That is, Figure 3B in the first MOSFET 61 shown, a gate terminal, a source terminal, and a drain terminal are provided on the surface of the substrate 70. Figure 3B In the first MOSFET 61 shown, since the source-drain distance can be shortened, high speed can be achieved. Whether the first MOSFET 61 and the second MOSFET 62 adopt the Figure 3A structure shown or the Figure 3B structure shown can be appropriately selected according to the type of the signal transmitted between the third terminal 3 and the fourth terminal 4.

[0059] In the solid-state relay 200, Figure 1 The respective functional blocks shown are provided on different substrates. Each of the substrates 151 to 155, 1545 is, for example, a silicon chip. The substrate 70 is a single-crystalline silicon substrate. However, depending on the types of the first MOSFET 61 and the second MOSFET 62, the fourth substrate 154, the fifth substrate 155, and the substrate 1545 may sometimes be compound semiconductor chips. The substrate 70 may sometimes be a compound semiconductor single-crystalline substrate.

[0060] Figure 4A is a schematic diagram showing a set of substrates mounted on the solid-state relay. Figure 4B is a schematic diagram showing another set of substrates mounted on the solid-state relay.

[0061] For example, as Figure 4A , 4B shows, the oscillation circuit 10 is provided on the first substrate 151; the inductor 20 is provided on the second substrate 152; the rectifier circuit 30, the voltage regulator circuit 40, and the charge and discharge circuit 50 are provided on the third substrate 153. By mounting the inductor 20 and other functional blocks on different substrates, electromagnetic noise can be prevented from mixing into the first to fourth signals. Moreover, the withstand voltage between the input and output of the solid-state relay 200 can also be improved. Also, as Figure 4A shows, by making the fourth substrate 154 on which the first MOSFET 61 is formed and the fifth substrate 155 on which the second MOSFET 62 is formed different substrates from each other, the withstand voltage and current capacity of the output circuit 60 can be improved. It should be noted that if the withstand voltage and current capacity of the output circuit 60 can be sufficiently ensured, the first MOSFET 61 and the second MOSFET 62 may also be formed on the same substrate 1545 as shown in Figure 4B .

[0062] [Operating conditions of the solid-state relay]

[0063] The fourth signal is respectively input between the gate and source of the first MOSFET 61 and between the gate and source of the second MOSFET 62.

[0064] When the voltage value of the fourth signal exceeds the threshold voltages of the first MOSFET 61 and the second MOSFET 62, the first MOSFET 61 and the second MOSFET 62 are respectively turned on, and the drains of the first MOSFET 61 and the second MOSFET 62 become conducting states. The third terminal 3 is connected to the drain of the first MOSFET 61, and the fourth terminal 4 is connected to the drain of the second MOSFET 62. Therefore, a conducting state is formed between the third terminal 3 and the fourth terminal 4, and thus a signal can be transmitted between the third terminal 3 and the fourth terminal 4.

[0065] In Figure 1 、 2 In the output circuit 60 shown, when the third terminal 3 is at a high potential relative to the fourth terminal 4, a signal is transmitted from the third terminal 3 to the fourth terminal 4 via the first MOSFET 61 and the second MOSFET 62. When the third terminal 3 is at a low potential relative to the fourth terminal 4, the signal is transmitted from the fourth terminal 4 to the third terminal 3 via the first MOSFET 61 and the second MOSFET 62.

[0066] When the voltage value of the fourth signal is lower than the threshold voltages of the first MOSFET 61 and the second MOSFET 62, the first MOSFET 61 and the second MOSFET 62 are respectively turned off, and the drains of the first MOSFET 61 and the second MOSFET 62 become non-conductive states. Therefore, the third terminal 3 and the fourth terminal 4 also become non-conductive states, and the transmission of the signal between the third terminal 3 and the fourth terminal 4 is cut off.

[0067] [Effects, etc.]

[0068] As described above, the solid-state relay 200 according to the present embodiment includes at least an oscillation circuit 10, an inductor 20, a rectifier circuit 30, a voltage regulator circuit 40, and a charge and discharge circuit 50. Moreover, the solid-state relay 200 further includes the first MOSFET 61 and the second MOSFET 62 as the output circuit 60.

[0069] The oscillation circuit 10 outputs a first signal; the inductor 20 amplifies the first signal input from the oscillation circuit 10 and outputs it as a second signal; the rectifier circuit 30 rectifies the second signal input from the inductor 20 and outputs it as a third signal.

[0070] The voltage regulator circuit 40 stabilizes the voltage of the third signal and outputs it as a fourth signal; the charge and discharge circuit 50 inputs the fourth signal input from the voltage regulator circuit 40 to the gates of the first MOSFET 61 and the second MOSFET 62 respectively, and charges these gates. Alternatively, the charge and discharge circuit 50 inputs the fourth signal input from the voltage regulator circuit 40 to the gates of the first MOSFET 61 and the second MOSFET 62 respectively, and takes away the charge based on the fourth signal accumulated in the gates from the gates to perform discharge.

[0071] The inductor 20 has a first inductor 21 to which the first signal is input from the oscillation circuit 10 and a second inductor 22 that outputs the second signal to the rectifier circuit 30.

[0072] According to the present embodiment, by providing the inductor 20, the first signal can be amplified at a voltage transformation ratio corresponding to the turn ratio between the first inductor 21 and the second inductor 22. In this way, even when the input signal Vin is a small signal with a small voltage value, the fourth signal for driving the gates of the first MOSFET 61 and the second MOSFET 62 can be made large enough. Therefore, even when the current driving forces of the first MOSFET 61 and the second MOSFET 62 are large and the withstand voltages are high, the first MOSFET 61 and the second MOSFET 62 can be sufficiently driven. Moreover, heat generation during switching can be suppressed, and high withstand voltage and high capacitance semiconductor switch elements containing compound semiconductors can be used as the first semiconductor switch 61 and the second semiconductor switch 62.

[0073] The output circuit 60 is composed of a first MOSFET 61 and a second MOSFET 62 whose sources are connected to each other. In this way, a signal can be transmitted from the third terminal 3 to the fourth terminal 4 and a signal can be transmitted from the fourth terminal 4 to the third terminal 3. That is, bidirectional signal transmission can be performed.

[0074] It should be noted that the output circuit 60 may have only either the first MOSFET 61 or the second MOSFET 62. For example, when the output circuit 60 has only the first MOSFET 61, the gate of the first MOSFET 61 is connected to the fifth terminal 5, and the source of the first MOSFET 61 is connected to the sixth terminal 6. In this case, when the fourth signal is input to the first MOSFET 61 from the charge and discharge circuit 50, the first MOSFET 61 is turned on, and a signal is transmitted from the third terminal 3 to the fourth terminal 4. When the input of the fourth signal from the charge and discharge circuit 50 stops, the first MOSFET 61 is turned off, and the transmission of the signal between the third terminal 3 and the fourth terminal 4 is cut off.

[0075] According to this embodiment, after the second signal output from the inductor 20 is rectified by the rectifier circuit 30, it is converted into a third signal. After the voltage of the third signal is stabilized in the voltage stabilizing circuit 40, it is output as a fourth signal to the charge and discharge circuit 50. By doing so, even when the voltage value of the second signal output from the inductor 20 fluctuates significantly due to load conditions or the like connected to the output circuit 60, the voltage stabilizing circuit 40 can also stabilize the voltage value of the third signal. In other words, by keeping the voltage value of the third signal constant by the voltage stabilizing circuit 40, it is ensured that the voltage value of the third signal does not exceed the specified value. In this way, it is possible to suppress the occurrence of failures in both the first semiconductor switch 61 and the second semiconductor switch 62, or the occurrence of a failure in either the first semiconductor switch 61 or the second semiconductor switch 62 due to excessive voltage input to the output circuit 60. Moreover, the operations of the first semiconductor switch 61 and the second semiconductor switch 62 can be stabilized respectively. The operating reliability of the solid-state relay 200 can also be improved.

[0076] Preferably, each functional block of the solid-state relay 200 is arranged on a different substrate. For example, as Figure 4A shown, the oscillation circuit 10 is arranged on the first substrate 151; the inductor 20 is arranged on the second substrate 152; the rectifier circuit 30, the voltage stabilizing circuit 40, and the charge and discharge circuit 50 are arranged on the third substrate 153. Moreover, the first MOSFET 61 is arranged on the fourth substrate 154. The second MOSFET 62 is arranged on the fifth substrate 155.

[0077] In this way, by arranging the inductor 20 and other functional blocks on different substrates, it is possible to prevent the electromagnetic noise amplified by the inductor 20 or generated by the inductor 20 from mixing into the first to fourth signals. The insulation withstand voltage between the input and output of the solid-state relay 200 can also be improved. By setting the fourth substrate 154 on which the first MOSFET 61 is arranged and the fifth substrate 155 on which the second MOSFET 62 is arranged as different substrates, the withstand voltage and current capacity of the output circuit 60 can be improved. It should be noted that the first MOSFET 61 and the second MOSFET 62 can also be formed on the substrate 1545. The substrate 1545 can be regarded as the substrate after the integration of the fourth substrate 154 and the fifth substrate 155.

[0078] <Variant 1>

[0079] Figure 5A is a schematic diagram showing a set of substrates installed in the solid-state relay according to Variant 1. Figure 5B is a schematic diagram showing another set of substrates installed in the solid-state relay according to Variant 1.

[0080] It should be noted that for ease of explanation, in Figure 5AIn each of the drawings shown hereinafter, the same reference numerals are given to the same parts as those in the first embodiment, and detailed descriptions thereof are omitted.

[0081] As described in the first embodiment, by arranging each functional block of the solid-state relay 200, particularly the inductor 20 and other functional blocks, on different substrates, it is possible to prevent electromagnetic noise amplified by the inductor 20 or generated by the inductor 20 from mixing into the first to fourth signals, and it is also possible to improve the withstand voltage between the input and output of the solid-state relay 200.

[0082] In the first embodiment, an example is shown in which the second substrate 152 on which the inductor 20 is arranged is completely separated from the first substrate 151, the third substrate 153 to the fifth substrate 155 on which other functional blocks are arranged.

[0083] However, if the purpose is to improve the withstand voltage between the input and output of the solid-state relay 200, then as Figure 5A shown, the inductor 20 and the oscillation circuit 10 as its pre-stage circuit can be arranged on the same substrate 1512. In this case, the substrate 1512 is separated from the third substrate 153 of the post-stage circuit in which the inductor 20 is arranged. The substrate 1512 can be said to be a substrate after the integration of the first substrate 151 and the second substrate 152.

[0084] Or, as Figure 5B shown, the inductor 20 and the rectifier circuit 30, the voltage regulator circuit 40, and the charge and discharge circuit 50 as its post-stage circuit can be arranged on the same substrate 1523. In this case, the substrate 1523 is separated from the first substrate 151 of the pre-stage circuit in which the inductor 20 is arranged, that is, the oscillation circuit 10. The substrate 1523 can be said to be a substrate after the integration of the second substrate 152 and the third substrate 153.

[0085] It should be noted that in the examples shown in Figure 5A 、 Figure 5B it is also possible to form the first MOSFET 61 and the second MOSFET 62 on the substrate 1545 as shown in Figure 4B shown.

[0086] <Variation 2>

[0087] Figure 6A is a circuit diagram of the first charge and discharge circuit according to Variation 2. Figure 6B is a circuit diagram of the second charge and discharge circuit according to Variation 2. Figure 6C is a circuit diagram of the third charge and discharge circuit according to Variation 2. Figure 7 is a circuit diagram of the voltage regulator circuit according to Variation 2.

[0088] As described above, the circuit structures of the charge and discharge circuit 50 and the voltage regulator circuit 40 are not limited toFigure 2 The example shown.

[0089] For example, it can also be configured like Figures 6A to 6C shown to form the charge and discharge circuit 50. In Figure 6A the example shown, the charge and discharge circuit 50 includes a PNP bipolar transistor 54, a resistor 52B, and a diode 53. The cathode of the diode 53 is connected to the emitter of the PNP bipolar transistor 54, and the anode of the diode 53 is connected to the oscillation circuit 10. The resistor 52B is connected between the base and collector of the PNP bipolar transistor 54.

[0090] In Figure 6A the charge and discharge circuit 50 shown, when the fourth signal is input from the voltage regulator circuit 40, the diode 53 is forward-biased, and the emitter of the PNP bipolar transistor 54 becomes high potential. On the other hand, since the base of the PNP bipolar transistor 54 also becomes high potential like the emitter, the PNP bipolar transistor 54 is cut off. Due to the current flowing through the diode 53, current flows between the gate and source of each of the first MOSFET 61 and the second MOSFET 62, and these gates are charged.

[0091] When the input of the fourth signal from the voltage regulator circuit 40 stops, the charges accumulated in the gates of the first MOSFET 61 and the second MOSFET 62 are supplied to the base of the PNP bipolar transistor 54 via the resistor 52B, and the PNP bipolar transistor 54 conducts. As soon as the PNP bipolar transistor 54 conducts, the charges are taken from the gates of the first MOSFET 61 and the second MOSFET 62 via the PNP bipolar transistor 54, and these gates are discharged. Moreover, since the diode 53 is reverse-biased, it prevents current from flowing backward toward the rectifier circuit 30.

[0092] In Figure 6B the example shown, the charge and discharge circuit 50 includes an N-channel depletion-type MOSFET (hereinafter simply referred to as D-MOSFET) 55 (hereinafter also simply referred to as D-MOSFET 55), a resistor 52C, and a diode array 56. The cathode of the diode array 56 is connected to the gate of the D-MOSFET 55, and the anode of the diode array 56 is connected to the source of the D-MOSFET 55. The resistor 52C is connected in parallel with the diode array 56 between the gate and source of the D-MOSFET 55.

[0093] In Figure 6BIn the charge and discharge circuit 50 shown, when a fourth signal is input from the voltage stabilizing circuit 40, the drain of the D-MOSFET 55 becomes a high potential. Therefore, the D-MOSFET 61 conducts temporarily, and current flows between the drain and source. However, when this current flows through the resistor 52C, a potential difference is generated across the resistor 52C, and the D-MOSFET 55 is turned off due to this potential difference. In this case, current flows between the gate-source of each of the first MOSFET 61 and the second MOSFET 62, and these gates are charged.

[0094] When the input of the fourth signal from the voltage stabilizing circuit 40 stops, current no longer flows through the resistor 52C. Therefore, the D-MOSFET 55 conducts. The charges stored in the gates of each of the first MOSFET 61 and the second MOSFET 62 are taken from the gates of each of the first MOSFET 61 and the second MOSFET 62 via the D-MOSFET 55, the resistor 52C, and the diode array 56, and these gates are discharged.

[0095] Figure 6C The charge and discharge circuit 50 shown, with respect to Figure 6B the circuit shown, an N-channel D-MOSFET 57 (hereinafter simply referred to as D-MOSFET 57) is provided in place of the D-MOSFET 55, and an N-channel D-MOSFET 58 (hereinafter simply referred to as D-MOSFET 58) is provided in place of the diode array 56. The D-MOSFET 58 has a diode connection structure in which the gate and drain are short-circuited.

[0096] In Figure 6C the charge and discharge circuit 50 shown, the role played by the D-MOSFET 57 is the same as that of Figure 6B the D-MOSFET 55 shown, and the role played by the D-MOSFET 58 is the same as that of Figure 6B the diode array 56 shown. The role played by the resistor 52D is the same as that of Figure 6B the resistor 52C shown. Therefore, since Figure 6C the charge and discharge operation of the charge and discharge circuit 50 shown is the same as that of Figure 6B the charge and discharge circuit 50 shown, the description thereof is omitted.

[0097] As Figure 7 shown, the voltage stabilizing circuit 40 can also be configured. Figure 7The voltage stabilizing circuit 40 shown is a so-called LDO (Low Drop Out) regulator, which includes an N-channel D-MOSFET 42 (hereinafter simply referred to as D-MOSFET 42), an error amplifier 43, and resistors 44 and 45. The resistors 44 and 45 are connected in series, and the connection point is connected to the feedback terminal (+ terminal) of the error amplifier 43. The reference terminal (- terminal) of the error amplifier 43 is connected to a reference voltage source (reference voltage: Vref). The output terminal of the error amplifier 43 is connected to the gate of the D-MOSFET 42.

[0098] When a third signal is input from the rectifying circuit 30, the D-MOSFET 42 conducts, and a fourth signal is supplied to the charge and discharge circuit 50. When the voltage value of the third signal is higher than a specified value, the feedback voltage input to the feedback terminal of the error amplifier 43 is higher than the reference voltage Vref. At this time, since the output voltage of the error amplifier 43 increases according to the difference between the feedback voltage and the reference voltage Vref, the on-resistance of the D-MOSFET 42 decreases. As a result, a fourth signal having a voltage value lower than that of the third signal is supplied to the charge and discharge circuit 50. In this way, an excessive voltage is prevented from being applied to the charge and discharge circuit 50, and further, an excessive voltage is prevented from being applied to the output circuit 60.

[0099] (Second Embodiment)

[0100] Figure 8 is a functional block diagram of the solid-state relay according to the second embodiment. Figure 9 is a schematic diagram showing a set of substrates mounted on the solid-state relay. Figure 10 is a functional block diagram of another solid-state relay according to the second embodiment. Figure 11 is a schematic diagram showing another set of substrates mounted on the solid-state relay. Figure 12 is a functional block diagram of yet another solid-state relay according to the second embodiment. Figure 13 is a schematic diagram showing another set of substrates mounted on the solid-state relay.

[0101] When various protection functions are given to the output circuit 60, various methods can be adopted. For example, as Figure 8 shown, in the solid-state relay 210, protection circuits 80A and 80B can also be given to the first MOSFET 61 and the second MOSFET, respectively. In this case, as Figure 9 shown, the first MOSFET 61 and the protection circuit 80A are formed on the fourth substrate 154; the second MOSFET 62 and the protection circuit 80B are formed on the fifth substrate 155.

[0102] That is to say, in Figure 8 , 9In the solid-state relay 210 shown, a protection circuit 80A for protecting the first MOSFET 61 is provided between the charge and discharge circuit 50 and the first MOSFET 61. Moreover, a protection circuit 80B for protecting the second MOSFET 62 is provided between the charge and discharge circuit 50 and the second MOSFET 62. As will be described later, the protection circuits 80A and 80B are not limited to one type, and there are cases where the protection circuits 80A and 80B include multiple circuits. It should be noted that the protection circuits 80A and 80B are sometimes collectively referred to as the protection circuit 80.

[0103] The protection circuit 80 can also be separately provided from the output circuit 60. For example, as Figure 10 , 11 shown, in the solid-state relay 211, the protection circuit 80 can also be further provided on the third substrate 153 where the rectification circuit 30, the voltage regulation circuit 40, and the charge and discharge circuit 50 are provided. It can also be as Figure 12 , 13 shown, in the solid-state relay 212, a sixth substrate 156 is further provided, and the protection circuit 80 is formed on the sixth substrate 156. Like the first to third substrates 151 to 153, the sixth substrate 156 is a silicon chip. The sixth substrate 156 is arranged between the third substrate 153, the fourth substrate 154, and the fifth substrate 155 where the rectification circuit 30, the voltage regulation circuit 40, and the charge and discharge circuit 50 are provided.

[0104] According to the present embodiment, by providing the protection circuit 80 that has appropriate functions respectively for changes in the voltage applied to the output circuit 60, changes in the current flowing into the output circuit 60, and temperature rise of the output circuit 60 during operation, it is possible to suppress the influence of the voltage change, current change, temperature rise, etc.

[0105] Figure 14A is the circuit diagram of the overcurrent protection circuit. Figure 14B is the circuit diagram of the overtemperature protection circuit. Figure 15A is the circuit diagram of the overvoltage protection circuit. Figure 15B is the circuit diagram of another overvoltage protection circuit. It should be noted that Figures 14A to 15B and Figure 18 the diode 61A shown is a parasitic diode (body diode) built in the first MOSFET 61, Figure 14A the diode 62A shown is a parasitic diode (body diode) built in the second MOSFET 62.

[0106] Select appropriate circuits from Figures 14A to 15B the various circuits shown to form the protection circuit 80. One can be selected only from these, or multiple can be selected.

[0107] Figure 14A The overcurrent protection circuit 90 shown has differential amplifiers 91, 92, detection resistors 93, 94, and a controller 95. The controller 95 includes one or more ICs (Integrated Circuit) or one or more LSIs (Large Scale Integration).

[0108] The detection resistors 93, 94 are connected in series between the source of the first MOSFET 61 and the source of the second MOSFET 62. Two input terminals of the differential amplifier 91 are respectively connected to both ends of the detection resistor 93, and two input terminals of the differential amplifier 92 are respectively connected to both ends of the detection resistor 94.

[0109] One input terminal (the - terminal) of the differential amplifiers 91, 92 is connected to the connection point of the detection resistor 93 and the detection resistor 94. The controller 95 has three input terminals which are respectively connected to the output terminal of the differential amplifier 91, the output terminal of the differential amplifier 92, and the connection point of the detection resistor 93 and the detection resistor 94. The controller 95 has two output terminals which are respectively connected to the gate of the first MOSFET 61 and the gate of the second MOSFET 62. The first MOSFET 61 and the second MOSFET 62 are driven based on the output signal of the controller 95.

[0110] When an overcurrent flows through at least one of the first MOSFET 61 and the second MOSFET 62, the potential differences across both ends of the detection resistor 93 and the potential differences across both ends of the detection resistor 94 increase respectively. The differential amplifiers 91, 92 output amplified signals to the controller 95 according to the potential differences, and the controller 95 stops outputting the fourth signal to the gates of the first MOSFET 61 and the second MOSFET 62 based on this signal, and turns off the first MOSFET 61 and the second MOSFET 62.

[0111] By doing so, it is possible to prevent the overcurrent from flowing into the first MOSFET 61 and the second MOSFET 62, and to prevent the output characteristics from degrading or the components from malfunctioning.

[0112] Figure 14BThe over-temperature protection circuit 100 shown is provided with a differential amplifier 101, a diode array 102 for detecting temperature, a resistor 103, and a controller 104, and is connected to the first MOSFET 61. The controller 104, like the controller 95, includes a plurality of ICs, or one or more LSIs. It should be noted that although not shown in the figure, the over-temperature protection circuit 100 is also connected to the second MOSFET 62. However, the differential amplifier 101, the diode array 102, and the resistor 103 are respectively provided for the first MOSFET 61 and the second MOSFET 62.

[0113] The resistor 103 and the diode array 102 are connected in series, and the anode side of the diode array 102 is connected to the gate of the first MOSFET 61 via the resistor 103. The midpoint of the diode array 102 is connected to the feedback terminal (+ terminal) of the differential amplifier 101; the reference terminal (- terminal) of the differential amplifier 101 is connected to a reference voltage source (reference voltage: Vref). The three input terminals of the controller 104 are respectively connected to the gate of the first MOSFET 61, the output terminal of the differential amplifier 101, and the cathode side of the diode array 102. The first MOSFET 61 is driven based on the output signal of the controller 104.

[0114] The voltage across the diode array 102 has a negative correlation with temperature. Therefore, during operation, when the temperature of the first MOSFET 61 rises, the voltage across the diode array 102 decreases, and the voltage input to the feedback terminal of the differential amplifier 101 also decreases. When the temperature of the first MOSFET 61 rises above a specified value and, correspondingly, the voltage across the diode array 102 decreases, the output of the differential amplifier 101 approaches zero. The controller 104 receives the output signal of the differential amplifier 101. When the magnitude of the output signal is lower than the set value, the controller 104 stops outputting the fourth signal to the gate of the first MOSFET 61, and turns off the first MOSFET 61.

[0115] This can suppress the temperature of the first MOSFET 61 from rising above the specified value, and prevent the output characteristics from deteriorating or the components from malfunctioning.

[0116] Figure 15A The over-voltage protection circuit 110 shown includes a differential amplifier 111, an N-channel enhancement-mode MOSFET 112 (hereinafter simply referred to as MOSFET 112), and resistors 113 and 114, and is connected to the first MOSFET 61. It should be noted that although not shown in the figure, the second MOSFET 62 is also connected with Figure 15AThe overvoltage protection circuit 110 shown. However, for the first MOSFET 61 and the second MOSFET 62, respective overvoltage protection circuits 110 are provided.

[0117] The MOSFET 112 is connected in parallel with the first MOSFET 61. Moreover, the resistors 113 and 114 connected in series are both connected in parallel with the MOSFET 112 and the first MOSFET 61. The connection point between the resistor 113 and the resistor 114 is connected to the feedback terminal (+ terminal) of the differential amplifier 111; the reference terminal (- terminal) of the differential amplifier 111 is connected to a reference voltage source (reference voltage: Vref). The output terminal of the differential amplifier 111 is connected to the gate of the MOSFET 112.

[0118] When an overvoltage is applied to the drain of the first MOSFET 61, correspondingly, the potential of the connection point between the resistor 113 and the resistor 114 rises, and the input voltage to the feedback terminal of the differential amplifier 111 also rises. When this input voltage exceeds a specified value, the output of the differential amplifier 111 rises and the MOSFET 112 conducts. Moreover, the on-resistance of the MOSFET 112 decreases. Correspondingly, the voltage applied to the drain of the first MOSFET 61 drops.

[0119] By doing so, it is possible to suppress the voltage applied to the drain of the first MOSFET 61 from rising above the specified value and prevent component failure or damage.

[0120] Figure 15B The overvoltage protection circuit 110 shown, for Figure 15A the overvoltage protection circuit 110 shown, the differential amplifier 111 is omitted. Moreover, a Zener diode 115 is arranged in place of the resistor 113. The anode of the Zener diode 115 is connected to the resistor 114, and the cathode is connected to the drains of the first MOSFET 61 and the MOSFET 112. It should be noted that although not shown in the figure, the same overvoltage protection circuit 110 is also connected to the second MOSFET 62. Figure 15B The overvoltage protection circuit 110 shown. However, for the first MOSFET 61 and the second MOSFET 62, respective overvoltage protection circuits 110 are provided.

[0121] When an overvoltage is applied to the drain of the first MOSFET 61, correspondingly, the reverse voltage applied to the Zener diode 115 also rises. When this reverse voltage exceeds the breakdown voltage, a large current flows through the Zener diode 115 and the MOSFET 112 conducts. Moreover, the on-resistance of the MOSFET 112 decreases. Correspondingly, the voltage applied to the drain of the first MOSFET 61 drops.

[0122] By doing so, it is possible to suppress the voltage applied to the drain of the first MOSFET 61 from rising above a specified value, preventing component failure or damage.

[0123] As described above, in the solid-state relays 210 to 212 of the present embodiment, the first signal input from the oscillation circuit 10 is subjected to signal processing such as amplification and rectification to generate a fourth signal. That is, it is possible to supply necessary drive power to the protection circuit 80.

[0124] As Figure 10 , 11 shown, by forming the protection circuit 80 on the third substrate 153 on which the voltage regulator circuit 40 and the like are formed, the protection circuit 80 can be constituted by the same circuit as the voltage regulator circuit 40 and the like. For example, the controllers 95 and 104 can be constituted by CMOS logic circuits. As a result, the protection circuit 80 can perform complex arithmetic processing, and thus more precise protection work for the output circuit 60 can be achieved. As Figure 12 , 13 shown, the same applies when the protection circuit 80 is formed on the dedicated sixth substrate 156. The protection circuit 80 can be constituted by a CMOS logic circuit to perform complex arithmetic processing, and thus more precise protection work for the output circuit 60 can be achieved.

[0125] It should be noted that Figure 14B shown, the over-temperature protection circuit 100 is preferably arranged near the first MOSFET 61 and the second MOSFET 62. For example, it is preferable to assemble the over-temperature protection circuit 100 in the protection circuit 80A provided on the fourth substrate 154 or the protection circuit 80B provided on the fifth substrate 155 as Figure 8 , 9 shown.

[0126] By doing so, it is possible to quickly detect the temperature changes of the first MOSFET 61 and the second MOSFET 62, achieve more precise over-temperature protection work for the output circuit 60, and also reduce the influence of temperature rise during the operation of other circuits.

[0127] (Third Embodiment)

[0128] Figure 16 is a functional block diagram of the solid-state relay according to the third embodiment. Figure 17A is a schematic diagram showing a set of substrates mounted on the solid-state relay. Figure 17B is a schematic diagram showing another set of substrates mounted on the solid-state relay. Figure 18 is a circuit diagram of the fault detection circuit.

[0129] As Figure 16As shown, the solid-state relay 220 of the present embodiment includes a fault detection circuit 120 between the charge and discharge circuit 50 and the output circuit 60. By providing the fault detection circuit 120, faults in the first MOSFET 61 and the second MOSFET 62 included in the output circuit 60 can be detected inside the solid-state relay 220. Moreover, in the solid-state relay 220, the first signal input from the oscillation circuit 10 is subjected to signal processing such as amplification and rectification to generate a fourth signal. That is, necessary driving power can be supplied to the fault detection circuit 120.

[0130] When a fault in the first MOSFET 61 or the second MOSFET 62 is detected, a fault detection signal is output from the fault detection circuit 120. The fault detection signal is input to the first inductor 131 of the feedback inductor 130. The fault detection signal is modulated at a voltage transformation ratio corresponding to the turns ratio of the first inductor 131 and the second inductor 132, and is fed back from the second inductor 132 to the oscillation circuit 10. When the fault detection signal is input, the oscillation circuit 10 stops operating. Alternatively, the oscillation circuit 10 may be stopped when the magnitude of the fault detection signal input to the oscillation circuit 10 exceeds a specified threshold value.

[0131] As Figure 17A shown, the feedback inductor 130 is provided on the seventh substrate 157. By doing so, electromagnetic noise can be prevented from mixing into the first to fourth signals. The insulation breakdown voltage between the input and output of the solid-state relay 200 can also be improved.

[0132] It should be noted that, as Figure 17B shown, the inductor 20 and the feedback inductor 130 can be provided on the same substrate 1527. In this case, electromagnetic noise can also be prevented from mixing into the first to fourth signals. The insulation breakdown voltage between the input and output of the solid-state relay 200 can also be improved.

[0133] For example, as Figure 18 shown, the fault detection circuit 120 includes a differential amplifier 121, a resistor 122, a drive amplifier 123, and a receiving amplifier 124.

[0134] The resistor 122 is connected to the source of the first MOSFET 61, and the two input terminals of the differential amplifier 121 are respectively connected to both ends of the resistor 122. The output terminal of the differential amplifier 121 is connected to the drive amplifier 123. The drive amplifier 123 is connected to the first inductor 131 of the feedback inductor 130, and the receiving amplifier 124 is connected to the second inductor 132.

[0135] It should be noted that, although not shown in the figure, the second MOSFET 62 is also connected with Figure 18The illustrated fault detection circuit 120. However, for the first MOSFET 61 and the second MOSFET 62, respective fault detection circuits 120 are provided.

[0136] For example, when a fault occurs in the first MOSFET 61 and a short circuit occurs between the source and the drain, the amount of current flowing into the resistor 122 increases, and the potential difference across the resistor 122 becomes larger. The differential amplifier 121 outputs a signal corresponding to the change in the potential difference to the drive amplifier 123. Since the magnitude of the signal output from the drive amplifier 123 to the first inductor 131 changes, the voltage induced in the second inductor 132 due to magnetic coupling changes. The receiving amplifier 124 receives this voltage change and outputs a fault detection signal to the oscillation circuit 10.

[0137] In the case where a fault occurs in the first MOSFET 61 and an open state occurs between the source and the drain, the amount of current flowing into the resistor 122 decreases, and the potential difference across the resistor 122 becomes smaller. The differential amplifier 121 outputs a signal corresponding to the change in the potential difference to the drive amplifier 123. Since the magnitude of the signal output from the drive amplifier 123 to the first inductor 131 changes, the voltage induced in the second inductor 132 due to magnetic coupling changes. The receiving amplifier 124 receives this voltage change and outputs a fault detection signal to the oscillation circuit 10.

[0138] (Fourth Embodiment)

[0139] Figure 19 is a functional block diagram of a solid-state relay according to the fourth embodiment. Figure 20 is a circuit diagram of a low-voltage malfunction prevention circuit.

[0140] As Figure 19 shown, the solid-state relay 230 of the present embodiment includes a first low-voltage malfunction prevention circuit (first under-voltage lockout circuit: UVLO (Under Voltage Lock Out)) 140A between the rectifier circuit 30 and the voltage regulator circuit 40. A second low-voltage malfunction prevention circuit (second under-voltage lockout circuit: second UVLO) 140B is included between the first terminal 1 and the second terminal 2 and the oscillation circuit 10. It should be noted that the circuit structures of the first low-voltage malfunction prevention circuit 140A and the second low-voltage malfunction prevention circuit 140B are the same. Therefore, they are sometimes collectively referred to as the low-voltage malfunction prevention circuit (UVLO) 140.

[0141] Although not shown in the figure, the first low-voltage malfunction prevention circuit 140A is arranged on the same third substrate 153 as the rectifier circuit 30 and the voltage regulator circuit 40. The second low-voltage malfunction prevention circuit 140B is arranged on the same first substrate 151 as the oscillation circuit 10.

[0142] As Figure 20 shown, the low-voltage malfunction prevention circuit 140 includes an operational amplifier 141, resistors 142, 143, and an N-channel enhancement-mode MOSFET 144 (hereinafter simply referred to as MOSFET 144).

[0143] The resistors 142 and 143 connected in series are connected in parallel with the rectifier circuit 30. The connection point between the resistor 142 and the resistor 143 is connected to one of the two input terminals (+ terminal) of the operational amplifier 141. The other input terminal (- terminal) of the operational amplifier 141 is connected to a reference voltage source (reference voltage: Vref). The drain of the MOSFET 144 is connected to the rectifier circuit 30, and the source of the MOSFET 144 is connected to the voltage regulator circuit 40. The output terminal of the operational amplifier 141 is connected to the gate of the MOSFET 144.

[0144] When the voltage value of the second signal input from the inductor 20 to the rectifier circuit 30 decreases, the voltage value of the third signal input from the rectifier circuit 30 to the first low-voltage malfunction prevention circuit 140A also decreases. In this case, the potential at the connection point between the resistor 142 and the resistor 143, and even the potential at the + terminal of the operational amplifier 141, decrease. When the voltage value of the third signal is lower than the specified value, the output of the operational amplifier 141 is inverted, and the MOSFET 144 is turned off. Therefore, the voltage value of the third signal output to the voltage regulator circuit 40 further decreases, and the subsequent circuits of the voltage regulator circuit 40, i.e., the charge and discharge circuit 50 and the output circuit 60, stop operating.

[0145] As described above, according to the present embodiment, by providing the first low-voltage malfunction prevention circuit 140A between the rectifier circuit 30 and the voltage regulator circuit 40, the operation of the solid-state relay 230 can be stopped when the voltage value of the second signal or the third signal is lower than the specified value. By doing so, the malfunction of the solid-state relay 230 can be prevented.

[0146] When the voltage value of the input signal Vin decreases, the voltage value input to the second low-voltage malfunction prevention circuit 140B also decreases. In this case, the potential at the connection point between the resistor 142 and the resistor 143 and the potential at the + terminal of the operational amplifier 141 also decrease. When the voltage value of the input signal Vin is lower than the specified value, the output of the operational amplifier 141 is inverted, and the MOSFET 144 is turned off. Therefore, the voltage value input to the oscillation circuit decreases, and the oscillation circuit stops. By doing so, the oscillation circuit 10 can be stopped from operating, and further, the solid-state relay 230 can be stopped from operating to prevent the malfunction of the solid-state relay 230.

[0147] (Other Embodiments)

[0148] The respective constituent elements shown in the first to fourth embodiments and Modifications 1 and 2 can also be appropriately combined to form a new embodiment. For example, the first low-voltage malfunction prevention circuit 140A shown in the fourth embodiment can be provided in the solid-state relays 210 to 212 shown in the second embodiment or the solid-state relay 220 shown in the third embodiment. In the solid-state relays 210 to 212, 220, and 230 shown in the second to fourth embodiments, the charge-discharge circuit 50 can also be Figures 6A to 6C the circuit shown in any one of the figures in Figure 7 It is also possible to make the voltage regulator circuit 40 the circuit shown in

[0149] In the first to fourth embodiments, the semiconductor switch constituting the output circuit 60 is a MOSFET, but it is not particularly limited thereto, and it may also be a MISFET or a JFET (Junction Field-Effect Transistor).

[0150] -Industrial Applicability-

[0151] The solid-state relay of the present disclosure stabilizes the output voltage of the inductor and improves the operating reliability, and is therefore extremely useful.

[0152] -Symbolic Explanation-

[0153] 1 to 6 First to Sixth Terminals

[0154] 10 Oscillation Circuit

[0155] 11 to 13 First to Third Inverters

[0156] 14 Resistor

[0157] 15 Capacitor

[0158] 20 Inductor

[0159] 21 First Inductor

[0160] 22 Second Inductor

[0161] 30 Rectifier Circuit

[0162] 31 Diode

[0163] 40 Voltage Regulator Circuit

[0164] 41 Zener Diode

[0165] 42 N-channel Depletion-type MOSFET (D-MOSFET)

[0166] 43 Error Amplifier

[0167] 44, 45 Resistors

[0168] 50 Charge and discharge circuit

[0169] 51 NPN bipolar transistor

[0170] 52A - 52D Resistors

[0171] 53 Diode

[0172] 54 PNP bipolar transistor

[0173] 55 N-channel depletion MOSFET (D-MOSFET)

[0174] 56 Diode array

[0175] 57, 58 N-channel depletion MOSFET (D-MOSFET)

[0176] 60 Output circuit

[0177] 61 First MOSFET (First semiconductor switch)

[0178] 61A Parasitic diode

[0179] 62 Second MOSFET (Second semiconductor switch)

[0180] 62A Parasitic diode

[0181] 70 Substrate

[0182] 70a n － Region

[0183] 70b n + Region

[0184] 71 p-type well

[0185] 72 n + Region

[0186] 73 Gate oxide film

[0187] 74 Gate electrode

[0188] 75 Source electrode

[0189] 76 Drain electrode

[0190] 80 Protection circuit

[0191] 80A, 80B Protection circuits

[0192] 90 Overcurrent protection circuit

[0193] 91, 92 Differential amplifiers

[0194] 93 and 94 Detection Resistors

[0195] 95 Controller

[0196] 100 Over - temperature Protection Circuit

[0197] 101 Differential Amplifier

[0198] 102 Diode Array

[0199] 103 Resistor

[0200] 104 Controller

[0201] 110 Over - voltage Protection Circuit

[0202] 111 Differential Amplifier

[0203] 112 N - channel Enhancement - mode MOSFET

[0204] 113 and 114 Resistors

[0205] 115 Zener Diode

[0206] 120 Fault Detection Circuit

[0207] 121 Differential Amplifier

[0208] 122 Resistor

[0209] 123 Driver Amplifier

[0210] 124 Receiver Amplifier

[0211] 130 Feedback Inductor

[0212] 131 First Inductor

[0213] 132 Second Inductor

[0214] 140 Low - voltage Malfunction Prevention Circuit (UVLO (Under Voltage Lock Out)) 140A First Low - voltage Malfunction Prevention Circuit

[0215] 140B Second Low - voltage Malfunction Prevention Circuit

[0216] 141 Operational Amplifier

[0217] 142 and 143 Resistors

[0218] 144 N - channel Enhancement - mode MOSFET

[0219] 151 - 157 First - Seventh Substrates

[0220] 1512 Substrate

[0221] 1523 Substrate

[0222] 1527 Substrate

[0223] 1545 Substrate

[0224] 200 Solid State Relay

[0225] 210 - 212 Solid State Relay

[0226] 220 Solid State Relay

[0227] 230 Solid State Relay

Claims

1. A solid state relay, characterized in that: The solid-state relay includes an oscillation circuit, an inductor, a rectification circuit, a voltage regulation circuit, a first MOSFET, and a charge and discharge circuit. The oscillation circuit outputs a first signal. The inductor amplifies the first signal input from the oscillation circuit and outputs it as a second signal. The rectification circuit rectifies the second signal input from the inductor and outputs it as a third signal. The voltage regulation circuit stabilizes the voltage of the third signal and outputs it as a fourth signal. The first MOSFET is input with the fourth signal. The charge and discharge circuit charges the gate of the first MOSFET with the fourth signal output from the voltage regulation circuit, or discharges the fourth signal output from the voltage regulation circuit from the gate of the first MOSFET. The inductor includes a first inductor and a second inductor. The first signal is input from the oscillation circuit to the first inductor, and the second inductor outputs the second signal to the rectification circuit.

2. The solid state relay according to claim 1, characterized in that: The oscillation circuit is arranged on a first substrate. The inductor is arranged on a second substrate. The rectification circuit, the voltage regulation circuit, and the charge and discharge circuit are arranged on a third substrate. The first MOSFET is arranged on a fourth substrate.

3. The solid state relay according to claim 2, characterized in that: The first substrate and the second substrate are integrated.

4. The solid state relay according to claim 2, characterized in that: The second substrate and the third substrate are integrated.

5. The solid state relay according to any one of claims 2 to 4, characterized in that: The solid-state relay further includes a second MOSFET. The fourth signal is input to the second MOSFET. The charge and discharge circuit charges the gate of the first MOSFET with the fourth signal output from the voltage regulation circuit, or discharges the fourth signal output from the voltage regulation circuit from the gate of the first MOSFET.

6. The solid state relay according to claim 5, characterized in that: The second MOSFET is arranged on a fifth substrate.

7. The solid state relay according to claim 6, characterized in that: The fourth substrate and the fifth substrate are integrated.

8. The solid state relay according to any one of claims 2 to 7, characterized in that: A protection circuit for protecting the first MOSFET is included between the charge and discharge circuit and the first MOSFET.

9. The solid state relay according to claim 8, characterized in that: One or more protection circuits are provided between the charge and discharge circuit and the first MOSFET. The protection circuit includes at least one of an overcurrent protection circuit, an overvoltage protection circuit, or an overtemperature protection circuit. The protection circuit is arranged on the third substrate or the fourth substrate.

10. The solid state relay according to claim 8, characterized in that: The solid-state relay further includes a sixth substrate. One or more protection circuits are provided between the charge and discharge circuit and the first MOSFET. The protection circuit includes at least one of an overcurrent protection circuit, an overvoltage protection circuit, or an overtemperature protection circuit. The protection circuit is arranged on the sixth substrate.

11. The solid-state relay according to claim 9, wherein: The protection circuit arranged on the fourth substrate is the overtemperature protection circuit.

12. The solid-state relay according to any one of claims 2 to 11, wherein: The solid-state relay further includes a fault detection circuit for detecting a fault of the first MOSFET, a feedback inductor, and a seventh substrate. The fault detection circuit is also arranged on the third substrate. The feedback inductor is arranged on the seventh substrate. The fault detection signal output from the fault detection circuit is input to the oscillation circuit via the feedback inductor.

13. The solid-state relay according to claim 12, wherein: The second substrate and the seventh substrate are integrated.

14. The solid-state relay according to any one of claims 2 to 13, wherein: The solid-state relay further includes a first low-voltage malfunction prevention circuit, which is referred to as a first under-voltage lockout circuit. The first low-voltage malfunction prevention circuit is located between the rectification circuit and the voltage regulation circuit and is arranged on the third substrate.

15. The solid-state relay according to any one of claims 1 to 14, wherein: The solid-state relay further includes a second low-voltage malfunction prevention circuit, which is referred to as a second under-voltage lockout circuit. The second low-voltage malfunction prevention circuit inputs a low-voltage malfunction prevention signal to the oscillation circuit.

16. The solid-state relay according to any one of claims 1 to 15, wherein: The first MOSFET has a gate terminal on the surface and a drain terminal on the back.

17. The solid-state relay according to any one of claims 1 to 15, wherein: The first MOSFET has a gate terminal, a source terminal, and a drain terminal on the surface.

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