Digital open pin detection

Abstract

The invention relates to digital open pin detection. Apparatuses, devices, and systems for detecting open pins are described. The controller may control at least one power stage. The controller may include a first set of interface pins, a digital communications bus, and circuitry configured to switch a connection between a reference voltage and the first set of interface pins. The controller may read a pin state of the at least one power stage via the digital communication bus. The pin state may indicate whether a reference voltage is detected at a second set of interface pins of the at least one power stage. The controller may detect whether an open pin condition exists between the first set of interface pins and the second set of interface pins based on the pin state.

Description

Technical Field

[0001] The present disclosure relates to systems, devices, and methods for detecting open pin conditions between a controller and multiple power stages. Background Art

[0002] Different devices can be connected to each other in different configurations, such as a master-slave configuration. The master-slave configuration means that the master device controls the slave device. An example system using the master-slave configuration is a power delivery system, where the controller is the master device and one or more power stages are slave devices. An external passive network including wiring or traces can connect different interface pins (including input pins and output pins) of the controller and the power stages. The controller can use the interface pins to provide commands to the power stages, and the power stages can also provide feedback signals encoding various operating conditions to the controller to operate the power stages. Summary of the Invention

[0003] In one embodiment, an integrated circuit is generally described. The integrated circuit can include a controller configured to control at least one power stage. The controller can include a first set of interface pins, a digital communication bus, and circuitry configured to switch the connection between a reference voltage and the first set of interface pins. The controller can be configured to read the pin status of at least one power stage via the digital communication bus. The pin status can indicate whether a reference voltage is detected at a second set of interface pins of the at least one power stage. The controller can detect the presence or absence of an open pin condition between the first set of interface pins and the second set of interface pins based on the pin status.

[0004] In one embodiment, an integrated circuit is generally described. The integrated circuit can include a power stage configured to convert an input voltage into an output voltage. The integrated circuit can further include a first set of interface pins, a digital communication bus, circuitry, and a switch. The circuitry can be configured to receive a command from the controller on the digital communication bus. The switch can be configured to switch the connection between the circuitry and the first set of interface pins based on the command from the controller. The circuitry can also be configured to detect a voltage on the first set of interface pins. The circuitry can also be configured to set a flag pin voltage and write the pin status of the power stage to a register based on the voltage detected on the first set of interface pins. The pin status can indicate whether a reference voltage is detected on at least one of the first set of interface pins.

[0005] In one embodiment, a system is generally described. The system may include a power stage configured to convert an input voltage to an output voltage. The system may further include a controller configured to control the power stage. The system may further include an external passive network that connects a first set of interface pins of the controller to a second set of interface pins of the power stage. The power stage may be configured to detect a voltage on the second set of interface pins. The power stage may be configured to set a flag pin voltage and write a pin state of the power stage to a register in the power stage based on the voltage detected on the second set of interface pins. The pin state may indicate whether a reference voltage is detected at the second set of interface pins of the power stage. The controller may be configured to switch a connection between a voltage source and the first set of interface pins. The voltage source may be configured to generate a reference voltage. The controller may further be configured to read the pin state of the power stage via a digital communication bus. The controller may also be configured to detect a presence or absence of an open pin condition in the external passive network based on the pin state.

[0006] Various other features as well as the structure and operation of the various embodiments will be described in detail below with reference to the drawings. In the drawings, like reference numerals indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating an example system in which digital open pin detection may be implemented in one embodiment.

[0008] Figure 2 is a diagram illustrating Figure 1 additional details of the example system in one embodiment.

[0009] Figure 3 is a diagram illustrating an example implementation in which digital open pin detection may be implemented in one embodiment.

[0010] Figure 4 is a flowchart illustrating a process for implementing digital open pin detection in one embodiment.

[0011] Figure 5 is a diagram illustrating another example implementation in which digital open pin detection may be implemented in one embodiment.

[0012] Figure 6 is a diagram illustrating another example implementation in which digital open pin detection may be implemented in one embodiment.

[0013] Figure 7 is a flowchart illustrating another process for implementing digital open pin detection in one embodiment.

[0014] Figure 8is a flowchart illustrating another process for implementing digital open pin detection in one embodiment.

[0015] Figure 9 is a flowchart illustrating another process for implementing digital open pin detection in one embodiment. Detailed Description

[0016] In the following description, numerous specific details (such as specific structures, components, materials, dimensions, processing steps, and techniques) are set forth in order to provide an understanding of various embodiments of the present application. However, one of ordinary skill in the art will understand that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

[0017] Figure 1 is a diagram showing an example system in which digital open pin detection may be implemented in one embodiment. System 100 may be a power delivery system configured to generate an output voltage Vout to provide power to a load 104. System 100 may be part of a device and may be implemented by one or more semiconductor devices. System 100 may include at least one controller 102 and at least one power stage 104-(1xM), …, 104-(NxM) (collectively referred to herein as power stage 104), where N varies from 1 to N, and M varies from 1 to M. The power stages 104 may be identical to each other, such as having the same interface pins. The controller 102 may be, for example, a microcontroller including hardware (such as various analog and digital circuit components). The controller 102 may be an integrated circuit including one or more semiconductor devices that implement, for example, a processor, a central processing unit (CPU), a field programmable gate array (FPGA), or any other circuitry configured to control and operate various aspects of the power stage 104.

[0018] In one embodiment, system 100 can be a vertical power transfer (VPD) multiphase converter, which can support high-current applications up to 64 SPS (e.g., if N varies from 1 to 8 and M varies from 1 to 8, then N*M = 64), where N is the number of PWM signals from controller 102, and M is the number of power stages 104 that are connected in parallel and share the same PWM signal. For example, if there are a total of 64 power stages, controller 102 can generate eight PWM signals, and each PWM signal can be used to control eight power stages connected in parallel. Power stage 104 can be a smart power stage (SPS), including various components configured to perform voltage regulation and detect and feedback information such as temperature and current to controller 102. Each of power stages 104 can include a power device (such as a pair of switches implemented by a metal-oxide-semiconductor field-effect transistor (MOSFET)). The pair of switches can be referred to as a high-side switch (e.g., connected between input voltage Vin and a corresponding switch node) and a low-side switch (e.g., connected between the switch node and ground). Controller 102 can be configured to generate and provide control signals (such as pulse-width modulation (PWM) signals or pulse-frequency modulation (PFM) signals) for power stage 104.

[0019] Controller 102 can generate individual control signals for individual power stages. By way of example, controller 102 can provide a first control signal to power stage 104-1 (e.g., when M = 1, power stage 104-(1xM)) via the PWM-1 output pin of controller 102, and power stage 104-1 can receive the first control signal at its PWM input pin. Controller 102 can also provide a second control signal to power stage 104-2 (e.g., power stage 104-(2xM) when M = 1) via the PWM-2 output pin of controller 102, and power stage 104-2 can receive the second control signal at its PWM input pin. In addition, each of power stages 104 can include a driver circuit configured to generate a gate voltage for driving the power switch. The power switch in each of power stages 104 can be turned on and off based on the PWM signal from controller 102. The duty cycle of the high-side switch being on determines the value of output voltage Vout.

[0020] The controller 102 and the power stage 104 can be connected to each other using an external passive network 108. The external passive network 108 can include, for example, wires, traces, transmission lines, and various components that can connect the interface pins (e.g., input and output pins) of the controller 102 and the power stage 104. The controller 102 and the power stage 104 can exchange signals using the external passive network 108. By way of example, the external passive network 108 can route control signals from the controller 102 to the power stage 104 and can route feedback signals from the power stage 104 to the controller 102.

[0021] In one aspect, an open - circuit condition can occur in the external passive network 108. For example, the open - circuit condition can be that an interface pin is disconnected such that there is an open circuit between two interface pins that are supposed to be connected to each other. In some aspects, the open - circuit condition can be caused by a broken wire, a poor connection between the external passive network 108 and the controller 102 or the power stage 104, a loose pin (or terminal or lead), or a faulty component within the external passive network 108. Some poor connections can be the result of soldering defects or circuit trace defects. Additionally, the open - circuit condition can lead to problems such as thermal runaway and delivering excessive current, which can damage the controller 102 and / or the power stage 104.

[0022] In one aspect, conventional open - circuit pin detection methods can apply a small current source to a target pin (e.g., the pin being examined for the open - circuit condition), but this method requires an external low impedance. This method can require connecting an external component (such as an external resistor or capacitor) in parallel with the interface pin (e.g., parallel to the Figure 1 y - direction shown in) in order to detect the open - circuit condition in the y - direction parallel to the component. Additionally, this method poses challenges for high - impedance pins and pins shared by multiple power stages. For example, for a power delivery system with a variable number of power stages (such as a VPD including 2 to 64 SPSs), for a pin that has an external capacitor and is shared by a variable number of power stages, the current applied to the pin for open - circuit detection varies with the number of power stages, and it may be infeasible to control the timing to effectively detect open pins.

[0023] To perform open - circuit condition or open - pin detection, the controller 102 may include circuitry 106, and each of the power stages 104 may include circuitry 110. The circuitry 106 and the circuitry 110 may include various circuit device components, which may be controlled by the controller 102 and / or the power stages to detect open pins in the external passive network 108 and between the controller 102 and the power stages 104. The controller 102 may be configured to provide commands for the power stages 104 to the control circuitry 110 using a digital communication bus or digital bus between the controller 102 and the power stages 104. The power stage 104 may use a fault pin to provide a flag indicating an open - circuit condition to the controller 102. The power stage 104 may also write to a status register, and the controller 102 may send commands to the power stage 104 to read the status register, thereby debugging the power stage and pins with open - pin problems. Additionally, the controller 102 and the power stage 104 may operate the circuitry 106 and the circuitry 110 respectively to detect open pins before the system 100 starts, so that the system 100 can operate under safe and reliable conditions. The open - pin detection performed by the system 100 may provide an open - pin detection solution applicable to a large and variable number of power stages.

[0024] Figure 2 is a diagram showing additional details of an example system in one embodiment Figure 1 in. Figure 2 The description of Figure 1 may refer to the components shown in Figure 2 In the example shown in, a plurality of interface pins 202 between the controller 102 and the power stage 104 are shown. Portions of the interface pins 202 may be shared between different power stages in the power stage 104. As will be described in more detail below, to perform open - pin detection, the controller 102 may control the circuitry 106 and provide commands to the power stage 104 to check for the presence or absence of an open - circuit condition in the external passive network 108.

[0025] In Figure 2In the embodiment shown, the interface pin 202 of the controller 102 may include a PWM-1 pin connected to the PWM pin of the power stage 104, … PWM-N pins for providing a control signal to the power stage 104. The interface pin 202 of the controller 102 may further include a TRI pin connected to the TRI# pin of the power stage 104 for activating the three-state mode of the power stage 104. The interface pin 202 of the controller 102 may further include an IMON pin connected to the ISHARE pin of the power stage 104 for receiving the sensed current from the power stage 104. The interface pin 202 of the controller 102 may further include a TEMP pin connected to the TOUT pin of the power stage 104 for receiving the sensed temperature from the power stage 104. The interface pin 202 of the controller 102 may further include an I2C_CLK pin connected to the CLK pin of the power stage 104 for providing a clock signal to the power stage 104 according to the Inter-Integrated Circuit (I2C) communication protocol. The interface pin 202 of the controller 102 may further include an I2C_DATA pin connected to the DATA pin of the power stage 104 for providing a data signal to the power stage 104 according to the I2C communication protocol. The interface pin 202 of the controller 102 may further include a VCTRL pin connected to the VCTRL pin of the power stage 104 for maintaining the voltage output at Vout at a target voltage level. The interface pin 202 of the controller 102 may further include a TEST_IN pin connected to the TEST pin of the power stage 104 for receiving various flags and test signals from the power stage 104. The interface pin 202 of the controller 102 may further include an EN pin connected to the EN pin of the power stage 104 for selectively enabling or disabling the power stage 104. The interface pin 202 of the controller 102 may further include a REF connected to the REF pin of the power stage 104 for providing a reference voltage to the power stage 104.

[0026] In one embodiment, the controller 102 may operate switches in the circuit 106 to connect a predefined reference voltage to the interface pins 202 in a sequential manner or in parallel (e.g., connected to all pins simultaneously). The controller 102 may provide commands to the power stage 104 via a digital bus, such as an I2C bus that connects the I2C_CLK pin and the I2C_DATA pin of the controller 102 to the CLK pin and the DATA pin of each power stage 104. The power stage 104 may receive the command and operate switches in the circuit 110 based on the command to connect the interface pins of the power stage 104 to a window comparator in the circuit 110 in a sequential or parallel manner. The window comparator in the circuit 110 may output a flag in response to the absence of a reference voltage on the interface pins connected to the window comparator. The flag may be stored in a register of the power stage 104, and the power stage 104 may notify the controller 102 of the presence of an open circuit condition via a flag pin. In one embodiment, one or more of the interface pins 202 may be used by the power stage 104 to provide a flag to the controller 102. By way of example, the power stage 104 may use the TEST pin and the TOUT pin of the power stage to provide a flag to the TEST_IN pin and the TEMP pin of the controller 102.

[0027] Figure 3 FIG. is a diagram illustrating an example implementation in which digital open pin detection may be implemented in one embodiment. Figure 2 The description of may refer to Figures 1 to 2 the components shown in Figure 3 In the embodiment shown in, the system 100 may perform a serial check to determine the presence or absence of an open pin in the external passive network 108. The circuit 106 in the controller 102 may include a voltage source 310, a resistor Rm, and a switch S1. The voltage source 310 may be configured to generate and output a reference voltage VREF. The switch S1 may be controlled by the controller 102 to switch the connection between the voltage source 310 and one or more interface pins PIN1,... PINn of the controller 102. One or more interface pins PIN1,... PINn may include Figure 2 the interface pins shown in. The controller 102 may include a digital engine 320 that is configured to generate a clock signal to be transmitted from the I2C_CLK pin of the controller 102 to the CLK pin of the power stage 104. The digital engine 320 may also be configured to generate and output a digital data signal encoding various information and / or commands to the power stage 104. In one embodiment, the digital engine 320 may be a processor (such as a CPU).

[0028] The circuit 110 in power stage 104-1 may include a switch S2, a voltage window comparator 304, a NAND gate 306, and a status register 308. The circuit 110 in power stage 104-2 may be the same as the circuit 110 in power stage 104-1 and may include a switch S3, a voltage window comparator 314, a NAND gate 316, and a status register 318. Interface pins PIN1, … PINn of each of the power stages 104 may be connected to corresponding interface pins among interface pins PIN1, … PINn of the controller 102.

[0029] In one embodiment, to perform a serial check to detect an open pin, the controller 102 may control the digital engine 302 to generate a digital signal that encodes one or more commands to perform a serial open pin check and other instructions (such as the timing for the open pin check). By way of example, the digital engine 320 may generate digital data that encodes commands to all of the power stages 104 to begin a serial open pin check. The digital engine 320 may also generate a timing for encoding the digital data to the power stages 104 to serially check each of the pins PIN1, … PINn. For example, the controller 102 may instruct all of the power stages in the power stage 104 to check their interface pin PIN1 during a first time interval and instruct the power stage 104 to check their interface pin PIN2 during a second time interval.

[0030] Using power stage 104-1 as an example, to perform an open pin check during a serial check, the controller 102 may control the switch S1 to connect VREF to the target pin, and the power stage 104-1 may control the switch S2 to connect the pin corresponding to the target pin to the voltage window comparator 304. By way of example, if pin PIN1 is the target pin for which an open pin is to be checked, the controller 102 may switch S1 to connect VREF to its PIN1, and the power stage 104-1 may switch S2 to connect the voltage window comparator 304 to its PIN1. In Figure 3In the example shown, due to the open pin 302 between the two PIN1s of the controller 102 and the power stage 104-1, the power stage 104-1 will not sense VREF. In response to the absence of VREF on PIN1 at the power stage 104-1, the input to the voltage window comparator 304 via the switch S2 will be outside the voltage window bounded by VREF- and VREF+. The input to the voltage window comparator 304 being outside the voltage window may cause the NAND gate 306 to output a high voltage or the binary value '1'. The high voltage output by the NAND gate 306 can write the binary value '1' to a specific bit in the status register 308, where this specific bit is assigned to PIN1. This high voltage can also set the flag pin high to report the open pin fault to the controller 102.

[0031] After checking PIN1, the controller 102 can control the switch S1 to connect VREF to a new target pin (such as pin PIN2), and the power stage 104-1 can control the switch S2 to connect the pin corresponding to the new target pin (such as PIN2 of the power stage 104-1) to the voltage window comparator 304. If the power stage 104-1 senses VREF from pin PIN2, then the input to the voltage window comparator 304 via the switch S2 will be within the voltage window bounded by VREF- and VREF+. The input to the voltage window comparator 304 being within the voltage window may cause the NAND gate 306 to output a low voltage or the binary value '0'. The low voltage output by the NAND gate 306 can write the binary value '0' to a specific bit in the status register 308 assigned to PIN2. The controller 102 and the power stage 104-1 can continue to perform a serial check until the last pin PINn. After checking the last pin PINn, the controller 102 can read the flag pin to determine whether there is an open pin between the controller 102 and the power stage 104. In one embodiment, the voltage of the flag pin can indicate whether any open pin fault has occurred. If a high voltage is detected on the flag pin, the controller 102 can determine that an open pin has occurred and can read the status register 308 using a digital bus (e.g., I2C bus) to determine the open pin between the controller 102 and the power stage 104-1. Each bit of the status register 308 represents the connection status of an interface pin.

[0032] Figure 4 is a flowchart illustrating the process of implementing digital open pin detection in one embodiment. Figure 2 The description of can refer to Figures 1 to 3The components shown in. Process 400 may include one or more operations, actions, or functions as shown in one or more of block 402, block 404, block 406, block 408, block 410, block 412, block 414, block 416, block 418, block 420, block 422, and / or block 424. Although shown as distributed blocks, depending on the desired implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or executed in parallel.

[0033] For example, process 400 may be performed by Figure 1 the system 100 shown in. Process 400 may start at block 402. At block 402, the controller 102 and the power stage 104 are powered on. Block 402 may proceed to block 404. At block 404, the controller 102 may determine whether the power stage 104 has been initialized, configured, and ready to receive commands. This determination may include determining a voltage power-on reset (VCCPOR) and / or being ready to receive and respond to PMBus or I2C communication protocol commands on a digital bus (e.g., an I2C bus). If the power stage 104 is not ready for commands, then process 400 returns to block 402. However, if the power stage 104 is ready for commands, then process 400 may continue from block 404 to block 406. At block 406, the controller 102 may send a command to the power stage 104 to scan and obtain device addresses. For example, the controller 102 may scan the number of device addresses configured for the controller 102. In one embodiment, the controller 102 may use commands (such as Ansible Report and Analysis (ARA) commands) to obtain device addresses. Process 400 may continue from block 406 to block 408. At block 408, the controller 102 may check for a matching configuration. For example, the controller 102 may check whether the total scanned device addresses match the amount of obtained device addresses and also match the amount of device addresses in the programming configuration of the controller 102.

[0034] If a mismatch is detected, process 400 can continue from block 408 to block 416. At block 416, controller 102 can stop operation to allow for manual debugging, e.g., checking the configuration file or checking the interface pins that are correctly connected. Additionally, at block 408, if no mismatch is detected, process 400 can continue from block 408 to block 410. At block 410, controller 102 can be configured to check whether the switches of power stage 104 (such as the high-side (HS) switch and the low-side (LS) switch) are off. In one aspect, it can be defaulted that the HS switch and the LS switch of power stage 104 are off. However, as an additional precautionary step, controller 102 can send commands to turn off all HS switches and LS switches of all connected SPSs. Then controller 102 can verify whether the switches in each SPS are in the "off" state. If not all switches are off, process 400 can continue from block 410 back to block 416 for debugging. If all switches are off, process 400 can continue from block 410 to block 412.

[0035] At block 412, controller 102 enables the serial open pin check operation. Controller 102 can send commands (such as "OPENPINCHECK_ENABLE") to all SPS addresses of each power stage 104 to prepare for the open pin check. In one embodiment, the command can include commanding power stage 104 to release or disconnect the target pin (e.g., the interface pin for which the open condition is to be checked) from ground, from any existing internal connection (such as any low-impedance push-pull), or from any voltage or current source. In block 412, the release of the pin connection by power stage 104 can ensure that the reference voltage VREF will be the only voltage source connected to the target pin (e.g., the pin being checked) during the open pin check. Process 400 can continue from block 412 to 414.

[0036] At block 414, controller 102 can be configured to sequentially provide VREF to each pin to check whether the connection is open. By way of example, controller 102 can check the first pin PIN1 by switching switch S1 to connect VREF to PIN1. Controller 102 can wait for a predefined amount of time to ensure that the circuit 110 in power stage 104 has enough time to read the output from the NAND gate and write the output to the corresponding status register (e.g., see Figure 3)。After a period of time, the controller 102 can continue to check the next pin by switching S1 to disconnect PIN1 from VREF and connect the next pin (such as PIN2) to VREF. In one embodiment, after a period of time, the controller 102 can send a command on the I2C bus to provide commands to the power stages 104 to switch the connections of their voltage window comparators to the next pin. The controller 102 can wait for a predefined amount of time before switching S1 again to check the next pin after PIN2. The controller 102 can continue to sequentially switch S1 to connect different pins to VREF to check for open circuit conditions until the last pin PINn. The power stages 104 can set the TMON and CFP pins to the "high" state, and if any of the power stages 104 detects an open circuit on one or more pins, set the corresponding status register bit to report a flag indicating the presence of a fault. After checking all the pins, process 400 can continue from block 414 to blocks 418 and 420.

[0037] At blocks 418 and 420, the controller 102 can be configured to check the flag pin. The controller 102 will decide whether any open pin faults are detected based on the voltage on the flag pin. If the controller 102 detects that the flag pin is high, the controller determines that an open pin fault has occurred at one or more power stages and at one or more pins. Process 400 will continue from 420 to 424. If the controller 102 does not detect any flag pins as high, the controller 102 determines that no open pin faults have occurred.

[0038] If no open pins are detected, process 400 can continue from block 420 to block 422. At block 422, the power stages will release their TMON pins. In one aspect, the TMON pin is a power stage multifunctional pin that operates as both a temperature sensing output pin and a fault flag. TMON is configured to remain low on power-up. If any open pin faults occur on power-up, it will be pulled high. At block 422, since no open pins are detected and TMON remains low, the power stages 104 can release TMON to output temperature sensing information. The controller 102 can proceed to startup after receiving a normal TMON voltage.

[0039] However, if an open pin is detected at block 420, process 400 may continue from block 420 to block 424. At block 424, controller 102 will assert a fault. Controller 102 may also send a command to read the status register of power stage 104. In one embodiment, controller 102 may also determine and specify the faulty pin by determining the power stage that provided the register word indicating an open pin (e.g., binary value '1'). Using the TMON and CFP pins allows controller 102 to detect open pin conditions without the need to add additional pins to controller 102 and / or power stage 104. Then, process 400 continues from block 424 back to block 416 for manual debugging.

[0040] Figure 5 FIG. is another example embodiment showing how digital open pin detection may be implemented in one embodiment. Figure 5 The description of may refer to Figures 1 to 4 the components shown in Figure 5 the embodiment shown in, system 100 may perform a parallel check to determine the presence or absence of open pins in external passive network 108.

[0041] In one embodiment, to perform a parallel check to detect open pins, controller 102 may control digital engine 320 to generate a digital signal that encodes one or more commands to perform a parallel open pin check and other instructions (such as the timing of the open pin check). By way of example, digital engine 320 may generate digital data by encoding commands to all power stages 104 to start a parallel open pin check. Digital engine 320 may also generate a digital data encoding timing for power stage 104 to parallel check each of pins PIN1,... PINn. For example, controller 102 may instruct power stage 104 to check its interface pin PIN1 during a first time interval and instruct power stage 104 to check interface pin PIN2 during a second time interval.

[0042] Using power stage 104-1 as an example, to perform an open pin check during a parallel check, controller 102 may control switch S1 to connect VREF to all pins PIN1-PINn of controller 102. Power stage 104-1 may control switch S2 to connect the pin corresponding to the target pin to voltage window comparator 304. By way of example, if pin PIN1 is the target pin to check for an open pin, controller 102 may switch S1 to connect VREF to all its pins, and power stage 104-1 may switch S2 to connect voltage window comparator 304 to its PIN1. In Figure 5In the example shown, due to the open circuit of pin 302 between the controller 102 and the two PIN1s of the power stage 104-1, the power stage 104-1 will not sense VREF. In response to the absence of VREF on PIN1 at the power stage 104-1, the NAND gate 306 outputs a high voltage or the binary value '1'. The high voltage output by the NAND gate 306 can write the binary value '1' to a specific bit in the status register 308, where the specific bit is assigned to PIN1. The power stage 104-1 also pulls up the flag pin to report a fault.

[0043] The controller 102 can maintain the switch S1 in a closed state for all pins PIN1 to PINn to keep VREF connected to all pins PIN1 to PINn. After all the power stages 104 have checked their PIN1s, the power stages 104 can control their corresponding switches S2 to connect the pins corresponding to the new target pins (such as PIN2 of the power stage 104) to their corresponding voltage window comparators. In comparison with Figure 3 the embodiment shown, since the controller 102 can perform an operation to connect to all pins without the need to sequentially switch the pin connections to VREF, the connection of all pins on the controller 102 to VREF can reduce the processing time. The power stages 104 can continue to perform parallel checks until the last pin PINn. After checking the last pin PINn, the controller 102 can detect the voltage on the flag pin. If the flag pin voltage is not high, indicating that all pins are connected properly, the controller can continue to start. If it is detected that the flag pin is high, which indicates an open pin fault, the controller 102 can read the status register 308 using a digital bus (e.g., I2C bus) to determine the power stage and the faulty pin.

[0044] Figure 6 FIG. is a diagram showing another exemplary implementation in which digital open pin detection can be implemented in one embodiment. Figure 2 The description of can refer to Figures 1 to 5 the components shown in Figure 5 In the embodiment shown in, the system 100 can perform a parallel check to determine the presence or absence of open pins in the external passive network 108.

[0045] In Figure 6 the embodiment shown, the system 100 can perform a parallel check to determine the presence or absence of open pins in the external passive network 108. The controller 102 can include a digital engine 320 configured to generate a clock signal to be transmitted to the CLK pin of the power stage 104. The digital engine 320 can also be configured to generate and output a digital data signal encoding various information and / or commands to the power stage 104.

[0046] In Figure 6 the example embodiments shown, each of the power stages 104 may include n copies of the circuit 110 for n interface pins PIN1 to PINn. Using the power stage 104-1 as an example, one copy of the circuit 110 is connected to PIN1 and another copy of the circuit 110 is connected to PIN2. PIN1 of the power stage 104-1 may be connected to the voltage window comparator 304-1 using the switch S2-1. The output of the voltage window comparator 304-1 may be connected to the NAND gate 306 and the status register 308. PIN2 of the power stage 104-1 may be connected to the voltage window comparator 304-2 using the switch S2-2. The output of the voltage window comparator 304-2 may be connected to another NAND gate 602 and the status register 308. The interface pins PIN1, … PINn of each of the power stages 104 may be connected to the corresponding interface pins PIN1, … PINn of the controller 102.

[0047] In one embodiment, to perform a parallel check to detect open pins, the controller 102 may control the digital engine 320 to generate a digital signal that encodes one or more commands to perform a parallel open pin check and other instructions (such as the timing of the open pin check). By way of example, the digital engine 320 may generate digital data that encodes commands to all of the power stages 104 to start a parallel open pin check. The commands of the digital engine 320 may be output as command signals on the CLK / DATA lines (e.g., the CLK line and the DATA line for I2C communication). The command signal on the CLK / DATA lines may trigger the controller 102 to control the switch S1 to connect VREF to all of the pins PIN1-PINn of the controller 102. The command signal on the CLK / DATA lines may also trigger the switches S2-1, S2-2, … S2-n to close to connect all of the pins PIN1 to PINn of the power stage 104-1 to the corresponding voltage window comparators. The command signal may also cause all of the switches of the power stages other than the power stage 104-1 to close. As a result of closing all of the switches on both the controller 102 side and the power stage side, an open pin detection may be performed in parallel.

[0048] In Figure 6In the example shown, due to the open pin 302 between the controller 102 and the two PIN1s of the power stage 104-1, the power stage 104-1 will not sense the VREF on PIN1. In response to the absence of VREF on PIN1 at the power stage 104-1, the NAND gate 306 outputs a high voltage or the binary value '1'. The high voltage output by the NAND gate 306 can write the binary value '1' to a specific bit in the status register 308, where this specific bit is assigned to PIN1. On the other hand, since there is no open pin between the controller 102 and the two PIN2s of the power stage 104-1, the power stage 104-1 will sense the VREF on PIN2. In response to the presence of VREF on PIN2 at the power stage 104-1, the NAND gate 602 can output a low voltage or the binary value '0'. The low voltage output by the NAND gate 602 can write the binary value '0' to a specific bit in the status register 308, where this specific bit is assigned to PIN2.

[0049] When compared with Figure 3 the embodiment shown in Figure 6 the connection of all pins on the controller 102 to VREF and the connection of all pins on all power stages 104 to the corresponding voltage window comparators can reduce the processing time because the controller 102 can perform the turn-on operation to connect to all pins without the need to sequentially switch the connection of the pins to VREF. When compared with Figure 3 the embodiment of Figure 6 the embodiment in

[0050] Figure 7 can occupy more silicon area. Therefore, the open pin detection described herein can be flexible for different applications (such as applications that may require fast open pin detection or applications implemented by smaller devices). After checking the last pin PINn, the controller 102 can read the status register 308 using a digital bus (e.g., I2C bus). If the controller 102 reads all zeros from the status register (such as the status register 308), the controller 102 can determine that there is no open pin between the controller 102 and the power stage 104-1. If the controller 102 reads at least one binary value '1' from the status register 308, then the controller 102 can determine that there is an open pin between the controller 102 and the power stage 104-1. Figure 2 The description of Figures 1 to 6The components shown in. Process 700 may include one or more operations, actions, or functions as shown by one or more of block 702, block 704, block 706, block 708, block 710, block 712, block 714, block 716, block 718, block 720, block 722, and / or block 724. Although shown as distributed blocks, depending on the desired implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel.

[0051] For example, process 700 may be performed by Figure 1The system 100 shown in executes. Process 700 may start at block 702. At block 702, controller 102 and power stage 104 are powered on. Block 702 may proceed to block 704. At block 704, controller 102 may determine whether power stage 104 has been initialized, configured, and is ready to receive commands. This determination may include determining a voltage power-on reset (VCCPOR) and / or being ready to receive and respond to PMBus or I2C communication protocol commands on a digital bus (e.g., an I2C bus). If power stage 104 is not ready for commands, process 700 returns to block 702. However, if power stage 104 is ready for commands, process 700 may continue from block 704 to block 706. At block 706, controller 102 may send a command to power stage 104 to scan and obtain device addresses. For example, controller 102 may scan the number of device addresses configured for controller 102. In one embodiment, controller 102 may use a command (such as an Ansible Report and Analysis (ARA) command) to obtain device addresses. Process 700 may continue from block 706 to block 708. At block 708, controller 102 may check for a matching configuration. For example, controller 102 may check whether the total number of scanned device addresses matches the amount of obtained device addresses and also matches the amount of device addresses in the programming configuration of controller 102. If a mismatch is found, process 700 may continue from block 708 to block 716. At block 716, controller 102 stops operation to allow manual debugging, e.g., checking a configuration file or checking properly connected pins. Additionally, at block 708, if no mismatch is found, process 700 may continue from block 708 to block 710. At block 710, controller 102 may be configured to check whether the power stage 104 switches (such as HS switches and LS switches) are off. Generally, it may be assumed that the HS switches and LS switches of power stage 104 are off by default. However, as an additional precaution, controller 102 may send a command to turn off all HS switches and LS switches of all connected devices. Then controller 102 may verify whether the switches in each SPS are in the "off" state. If not all switches are off, process 700 may continue from block 710 back to block 716 for debugging. If all switches are off, process 700 may continue from block 710 to block 712.

[0052] At block 712, the controller 102 enables a parallel open pin check operation. The controller 102 may send commands (such as "OPENPINCHECK_ENABLE") to all SPS addresses of each power stage 104 to prepare for performing an open pin check. In one embodiment, the command may include commanding the power stage 104 to release or disconnect a target pin (e.g., an interface pin for which an open condition is to be checked) from ground and from any existing internal connections (such as a low impedance push-pull or a connection from any voltage or current source). In block 712, the power stage 104 releasing the pin connection can ensure that during the open pin check, the reference voltage VREF will be the only voltage source connected to the target pin (e.g., the pin being checked). Process 700 may continue from block 712 to 714. At block 714, the controller 102 may be configured to provide VREF to each pin from PIN1 to PINn.

[0053] In a first embodiment (e.g., corresponding to Figure 5 ), all power stages 104 may turn on their respective switches to connect PIN1 to the corresponding voltage window comparator. In the first embodiment, at block 714, the power stages may sequentially check the open pins from PIN1 to PINn while the controller 102 maintains the state of switch S1 to keep all pins on the controller 102 connected to VREF. For example, all power stages may check PIN1 in parallel. Each of the power stages 104 may wait for a predefined amount of time to ensure that the output is read from the NAND gate and the output from the NAND gate is written to the corresponding status register (e.g., see Figure 5 or Figure 6 ). In the first embodiment, after a period of time, all of the power stages 104 may check the next pin (such as PIN2) by switching their respective switches to connect the next pin to the corresponding NAND gate. Then, all power stages may check PIN2 in parallel. The controller 102 may maintain the connection between all of its pins and VREF until all pins of all power stages 104 have been checked.

[0054] In a second embodiment (e.g., corresponding to Figure 6 ), all power stages 104 may turn on all switches to connect all pins PIN1 to PINn to the corresponding voltage window comparator. In the second embodiment, at block 714, the power stages may check the open pins of all pins PIN1 to PINn in parallel while the controller 102 maintains the state of switch S1 to keep all pins on the controller 102 connected to VREF. The controller 102 may maintain the connection between all of its pins and VREF until all pins of all power stages 104 have been checked.

[0055] In one embodiment, after a predefined amount of time has elapsed, the controller 102 may send a command on the I2C bus to provide a command to the power stages 104 to switch the connections of their voltage window comparators to the next pin while maintaining the connection between VREF and all interface pins of the controller 102. The power stages 104 may set the TMON and CFP pins to a "high" state so that if any power stage senses an open circuit on any of the pins PIN1 to PINn, a flag indicating the presence of a fault is reported.

[0056] After checking all the pins, process 700 may continue from block 714 to blocks 718 and 720. At block 718, the controller 102 is configured to check the flag pins (e.g., TMON and CFP). The controller 102 will determine whether any open pin faults have been detected based on the voltage on the flag pins. If the controller 102 detects that the flag pins are high, the controller determines that an open pin fault has occurred at one or more of the power stages and at one or more of the pins. Process 700 will continue from 720 to 724. If the controller does not detect any flag pins as high, the controller determines that no open pin fault has occurred.

[0057] If no open pins are detected, process 700 may continue from block 720 to block 722. At block 722, the power stages 104 will release their TMON pins. In one aspect, the TMON pin is a power stage multifunctional pin that functions as both a temperature sensing output pin and a fault flag. TMON is configured to be low on power-up. If any open pin faults occur on power-up, it will be pulled high. At block 422, since no open pins are detected and TMON remains low, the power stages 104 may release TMON to output temperature sensing information. The controller 102 will continue to start up after receiving a normal TMON voltage.

[0058] However, if an open pin is detected at block 720, process 700 may continue from block 720 to block 724. At block 724, the controller 102 will assert a fault. The controller 102 may also send a command to read the status register of the power stages 104. In one embodiment, the controller 102 may also determine and specify the faulty pin by determining the power stage that is provided with a register word including an indication of an open pin (e.g., binary value '1'). The use of the TMON and CFP pins may allow the controller 102 to detect open pin conditions without the need to add additional pins to the controller 102 and / or the power stages 104. Then, process 700 continues from block 724 back to block 716 for manual debugging.

[0059] Figure 8FIG. 0 is a flow chart illustrating another process for implementing digital open pin detection in one embodiment. Process 800 may include one or more operations, actions, or functions as shown in one or more of block 802, block 804, block 806, and / or block 808. Although shown as distributed blocks, depending on the desired implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or executed in parallel.

[0060] Process 800 may be performed by, for example, a controller such as controller 102 described herein. Process 800 may begin at block 802. At block 802, the controller may be configured to control at least one power stage (e.g., power stage 104 described herein). The controller may include a first set of interface pins, a digital communication bus, and circuitry. The circuitry may be configured to switch the connection between a reference voltage and the first set of interface pins. In one embodiment, the digital communication bus may be an Inter-Integrated Circuit (I2C) communication bus.

[0061] Process 800 may proceed from block 802 to block 804. At block 804, the controller may switch the connection between the reference voltage and the first set of interface pins. In one embodiment, the controller may be configured to control the circuitry to connect the reference voltage to a first interface pin among the first set of interface pins. The controller may wait for a predefined amount of time to elapse. In response to the predefined amount of time elapsing, the controller may control the circuitry to connect the reference voltage to a second interface pin among the first set of interface pins. In one embodiment, the controller may control the circuitry to connect the reference voltage to all of the interface pins in the first set of interface pins.

[0062] In one embodiment, in response to the predefined amount of time elapsing, the controller may send a command via the digital communication bus to at least one power stage to command the at least one power stage to switch the connection of a second set of interface pins in the at least one power stage.

[0063] Process 800 may proceed from block 802 to block 806. At block 806, the controller may read the pin status of at least one power stage via the digital communication bus. The pin status may indicate whether a reference voltage is detected at the second set of interface pins of the at least one power stage.

[0064] Process 800 may proceed from block 806 to block 808. At block 808, the controller may detect the presence or absence of an open pin condition between the first set of interface pins and the second set of interface pins based on the pin condition. In one embodiment, the controller may detect the presence of an open pin condition between the first set of interface pins and the second set of interface pins and set at least one of the interface pins in the first set of interface pins to a high voltage to indicate the presence of the open pin condition.

[0065] In one embodiment, the controller may control the circuit to switch the connection between the reference voltage and the first set of interface pins before starting a system including a power stage. The controller may detect an open pin condition between the first set of interface pins and the second set of interface pins, and stop the startup of the system in response to detecting the open pin condition.

[0066] In one embodiment, the controller may control the circuit to switch the connection between the reference voltage and the first set of interface pins before starting a system including a power stage. The controller may detect that there is no open pin condition between the first set of interface pins and the second set of interface pins, and continue the startup of the system in response to detecting that there is no open pin condition.

[0067] Figure 9 FIG. is a flowchart illustrating another process for implementing digital open pin detection in one embodiment. Process 900 may include one or more operations, actions, or functions shown in one or more of block 902, block 904, block 906, and / or block 912. Although shown as distributed blocks, depending on the desired implementation, the various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or executed in parallel.

[0068] Process 900 may be performed, for example, by a power stage (such as any of the power stages 104 described herein). Process 900 may start at block 902. At block 902, the power stage may receive a command from the controller on a digital communication bus. The power stage may include a first set of interface pins, a digital communication bus, a switch, and a circuit. The circuit may be configured to receive a command from the controller on the digital communication bus. The switch may be configured to switch the connection between the circuit and the first set of interface pins based on a command from the controller. In one embodiment, the digital communication bus may be an Inter-Integrated Circuit (I2C) communication bus.

[0069] Process 900 may proceed from block 902 to block 904. At block 904, the power stage may switch the connection between the circuit and the first set of interface pins based on a command from the controller. In one embodiment, the switch in the power stage may connect the circuit to a first interface pin among the first set of interface pins. The power stage may wait for a predefined amount of time to elapse. The power stage may receive a new command to switch the connection between the circuit and the first set of interface pins, and in response to the predefined amount of time having elapsed, control the switch to connect the circuit to a second interface pin among the first set of interface pins.

[0070] Process 900 can proceed from block 904 to block 906. At block 906, the circuitry in the power stage can detect a voltage on a first set of interface pins. Process 900 can proceed from block 906 to block 908. At block 908, based on the voltage detected on the first set of interface pins, the circuitry in the power stage writes the pin state of the power stage to a register, where the pin state indicates whether a reference voltage is detected on at least one of the first set of interface pins.

[0071] In one embodiment, the circuitry in the power stage can include a voltage window comparator configured to compare the voltage detected on the first set of interface pins with a voltage window defined by a reference voltage. The circuitry in the power stage can also include a NAND gate configured to write a binary value of 0 to the pin state in the register when the voltage is within the voltage window and a binary value of 1 to the pin state in the register when the voltage is outside the voltage window.

[0072] In one embodiment, the circuitry in the power stage can receive a command from a controller before a system including the power stage is started. When a reference voltage is not detected on at least one of the first set of interface pins, the circuitry in the power stage can receive a command to stop the start-up. When a reference voltage is detected on all of the first set of interface pins, the circuitry in the power stage can receive a command to continue the start-up.

[0073] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, in fact depending on the functions involved, two blocks shown in succession may be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a special hardware-based system that performs the specified functions or acts or implements a combination of special hardware and computer instructions.

[0074] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms as well. It will also be understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0075] In the following claims, corresponding structural, material, acts and all means or step plus function elements equivalents, if any, are intended to include any structural, material or act for performing the function in combination with other claimed elements for a particular claimed function. For purposes of illustration and description, embodiments of the invention have been presented, but these embodiments are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. An integrated circuit, comprising: A controller configured to control at least one power stage, wherein the controller comprises: The first set of interface pins; digital communications bus; and circuitry configured to switch a connection between a reference voltage and the first set of interface pins; The controller is configured to: reading a pin status of the at least one power stage via the digital communication bus, wherein the pin status indicates whether the reference voltage is detected at a second set of interface pins of the at least one power stage; and Based on the pin states, the presence or absence of an open pin condition is detected between the first group of interface pins and the second group of interface pins.

2. The integrated circuit of claim 1, wherein the digital communication bus is an Inter-Integrated Circuit Interconnect (I2C) communication bus.

3. The integrated circuit of claim 1 , wherein the controller is configured to: controlling the circuit to connect the reference voltage to a first interface pin in the first group of interface pins; Waiting for a predefined amount of time to elapse; and In response to the predefined amount of time elapsing, the circuit is controlled to connect the reference voltage to a second interface pin in the first set of interface pins.

4. The integrated circuit of claim 3, wherein the controller is configured to: In response to the predefined amount of time elapsing, a command is sent to the at least one power stage via the digital communication bus to command the at least one power stage to switch connections of the second set of interface pins in the at least one power stage. 5 . The integrated circuit of claim 1 , wherein the controller is configured to control the circuit to connect the reference voltage to all interface pins in the first group of interface pins.

6. The integrated circuit of claim 1 , wherein the controller is configured to: detecting the presence of the open pin condition between the first set of interface pins and the second set of interface pins; and At least one interface pin of the first set of interface pins is set to a high voltage to indicate that the open pin condition exists.

7. The integrated circuit of claim 1 , wherein the controller is configured to: Before a system including the power stage is started, controlling the circuit to switch a connection between the reference voltage and the first set of interface pins; detecting the presence of the open pin condition between the first set of interface pins and the second set of interface pins; and In response to detecting the presence of the open pin condition, the startup of the system is stopped.

8. The integrated circuit of claim 1 , wherein the controller is configured to: Before a system including the power stage is started, controlling the circuit to switch a connection between the reference voltage and the first set of interface pins; detecting an absence of the open pin condition between the first group of interface pins and the second group of interface pins; In response to detecting that the open pin condition is absent, the startup of the system continues.

9. An integrated circuit comprising: a power stage configured to convert an input voltage into an output voltage; The first set of interface pins; Digital communication bus; circuitry configured to receive commands from a controller on the digital communications bus; as well as a switch configured to switch a connection between the circuit and the first set of interface pins based on the command from the controller; The circuit is also configured to: detecting a voltage on the first set of interface pins; and Based on the voltage detected on the first set of interface pins, a flag pin voltage is set and a pin state of the power stage is written to a register, wherein the pin state indicates whether a reference voltage is detected on at least one of the first set of interface pins.

10. The integrated circuit of claim 9, wherein the digital communication bus is an Inter-Integrated Circuit Interconnect (I2C) communication bus.

11. The integrated circuit of claim 9, wherein: The switch is configured to connect the circuit to a first interface pin of the first set of interface pins; Wait for a predefined amount of time to elapse; receiving a new command to switch said connection between said circuit and said first set of interface pins; as well as In response to the predefined amount of time elapsing, the switch is controlled to connect the circuit to a second interface pin in the first set of interface pins.

12. The integrated circuit of claim 9, wherein the circuit comprises: a voltage window comparator configured to compare a voltage detected on the first set of interface pins with a voltage window defined by the reference voltage; NAND gates, configured as: When the voltage is within the voltage window, writing a binary value of 0 to the pin state in the register; as well as When the voltage is outside the voltage window, a binary value of 1 is written to the pin state in the register and the flag pin voltage is set high in the register.

13. The integrated circuit of claim 9, wherein the circuit is configured to: receiving the command from the controller prior to startup of a system including the power stage; receiving a command to stop the enabling when the reference voltage is not detected on at least one of the first set of interface pins; and When the reference voltage is detected on all pins of the first set of interface pins, a command to continue the startup is received.

14. A system comprising: a power stage configured to convert an input voltage into an output voltage; a controller configured to control the power stage; as well as an external passive network connecting a first set of interface pins of the controller to a second set of interface pins of the power stage; The power stage is configured as: detecting a voltage on the second set of interface pins; and based on the voltage detected on the second set of interface pins, setting a flag pin voltage and writing a pin state of the power stage to a register in the power stage, wherein the pin state indicates whether a reference voltage is detected at the second set of interface pins of the power stage; The controller is configured to: switching a connection between a voltage source and the first set of interface pins, wherein the voltage source is configured to generate the reference voltage; reading the pin status of the power stage via a digital communication bus; as well as Based on the pin status, the presence or absence of an open pin condition is detected in the external passive network.

15. The system of claim 14, wherein the digital communication bus is an Inter-Integrated Circuit (I2C) communication bus.

16. The system of claim 14, wherein the controller is configured to: connecting the reference voltage to a first interface pin in the first group of interface pins; Waiting for a predefined amount of time to elapse; and In response to the predefined amount of time elapsing, the reference voltage is connected to a second interface pin in the first set of interface pins.

17. The system of claim 14, wherein the controller is configured to connect the reference voltage to all interface pins in the first set of interface pins.

18. The system of claim 14, wherein the controller is configured to: before a system including the power stage is started, switching a connection between the reference voltage and the first set of interface pins; detecting the presence of the open pin condition between the first set of interface pins and the second set of interface pins; and In response to detecting the presence of the open pin condition, the startup of the system is stopped.

19. The system of claim 14, wherein the controller is configured to: before a system including the power stage is started, switching a connection between the reference voltage and the first set of interface pins; detecting an absence of the open pin condition between the first group of interface pins and the second group of interface pins; In response to detecting that the open pin condition is absent, the startup of the system continues.

20. The system of claim 14, wherein the power stage comprises: a voltage window comparator configured to compare a voltage detected on the first set of interface pins with a voltage window defined by the reference voltage; as well as NAND gates, configured as: When the voltage is within the voltage window, writing a binary value of 0 to the pin state in the register; as well as When the voltage is outside the voltage window, a binary value of 1 is written to the pin state in the register and the flag pin voltage is set high.

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