Interrupt verification method and device for C2F, storage medium and equipment

Abstract

The embodiment of the invention provides an interrupt verification method and device for C2F, a storage medium and equipment, and the method comprises the steps: obtaining a test constraint condition, and generating global configuration information and interrupt configuration information of a to-be-tested interrupt signal according to the test constraint condition; a configuration file is generated according to the two kinds of configuration information, the file comprises a global configuration code, an interrupt configuration code and a program configuration code of an interrupt verification program, and the global configuration code, the interrupt configuration code and the program configuration code are respectively used for configuring global registers of a simulation processor and an interrupt controller, an interrupt register corresponding to an interrupt signal to be tested and the interrupt verification program; then, the configuration file is sent to the simulation processor to complete configuration; after configuration is completed, a to-be-tested interrupt signal conforming to interrupt configuration information is sent to the interrupt controller, and the interrupt controller processes the interrupt signal and then sends an interrupt request to the simulation processor; when it is detected that the simulation processor enters the interrupt verification program, the interrupt signal identifier and the interrupt level are obtained, if the two are consistent with the interrupt configuration information, verification is passed, and the test efficiency is improved.

Description

Technical Field

[0001] This application relates to the technical field of chip verification, and in particular, to an interrupt verification method, device, storage medium, and equipment for C2F. Background Art

[0002] The Customer to Factory (C2F) industrial model is an industrial model driven by customer needs, which realizes highly customized and flexible production and supply chains. In the traditional industrial model, product design and production processes are often unidirectionally pushed by manufacturers based on market forecasts. In the C2F model, customer needs reach the factory directly, enabling the entire production process to be adjusted in real time according to the personalized needs of customers. The core advantage of the C2F model lies in its ability to significantly improve production flexibility and response speed, reduce intermediate circulation links, reduce inventory backlogs, improve production efficiency, and quickly respond to changes in the market and consumer demands.

[0003] The Reduced Instruction Set Computer - Fifth Generation (RISC-V), as an open-source, customizable, and extensible Central Processing Unit (CPU) architecture, has multiple application scenarios in the C2F scenario. The RISC-V CPU can be used as a programmable logic controller to provide precise motion control for industrial robots, receive sensor data in real time and process it efficiently, thereby enabling quick decision-making and precise operation. At the same time, the low-power characteristics of the RISC-V chip enable it to maintain efficient operation in an environment where device power is limited, reducing energy consumption and operating costs.

[0004] In the traditional chip interrupt verification process, it is usually necessary to manually write software code in advance, compile it into an executable file and run it in a simulation environment, and then the verification environment generates an interrupt signal for verification. When the test content changes, it is necessary to manually rewrite the software and repeat the entire test process, which is not only inefficient but also prone to introducing human errors, increasing the complexity and cost of verification. Therefore, related technologies urgently need to propose an interrupt verification method to solve the above technical problems. Summary of the Invention

[0005] The main purpose of this application is to provide an interrupt verification method, device, storage medium, and equipment for C2F, which can automatically perform interrupt tests according to constraint conditions, avoid manually writing software, and improve test efficiency.

[0006] In a first aspect, an embodiment of this application provides an interrupt verification method for C2F, including: Obtain test constraint conditions, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraint conditions; Generate a configuration file based on the global configuration information and the interrupt configuration information. The configuration file includes global configuration codes for configuring the global registers of the simulation processor and the interrupt controller according to the global configuration information, interrupt configuration codes for configuring the interrupt registers corresponding to the interrupt signal to be tested according to the interrupt configuration information, and program configuration codes of the interrupt verification program; Send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt registers corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program; When the simulation processor finishes the configuration, send the interrupt signal to be tested that conforms to the interrupt configuration information to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt registers, and sends the generated interrupt request to the simulation processor; When it is detected that the interrupt verification program is entered during the process of the simulation processor responding to the interrupt request, obtain the interrupt signal identifier and the interrupt level; When the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, determine that the verification is passed.

[0007] In a second aspect, an embodiment of the present application provides an interrupt verification device for C2F, including: A first acquisition unit, configured to acquire test constraint conditions, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraint conditions; A generation unit, configured to generate a configuration file based on the global configuration information and the interrupt configuration information. The configuration file includes global configuration codes for configuring the global registers of the simulation processor and the interrupt controller according to the global configuration information, interrupt configuration codes for configuring the interrupt registers corresponding to the interrupt signal to be tested according to the interrupt configuration information, and program configuration codes of the interrupt verification program; A first sending unit, configured to send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt registers corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program; A second sending unit, configured to send a to-be-tested interrupt signal conforming to the interrupt configuration information to the interrupt controller when the simulation processor is configured, so that the interrupt controller processes the to-be-tested interrupt signal according to the interrupt register and sends the processed interrupt request to the simulation processor; A second obtaining unit, configured to obtain an interrupt signal identifier and an interrupt level when it is detected that an interrupt verification program is entered during the process that the simulation processor responds to the interrupt request; A verification unit, configured to determine that the verification is passed when the interrupt signal identifier and the interrupt level conform to the interrupt configuration information.

[0008] In a third aspect, an embodiment of the present application provides a storage medium. The computer-readable storage medium stores multiple instructions, and the instructions are suitable for being loaded by a processor to execute the interrupt verification method for C2F as described in any one of the above.

[0009] In a fourth aspect, an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the interrupt verification method for C2F as described in any one of the above is implemented.

[0010] In an embodiment of the present application, by obtaining test constraint conditions, global configuration information and interrupt configuration information of a to-be-tested interrupt signal are generated according to the test constraint conditions; based on the global configuration information and the interrupt configuration information, a configuration file is generated, and the configuration file includes global configuration codes for configuring global registers of a simulation processor and an interrupt controller according to the global configuration information, interrupt configuration codes for configuring interrupt registers corresponding to the to-be-tested interrupt signal according to the interrupt configuration information, and program configuration codes of an interrupt verification program; the configuration file is sent to the simulation processor, so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt registers corresponding to the to-be-tested interrupt signal in the interrupt controller, and the interrupt verification program; when the simulation processor finishes the configuration, a to-be-tested interrupt signal conforming to the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the to-be-tested interrupt signal according to the interrupt registers and sends the processed interrupt request to the simulation processor; when it is detected that the simulation processor enters the interrupt verification program during the process of responding to the interrupt request, an interrupt signal identifier and an interrupt level are obtained; when the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed. Compared with the related art where software needs to be manually written and the entire test process needs to be repeated for each test, in the embodiment of the present application, the global configuration information and the interrupt configuration information generated by the constraint conditions are used to generate a configuration file for the simulation processor to configure, and the verification of the to-be-tested interrupt signal is automatically performed after the configuration is completed, avoiding manual software writing and improving the test efficiency.

[0011] Other features and advantages of the present disclosure will be described in subsequent specifications, and part of them will become obvious from the specifications or be understood by implementing the present disclosure. The objectives and other advantages of the present disclosure can be achieved and obtained through the structures specifically pointed out in the specifications, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of this specification. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a schematic diagram of a scenario of an interrupt verification system for C2F provided by an embodiment of the present application.

[0014] Figure 2A flowchart showing the process of the interrupt verification method for C2F provided by an embodiment of the present application.

[0015] Figure 3 A schematic diagram showing the structure of the global register provided by an embodiment of the present application.

[0016] Figure 4 A schematic diagram showing the register structure related to a single interrupt signal in the interrupt controller provided by an embodiment of the present application.

[0017] Figure 5 A flowchart showing the determination of the interrupt verification method provided by an embodiment of the present application.

[0018] Figure 6 Another flowchart showing the determination of the interrupt verification method provided by an embodiment of the present application.

[0019] Figure 7 A schematic diagram showing the structure of the interrupt verification device for C2F provided by an embodiment of the present application.

[0020] Figure 8 A schematic diagram showing the structure of the computer device provided by an embodiment of the present application. Detailed implementation manners

[0021] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0022] It should be noted that in some processes described in the specification, claims and the above-mentioned drawings, there are multiple steps that appear in a specific order. However, it should be clearly understood that these steps may not be executed in the order in which they appear in this text or may be executed in parallel. The step numbers are only used to distinguish different steps, and the numbers themselves do not represent any execution order. In addition, descriptions such as "first", "second" or "target" in this text are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0023] Before further elaborating on the embodiments of the present disclosure, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are applicable to the following explanations: The Core-Local Interrupt Controller (CLIC) is an important component for handling interrupts in the RISC-V architecture. In a computer system, interrupts are an important mechanism for handling requests from external devices or internal exception situations. As the interrupt controller under the RISC-V architecture, CLIC is responsible for managing and coordinating the interrupt requests of multiple interrupt sources to ensure that the processor can respond to these requests in a timely and orderly manner.

[0024] Rich interrupt source support: CLIC can support a large number of external interrupt sources, and each interrupt source can be independently configured and managed. This enables the system to connect more types and quantities of external devices, such as sensors, communication interfaces, etc., and provide dedicated processing methods for the interrupt requests of each device.

[0025] Flexible priority management: Introduced the concept of multi-level interrupt priorities, allowing different priorities to be assigned to each interrupt source. When multiple interrupts occur simultaneously, the processor will process the interrupts in the order of priority, ensuring that high-priority interrupts can be responded to in a timely manner, which is particularly important for real-time systems.

[0026] Diverse trigger modes: Supports multiple interrupt trigger modes, including level trigger and edge trigger. Different trigger modes are suitable for different types of external devices and application scenarios, increasing the flexibility of the system.

[0027] Interrupt vector table mechanism: Uses an interrupt vector table to manage the entry addresses of interrupt verification programs. Each interrupt source corresponds to a unique interrupt vector. When an interrupt occurs, the processor can quickly locate the corresponding interrupt verification program by looking up the interrupt vector table, reducing the interrupt response latency and improving the efficiency of interrupt processing.

[0028] The Executable and Linkable Format (ELF) is a file format used to represent executable files, object files, shared libraries, and core dump files, etc. ELF is a binary file format standard designed to provide a unified, flexible, and extensible file format to support program execution and linking on different architectures and operating systems. Nowadays, ELF has become a widely used standard file format in Linux, Unix-like systems, and many embedded systems.

[0029] For details, please continue to refer to the following specific embodiments.

[0030] Please refer to Figure 1 , Figure 1This is a schematic diagram of the scenario of the interruption verification system for C2F provided by the embodiments of the present application. It includes a terminal 140, the Internet 130, a gateway 120, a server 110, etc.

[0031] The terminal 140 includes, but is not limited to, pre-configured laptop computers, tablet computers, desktop computers, and other electronic devices with data reporting capabilities. Additionally, it can be a single device or a collection of multiple devices. The terminal 140 can communicate with the Internet 130 in a wired or wireless manner to exchange data.

[0032] The terminal 140 refers to a computer system that can report data to the server 110. Compared with ordinary terminals, the server 110 has higher requirements in terms of stability, security, performance, etc. The server 110 can be a high-performance computer in a network platform, a cluster of multiple high-performance computers, a part (such as a virtual machine) allocated from a high-performance computer, a combination of parts (such as virtual machines) allocated from multiple high-performance computers, etc.

[0033] The gateway 120 is also known as an inter-network connector and protocol converter. The gateway realizes network interconnection at the transport layer and is a computer system or device that acts as a converter. Between two systems using different communication protocols, data formats, or languages, and even with completely different architectures, the gateway is a translator. At the same time, the gateway can also provide filtering and security functions. The message sent by the terminal 140 to the server 110 needs to be sent to the corresponding server 110 through the gateway 120. The message sent by the server 110 to the terminal 140 also needs to be sent to the corresponding terminal 140 through the gateway 120.

[0034] The interruption verification method of the embodiments of the present disclosure can be implemented on the server 110.

[0035] It should be noted that Figure 1 The schematic diagram of the scenario of the interruption verification system for C2F shown is only an example. The interruption verification system and scenario described in the embodiments of the present application are for more clearly explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art know that with the evolution of image processing technology and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0036] In this embodiment, the description will be made from the perspective of the interruption verification device, which can be specifically integrated in a computer device with a storage unit and installed with a microprocessor and having computing capabilities.

[0037] Please refer to Figure 2 , Figure 2Schematic flowchart of the interrupt verification method for C2F provided by the embodiments of this application. The interrupt verification method for C2F includes: In step 201, obtain test constraint conditions, and generate global configuration information and interrupt configuration information for the interrupt signal to be tested according to the test constraint conditions.

[0038] Among them, the constraint conditions are a series of restrictions and requirements for the simulation test process, used to define the scope and objectives of the test, and ensure the effectiveness and reliability of the test results. The global configuration information is a set of configuration parameters that affect the operation of the entire simulation system, involving global settings of multiple components such as the simulation processor and the interrupt controller. The interrupt signal to be tested is the interrupt signal that needs to be tested and verified, usually from the driver in the test environment. The interrupt configuration information is the detailed configuration parameters for a specific interrupt signal, used to control behaviors such as the triggering, processing, and priority of the interrupt.

[0039] Specifically, collect relevant information from test cases, requirement documents, or user inputs. These information stipulate the specific requirements of the simulation test, such as the working mode of the simulation processor, the triggering conditions of the interrupt, the priority settings, etc. According to the test constraint conditions, determine the configuration parameters related to the entire simulation system, such as the privileged mode of the simulation processor, the interrupt enable status, etc. For the interrupt signal to be tested, generate the corresponding configuration information according to the test constraint conditions, including the interrupt number, the triggering mode (level trigger or edge trigger), the priority, etc.

[0040] In step 202, generate a configuration file based on the global configuration information and the interrupt configuration information. The configuration file includes global configuration codes for configuring the global registers of the simulation processor and the interrupt controller according to the global configuration information, interrupt configuration codes for configuring the interrupt registers corresponding to the interrupt signal to be tested according to the interrupt configuration information, and program configuration codes for the interrupt verification program.

[0041] Among them, since the global configuration information and the interrupt configuration information are generated according to the constraint conditions, for the purpose of realizing automated testing, these configuration information need to be automatically configured to the simulation processor and the interrupt controller. Therefore, it is necessary to generate a configuration file in elf format according to the global configuration information and the interrupt configuration information for the simulation processor to execute, so as to realize automated configuration.

[0042] Specifically, the CLIC standard defines that the CPU design code also needs to be modified, including: xstatus, xedeleg / xideleg, xie / xip, xtvec, xcause control and status registers (Control and Status Register, CSR), and xtvt, xnxti, xintstatus, xintthresh CSR registers need to be added, so the design under test (DUT) in the implementation of this application verifies the CLIC interrupt controller and the simulation processor after the modified code as a whole, otherwise it is impossible to verify the CPU modified and added code, and the quality of the design cannot be guaranteed. However, the interrupt is generated by the verification environment, rather than by the various functional modules in the system verification environment of the System on a Chip (SOC), so the flexibility and controllability of the interrupt generation are greatly improved, and the cost of generating interrupts is also greatly reduced. Therefore, it is necessary to configure both the simulation processor and the interrupt controller, so the configuration file includes the global configuration code of the global registers of the simulation processor and the global configuration code of the global registers of the interrupt controller, as well as the interrupt configuration code of the interrupt register corresponding to the interrupt signal to be tested, and the program configuration code of the interrupt verification program. The program configuration code is used to configure the interrupt verification program, and the interrupt verification program is used to verify whether the simulation processor responds to the interrupt request correctly. These codes are usually written in assembly language or high-level programming language, and the configuration is completed by writing corresponding values ​​to specific registers and building an interrupt verification program.

[0043] In some implementations, generating a configuration file based on the global configuration information and the interrupt configuration information includes: (1) Obtaining a first privileged mode, a parent interrupt control mode, and a child interrupt control mode required for the current test from the global configuration information and the interrupt configuration information; (2) Obtain the second privileged mode currently running in the simulation processor; (3) determining a target interrupt verification mode of the interrupt signal to be tested based on the first privileged mode, the parent interrupt control mode, the child interrupt control mode, and the second privileged mode; (4) determining a target code template corresponding to the interrupt verification program based on a mapping relationship between the interrupt verification method and the code template of the interrupt verification program; (5) Obtaining the content to be replaced included in the target code template, and the content type corresponding to each of the content to be replaced; (6) Obtain the replacement content corresponding to each of the content types from the interruption configuration information, and replace the replacement content under the corresponding content type in the target code template to obtain the program configuration code of the interruption verification program; (7) Obtain the first register configuration content of the simulation processor and the second register configuration content of the interruption controller from the global configuration information; (8) Generate global configuration code according to the first register configuration content and the second register configuration content; (9) Obtain the third register configuration content of the interruption register corresponding to the to-be-tested interruption signal in the interruption controller from the interruption configuration information; (10) Generate interruption configuration code according to the third register configuration content; (11) Combine the program configuration code, the global configuration code and the interruption configuration code to obtain a configuration file.

[0044] Among them, as Figure 3 shown, Figure 3This is a schematic diagram of the structure of the global register provided by the embodiment of the present application. The global register includes cliccfg, Xtvec, Xinthresh, and Xie. Among them, cliccfg is the CLIC configuration register (CLIC Configuration Register). It is located within the CLIC interrupt controller and is used for overall configuration and setting of the CLIC interrupt controller. For example, it can configure the working mode, global enable status, etc. of the interrupt controller to determine how to handle incoming interrupt signals. Xtvec is the exception vector table base address register (Exception Vector Table Base Address Register). In the RISC-V architecture, when an exception or interrupt occurs, the processor needs to jump to the corresponding handler for execution. The Xtvec register stores the starting address of the exception vector table, and the processor finds the corresponding exception or interrupt verification program entry based on this address to perform subsequent processing operations. Xinthresh is the interrupt threshold register (Interrupt Threshold Register). It is used to set the priority threshold of interrupts. Only when the priority of a certain interrupt is higher than the value set in the Xinthresh register, will this interrupt be responded to and processed by the processor. By adjusting the value of this register, it is possible to flexibly control which interrupts can be processed in a timely manner and which ones need to wait. Xie is the interrupt enable bit (Interrupt Enable). Xstatus is a CSR, and Xie is a specific field in the Xstatus register, which is used for global control of the enable or disable of interrupts. When the Xie bit is set to the enabled state, the processor can respond to externally or internally generated interrupts; when this bit is disabled, all interrupts will be masked and the processor will not respond to them.

[0045] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the register structure related to a single interrupt signal in the interrupt controller provided by the embodiment of the present application. Each interrupt signal in the interrupt controller corresponds to Figure 4The clicintie, clicintattr, clicintctl, and intid as shown. The clicintie is the Core - Local Interrupt Controller Individual Interrupt Enable Register. In the CLIC architecture, the system may have multiple interrupt sources, and each interrupt source corresponds to a unique interrupt. The clicintie register is used to individually control whether each interrupt is enabled. By setting the bit corresponding to the interrupt in this register, it can be determined whether a specific interrupt can be responded to and processed by the system. For example, if the clicintie bit corresponding to the interrupt generated by a certain device is set to 1, then the interrupt is enabled and the system will process the interrupt at the appropriate time; if it is set to 0, the interrupt is disabled and the system will not respond to it. The clicintattr is the Core - Local Interrupt Controller Individual Interrupt Attribute Register. This register is used to configure the attribute information of each interrupt, and these attributes may include the trigger mode of the interrupt (such as rising - edge trigger, falling - edge trigger, high - level trigger, low - level trigger, etc.), the privilege mode (i.e., at what privilege level the interrupt is processed), etc. Different attribute settings will affect the way the interrupt is processed and the system's response strategy to the interrupt. The clicintctl is the Core - Local Interrupt Controller Individual Interrupt Control Register. It is used for more detailed control and management of individual interrupts and may contain control information such as the priority setting of the interrupt and whether to use hardware vectoring. The priority setting determines the order in which the system processes interrupts when multiple interrupts occur simultaneously; hardware vectoring can improve the efficiency of interrupt processing and reduce software overhead. The intid is the Interrupt Identifier. In a system, each interrupt source is assigned a unique number, that is, the interrupt number. When an interrupt occurs, the system determines which interrupt source generated the interrupt by identifying the intid of the interrupt, and then looks up the corresponding interrupt verification program entry address according to the intid to perform the corresponding interrupt handling operation. For example, in a system with multiple peripherals, the interrupt generated by keyboard input may be assigned intid = 10, and the interrupt generated by mouse movement may be assigned intid = 11. The system distinguishes and processes different interrupt events according to different intids.

[0046] Specifically, during the process of generating the configuration file, since it involves the generation of the program configuration code for the interrupt verification program, it is necessary to determine the specific target interrupt verification method for the interrupt signal to be tested according to the relevant configuration of the interrupt signal to be tested in this test and the relevant information of the current operation of the simulation processor.

[0047] Among them, the main factors affecting the interrupt verification method include the privilege mode, the parent interrupt control mode, and the sub-interrupt control mode. The RISC-V architecture defines multiple privilege modes, such as the machine mode (M-mode), the supervisor mode (S-mode), and the user mode (U-mode) which are common, and the privileges decrease in turn. The machine mode has the highest privilege and can access all system resources and execute all instructions, and is often used for system startup, hardware initialization, etc.; the supervisor mode is used for the operating system kernel and can execute some privileged instructions and manage system resources; the user mode has the lowest privilege and can only execute non-privileged instructions and is used to run ordinary user programs. The parent interrupt control mode includes two different interrupt handling modes, CLINT (Core-Local Interruptor) and CLIC (Core-Local Interrupt Controller). Under both the CLINT mode and the CLIC mode, there are two different sub-interrupt control modes, namely the direct mode (Direct mode) and the hardware vector mode.

[0048] Specifically, the xtvec in the global configuration information is configured with the parent interrupt control mode (such as the CLINT mode or the CLIC mode), the clicintattr in the interrupt configuration information is configured with the first privilege mode (such as the machine mode, the supervisor mode, the user mode) required for the interrupt signal to be tested in the current test, and the clicintctl is configured with the sub-interrupt control mode (such as the Direct mode or the hardware vector mode). Since the privilege mode and other information of the current operation of the simulation processor are known, it can be identified whether it is necessary to enter the interrupt verification program and which interrupt verification program to enter. Different interrupt verification methods correspond to different code templates of the interrupt verification program. Therefore, after determining the target interrupt verification method for the interrupt signal to be tested, the target code template corresponding to the interrupt verification program can be determined according to this mapping relationship. The code template reserves the content to be replaced with specific content. By obtaining the content to be replaced included in the target code template and the content type corresponding to each content to be replaced, the replacement content corresponding to each content type is obtained from the interrupt configuration information, and the replacement content is replaced under the corresponding content type in the target code template to obtain the program configuration code of the interrupt verification program.

[0049] Among them, according to Figure 3 and Figure 4, it is also necessary to separately configure the global registers of the simulation processor (the first registers xtvec, xinthresh, and xstatus.xie), the global registers of the interrupt controller (the second register cliccfg), and the interrupt registers of the interrupt registers corresponding to the interrupt signals to be tested in the interrupt controller (the third registers clicintie, clicintattr, clicintctl, and intid). Therefore, it is necessary to obtain the configuration content of the first register of the simulation processor and the configuration content of the second register of the interrupt controller from the global configuration information; generate global configuration code according to the configuration content of the first register and the configuration content of the second register; obtain the configuration content of the third register of the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller from the interrupt configuration information; generate interrupt configuration code according to the configuration content of the third register; and finally combine the program configuration code, the global configuration code, and the interrupt configuration code to obtain the configuration file.

[0050] In some embodiments, determining the target interrupt verification method for the interrupt signal to be tested based on the first privilege mode, the parent interrupt control mode, the sub - interrupt control mode, and the second privilege mode includes: (1.1) Comparing the first interrupt privilege mode with the second interrupt privilege mode to obtain a comparison result; (1.2) When the comparison result indicates that the first interrupt privilege mode is greater than the second interrupt privilege mode, determining that the interrupt signal to be tested is processed as a vertical interrupt; (1.3) When the parent interrupt control mode is the CLINT mode and the sub - interrupt control mode is the Direct mode, determining the interrupt verification method of the Direct mode as the target interrupt verification method for the interrupt signal to be tested; (1.4) When the parent interrupt control mode is the CLINT mode and the sub - interrupt control mode is not the Direct mode, determining the interrupt verification method of the vector mode as the target interrupt verification method for the interrupt signal to be tested.

[0051] Among them, please refer to Figure 5 , Figure 5A flowchart for determining an interrupt verification method provided by an embodiment of the present application. First, compare the privilege mode of the interrupt (the first privilege mode) with the current privilege mode of the emulation processor (the second privilege mode) to obtain a comparison result; when the comparison result indicates that the first privilege mode is less than the second privilege mode, the interrupt is ignored; when the comparison result indicates that the first privilege mode is greater than the second privilege mode, determine that the current interrupt is processed according to a vertical interrupt; when the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, determine the interrupt verification method of the Direct mode as the target interrupt verification method of the interrupt signal to be measured; when the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, determine the interrupt verification method of the vector mode as the target interrupt verification method of the interrupt signal to be measured.

[0052] In some embodiments, the method further includes: (1.1) When the parent interrupt control mode is the CLIC mode and the child interrupt control mode is the hardware vector mode, determine the interrupt verification method of the vector mode as the target interrupt verification method of the interrupt signal to be measured; (1.2) When the parent interrupt control mode is the CLIC mode and the child interrupt control mode is not the hardware vector mode, determine the interrupt verification method of the non-vector mode as the target interrupt verification method of the interrupt signal to be measured.

[0053] Wherein, referring further to Figure 5 , when the parent interrupt control mode is the CLIC mode and the child interrupt control mode is the hardware vector mode, determine the interrupt verification method of the vector mode as the target interrupt verification method of the interrupt signal to be measured; when the parent interrupt control mode is the CLIC mode and the child interrupt control mode is not the hardware vector mode, determine the interrupt verification method of the non-vector mode as the target interrupt verification method of the interrupt signal to be measured.

[0054] In some embodiments, the method further includes: (1.1) When the comparison result indicates that the first interrupt privilege mode is equal to the second interrupt privilege mode, determine that the interrupt signal to be measured is processed according to a horizontal interrupt; (1.2) When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, determine the interrupt verification method of the Direct mode as the target interrupt verification method of the interrupt signal to be measured; (1.3) When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, determine the interrupt verification method of the vector mode as the target interrupt verification method of the interrupt signal to be measured.

[0055] Please refer to Figure 6 , Figure 6 which is another flowchart for determining the interrupt verification method provided by the embodiment of the present application. If the comparison result indicates that the first privilege mode is equal to the second privilege mode, it is determined that the current interrupt is processed as a level interrupt; when the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, the interrupt verification method of the Direct mode is determined as the target interrupt verification method of the to-be-tested interrupt signal; when the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, the interrupt verification method of the vector mode is determined as the target interrupt verification method of the to-be-tested interrupt signal.

[0056] In some embodiments, the method further includes: (1.1) When the parent interrupt control mode is the CLIC mode, obtain the global enable status from the global configuration information and obtain the interrupt enable status of the to-be-tested interrupt signal from the interrupt configuration information; (1.2) When the global enable status and the interrupt enable status are enabled, obtain the priority threshold from the global configuration information and obtain the interrupt priority of the to-be-tested interrupt signal from the interrupt configuration information; (1.3) Determine the highest target priority among the priority threshold and the current priority of the simulation processor; (1.4) When the interrupt priority is higher than the target priority and the child interrupt control mode is the hardware vector mode, determine the interrupt verification method of the vector mode as the target interrupt verification method of the to-be-tested interrupt signal.

[0057] Among them, when the parent interrupt control mode is the CLIC mode, obtain the global enable status (such as enabled or disabled) from the global configuration information, and obtain the interrupt enable status of the interrupt signal to be measured from the interrupt configuration information (such as the interrupt signal to be measured is configured to be enabled or disabled); if at least one of the two is 0, that is, when it is disabled, the interrupt is not enabled and invalid; if both are 1, it means that the enable status is enabled, and then interrupt processing is performed. The condition for whether to perform interrupt processing is: whether the interrupt priority of the interrupt signal to be measured is higher than L, where L is the highest target priority in the priority threshold xintstatus.xil in the global configuration information and the current priority xintthresh.th of the simulation processor, which can be expressed as max(xintstatus.xil, xintthresh.th). Therefore, it is necessary to obtain the priority threshold from the global configuration information, and obtain the interrupt priority of the interrupt signal to be measured from the interrupt configuration information, and determine the highest target priority L among the priority threshold and the current priority of the simulation processor; when the interrupt priority is higher than the target priority L and the sub-interrupt control mode is the hardware vector mode, determine the interrupt verification method of the vector mode as the target interrupt verification method of the interrupt signal to be measured.

[0058] In some embodiments, the method further includes: When the interrupt priority is higher than the target priority and the sub-interrupt control mode is not the hardware vector mode, determine the interrupt verification method of the non-vector mode as the target interrupt verification method of the interrupt signal to be measured.

[0059] Among them, if the interrupt priority is higher than the target priority, it means that the interrupt can be processed, and when the sub-interrupt control mode is not the hardware vector mode, it means that the sub-interrupt control mode is not the vector mode, so determine the interrupt verification method of the non-vector mode as the target interrupt verification method of the interrupt signal to be measured.

[0060] In step 203, send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure the global register of the simulation processor, the global register of the interrupt controller, the interrupt register corresponding to the interrupt signal to be measured in the interrupt controller, and the interrupt verification program.

[0061] Among them, send the configuration file in elf format to the simulation processor. After the simulation processor receives the configuration file, trigger it to configure the global register, the global register of the interrupt controller, the interrupt register, and the interrupt verification program in sequence according to the configuration code in the file. The simulation processor is a software or hardware model used to simulate the behavior of a real processor, and realizes corresponding functions and configurations by executing the configuration file.

[0062] In step 204, when the simulation processor is configured, a to-be-tested interrupt signal conforming to the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the to-be-tested interrupt signal according to the interrupt register and sends the processed interrupt request to the simulation processor.

[0063] Among them, after the simulation processor is configured, the drv_start flag register is written. When the written flag is read from the flag register, a to-be-tested interrupt signal conforming to the interrupt configuration information is sent to the interrupt controller through a driver (Driver), so that the interrupt controller processes the to-be-tested interrupt signal according to the interrupt register and sends the processed interrupt request to the simulation processor. The interrupt request is a signal generated by the interrupt controller after receiving the interrupt signal and processed to request the processor to perform interrupt processing.

[0064] In step 205, when it is detected that the interrupt verification program is entered during the process of the simulation processor responding to the interrupt request, the interrupt signal identifier and the interrupt level are obtained.

[0065] Among them, it is judged whether the interrupt verification program can be entered. If the interrupt verification program can be entered, the interrupt level, interrupt id, etc. are judged and PASS or FAIL is printed.

[0066] Specifically, in the interrupt verification program, it is checked whether the exccode field in the xcause CSR register is the same as the specified interrupt number, and whether the xil field (i.e., the interrupt level) of the xintstatus CSR register is correct, etc. If it is correct, PASS is printed; if it is incorrect, FAIL is printed. The xcause register is a special control and status register, and its main function is to record the reason for the most recent exception or interrupt. When the system encounters an exception (such as an illegal instruction, out-of-bounds access, etc.) or receives an interrupt signal, the hardware will automatically write the relevant exception or interrupt information into the xcause register. The exccode field is a part of the xcause register and is used to store the specific exception or interrupt encoding. The highest bit of the xcause register is used to distinguish whether it is an exception (value 0) or an interrupt (value 1), and the remaining low bits form the exccode field. Different exception or interrupt types correspond to different exccode values. By parsing this value, the software can know which specific exception or interrupt has occurred.

[0067] In step 206, when the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed.

[0068] Among them, if the interrupt signal identifier and the interrupt level conform to the signal identifier and interrupt level of the interrupt signal to be tested in the interrupt configuration information, it is determined that the verification is passed.

[0069] In some embodiments, the method further includes: (1) When it is detected that the interrupt verification program is not entered during the process of the simulation processor responding to the interrupt request, the monitor checks whether the interrupt signal to be tested sent to the interrupt controller and the interrupt request sent by the interrupt controller to the simulation processor conform to the global configuration information and the interrupt configuration information; (2) If they conform, it is determined that the verification is passed; (3) If they do not conform, it is determined that the verification fails.

[0070] Among them, if the interrupt verification program cannot be entered, a monitor can be used to check whether the signals sent by the Driver to the CLIC interrupt controller and the CLIC interrupt controller to the simulation processor meet the expectations, and print PASS or FAIL messages in the Monitor.

[0071] As described above, in the embodiment of the present application, by obtaining test constraint conditions, global configuration information and interrupt configuration information of a to-be-tested interrupt signal are generated according to the test constraint conditions; based on the global configuration information and the interrupt configuration information, a configuration file is generated, and the configuration file includes global configuration code for configuring global registers of a simulation processor and an interrupt controller according to the global configuration information, interrupt configuration code for configuring an interrupt register corresponding to the to-be-tested interrupt signal according to the interrupt configuration information, and program configuration code of an interrupt verification program; the configuration file is sent to the simulation processor, so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt register corresponding to the to-be-tested interrupt signal in the interrupt controller, and the interrupt verification program; when the simulation processor finishes configuration, a to-be-tested interrupt signal conforming to the interrupt configuration information is sent to the interrupt controller, so that the interrupt controller processes the to-be-tested interrupt signal according to the interrupt register and sends the processed interrupt request to the simulation processor; when it is detected that the interrupt verification program is entered during the process of the simulation processor responding to the interrupt request, an interrupt signal identifier and an interrupt level are obtained; when the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed. Compared with the related art where software needs to be manually written and the entire test process needs to be repeated for each test, in the embodiment of the present application, the global configuration information and the interrupt configuration information generated by the constraint conditions are used to generate a configuration file for the simulation processor to configure, and the to-be-tested interrupt signal is automatically verified after the configuration is completed, avoiding manual software writing and improving the test efficiency.

[0072] For the specific implementation of each of the above steps, reference may be made to the previous embodiments and will not be elaborated herein.

[0073] To facilitate better implementation of the interrupt verification method for C2F provided in the embodiment of the present application, the embodiment of the present application further provides a device based on the above interrupt verification method for C2F. The meanings of the nouns are the same as those in the above interrupt verification method, and the specific implementation details may refer to the description in the method embodiment.

[0074] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of the interrupt verification device provided in the embodiment of the present application. The interrupt verification device for C2F is applied to a computer device. The interrupt verification device for C2F may include a first acquisition unit 601, a generation unit 602, a first sending unit 603, a second sending unit 604, a second acquisition unit 605, a verification unit 606, etc.

[0075] The first acquisition unit 601 is configured to acquire test constraint conditions, and generate global configuration information and interruption configuration information of the interruption signal to be tested according to the test constraint conditions; The generation unit 602 is configured to generate a configuration file based on the global configuration information and the interruption configuration information. The configuration file includes global configuration codes for configuring global registers of the simulation processor and the interruption controller according to the global configuration information, interruption configuration codes for configuring interruption registers corresponding to the interruption signal to be tested according to the interruption configuration information, and program configuration codes of an interruption verification program; The first sending unit 603 is configured to send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure global registers of the simulation processor, global registers of the interruption controller, interruption registers corresponding to the interruption signal to be tested in the interruption controller, and an interruption verification program; The second sending unit 604 is configured to send the interruption signal to be tested that conforms to the interruption configuration information to the interruption controller when the simulation processor finishes configuration, so that the interruption controller processes the interruption signal to be tested according to the interruption registers, and sends the obtained interruption request to the simulation processor; The second acquisition unit 605 is configured to acquire an interruption signal identifier and an interruption level when it is detected that the simulation processor enters an interruption verification program during the process of responding to the interruption request; The verification unit 606 is configured to determine that the verification is passed when the interruption signal identifier and the interruption level conform to the interruption configuration information.

[0076] In some embodiments, the generation unit 602 includes: The first acquisition subunit is configured to acquire a first privilege mode, a parent interruption control mode, and a sub-interruption control mode required for the current test from the global configuration information and the interruption configuration information; The second acquisition subunit is configured to acquire a second privilege mode in which the simulation processor is currently running; The first determination subunit is configured to determine a target interruption verification method for the interruption signal to be tested based on the first privilege mode, the parent interruption control mode, the sub-interruption control mode, and the second privilege mode; The second determination subunit is configured to determine a target code template corresponding to the interruption verification program based on a mapping relationship between an interruption verification method and a code template of the interruption verification program; The third acquisition subunit is configured to acquire content to be replaced included in the target code template, and a content type corresponding to each content to be replaced; A replacement subunit, configured to obtain replacement content corresponding to each content type from the interruption configuration information, and replace the replacement content under the corresponding content type in the target code template to obtain a program configuration code of an interruption verification program; A fourth obtaining subunit, configured to obtain first register configuration content of the simulation processor and second register configuration content of an interruption controller from the global configuration information; A first generating subunit, configured to generate global configuration code according to the first register configuration content and the second register configuration content; A fifth obtaining subunit, configured to obtain third register configuration content of an interruption register corresponding to the to-be-tested interruption signal in the interruption controller from the interruption configuration information; A second generating subunit, configured to generate interruption configuration code according to the third register configuration content; An associating subunit, configured to associate the program configuration code, the global configuration code, and the interruption configuration code to obtain a configuration file.

[0077] In some embodiments, a first determining subunit is configured to: Compare the first interruption privilege mode with the second interruption privilege mode to obtain a comparison result; When the comparison result indicates that the first interruption privilege mode is greater than the second interruption privilege mode, determine that the to-be-tested interruption signal is processed according to a vertical interruption; When the parent interruption control mode is a CLINT mode and the child interruption control mode is a Direct mode, determine the interruption verification method of the Direct mode as the target interruption verification method of the to-be-tested interruption signal; When the parent interruption control mode is a CLINT mode and the child interruption control mode is not a Direct mode, determine the interruption verification method of a vector mode as the target interruption verification method of the to-be-tested interruption signal.

[0078] In some embodiments, the first determining subunit is further configured to: When the parent interruption control mode is a CLIC mode and the child interruption control mode is a hardware vector mode, determine the interruption verification method of the vector mode as the target interruption verification method of the to-be-tested interruption signal; When the parent interruption control mode is a CLIC mode and the child interruption control mode is not a hardware vector mode, determine the interruption verification method of a non-vector mode as the target interruption verification method of the to-be-tested interruption signal.

[0079] In some embodiments, the first determining subunit is further configured to: When the comparison result indicates that the first interrupt privilege mode is equal to the second interrupt privilege mode, it is determined that the interrupt signal to be measured is processed according to the horizontal interrupt; When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is the Direct mode, the interrupt verification method of the Direct mode is determined as the target interrupt verification method of the interrupt signal to be measured; When the parent interrupt control mode is the CLINT mode and the child interrupt control mode is not the Direct mode, the interrupt verification method of the vector mode is determined as the target interrupt verification method of the interrupt signal to be measured.

[0080] In some embodiments, the first determination subunit is further configured to: When the parent interrupt control mode is the CLIC mode, obtain the global enable status from the global configuration information and obtain the interrupt enable status of the interrupt signal to be measured from the interrupt configuration information; When the global enable status and the interrupt enable status are enabled, obtain the priority threshold from the global configuration information and obtain the interrupt priority of the interrupt signal to be measured from the interrupt configuration information; Determine the target priority, which is the highest one between the priority threshold and the current priority of the simulation processor; When the interrupt priority is higher than the target priority and the child interrupt control mode is the hardware vector mode, the interrupt verification method of the vector mode is determined as the target interrupt verification method of the interrupt signal to be measured.

[0081] In some embodiments, the first determination subunit is further configured to: When the interrupt priority is higher than the target priority and the child interrupt control mode is not the hardware vector mode, the interrupt verification method of the non-vector mode is determined as the target interrupt verification method of the interrupt signal to be measured.

[0082] For the specific implementation of each of the above units, reference may be made to the previous embodiments and will not be elaborated here.

[0083] As described above, in the embodiment of the present application, the first acquisition unit 601 acquires test constraint conditions, and generates global configuration information and interruption configuration information of the interruption signal to be tested according to the test constraint conditions; the generation unit 602 generates a configuration file based on the global configuration information and the interruption configuration information, where the configuration file includes global configuration codes for configuring global registers of the simulation processor and the interruption controller according to the global configuration information, interruption configuration codes for configuring interruption registers corresponding to the interruption signal to be tested according to the interruption configuration information, and program configuration codes of an interruption verification program; the first sending unit 603 sends the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interruption controller, the interruption registers corresponding to the interruption signal to be tested in the interruption controller, and the interruption verification program; when the simulation processor finishes configuration, the second sending unit 604 sends the interruption signal to be tested that conforms to the interruption configuration information to the interruption controller, so that the interruption controller processes the interruption signal to be tested according to the interruption registers, and sends the processed interruption request to the simulation processor; when detecting that the simulation processor enters the interruption verification program during the process of responding to the interruption request, the second acquisition unit 605 acquires an interruption signal identifier and an interruption level; when the interruption signal identifier and the interruption level conform to the interruption configuration information, the verification unit 606 determines that the verification is passed. Compared with the related art in which software needs to be manually written and the entire test process needs to be repeated for each test, in the embodiment of the present application, the global configuration information and the interruption configuration information generated by the constraint conditions are used to generate a configuration file for the simulation processor to configure, and the interruption signal to be tested is automatically verified after the configuration is completed, avoiding manual software writing and improving the test efficiency.

[0084] For the specific implementation of each of the above units, reference may be made to the previous embodiments and will not be elaborated herein.

[0085] Refer to Figure 8 , Figure 8A structural block diagram of a part of the computer device 1000 for implementing the embodiments of the present disclosure. The computer device 1000 may vary greatly due to different configurations or performances, and may include one or more central processing units (CPUs) 622 (for example, one or more processors) and a memory 632, and one or more storage media 630 (for example, one or more mass storage devices) for storing application programs 642 or data 644. Among them, the memory 632 and the storage media 630 may be transient storage or persistent storage. The program stored in the storage media 630 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the server 600. Further, the central processing unit 622 may be configured to communicate with the storage media 630 and execute a series of instruction operations in the storage media 630 on the server 600.

[0086] The computer device 1000 may further include one or more power supplies 626, one or more wired or wireless network interfaces 650, one or more input / output interfaces 658, and / or one or more operating systems 641, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, and so on.

[0087] The central processing unit 622 in the computer device 1000 may be used to execute the interrupt verification method of the embodiments of the present disclosure, for example: Obtain test constraint conditions, and generate global configuration information and interrupt configuration information of the to-be-tested interrupt signal according to the test constraint conditions; Generate a configuration file based on the global configuration information and the interrupt configuration information, where the configuration file includes global configuration codes for configuring the global registers of the simulation processor and the interrupt controller according to the global configuration information, interrupt configuration codes for configuring the interrupt registers corresponding to the to-be-tested interrupt signal according to the interrupt configuration information, and program configuration codes of the interrupt verification program; Send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt registers corresponding to the to-be-tested interrupt signal in the interrupt controller, and the interrupt verification program; When the simulation processor finishes the configuration, send the to-be-tested interrupt signal that conforms to the interrupt configuration information to the interrupt controller, so that the interrupt controller processes the to-be-tested interrupt signal according to the interrupt registers, and sends the processed interrupt request to the simulation processor; When it is detected that the simulation processor enters the interrupt verification program during the process of responding to the interrupt request, obtain the interrupt signal identifier and the interrupt level; When the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed.

[0088] The embodiments of the present disclosure further provide a computer-readable storage medium, which is used to store program codes, and the program codes are used to execute the interrupt verification method of each of the foregoing embodiments.

[0089] The embodiments of the present disclosure further provide a computer program product, which includes a computer program. The processor of the computer device reads and executes the computer program, so that the computer device executes to implement the above-mentioned interrupt verification method. For example: Obtain test constraint conditions, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraint conditions; Based on the global configuration information and the interrupt configuration information, generate a configuration file, where the configuration file includes global configuration codes for configuring the global registers of the simulation processor and the interrupt controller according to the global configuration information, interrupt configuration codes for configuring the interrupt registers corresponding to the interrupt signal to be tested according to the interrupt configuration information, and program configuration codes of the interrupt verification program; Send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt registers corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program; When the simulation processor finishes configuration, send the interrupt signal to be tested that conforms to the interrupt configuration information to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt registers, and sends the processed interrupt request to the simulation processor; When it is detected that the simulation processor enters the interrupt verification program during the process of responding to the interrupt request, obtain the interrupt signal identifier and the interrupt level; When the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, it is determined that the verification is passed.

[0090] In addition, the terms "include" and "comprise" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these process, method, product or device.

[0091] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist at the same time. Here, A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the associated objects before and after. "At least one (of the following)" or its similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one (of) a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0092] It should be understood that in the description of the embodiments of this application, the meaning of "a plurality (or multiple items)" is more than two. Understandings such as "greater than", "less than", and "exceeding" do not include the present number, and understandings such as "above", "below", and "within" include the present number.

[0093] In several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be in electrical, mechanical, or other forms.

[0094] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] In addition, the functional units in each embodiment of this application can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0096] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM for short), random access memories (RAM for short), magnetic disks, or optical discs.

[0097] It should also be understood that the various embodiments provided in the embodiments of this application can be combined arbitrarily to achieve different technical effects.

[0098] In the embodiments of this application, the term "module" or "unit" refers to a computer program with a predetermined function or a part of a computer program, which works together with other related parts to achieve a predetermined goal, and can be fully or partially implemented by using software, hardware (such as a processing circuit or a memory), or a combination thereof. Similarly, a processor (or multiple processors or memories) can be used to implement one or more modules or units. In addition, each module or unit can be a part of the overall module or unit that includes the function of this module or unit.

[0099] The above is a specific description of the embodiments of this application, but this application is not limited to the above embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of this application, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. An interruption verification method for C2F, characterized in that, Including: Obtain test constraint conditions, and generate global configuration information and interrupt configuration information of the interrupt signal to be tested according to the test constraint conditions; Generate a configuration file based on the global configuration information and the interrupt configuration information, where the configuration file includes global configuration code for configuring global registers of a simulation processor and an interrupt controller according to the global configuration information, interrupt configuration code for configuring an interrupt register corresponding to the interrupt signal to be tested according to the interrupt configuration information, and program configuration code of an interrupt verification program; Send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure the global registers of the simulation processor, the global registers of the interrupt controller, the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller, and the interrupt verification program; When the simulation processor finishes configuration, send the interrupt signal to be tested that conforms to the interrupt configuration information to the interrupt controller, so that the interrupt controller processes the interrupt signal to be tested according to the interrupt register, and sends the processed interrupt request to the simulation processor; When it is detected that the interrupt verification program is entered during the process of the simulation processor responding to the interrupt request, obtain an interrupt signal identifier and an interrupt level; When the interrupt signal identifier and the interrupt level conform to the interrupt configuration information, determine that the verification is passed.

2. The interruption verification method for C2F according to claim 1, characterized in that The generating a configuration file based on the global configuration information and the interrupt configuration information includes: Obtain the first privilege mode, parent interrupt control mode, and sub-interrupt control mode required for the current test from the global configuration information and the interrupt configuration information; Obtain the second privilege mode in which the simulation processor is currently running; Determine the target interrupt verification method of the interrupt signal to be tested based on the first privilege mode, parent interrupt control mode, sub-interrupt control mode, and the second privilege mode; Determine the target code template corresponding to the interrupt verification program based on the mapping relationship between the interrupt verification method and the code template of the interrupt verification program; Obtain the content to be replaced included in the target code template, and the content type corresponding to each content to be replaced; Obtain the replacement content corresponding to each content type from the interrupt configuration information, and replace the replacement content under the corresponding content type in the target code template to obtain the program configuration code of the interrupt verification program; Obtain the first register configuration content of the simulation processor and the second register configuration content of the interrupt controller from the global configuration information; Generate global configuration code according to the first register configuration content and the second register configuration content; Obtain the third register configuration content of the interrupt register corresponding to the interrupt signal to be tested in the interrupt controller from the interrupt configuration information; Generate interrupt configuration code according to the third register configuration content; Combine the program configuration code, the global configuration code, and the interrupt configuration code to obtain a configuration file.

3. The interruption verification method for C2F according to claim 2, characterized in that Determining a target interrupt verification method for the interrupt signal to be measured based on the first privilege mode, the parent interrupt control mode, the sub - interrupt control mode, and the second privilege mode includes: Comparing the first interrupt privilege mode with the second interrupt privilege mode to obtain a comparison result; When the comparison result indicates that the first interrupt privilege mode is greater than the second interrupt privilege mode, determining that the interrupt signal to be measured is processed according to a vertical interrupt; When the parent interrupt control mode is the CLINT mode and the sub - interrupt control mode is the Direct mode, determining the interrupt verification method of the Direct mode as the target interrupt verification method for the interrupt signal to be measured; When the parent interrupt control mode is the CLINT mode and the sub - interrupt control mode is not the Direct mode, determining the interrupt verification method of the vector mode as the target interrupt verification method for the interrupt signal to be measured.

4. The interruption verification method for C2F according to claim 3, characterized in that The method further includes: When the parent interrupt control mode is the CLIC mode and the sub - interrupt control mode is the hardware vector mode, determining the interrupt verification method of the vector mode as the target interrupt verification method for the interrupt signal to be measured; When the parent interrupt control mode is the CLIC mode and the sub - interrupt control mode is not the hardware vector mode, determining the interrupt verification method of the non - vector mode as the target interrupt verification method for the interrupt signal to be measured.

5. The interruption verification method for C2F according to claim 3, characterized in that, The method further includes: When the comparison result indicates that the first interrupt privilege mode is equal to the second interrupt privilege mode, determining that the interrupt signal to be measured is processed according to a horizontal interrupt; When the parent interrupt control mode is the CLINT mode and the sub - interrupt control mode is the Direct mode, determining the interrupt verification method of the Direct mode as the target interrupt verification method for the interrupt signal to be measured; When the parent interrupt control mode is the CLINT mode and the sub - interrupt control mode is not the Direct mode, determining the interrupt verification method of the vector mode as the target interrupt verification method for the interrupt signal to be measured.

6. The interruption verification method for C2F according to claim 5, characterized in that, The method further includes: When the parent interrupt control mode is the CLIC mode, obtaining a global enable status from the global configuration information and obtaining an interrupt enable status of the interrupt signal to be measured from the interrupt configuration information; When the global enable status and the interrupt enable status are enabled, obtaining a priority threshold from the global configuration information and obtaining an interrupt priority of the interrupt signal to be measured from the interrupt configuration information; Determining the highest target priority among the priority threshold and the current priority of the simulation processor; When the interrupt priority is higher than the target priority and the sub - interrupt control mode is the hardware vector mode, determining the interrupt verification method of the vector mode as the target interrupt verification method for the interrupt signal to be measured.

7. The interruption verification method for C2F according to claim 6, characterized in that The method further includes: When the interrupt priority is higher than the target priority and the sub - interrupt control mode is not the hardware vector mode, determining the interrupt verification method of the non - vector mode as the target interrupt verification method for the interrupt signal to be measured.

8. An interruption verification device for C2F, characterized in that including: A first acquisition unit, configured to acquire test constraint conditions, and generate global configuration information and interruption configuration information of an interruption signal to be measured according to the test constraint conditions; A generation unit, configured to generate a configuration file based on the global configuration information and the interruption configuration information, where the configuration file includes global configuration codes for configuring global registers of a simulation processor and an interruption controller according to the global configuration information, interruption configuration codes for configuring interruption registers corresponding to the interruption signal to be measured according to the interruption configuration information, and program configuration codes of an interruption verification program; A first sending unit, configured to send the configuration file to the simulation processor, so that the simulation processor executes the configuration file to configure global registers of the simulation processor, global registers of the interruption controller, interruption registers corresponding to the interruption signal to be measured in the interruption controller, and an interruption verification program; A second sending unit, configured to send the interruption signal to be measured that conforms to the interruption configuration information to the interruption controller when the simulation processor finishes configuration, so that the interruption controller processes the interruption signal to be measured according to the interruption registers, and sends an interruption request obtained by processing to the simulation processor; A second acquisition unit, configured to acquire an interruption signal identifier and an interruption level when it is detected that an interruption verification program is entered during a process in which the simulation processor responds to the interruption request; A verification unit, configured to determine that verification is passed when the interruption signal identifier and the interruption level conform to the interruption configuration information.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores multiple instructions, and the instructions are suitable for being loaded by a processor to execute the interruption verification method for C2F according to any one of claims 1 to 7.

10. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, the interruption verification method for C2F according to any one of claims 1 to 7 is implemented.

Images