Data buffer management method and equipment

Abstract

The invention discloses a data buffer management method and equipment, and the method comprises the steps: responding to a first writing request, used for writing first buffer data, of a first channel, distributing a first buffer address in a data buffer module for the first buffer data, the first channel is any one of a plurality of channels; writing first buffer data corresponding to the first write-in request into a first buffer address of a data buffer module, and writing the first buffer address into an address buffer module corresponding to the first channel; each channel corresponds to a different address buffer module, and the address buffer module is used for buffering the buffer address of the data of the corresponding channel in the data buffer module.

Description

Technical Field

[0001] This application relates to the field of buffering technology, and particularly relates to a data buffering management method and device. Background Art

[0002] Generally, a buffering module is provided in various electronic devices. During the operation of the electronic device, the buffering module can buffer the data input by the input processing module and the data output by the processing module.

[0003] In the related art, in order to avoid the confusion of data in different channels buffered in the buffering module, generally, multiple buffer areas corresponding to multiple channels are divided in the buffering module, and the data of each channel is buffered in the corresponding buffer area. In this buffering method, it is easy to occur that the buffer space of the buffer areas of some channels is insufficient while the buffer areas of some other channels have redundant buffer space, and the utilization rate of the buffering module is relatively low. Summary of the Invention

[0004] Therefore, the following technical solutions are disclosed in this application:

[0005] In a first aspect of this application, a data buffering management method is provided, including:

[0006] In response to a first write request for writing first buffer data to a first channel, allocate a first buffer address in a data buffering module for the first buffer data, where the data buffering module is used to buffer data of multiple channels, and the first channel is any one of the multiple channels;

[0007] Write the first buffer data corresponding to the first write request to the first buffer address of the data buffering module, and write the first buffer address to the address buffering module corresponding to the first channel;

[0008] Wherein, each of the channels corresponds to a different address buffering module, and the address buffering module is used to buffer the buffer address of the data of the corresponding channel in the data buffering module.

[0009] Optionally, it further includes:

[0010] In response to a first read request of the first channel, obtain a second buffer address corresponding to the first read request from the address buffering module corresponding to the first channel;

[0011] Read the buffer data corresponding to the first read request from the data buffering module according to the second buffer address.

[0012] Optionally, the data buffering module includes a buffer area;

[0013] The amount of buffer data transferred between each channel and the data buffering module in a single transmission is the same;

[0014] The buffered data for a single transmission of a channel is buffered in multiple said buffer areas corresponding to the same buffer address;

[0015] The sum of the buffer space sizes of all buffer areas corresponding to the same buffer address matches the amount of buffered data for the single transmission.

[0016] Optionally, all the buffered data for a single transmission of any channel is simultaneously written into multiple said buffer areas corresponding to the same buffer address within one clock cycle, or simultaneously read out from multiple said buffer areas corresponding to the same buffer address within one clock cycle.

[0017] Optionally, it further includes:

[0018] Determine the amount of buffered data for a single transmission between each channel and the data buffer module according to the number of channels.

[0019] Optionally, it further includes:

[0020] In the case of receiving a write request and a read request simultaneously, perform write and read operations on the data buffer module simultaneously;

[0021] The simultaneous write and read operations include:

[0022] Divide the data buffer module into at least a first buffer unit and a second buffer unit according to the buffer address, and each buffer unit includes buffer areas corresponding to several consecutive addresses;

[0023] In the first clock cycle, write the first part of the buffered data to be written into the buffer area corresponding to the write buffer address in the first buffer unit, and read the second part of the buffered data to be read out from the buffer area corresponding to the read buffer address in the second buffer unit. The buffered data to be written corresponds to the write request, the buffered data to be read out corresponds to the read request, the write buffer address is the buffer address of the buffered data to be written, and the read buffer address is the buffer address of the buffered data to be read out;

[0024] In the second clock cycle, write the second part of the buffered data to be written into the buffer area corresponding to the write buffer address in the second buffer unit, and read the second part of the buffered data to be read out from the buffer area corresponding to the read buffer address in the first buffer unit.

[0025] Optionally, it further includes:

[0026] Divide each said buffer unit into multiple segments, each segment corresponds to a buffer address range, and the working modes between the segments are independent.

[0027] Optionally, the first buffer address in the first buffer data allocation data buffer module includes any of the following:

[0028] Determine the buffer address pointed to by the address counter in the data buffer module as the first buffer address of the first buffer data, and update the address counter so that the address counter points to the next buffer address after the first buffer address. The address counter is used to record the number of buffer addresses of the data stored in the data buffer module;

[0029] Update the address counter, and determine the buffer address pointed to by the updated address counter in the data buffer module as the first buffer address of the first buffer data.

[0030] A second aspect of the present application provides a data buffer management device, including:

[0031] A data buffer module for buffering data of multiple channels;

[0032] An input module, the output end of which is connected to the data buffer module, and is used to write the first buffer data corresponding to the first write request of the first channel into the data buffer module, where the first channel is any one of the multiple channels;

[0033] A control module, connected to the data buffer module and the input module, and is used to respond to the first write request and allocate a first buffer address in the data buffer module for the first buffer data;

[0034] Multiple address buffer modules, connected to the control module and corresponding to the multiple channels one by one, and are used to store the buffer addresses of the buffer data of the corresponding channels in the data buffer module.

[0035] Optionally, the control module is further used for:

[0036] In response to the first read request of the first channel, output the second buffer address corresponding to the first read request from the address buffer module corresponding to the first channel;

[0037] The device further includes:

[0038] An output module, the input end of which is connected to the data buffer module, and is used to read out the second buffer data at the second buffer address in the data buffer module.

[0039] Optionally, the input module includes:

[0040] Multiple first registers, corresponding to the multiple channels one by one, and are used to store the buffer data transmitted between the corresponding channels and the data buffer module;

[0041] A first selector, an input end of the first selector is connected to the multiple first registers, and an output end thereof is connected to the data buffer module, configured to input buffered data of the first register into the data buffer module.

[0042] Optionally, the output module includes:

[0043] A third selector, an input end thereof is connected to the data buffer module, and an output end thereof is connected to multiple second registers;

[0044] Multiple second registers, corresponding to the multiple channels one by one, configured to obtain and store buffered data of corresponding channels on the second buffer address through the third selector. Description of the Drawings

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0046] Figure 1 is a flowchart of a data buffer management method provided by an embodiment of the present application;

[0047] Figure 2 is a schematic structural diagram of a data buffer module provided by an embodiment of the present application;

[0048] Figure 3 is a schematic diagram of the division of a buffer unit and address segmentation provided by an embodiment of the present application;

[0049] Figure 4 is a schematic structural diagram of a data buffer management device provided by an embodiment of the present application;

[0050] Figure 5 is a schematic structural diagram of another data buffer management device provided by an embodiment of the present application;

[0051] Figure 6 is a schematic circuit diagram of a data buffer management device provided by an embodiment of the present application. Detailed Embodiments

[0052] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0053] The buffer module of an electronic device generally needs to buffer data of multiple channels. Exemplarily, in some electronic devices with multiple screens, each screen can correspond to one channel. When the processor transmits the image data to be displayed on each screen obtained by processing to the screen, it can be temporarily stored in the buffer module, and then based on the characteristic that the images are sequentially displayed on the screen in order, it is output from the buffer module to the screen for display.

[0054] In the related art, to avoid confusing the data of different channels, the buffer module is generally divided into multiple relatively independent buffers (buffers) corresponding one by one to multiple channels. When writing the buffer data of one channel, the buffer data of this channel can be temporarily stored in the buffer area of this channel; when reading the buffer data of one channel, it can be read from the buffer area corresponding to this channel.

[0055] In this buffering scheme, the buffer space size of each buffer area is relatively fixed, while the amount of data that needs to be buffered by different channels may change in real time during the operation of the electronic device. Therefore, when buffering data in this way, it is easy to occur that the buffer space of some channels is insufficient while there is redundant space in the buffer areas of other channels.

[0056] For example, during a certain period, the amount of data transmitted between the processor and screen 1 is relatively large. At this time, the amount of data that needs to be written to channel 1 of the buffer module exceeds the buffer space of the buffer area of channel 1, resulting in the data output by the processor not being able to be provided to screen 1 for display in time through the buffer module. At the same time, the amount of data transmitted between the processor and screen 2 is relatively small. At this time, the amount of data that needs to be written to channel 2 of the buffer module is much smaller than the buffer space of the buffer area of channel 2, and there is a large amount of unused free buffer space in the buffer area of channel 2.

[0057] It can be seen from this that in the above method of buffering data, due to the mismatch between the relatively fixed buffer area and the buffer data volume that changes in real time for different channels, it is easy to occur that the buffer space of the buffer module is not fully utilized.

[0058] In view of the above problems, this embodiment provides a data buffering management method. Please refer to Figure 1 , which is the flowchart of this method.

[0059] S101, In response to a first write request for writing first buffer data to a first channel, allocate a first buffer address in a data buffer module for the first buffer data. The data buffer module is used to buffer data of multiple channels, and the first channel is any one of the multiple channels.

[0060] The method provided in this embodiment can be executed by a data buffer management device integrating the above data buffer module.

[0061] The data buffer module can be used to buffer data of any number of channels, and the number of channels is not limited. As an example, the data buffer module in this embodiment can buffer data of 4 different channels.

[0062] One channel can correspond to a component or module of an electronic device to which the data buffer module belongs. The data of the channel can include data that needs to be transmitted when the corresponding component or module interacts with other components or modules of the electronic device.

[0063] The type of the electronic device to which the data buffer module belongs is not limited. For example, it can be a computer, a tablet device, a smart phone, etc. The components or modules of the electronic device can refer to the components or modules integrated on the electronic device body, or can refer to the components or modules communicatively connected to the electronic device.

[0064] As an example, the data buffer module can be used to buffer data of 4 channels, which are sequentially denoted as channel 1, channel 2, channel 3, and channel 4. Each channel corresponds to a screen of the computer to which the data buffer module belongs.

[0065] The data buffer management device can be deployed at the display interface end of the computer to buffer the data transmitted by the processor (central processing unit CPU and / or graphics processing unit GPU) of the computer to the screen. The buffer data corresponding to one channel can be the data transmitted by the processor to the screen corresponding to the channel. For example, the buffer data corresponding to channel 1 is the data transmitted by the processor to screen 1 corresponding to channel 1.

[0066] The first write request corresponding to the first channel can be output to the data buffer management device by a component or module that needs to write data to the data buffer module corresponding to the first channel. Combining the above example, the first write request can be output to the data buffer management device by the processor that needs to transmit data to screen 1.

[0067] The first write request corresponding to the first channel can also be generated by the data buffer management device in response to obtaining the first buffer data, that is, the data buffer management device only receives the first buffer data corresponding to the first channel, and in response to obtaining the first buffer data, generates a first write request.

[0068] The buffered data and write requests of different channels can be transmitted to the data buffer management device through different links. Based on the link through which the buffered data and write requests are obtained, the data buffer management device can distinguish which channel the buffered data and write requests belong to.

[0069] The order in which the data buffer management device obtains the first write request and the corresponding first buffered data is not limited. It can obtain the data first and then the request, or obtain the request first and then the data, or obtain them simultaneously.

[0070] The first buffered data refers to the data that the first write request requests to be written into the data buffer module.

[0071] The data buffer module in this embodiment can be any type of data memory. As an example, it can be a Static Random-Access Memory (SRAM).

[0072] The data buffer module includes multiple buffer addresses. The first buffer address assigned to the first buffered data can be any one of the multiple buffer addresses, and the policy for assigning buffer addresses is not limited.

[0073] S102, write the first buffered data corresponding to the first write request into the first buffer address of the data buffer module, and write the first buffer address into the address buffer module corresponding to the first channel; wherein, each channel corresponds to a different address buffer module, and the address buffer module is used to buffer the buffer addresses of the data of the corresponding channel in the data buffer module.

[0074] The data buffer management device can include multiple address buffer modules, and each address buffer module corresponds to a unique channel.

[0075] Combined with the foregoing example, the data buffer management device can have 4 address buffer modules, including address buffer module 1 corresponding to channel 1, address buffer module 2 corresponding to channel 2, address buffer module 3 corresponding to channel 3, and address buffer module 4 corresponding to channel 4. Each address buffer module is only used to buffer the buffer addresses of the data of its corresponding channel in the data buffer module.

[0076] The address buffer module can be SRAM or other types of memories.

[0077] The buffer space size of an address buffer module can be determined based on the number of buffer addresses included in the data buffer module. Optionally, the buffer space size of an address buffer module can be configured to be slightly larger than the buffer space size required to store all the buffer addresses in the data buffer module.

[0078] As an example, assume that the data buffer module includes 1152 buffer addresses. In the case where each buffer address corresponds to only 1 bit of space in the data buffer module, the value range of one buffer address can be from 0 to 1151. To represent this value range, one buffer address requires 11 bits of space, and at most 1152 buffer addresses need to be stored. Therefore, the buffer space size of an address buffer module can be configured to be slightly larger than 1152 * 11 bits, for example, configured to 1152 * 11 * 1.5 bits. In other words, the buffer space size of an address buffer module can be configured to be about 19 kilobits.

[0079] In other embodiments, one buffer address can also correspond to multiple bits of space in the data buffer module, not limited to 1 bit in the above example. For example, each buffer address can correspond to 5 bits of space in the data buffer module, or can correspond to 12 bits of space in the data buffer module, without limitation. When one buffer address corresponds to multiple bits, the value range of one buffer address can be greater than 1151.

[0080] Writing the first buffer data and writing the first buffer address can be performed simultaneously or sequentially, and the order is not limited. For example, in S102, different modules of the data buffer management device can perform the writing actions simultaneously. One module is responsible for writing the first buffer data to the first buffer address of the data buffer module, and another module is responsible for writing the first buffer address to the address buffer module corresponding to the first channel.

[0081] The beneficial effects of this embodiment are as follows:

[0082] On the one hand, based on the above management method, the buffer data obtained from any channel can be written to any buffer address of the data buffer module, without restricting that it can only be written to a specific buffer corresponding to the channel. That is to say, multiple channels corresponding to the data buffer module can share all buffer addresses of the data buffer module. Obviously, there will be no problem that one buffer has redundant buffer space while the buffer space of another buffer is insufficient, significantly improving the utilization rate of the buffer space in the data buffer module;

[0083] On the other hand, when writing the buffer data of one channel, write the buffer address of the buffer data to the address buffer module corresponding to the channel. Thus, the data buffer management device can accurately distinguish and read the buffer data of different channels in the data buffer module based on the buffer addresses recorded in the address buffer modules of different channels, and there will be no situation of data confusion between different channels;

[0084] In summary, the method of this embodiment can improve the utilization rate of the buffer space in the data buffer module on the premise of avoiding data confusion between different channels in the data buffer module.

[0085] Optionally, when obtaining a read request, the management method of this embodiment may also read data from the data buffer module according to the following method:

[0086] In response to a first read request of the first channel, obtain a second buffer address corresponding to the first read request from the address buffer module corresponding to the first channel;

[0087] Read the buffer data corresponding to the first read request from the data buffer module according to the second buffer address.

[0088] The first read request of the first channel may be output to the data buffer management device by a component or module corresponding to the first channel that needs to read data from the data buffer module. Combining the above example, the first read request may be sent from screen 1 corresponding to channel 1 to the data buffer management device.

[0089] Read requests of different channels may be transmitted to the data buffer management device through different links. The data buffer management device can distinguish which channel a read request belongs to according to the link where the read request is obtained.

[0090] The method of obtaining the second buffer address corresponding to the first read request may be:

[0091] Read out the buffer address that was buffered earliest in the address buffer module at the current moment (i.e., the moment when the first read request is obtained) from the address buffer module corresponding to the first channel as the second buffer address corresponding to the first read request.

[0092] As an example, assume that buffer addresses 4, 25, and 80 are stored in address buffer module 1 corresponding to channel 1, where buffer address 4 was stored in address buffer module 1 earliest and buffer address 80 was stored in address buffer module 1 latest;

[0093] When obtaining a read request of channel 1, take out the earliest stored buffer address 4 from address buffer module 1 as the buffer address corresponding to this read request, and read the buffer data stored at buffer address 4 of the data buffer module as the buffer data corresponding to this read request;

[0094] When obtaining another read request of channel 1, at this time buffer address 4 has been taken out, and the earliest stored buffer address in address buffer module 1 is buffer address 25. So take out buffer address 25 as the buffer address corresponding to the second received read request, and read the buffer data stored at buffer address 25 of the data buffer module as the buffer data corresponding to the second received read request.

[0095] After reading the data corresponding to the read request, the read data can be fed back to the component or module that sent the read request. Combining the above example, after receiving the read request from Screen 1, the data buffer management device reads the buffer data corresponding to the read request according to the above method and sends the buffer data to Screen 1.

[0096] In the method of this embodiment, the data buffer management device can receive each read request of any channel, and can read the data according to the above method for each received read request, not limited to the first channel and the first read request as examples above. For example, when receiving a read request from Channel 2, the buffer address corresponding to the read request is obtained from the address buffer module 2 corresponding to Channel 2, and the buffer data of Channel 2 written before is read from the data buffer module according to the buffer address.

[0097] Based on the above reading method, when receiving a read request of any channel, the buffer data of the channel can be accurately read from the data buffer module based on the buffer address recorded by the address buffer module corresponding to the channel, avoiding the situation of reading the wrong data.

[0098] Optionally, if the data buffer management device obtains the buffer data of multiple channels at the same time, the buffer data of each channel can be written successively according to a certain polling strategy. For example, when obtaining the buffer data of Channels 1 to 4 at the same time, the buffer data of Channel 1 can be written first, then the buffer data of Channel 2, then the buffer data of Channel 3, and finally the buffer data of Channel 4. Similarly, if the data buffer management device obtains the read requests of multiple channels at the same time, the buffer data corresponding to the read requests of each channel can be read successively according to a certain polling strategy.

[0099] Optionally, the data buffer module includes a buffer area;

[0100] The amount of buffer data transferred once between each channel and the data buffer module is the same;

[0101] The buffer data transferred once by one channel is buffered in multiple buffer areas corresponding to the same buffer address;

[0102] The sum of the buffer space sizes of all buffer areas corresponding to the same buffer address matches the amount of buffer data transferred once.

[0103] The data buffer module can be composed of multiple buffers, and each buffer can store 1 bit of data, that is, one buffer can store 0 or 1.

[0104] Please refer to Figure 2 , which is the structural schematic diagram of the data buffer module of this embodiment. Figure 2The smallest square in it is equivalent to a buffer. Multiple buffers of the data buffer module can be managed in the form of a matrix. Each column of the matrix can include N buffers, and there are M columns in total. Among them, each column corresponds to a buffer address. For example Figure 2 In Figure 2 , the first column starting from the left corresponds to address 0, the second column corresponds to address 1, and so on. The Mth column corresponds to address M - 1. There are M buffer addresses in total. The N buffers in each column can be divided at a certain interval N0. After division, every N0 buffers in a column are equivalent to a buffer area. A buffer area can buffer N0 bits of data. In a column corresponding to a buffer address, there are N / N0 buffer areas. The data buffer module can be equivalent to an array formed by logically connecting multiple buffers. Each buffer has a certain depth (buffer depth). The size configuration of N0 for each buffer area can be configured according to the physical design rules of the buffer. Generally, N0 can be less than the depth of a single buffer. For example, when the depth is 192, N0 can be equal to 48.

[0105] Exemplarily, N can be equal to 1152 and N0 can be equal to 48. At this time, each column can be divided into 1152÷48, that is, 24 buffer areas. Multiple buffers in the same column correspond to the same buffer address. This buffer address can be characterized by the column number where it is located. That is, the buffer address corresponding to the buffers in the first column on the left can be 0, and the buffer address corresponding to the buffers in the second column on the left can be 1. Representing the buffer address in this way can make each buffer address correspond to only 1 bit of space in the data buffer module, thereby reducing the space required to store the buffer address in the address buffer module.

[0106] The amount of buffered data for a single transmission refers to the amount of buffered data transmitted between a channel and the data buffer module once, and generally can be expressed by the number of bits of buffered data for one transmission.

[0107] The amount of buffered data transmitted between each channel and the data buffer module once is the same. That is to say, for any two channels, the amount of buffered data written by one channel to the data buffer module once is the same as the amount of buffered data written by the other channel to the data buffer module once. And, the amount of buffered data written by any channel to the data buffer module once is the same as the amount of buffered data read by this channel from the data buffer module once.

[0108] In the data buffer module, the total number of buffers in each column can be designed to be equal to the amount of buffered data transmitted between the channel and the data buffer module once. The amount of buffered data can be expressed by the number of bits of buffered data for one transmission. That is, since the amount of buffered data for one transmission is N bits, the total number of buffers in each column of the data buffer module is set to N.

[0109] Based on the above design, the buffering method of the buffered data for a single transmission can be that the buffered data for a single transmission of one channel is buffered in multiple buffer areas corresponding to the same buffer address, that is, in the buffers of multiple buffer areas corresponding to the same buffer address.

[0110] Combined with Figure 2 the example of Figure 2 assuming that the first buffer address is the buffer address 6 shown in Figure 2 the N / N0 buffer areas in the 7th column starting from the left in

[0111] That is, it is buffered in the N buffers in the 7th column. Assuming that the second buffer address determined based on the first read request is buffer address 4, when reading data, it can be read from Figure 2 the N / N0 buffer areas in the 5th column of

[0112] That is, the buffered data that the first channel needs to read this time, which is the buffered data corresponding to the first read request, is read from the N buffers in the 5th column. The sum of the buffer space sizes of all buffer areas corresponding to the same buffer address matches the amount of buffered data for a single transmission. That is to say, in the data buffer module, the amount of data that all buffer areas corresponding to any buffer address can store is equal to the amount of buffered data for a single transmission. Therefore, the buffered data that any channel writes to the data buffer module once can exactly be buffered in all buffer areas corresponding to the allocated buffer address; the buffered data that any channel reads from the data buffer module once according to the buffer address is exactly the buffered data stored on all buffer areas corresponding to this buffer address.

[0113] Combined with Figure 2 the example of

[0114] The advantage of managing the data buffer module in the above way is that:

[0115] After determining a buffer address, all the buffered data for a single transmission can be directly written to all buffer areas corresponding to this buffer address within one clock cycle, or the data can be directly read from all buffer areas corresponding to this buffer address as the buffered data for a single transmission, without the need to determine which buffer areas to write the buffered data to or from which buffer areas to read the data, thereby improving the read and write efficiency of the buffered data.

[0116] Based on the above data buffer module, the data buffer management device can pre-define the mapping relationship between each bit of the buffered data for a single transmission and multiple buffers corresponding to buffer addresses, so as to correctly write or read the buffered data according to this mapping relationship.

[0117] The mapping relationship can be:

[0118] Among the buffers in a column corresponding to the same buffer address, the buffer at the first row of the column corresponds to the lowest bit in the buffered data for a single transmission, and the buffer at the last row of the column corresponds to the highest bit in the buffered data for a single transmission. From the first row to the last row, the bit of the buffer in each row is 1 bit higher than the bit of the buffer corresponding to the previous row.

[0119] Among them, taking Figure 2 as an example, the first row can be the top row of the matrix, and the last row can be the bottom row of the matrix.

[0120] The buffered data for a single transmission refers to the buffered data for a single transmission between a channel and the data buffer module; in combination with the foregoing embodiments, the buffered data for a single transmission can be the data written into the data buffer module at one time, that is, when obtaining a write request corresponding to a channel, the buffered data that needs to be written corresponding to the write request, such as the above first buffered data; it can also be the buffered data read from the data buffer module at one time, that is, when obtaining a read request corresponding to a channel, the buffered data read based on the read request, such as the buffered data corresponding to the above first read request.

[0121] That is to say, writing the first buffered data to the data buffer module according to the first buffer address can include writing the data of the lowest bit in the first buffered data, that is, the data of the 0th bit, into the buffer at the 1st row in a column corresponding to the first buffer address;

[0122] writing the data of the 1st bit in the first buffered data into the buffer at the 2nd row in the column;

[0123] writing the data of the 2nd bit in the first buffered data into the buffer at the 3rd row in the column;

[0124] and so on, until writing the data of the (N - 1)th bit in the first buffered data into the buffer at the Nth row in the column, thereby completing the writing of the first buffered data of N bits.

[0125] Reading the buffered data corresponding to the first read request from the data buffer module according to the second buffer address can include:

[0126] Read 1 bit of data from the buffer at the first row in a column corresponding to the second buffer address as the 0th bit of the buffer data corresponding to the first read request;

[0127] Read 1 bit of data from the buffer at the second row in this column as the 1st bit of the buffer data corresponding to the first read request;

[0128] And so on until 1 bit of data is read from the buffer at the Nth row in this column as the (N - 1)th bit of the buffer data corresponding to the first read request, thus reading N bits of buffer data corresponding to the first read request.

[0129] Based on the above mapping relationship, each bit of the buffer data for a single transmission can be directly written to the corresponding row of a specific buffer address, or can be directly read from the corresponding row of a specific buffer address, without the need for additional organization and sorting, further improving the read and write efficiency.

[0130] Optionally, all the buffer data for a single transmission on any channel is simultaneously written to multiple buffer regions corresponding to the same buffer address within one clock cycle, or is simultaneously read from multiple buffer regions corresponding to the same buffer address within one clock cycle.

[0131] That is to say, each time a write request is obtained, the data buffer management device can, within one clock cycle, write all the buffer data corresponding to this write request to all the buffer regions corresponding to the allocated buffer address; each time a read request is obtained, the data buffer management device can, within one clock cycle, read the buffer data corresponding to this read request from all the buffer regions corresponding to the corresponding buffer address.

[0132] To simultaneously write the buffer data for a single transmission to multiple buffer regions corresponding to the same buffer address within one clock cycle, the data buffer management device may include multiple data writers for writing data to the data buffer module. Each data writer can write buffer data to the buffer region corresponding to this data writer at any buffer address within one clock cycle. Thus, by writing the buffer data in parallel with multiple data writers, the writing of the buffer data for a single transmission can be completed within one clock cycle.

[0133] As an example, assume Figure 2 In the shown data buffer module, there are 24 buffer regions in each column. The 24 buffer regions in each column are sequentially denoted as buffer region 0 to buffer region 23 from top to bottom. Each buffer region can store 48 bits of buffer data. Then the data buffer management device may include 24 data writers for writing data to the data buffer module, sequentially denoted as data writer 0 to data writer 23;

[0134] After allocating the first buffer address, according to the mapping relationship between the bit positions of the buffered data and the buffers corresponding to the buffer addresses in the foregoing embodiments, within the same clock cycle, data writer 0 writes the 48-bit data in the first buffered data that is mapped to buffer area 0 into buffer area 0 of the first buffer address, data writer 1 writes the 48-bit data in the first buffered data that is mapped to buffer area 1 into buffer area 1 of the first buffer address, and so on. Data writer 23 writes the 48-bit data in the first buffered data that is mapped to buffer area 23 into buffer area 23 of the first buffer address. Thus, the 1152-bit first buffered data is all written into the 24 buffer areas corresponding to the first buffer address within one clock cycle.

[0135] In order to read the buffered data of a single transmission from multiple buffer areas corresponding to the same buffer address within one clock cycle, the data buffer management device may include a data reader directly connected to the data buffer module. The data reader may have a certain buffer space, and the size of the buffer space may be the same as the data volume of the buffered data of a single transmission. In this way, after obtaining the buffer address corresponding to the read request, all the buffered data contained in all the buffer areas corresponding to the buffer address can be transmitted to the data reader within one clock cycle, so as to complete the reading of the buffered data of a single transmission within one clock cycle.

[0136] Through the above embodiments, the write or read operation of the buffered data of a single transmission for any channel can be completed within one clock cycle, effectively improving the data read / write efficiency.

[0137] In some alternative embodiments, the data volume of the buffered data of a single transmission may also be determined according to the following method:

[0138] According to the number of channels, determine the data volume of the buffered data of a single transmission between each channel and the data buffer module.

[0139] In the above embodiments, the data transmission bandwidth between the component or module corresponding to a channel and the data buffer management device can be obtained. The data transmission bandwidth can be represented by the data volume that can be transmitted within one clock cycle.

[0140] Then, multiply the data transmission bandwidth between the component or module corresponding to a channel and the data buffer management device by the number of channels used by the data buffer module for buffering, and use the obtained product as the data volume of the buffered data of a single transmission.

[0141] Combined with the foregoing example, the processor can send 288 bits of data to the data buffer management device within one clock cycle, and any screen can receive 288 bits of data from the data buffer management device within one clock cycle. Therefore, the above data transmission bandwidth is 288 bits. Assuming that the data buffer module is used to buffer the buffered data of 4 channels, the amount of buffered data for a single transmission can be determined to be 288 * 4 bits, that is, 1152 bits. When the cumulative amount of buffered data received by the data buffer management device for any one channel reaches 1152 bit, this 1152-bit buffered data can be written into the data buffer module.

[0142] In some cases, the amount of buffered data for a single transmission can also be designed to be greater than the product of the number of channels and the bandwidth, that is, the amount of buffered data for a single transmission should be greater than or equal to the product of the number of channels and the bandwidth. The reason why the amount of buffered data for a single transmission is not less than this product is that if the data volume is less than this product, the amounts of buffered data to be written for multiple channels received by the data buffer management device may reach the data volume for a single transmission simultaneously, resulting in conflicts in the write operations of the buffered data for multiple channels.

[0143] The advantage of determining the amount of buffered data for a single transmission in the above manner is as follows:

[0144] When components or modules corresponding to multiple channels need to write buffered data to the data buffer management device simultaneously, or need to read data from the data buffer management device simultaneously, if the amount of buffered data for a single transmission is determined in the above manner, then the time taken to sequentially transfer the buffered data between the data buffer module and each channel is exactly equal to the time taken to transfer the buffered data between the data buffer management device and the component or module corresponding to one channel. In this way, the read and write efficiency of the data buffer module can be matched with the data transmission rate of the components or modules corresponding to each channel, so as to meet the data read and write requirements of the components or modules corresponding to each channel.

[0145] Combined with the above example, assuming that the data buffer management device obtains the buffered data of 4 channels from the processor simultaneously, then according to the foregoing embodiment, the data buffer management device needs 4 clock cycles to sequentially write the buffered data of 4 channels into the data buffer module, writing the buffered data of one channel per clock cycle. The time taken for the processor to send the buffered data of one channel to the data buffer management device is also 4 clock cycles, and the two are exactly equal. Therefore, starting from the 5th clock cycle, the processor can continuously send the buffered data corresponding to each channel to the data buffer management device, and the data buffer management device can immediately write the buffered data of each channel into the data buffer module after receiving the buffered data of one channel each time, so as to meet the requirement of the processor to write the buffered data of each channel to the data buffer management device.

[0146] The scenario of reading buffered data is similar and will not be elaborated.

[0147] In some embodiments, the allocation method for allocating the first buffer address to the first buffer data may be any of the following:

[0148] Allocation method 1: Determine the buffer address pointed to by the address counter in the data buffer module as the first buffer address of the first buffer data, and update the address counter so that the address counter points to the next buffer address after the first buffer address. The address counter is used to record the number of buffer addresses of the data already stored in the data buffer module.

[0149] The buffer address pointed to by the address counter corresponds to the number it records.

[0150] In allocation method 1, the data buffer management device may include an address counter. When the data buffer management device is started, the address counter may be initialized to 0, indicating that there is no buffer address of the data already stored in the data buffer module. At this time, the address counter points to the first buffer address in the data buffer module, that is, buffer address 0;

[0151] Then, each time a write request is obtained, the buffer address pointed to by the address counter at this time can be determined as the buffer address of the buffer data corresponding to the write request, and then the address counter is incremented by 1, so that the address counter points to the next buffer address in the data buffer module.

[0152] Combined with the above example, after the data buffer management device is started, when the first write request is obtained, buffer address 0 is allocated for the write request, and the corresponding buffer data is written to buffer address 0. Then the address counter is incremented by 1. At this time, the value of the address counter is 1, and it points to buffer address 1 in the data buffer module;

[0153] When the second write request is obtained, based on the address counter, buffer address 1 is allocated for the write request, and the corresponding buffer data is written to buffer address 1. Then the address counter is incremented by 1. At this time, the value of the address counter is 2, and it points to buffer address 2 in the data buffer module.

[0154] Allocation method 2: Update the address counter, and determine the buffer address pointed to by the updated address counter in the data buffer module as the first buffer address of the first buffer data.

[0155] In allocation method 2, after the data buffer management device is started, when the first write request is obtained, the address counter can be initialized to 0, and then the pointed buffer address 0 is allocated to the write request to store the corresponding buffer data;

[0156] After that, for each write request obtained, the address counter can be incremented by 1 based on the current count, and the buffer address pointed to by the incremented address counter is allocated to the write request as the buffer address for the buffered data corresponding to the write request.

[0157] In the above embodiments, the upper limit of the address counter can be equal to the total number of buffer addresses in the data buffer module minus 1. For example, if the data buffer module has 1152 buffer addresses, the upper limit of the address counter can be 1151. Each time the address counter is updated, if the value of the current address counter is less than the upper limit, the update method can be to increment the value of the address counter by 1. If the value of the current address counter is equal to the upper limit, the update method can be to initialize the value of the address counter to 0 so as to continue writing buffered data starting from the first buffer address of the data buffer module.

[0158] In some alternative embodiments, if the data buffer management device receives a write request and a read request simultaneously, data can be transferred between the data buffer module and the corresponding channel according to the following method:

[0159] In the case of receiving a write request and a read request simultaneously, write and read operations are performed on the data buffer module simultaneously;

[0160] Performing write and read operations simultaneously includes:

[0161] According to the buffer addresses, the data buffer module is at least divided into a first buffer unit and a second buffer unit, and each buffer unit includes buffer regions corresponding to several consecutive addresses;

[0162] In the first clock cycle, the first part of the buffered data to be written is written into the buffer region corresponding to the write buffer address in the first buffer unit, and the second part of the buffered data to be read is read from the buffer region corresponding to the read buffer address in the second buffer unit. The buffered data to be written corresponds to the write request, the buffered data to be read corresponds to the read request, the write buffer address is the buffer address of the buffered data to be written, and the read buffer address is the buffer address of the buffered data to be read;

[0163] In the second clock cycle, the second part of the buffered data to be written is written into the buffer region corresponding to the write buffer address in the second buffer unit, and the second part of the buffered data to be read is read from the buffer region corresponding to the read buffer address in the first buffer unit.

[0164] In the above embodiments, the simultaneously received write request and read request can correspond to the same channel or different channels. For example, a write request for channel 1 and a read request for channel 2 can be received simultaneously, or a write request for channel 1 and a read request for channel 1 can be received simultaneously.

[0165] The data buffer module can be divided into multiple buffer units. Each buffer unit includes buffer regions corresponding to several consecutive addresses. The number of buffer units can be the same as the number of buffer regions corresponding to the same buffer address.

[0166] Take Figure 3 as an example. Suppose each buffer address corresponds to 24 buffer regions. Then the data buffer module can be divided into 24 buffer units, denoted as buffer unit 0, buffer unit 1, buffer unit 2, up to buffer unit 23 in sequence. Each buffer unit can include the buffer regions corresponding to all buffer addresses in the data buffer module. For example, buffer unit 0 includes buffer region 0 corresponding to all buffer addresses, and buffer unit 1 includes buffer region 1 corresponding to all buffer addresses.

[0167] In the case of dividing buffer units, the aforementioned data writer can correspond to the buffer unit to which the buffer region belongs. For example, data writer 0 corresponds to buffer unit 0, data writer 1 corresponds to buffer unit 1, and so on. Each data writer is used to write data to the buffer region of the corresponding buffer unit.

[0168] When the number of buffer units is greater than 2, half of them can be used as the first buffer unit and the other half as the second buffer unit. For example Figure 3 in it, buffer units 0 to 11 can be used as the first buffer unit, and buffer units 12 to 23 can be used as the second buffer unit.

[0169] Due to the characteristics of the data buffer module, within one clock cycle, only a write operation or a read operation can be performed on one buffer unit. Taking buffer unit 0 as an example, within one clock cycle, either read buffer data from a certain buffer region of buffer unit 0 or write buffer data to another buffer region of buffer unit 0. It is not possible to both read buffer data from buffer unit 0 and write buffer data to buffer unit 0.

[0170] In response to the above characteristics, the data buffer management device can perform read operations and write operations on the first buffer unit and the second buffer unit respectively within each clock cycle, so that within the first clock cycle and the second clock cycle, a part of the buffer data to be read and the buffer data to be written are both read and written, thus realizing simultaneous write and read operations.

[0171] The following combines Figure 3 with relevant examples to illustrate the above write and read methods.

[0172] The data buffer management device simultaneously obtains the write request 1 of channel 1 and the read request 2 of channel 2. The buffer data to be written corresponding to the write request 1 is buffer data 1, and the buffer data to be read corresponding to the read request 2 stored in the data buffer module is denoted as buffer data 2. The write buffer address is buffer address 20, and the read buffer address is buffer address 10. Figure 3 Among them, buffer units 0 to 11 are used as the first buffer units, and buffer units 12 to 23 are used as the second buffer units. Both buffer data 1 and buffer data 2 are 1152-bit data.

[0173] According to the mapping relationship configured in the foregoing embodiment, among the 1152-bit buffer data transmitted once, the 576-bit data at the lower bits is located in the buffer area of the first buffer unit, and the 576-bit data at the higher bits is located in the buffer area of the second buffer unit.

[0174] Therefore, in the first clock cycle after the data buffer management device obtains the write request 1 and the read request 2, the 576-bit data at the lower bits in buffer data 1, that is, the data from bit 0 to bit 575, is used as the first part of buffer data 1 and written into the buffer area corresponding to buffer address 20 in the first buffer unit; at the same time, the 576-bit data at the higher bits in buffer data 2, that is, the data from bit 576 to bit 1151, is read out as the second part of buffer data 2 from the buffer area corresponding to buffer address 10 in the second buffer unit;

[0175] Then, in the second clock cycle, the 576-bit data at the higher bits in buffer data 1, that is, the data from bit 576 to bit 1151, is used as the second part of buffer data 1 and written into the buffer area corresponding to buffer address 20 in the second buffer unit; at the same time, the 576-bit data at the lower bits in buffer data 2, that is, the data from bit 0 to bit 575, is read out as the first part of buffer data 2 from the buffer area corresponding to buffer address 10 in the first buffer unit.

[0176] The advantage of performing writing and reading simultaneously in the above manner is as follows:

[0177] On the one hand, when the write request and the read request are obtained simultaneously, a part of the data can be written and a part of the data can be read in the first clock cycle, without waiting until the second clock cycle to start writing data or start reading data;

[0178] On the other hand, since the amount of data that can be transferred in one clock cycle between the data buffer management device and the components or modules corresponding to each channel is less than the amount of buffered data transferred in a single transmission between the internal channels and the data buffer module of the data buffer management device, even though the above method reduces the time for a single write of buffered data and a single read of buffered data, it will not affect the time for transferring data between the data buffer management device and the components or modules corresponding to each channel. Instead, it can start transferring data between the data buffer management device and the components or modules corresponding to each channel earlier, thus completing the transfer earlier.

[0179] Combined with the above example, assume that the data buffer management device and Screen 2 can only transfer 288 bits of data in one clock cycle. If the first clock cycle is only used to write buffered data 1, and buffered data 2 waits until the second clock cycle to be read, and the read buffered data 2 still needs 4 clock cycles to be sent to Screen 2, then Screen 2 that requires buffered data 2 can start obtaining the complete buffered data 2 in 4 clock cycles at the earliest from the third clock cycle, that is, it can receive the complete buffered data 2 at the earliest at the end of the sixth clock cycle.

[0180] However, through the above method, at the end of the first clock cycle, the data buffer management device reads the second part of buffered data 2. Therefore, the second part of buffered data 2 can be sent to Screen 2 in the second and third clock cycles. At the beginning of the fourth clock cycle, since the first part of buffered data 2 has been read in the second clock cycle, the first part of buffered data 2 can be directly sent to Screen 2 in the fourth and fifth clock cycles. Thus, Screen 2 can obtain the complete buffered data 2 at the end of the fifth clock cycle. It can be seen that through the above method, the components or modules corresponding to the channels can obtain data from the data buffer management device faster or write data to the data buffer management device faster.

[0181] Optionally, the method of this embodiment may further include:

[0182] Each buffer unit is divided into multiple segments, each segment corresponding to a buffer address range, and the working modes between the segments are independent.

[0183] The number of segments of each buffer unit can be set as required, without limitation. Each buffer address range can correspond to multiple segments of different buffer units, so as to Figure 3 For example, 1152 buffer addresses can be divided into 6 equal-length buffer address ranges, and each buffer unit is divided into 6 address segments according to these buffer address ranges. For example, buffer unit 0 is divided into address segment 0a, address segment 0b, address segment 0c, address segment 0d, address segment 0e, and address segment 0f.

[0184] Address segments 0a to 23a all correspond to buffer address range a;

[0185] Address segments 0b to 23b all correspond to buffer address range b;

[0186] Address segments 0c to 23c all correspond to buffer address range c;

[0187] Address segments 0d to 23d all correspond to buffer address range d;

[0188] Address segments 0e to 23e all correspond to buffer address range e;

[0189] Address segments 0f to 23f all correspond to buffer address range f.

[0190] For segments corresponding to different buffer address ranges, their working modes are independent of each other, that is, both parties can be in the same working mode or different working modes, and the working modes of segments corresponding to the same buffer address range always remain the same. For example, the working modes can include a first mode and a second mode. Address segments 0a to 23a are either all in the first mode or all in the second mode. However, when address segments 0a to 23a are in the first mode, address segments 0b to 23b can be in the first mode or the second mode.

[0191] The first mode can be a mode with lower power consumption, and the second mode can be a mode with higher power consumption. For example, the first mode can be a mode in which all buffer areas in the corresponding address segment are powered off, and the second mode can be a mode in which all buffer areas in the corresponding address segment are powered on; or the first mode can be a mode in which all buffer areas in the corresponding address segment are in the sleep state, and the second mode can be a mode in which all buffer areas in the corresponding address segment are activated.

[0192] Based on the above management method, the data buffer management device can determine the unused address segments in the data buffer module as the target address segments, set the target address segments to the first mode, and keep the non-target address segments in the second mode.

[0193] The unused address segment can be understood as that all buffer addresses in this address segment do not store buffer data.

[0194] The method for determining the unused address segments can be to determine the total number of buffer data currently stored in the data buffer module, and determine the address segments whose included buffer addresses are all greater than the total number of buffer data as the unused address segments.

[0195] Exemplarily, assume that the data buffer module has 1152 buffer addresses, and currently, a total of 350 buffer data are stored in the data buffer module. It can be determined that the buffer addresses from buffer address 384 to buffer address 575 included in buffer address range c are all greater than 350, and the buffer addresses in other buffer address ranges d, e, and f are all greater than the buffer addresses in buffer address range c. Therefore, the buffer addresses corresponding to the above ranges can be segmented, that is, address segments 0c to 23c, address segments 0d to 23d, address segments 0e to 23e, and address segments 0f to 23f are all determined as unused address segments.

[0196] Based on the above method, it is possible to conveniently control the switching of address segments corresponding to the same buffer address range in multiple buffer units between working modes with different power consumptions, which can not only reduce the power consumption of the data buffer module but also meet the data reading and writing requirements.

[0197] The embodiment of the present application further provides a data buffer management device. Please refer to Figure 4 for the structural schematic diagram of the electronic device. The electronic device may include the following modules:

[0198] A data buffer module 401, which is used to buffer data of multiple channels;

[0199] An input module 402, the output end of the input module 402 is connected to the data buffer module 401, and is used to write the first buffer data corresponding to the first write request of the first channel into the data buffer module 401, where the first channel is any one of the multiple channels;

[0200] A control module 403, connected to the data buffer module 401 and the input module 402, and is used to respond to the first write request and allocate a first buffer address in the data buffer module 401 for the first buffer data;

[0201] Multiple address buffer modules, connected to the control module 403 and corresponding to the multiple channels one by one, and are used to store the buffer addresses of the buffer data of the corresponding channels in the data buffer module 401.

[0202] As an example, assume that the data buffer module 401 is used to buffer data of 4 channels. Then, the above multiple address buffer modules may include an address buffer module 4041 corresponding to channel 1, an address buffer module 4042 corresponding to channel 2, an address buffer module 4043 corresponding to channel 3, and an address buffer module 4044 corresponding to channel 4.

[0203] In some optional embodiments, please refer to Figure 5 for the control module 403 may also be used for:

[0204] In response to a first read request of a first channel, a second buffer address corresponding to the first read request is output from an address buffer module corresponding to the first channel;

[0205] The above data buffer management device may further include:

[0206] An output module 501, with its input end connected to the data buffer module 401, is configured to obtain the second buffer address output by the control module 403 and read out the second buffer data at the second buffer address in the data buffer module 401.

[0207] In some alternative embodiments, the above data buffer management device can be implemented with Figure 6 the circuit structure shown.

[0208] In Figure 6 the circuit structure shown, the input module 402 may include:

[0209] Multiple first registers, corresponding to multiple channels one by one, are configured to store buffer data transmitted between the corresponding channels and the data buffer module;

[0210] A first selector 602, with its input end connected to the multiple first registers and its output end connected to the data buffer module, is configured to input the buffer data of the first registers into the data buffer module.

[0211] The number of the first selectors 602 may be multiple, and its number may be the same as the number of buffer areas corresponding to the same buffer address in the data buffer module 401. For example, if there are 24 buffer areas corresponding to the same buffer address, then there may be 24 first selectors 602. The first selector 602 in this embodiment may be equivalent to the data writer in the foregoing embodiment.

[0212] As some examples, in the case of 4 channels, the multiple first registers may include Figure 6 the first registers 6011, 6012, 6013, and 6014 shown, corresponding to channel 1, channel 2, channel 3, and channel 4 in sequence.

[0213] Further, in Figure 6 the circuit structure shown, the control module 403 may include a counter 603, a fourth selector 604, and an arbiter 605 therein. The counter 603 is configured to allocate buffer addresses, the fourth selector 604 is configured to write the allocated buffer addresses into the corresponding address buffer module, and the arbiter 605 is configured to perform polling when buffer data of multiple channels are obtained simultaneously. The fourth selector 604 may be connected to the arbiter 605.

[0214] Next, based on Figure 6The circuit structure is used to illustrate the working principle of the data buffer management device in this embodiment with examples.

[0215] The processor transfers the first buffered data of Channel 1 to the first register 6011 in 4 clock cycles. After the obtained first buffered data reaches the buffered data volume of a single transfer, the first register 6011 generates a first write request corresponding to Channel 1 and outputs it to the arbiter 605.

[0216] If the arbiter 605 obtains multiple write requests simultaneously at this time, or obtains a write request and a read request simultaneously, the arbiter 605 can decide whether to write the first buffered data in the current clock cycle or in other subsequent clock cycles according to a certain polling strategy. If the arbiter 605 only receives the first write request, it is determined that the first buffered data is written in the current clock cycle.

[0217] Generally, since the moments when the buffered data volumes received by each channel reach the buffered data volume of a single transfer are different, and the moments when the first registers corresponding to each channel are full are different, the arbiter 605 can control the first selector 602 in chronological order, so as to select the first registers of different channels in chronological order and write the buffered data in different first registers into the data buffer module.

[0218] Assume that it is determined to write the first buffered data in the current clock cycle. Then the arbiter 605 outputs a control signal corresponding to the first buffered data to the first selector 602. This control signal is used to control the first selector 602 to select the first register 6011 corresponding to Channel 1. The first selector 602 responds to the received control signal and sends a trigger signal to the counter 603. The trigger signal is used to trigger the counter 603 to allocate a buffer address. The counter 603 responds to this trigger signal and allocates the first buffer address corresponding to the first buffered data according to the aforementioned allocation method 1 or allocation method 2.

[0219] The control signal received by the first selector 602 may include the identifier of Channel 1.

[0220] The first buffer address allocated by the counter 603 is transmitted to the data buffer module 401 on the one hand, so that 24 buffer areas corresponding to the first buffer address in the data buffer module 401 are in a writable state. The first selector 602 writes 1152-bit first buffered data from the first register 6011 into 24 buffer areas corresponding to the first buffer address, and each buffer area stores 48-bit data therein.

[0221] On the other hand, the first buffer address allocated by the counter 603 can be transmitted to the fourth selector 604. Under the control of the arbiter 605, the fourth selector 604 can strobe the address buffer module 4041 corresponding to Channel 1, and then write the received first buffer address into the address buffer module 4041 corresponding to Channel 1. Thus, the process of writing the first buffer data into the data buffer module ends.

[0222] In some other embodiments, the arbiter 605 can also send the identifier of Channel 1 to the counter 603. In response to the received identifier, the counter 603 allocates the first buffer address corresponding to the first buffer data according to the aforementioned allocation method 1 or allocation method 2.

[0223] On the one hand, the first buffer address is transmitted to the data buffer module 401, so that the first selector 602 writes 1152-bit first buffer data from the first register 6011 into 24 buffer areas corresponding to the first buffer address in the aforementioned manner.

[0224] On the other hand, the first buffer address and the identifier of Channel 1 are transmitted by the counter 603 to the fourth selector 604 together. Based on the identifier of Channel 1, the fourth selector 604 writes the received first buffer address into the address buffer module 4041 corresponding to Channel 1. Thus, the process of writing the first buffer data into the data buffer module ends.

[0225] The writing methods of the buffer data of Channel 2 to Channel 4 are the same, and the writing methods of the first buffer data in other clock cycles are the same, which will not be elaborated here.

[0226] Optionally, each first register can have two storage areas, and the storage space size of each storage area can be equal to the amount of buffer data transmitted each time. In this way, when the buffer data sent by the component or module corresponding to a channel (such as the aforementioned processor) fills one of the storage areas, the data buffer management device can write the buffer data in this storage area into the data buffer module, and at the same time, the component or module corresponding to a channel can continue to send the next buffer data to be written to the other storage area. In this way, the data transmission between the first register and the data buffer module, and the data transmission between the first register and the component or module corresponding to the channel can be carried out simultaneously, improving the transmission efficiency.

[0227] In Figure 6 the circuit structure shown, the output module 501 may include:

[0228] A third selector 607, with an input end connected to the data buffer module and an output end connected to multiple second registers;

[0229] A plurality of second registers, corresponding to the plurality of channels one by one, are configured to obtain and store the buffer data corresponding to the channels at the second buffer address of the data buffer module through a third selector.

[0230] As some examples, in the case of having 4 channels, the plurality of second registers may include Figure 6 the second register 6081, the second register 6082, the second register 6083, and the second register 6084 shown in the figure, corresponding to channel 1, channel 2, channel 3, and channel 4 in sequence.

[0231] Optionally, the output module 501 may further include a third register 610, which is located between the third selector 607 and the data buffer module.

[0232] Optionally, the control module 403 may include a second selector 606, with its input end connected to a plurality of address buffer modules, its output end connected to the data buffer module, and a control end connected to the arbiter 605, configured to output the buffer address corresponding to the read request to the data buffer module 401 from the address buffer module corresponding to the channel that currently needs to read buffer data according to the output of the arbiter 605.

[0233] Optionally, the control module 403 may further include a buffer queue 609, which is located between the third selector 607 and the arbiter 605. The buffer queue 609 may be a first-in-first-out (FIFO) buffer queue.

[0234] Next, based on Figure 6 the circuit structure, the working principle of the data buffer management device of this embodiment will be described in combination with examples.

[0235] The arbiter 605 obtains a first read request for channel 2. If the arbiter 605 obtains multiple read requests simultaneously at this time, or obtains a write request and a read request simultaneously, then the arbiter 605 may decide whether to read the second buffer data in the current clock cycle or in other subsequent clock cycles according to a certain polling strategy. If the arbiter 605 only receives the first read request, it is determined to read the second buffer data in the current clock cycle. The second buffer data refers to the buffer data to be read corresponding to the first read request.

[0236] Assume that it is determined to read the second buffer data in the current clock cycle. Then the arbiter 605 outputs the identifier of channel 2 corresponding to the first read request to the second selector 606, and outputs the identifier of channel 2 to the buffer queue 609.

[0237] On the one hand, the second selector 606 is connected to the address buffer module 4042 corresponding to channel 2 based on the identification of channel 2, so the address buffer module 4042 outputs the earliest written buffer address among at least one buffer address stored in itself to the second selector 606, and the second selector 606 outputs the buffer address to the data buffer module 401, and then the data buffer module 401 outputs the 1152-bit buffer data buffered in the 24 buffer areas corresponding to the buffer address. In this process, the buffer address output by the address buffer module 4042 is equivalent to the second buffer address corresponding to the first read request, and the 1152-bit buffer data output by the data buffer module 401 is equivalent to the second buffer data.

[0238] On the other hand, the buffer queue 609 outputs the identification of channel 2 to the third selector 607. The third selector 607 responds to the identification of channel 2 and connects to the second register 6082 corresponding to channel 2. Therefore, the second buffer data output by the data buffer module 401 reaches the second register 6082 via the third register 610 and the third selector 607 in the current clock cycle. At this point, the process of reading the second buffer data from the data buffer module 401 ends. The second register 6082 can then send the second buffer data to the screen 2 corresponding to channel 2 in 4 clock cycles.

[0239] In some optional embodiments, the third register 610 and the buffer queue 609 may be omitted, the identifier of channel 2 is directly transmitted to the third selector 607 , and the second buffered data is directly output by the data buffer module 401 to the third selector 607 .

[0240] Optionally, each second register may have two storage areas, and the storage space size of each storage area may be equal to the amount of buffered data transmitted in a single time. Thus, when the buffered data read out from the data buffer module at a single time fills up one of the storage areas, the data buffer management device may send the buffered data in the storage area to the component or module corresponding to the channel (such as the aforementioned screen), and at the same time, the data buffer management device may continue to write the buffered data read by the channel next time into another storage area of ​​the second register. In this way, the data transmission between the second register and the data buffer module, and the data transmission between the second register and the component or module corresponding to the channel can be carried out simultaneously, thereby improving the transmission efficiency.

[0241] Optionally, the third register may also have two storage areas, and the storage space size of each storage area may be equal to the amount of buffered data for a single transmission. Its function is similar to that of the second register and will not be described in detail.

[0242] Optionally, if the arbitrator obtains the first write request and the first read request at the same time, the data buffer management device may perform the read and write operations simultaneously in the following manner:

[0243] In the first clock cycle after simultaneously obtaining the first write request and the first read request, the arbiter 605 outputs the identification of channel 1 to the first selectors 602 corresponding to the buffer area of ​​the first buffer unit, for example, to the first selectors 602 corresponding to buffer units 0 to 11. These first selectors 602 output the identification of channel 1 to the counter 603, and after the counter 603 allocates the first buffer address, the lower 576 bits of the first buffer data are written as the first part into the buffer area corresponding to the first buffer address in buffer units 0 to 11, and the first buffer address is stored in the address buffer module 4041 in the aforementioned manner;

[0244] At the same time, in the first clock cycle, the arbiter 605 outputs the identification of channel 2 to the second selector 606 and the buffer queue 609, the buffer queue 609 outputs the identification of channel 2 to the third selector 607, the second selector 606 outputs the second buffer address to the second buffer unit of the data buffer module, for example, to the buffer unit 12 to the buffer unit 23, so that the buffer unit 12 to the buffer unit 23 output the higher 576 bits of data in the buffer area corresponding to the second buffer address as the second part of the second buffer data, and the second part of the second buffer data is transmitted to the second register 6082 via the third register 610 and the third selector 607;

[0245] In the second clock cycle, the arbiter 605 outputs the identification of channel 1 to the first selectors 602 corresponding to the buffer area of ​​the second buffer unit, for example, to the first selectors 602 corresponding to the buffer units 12 to 23. Because the counter 603 has been assigned the first buffer address in the first clock cycle, these first selectors 602 may no longer output the identification of channel 1 to the counter 603 at this time, but directly write the higher-order 576 bits of the first buffer data as the second part into the buffer area corresponding to the first buffer address in the buffer units 12 to 23. At this point, the first buffer data is all written into the data buffer module 401.

[0246] At the same time, in the second clock cycle, the arbiter 605 outputs the identification of channel 2 to the second selector 606 and the buffer queue 609, the buffer queue 609 outputs the identification of channel 2 to the third selector 607, and the second selector 606 outputs the second buffer address to the first buffer unit of the data buffer module, for example, to buffer unit 0 to buffer unit 11, so that buffer unit 0 to buffer unit 11 outputs the lower 576 bits of data in the buffer area corresponding to the second buffer address as the first part of the second buffer data, and the first part of the second buffer data is transmitted to the second register 6082 via the third register 610 and the third selector 607. At this point, the second buffer data is all read from the data buffer module 401 to the second register 6082.

[0247] based on Figure 6 In the circuit structure, the amount of buffered data transmitted in a single time in the aforementioned embodiment can be the amount of buffered data transmitted between a first register and the data buffer module 401 within a clock cycle in the case of only writing, or the amount of buffered data transmitted between a second register and the data buffer module 401 within a clock cycle in the case of only reading.

[0248] The working principle of the above data buffer management device can refer to the relevant steps in the data buffer management method of the above embodiment, which will not be described in detail.

[0249] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0250] For the convenience of description, the above system or device is described as being divided into various modules or units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0251] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0252] Finally, it should also be noted that in this text, relational terms such as first, second, third, and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the said element.

[0253] The above are only the preferred embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A data buffer management method, comprising: In response to a first write request for writing first buffered data from a first channel, allocating a first buffer address in a data buffer module for the first buffered data, the data buffer module being used to buffer data of a plurality of channels, the first channel being any one of the plurality of channels; Writing the first buffer data corresponding to the first write request into a first buffer address of the data buffer module, and writing the first buffer address into an address buffer module corresponding to the first channel; Each of the channels corresponds to a different address buffer module, and the address buffer module is used to buffer the buffer address of the data of the corresponding channel in the data buffer module.

2. The method according to claim 1, further comprising: In response to a first read request of the first channel, acquiring a second buffer address corresponding to the first read request from an address buffer module corresponding to the first channel; The buffer data corresponding to the first read request is read from the data buffer module according to the second buffer address.

3. The method according to claim 1, wherein the data buffer module comprises a buffer area; The amount of buffered data transmitted in a single time between each channel and the data buffer module is the same; The buffered data of a single transmission of a channel is buffered in a plurality of said buffer areas corresponding to the same buffer address; The sum of the buffer space sizes of all buffer areas corresponding to the same buffer address matches the buffer data volume of the single transmission.

4. According to the method of claim 3, all buffered data transmitted in a single transmission by any channel are simultaneously written into the multiple buffer areas corresponding to the same buffer address within one clock cycle, or are simultaneously read out from the multiple buffer areas corresponding to the same buffer address within one clock cycle.

5. The method according to claim 3, further comprising: According to the number of the channels, the amount of buffered data for a single transmission between each channel and the data buffer module is determined.

6. The method according to claim 3, further comprising: When a write request and a read request are received simultaneously, performing write and read operations on the data buffer module simultaneously; The simultaneous writing and reading operations include: According to the buffer address, the data buffer module is divided into at least a first buffer unit and a second buffer unit, each buffer unit includes a plurality of buffer areas corresponding to consecutive addresses; In a first clock cycle, a first part of the buffer data to be written is written into a buffer area corresponding to a write buffer address in the first buffer unit, and a second part of the buffer data to be read is read from a buffer area corresponding to a read buffer address in the second buffer unit, wherein the buffer data to be written corresponds to the write request, and the buffer data to be read corresponds to the read request, the write buffer address is the buffer address of the buffer data to be written, and the read buffer address is the buffer address of the buffer data to be read; In the second clock cycle, the second part of the buffer data to be written is written into the buffer area corresponding to the write buffer address in the second buffer unit, and the second part of the buffer data to be read is read from the buffer area corresponding to the read buffer address in the first buffer unit.

7. The method according to claim 6, further comprising: Each of the buffer units is divided into a plurality of segments, each segment corresponds to a buffer address interval, and the working modes of the segments are independent.

8. The method according to claim 1, wherein allocating a first buffer address in a data buffer module to the first buffer data comprises any one of the following: Determine a buffer address pointed to by an address counter in a data buffer module as a first buffer address of the first buffered data, update the address counter so that the address counter points to a buffer address subsequent to the first buffer address, and the address counter is used to record the number of buffer addresses in which data has been stored in the data buffer module; The address counter is updated, and the buffer address pointed to by the updated address counter in the data buffer module is determined as the first buffer address of the first buffer data.

9. A data buffer management device, comprising: A data buffer module, wherein the data buffer module is used to buffer data of multiple channels; an input module, an output end of which is connected to the data buffer module, and is used to write first buffered data corresponding to a first write request of a first channel into the data buffer module, wherein the first channel is any one of the multiple channels; a control module connected to the data buffer module and the input module, and configured to respond to the first write request and allocate a first buffer address in the data buffer module to the first buffer data; A plurality of address buffer modules are connected to the control module and correspond one-to-one to the plurality of channels, and are used to store the buffer data of the corresponding channels at the buffer addresses of the data buffer modules.

10. The device according to claim 9, wherein the control module is further configured to: In response to a first read request of the first channel, outputting a second buffer address corresponding to the first read request from the address buffer module corresponding to the first channel; The device also includes: The output module has an input end connected to the data buffer module, and is used to obtain the second buffer address output by the control module, and read out the second buffer data at the second buffer address in the data buffer module.

11. The device according to claim 9, wherein the input module comprises: A plurality of first registers, corresponding one to one with the plurality of channels, and used for storing buffer data transmitted between the corresponding channels and the data buffer module; A first selector, wherein an input end of the first selector is connected to the plurality of first registers, and an output end of the first selector is connected to the data buffer module, and is used for inputting the buffered data of the first registers into the data buffer module.

12. The device according to claim 10, wherein the output module comprises: A third selector, an input end of which is connected to the data buffer module, and an output end of which is connected to the plurality of second registers; A plurality of second registers correspond one-to-one to the plurality of channels and are used to obtain and store buffer data of the corresponding channels at the second buffer address through the third selector.

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