Signal transmission method, related equipment and storage medium

Abstract

The invention provides a signal transmission method. The method can be applied to electronic systems such as computer equipment (such as a host) or storage equipment (such as an SSD). The electronic system comprises an electronic device and one or more memories, and the electronic device and the one or more memories are connected through a parallel interface. The electronic equipment can configure different values for parameters adopted by the parallel interface for transmitting signals through different links, so that the power consumption of the parallel interface can be reduced under the condition of ensuring that the SI allowance of the signals in each link meets the requirement. The invention further provides a processing device, related equipment and a computer readable storage medium.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and in particular, to a signal transmission method, related devices, and a storage medium. Background Art

[0002] Currently, high-speed parallel buses are widely used in communication products, computers, and servers. For example, many wireless products, data communication products, etc. use high-speed memories such as solid-state drives (SSD) and double data rate synchronous dynamic random access memories (DDR SDRAM). To ensure communication quality, circuit designs for improving signal integrity (SI), such as on-die termination (ODT), are introduced in the parallel interface. ODT can reduce signal reflection between the transmitter and the receiver to improve signal integrity.

[0003] As the operating frequency and transmission rate of the parallel interface continue to increase, the signal integrity (SI) of the signals in the parallel bus continues to decrease. To ensure that the SI margin meets the requirements, it is necessary to correspondingly reduce the resistance value of the ODT in the parallel interface. However, this will increase the power consumption of the parallel interface, thereby leading to an increase in the heat generation of the chip and a decrease in reliability. Summary of the Invention

[0004] This application provides a signal transmission method, related devices, and a storage medium, which are used to reduce the power consumption of the parallel interface while ensuring that the SI margin of the signals in the parallel bus meets the requirements, thereby helping to avoid an increase in the heat generation of the chip and a decrease in reliability.

[0005] In a first aspect, this application provides a signal transmission method in a communication system. The system includes an electronic device and one or more memories, and the parallel interface of the electronic device is connected to the parallel interfaces of the one or more memories through multiple links. For ease of description, the parallel interface in the electronic device is referred to as the first parallel interface, and the parallel interfaces of the one or more memories are collectively referred to as the second parallel interface. The execution subject of this method can be a processing device. The processing device can be disposed in the electronic device. Optionally, the processing device can be connected to the first parallel interface.

[0006] The processing device may configure one or more parameters respectively adopted by the target interface to transmit signals through at least two of the multiple links. For example, for the first link and the second link among at least two links, the processing device may configure one or more parameters adopted by the target interface to transmit signals through the first link, and configure one or more parameters adopted by the target interface to transmit signals through the second link.

[0007] After that, the processing device may control the first parallel interface to transmit multiplexed signals to the second parallel interface through the at least two links. The target interface includes the first parallel interface and / or the second parallel interface. When the target interface is the first parallel interface, the processing device may control the configured first parallel interface to transmit multiplexed signals to the second parallel interface through the at least two links. When the target interface is the second parallel interface, the processing device may control the first parallel interface to transmit multiplexed signals to the configured second parallel interface through the at least two links. When the target interface includes the first parallel interface and the second parallel interface, the processing device may control the configured first parallel interface to transmit multiplexed signals to the configured second parallel interface through the at least two links.

[0008] Through analysis, it is found that by adjusting the values of the parameters for the parallel interface to transmit signals through the link, the SI of the signals in this link can be changed, and further the SI margin of the signals can be changed. Moreover, the parameter configuration that makes the SI margin larger usually increases the power consumption of the parallel interface. On the contrary, the parameter configuration that makes the SI margin smaller usually can reduce the power consumption of the parallel interface. And when the same value is configured for the parameters adopted by the parallel interface to transmit signals through different links, although the power consumption of the parallel interface to transmit signals through these two links is the same or close, however, due to the differences in aspects such as trace length, impedance consistency, and crosstalk in different links, the SI margins of the signals in different links are generally different. In this application, the link with a larger SI margin is called the link with better routing conditions.

[0009] Based on the above findings, the present application proposes that for the first link and the second link among at least two links and the target parameter among the one or more parameters, the processing device may configure a first value for the target parameter used by the target interface to transmit signals through the first link, and configure a second value for the target parameter used by the target interface to transmit signals through the second link. Since the routing conditions of the first link and the second link are generally different, configuring the same value for the target parameters corresponding to the two will result in the SI margin of the link with better routing conditions being much higher than the required threshold. By configuring different first values and second values for the target parameters corresponding to the two respectively, it is beneficial to reduce the difference between the SI margin of the link with better routing conditions and the threshold, thereby facilitating reducing the power consumption of the target interface when transmitting signals through these two links on the premise that the SI margins of the signals in the first link and the second link both meet the requirements, thus reducing the overall power consumption of the target interface, and being beneficial to avoiding the increase in the heat generation and the decrease in the reliability of the chip.

[0010] Assume that after the processing device configures one or more parameters used by the target interface to transmit signals through a certain link according to the target parameter with a certain value, the SI margin of the signal in this link meets the requirements. The present application refers to this value as an alternative value of the target parameter corresponding to this link. Among the multiple alternative values of the target parameter corresponding to the link, the present application refers to the alternative value that makes the power consumption of the target interface when transmitting signals through this link the smallest as the optimal value of the target parameter corresponding to this link. Optionally, the processing device may determine the optimal value of the target parameter corresponding to each link, and then configure the target parameter used by the target interface to transmit signals through the corresponding link according to the optimal value of the target parameter corresponding to each link. Since the routing conditions of different links are usually different, the values of the target parameters used by the target interface to transmit signals through any two of at least two links after configuration may be different. In this way, it is beneficial to further reduce the overall power consumption of the target interface.

[0011] To reduce the complexity of configuration, optionally, the processing device may determine at least one link group from at least two links. A single link group includes multiple links among at least two links, and different link groups include different links. The processing device may configure the target parameters used by the target interface to transmit signals through each link in the same link group to be the same value. One of the at least one link groups is the first link group including the first link. Correspondingly, in addition to including the first link, the first link group further includes other links other than the first link, and the processing device also configures the target parameters used by the target interface to transmit signals through the other links to be the first value.

[0012] Since the first link group includes a part of the at least two links, for example, the first link group does not include the second link, it is beneficial to divide all or a part of the links other than the link with the worst routing situation (referred to as the worst link) into the first link group. In this way, compared with configuring the same value for the target parameter corresponding to the first link group and the target parameter corresponding to the worst link, it is beneficial to reduce the power consumption of the target interface transmitting signals through the first link group on the premise that the SI margin of the signals in each link within the first link group meets the requirements, thereby reducing the overall power consumption of the target interface, and it is beneficial to avoid the increase in the heat generation and the decrease in the reliability of the chip.

[0013] Based on the above analysis, optionally, the processing device may divide multiple links with similar routing situations into the first link group. In this way, it is beneficial for the SI margin of the signals in each link within the first link group to be close to the required threshold, thereby being beneficial to reducing the power consumption of the target interface transmitting signals through the first link group, and thus reducing the overall power consumption of the target interface, and it is beneficial to avoid the increase in the heat generation and the decrease in the reliability of the chip.

[0014] Signals can be transmitted between the first parallel interface and the second parallel interface through multiple channels. Since the routing situations of the links in the same channel are generally relatively close, optionally, the first link group may include multiple links in the same channel, or rather, the first link group is used to transmit signals in the same channel (data).

[0015] The bit width of a single channel may include multiple bytes. Since the routing situations of the links in the same byte are generally relatively close, optionally, the first link group may include multiple links in the same byte, or rather, the first link group is used to transmit signals in the same byte (data).

[0016] Optionally, before the processing device configures one or more parameters respectively used by the target interface to transmit signals through the first link and the second link, the processing device may obtain the first value of the target parameter corresponding to the first link group from the firmware.

[0017] Optionally, before the processing device configures one or more parameters respectively used by the target interface to transmit signals through the first link and the second link, the processing device controls the target interface to transmit test signals through the first link group respectively using multiple different values of the target parameter, and then determines the first value from the multiple different values according to the signal integrity SI margin of the transmitted multiple test signals. In this way, it is beneficial for the signals transmitted through the first link group by the target interface configured according to the target parameter of the first value to meet the SI margin requirements.

[0018] Suppose there are multiple different values including value 1, value 2, ……, value n. The processing device can control the target interface to transmit a test signal (denoted as test signal 1) through the first link group with the target parameter of value 1, control the target interface to transmit a test signal (denoted as test signal 2) through the first link group with the target parameter of value 2, ……, control the target interface to transmit a test signal (denoted as test signal n) through the first link group with the target parameter of value n, where n is a positive integer greater than 1. Then, the processing device can determine a first value from the multiple different values according to the SI margin 1 of test signal 1, the SI margin 2 of test signal 2, ……, the SI margin n of test signal n.

[0019] Optionally, the processing device can determine one or more values from the multiple different values. The SI margins of the test signals respectively transmitted by the target interface with the target parameters of the one or more values are not lower than the required threshold. Then, among the one or more values, determine the value corresponding to the minimum power consumption as the first value. In this way, it is beneficial to ensure that the SI margins of the signals in each link of the first link group meet the requirements, reduce the power consumption of the target interface for transmitting signals through the first link group, thereby reducing the overall power consumption of the target interface, and helping to avoid the increase in the heat generation and the decrease in the reliability of the chip.

[0020] Optionally, the first value can be the optimal value of the target parameter corresponding to the link with the worst routing situation (referred to as the target link) in the first link group. Correspondingly, the processing device can control the target interface to transmit test signals through the target link respectively with the target parameters of multiple different values, and then determine the first value from the multiple different values according to the signal integrity SI margins of the multiple transmitted test signals.

[0021] This application does not limit the processing device to compare the magnitude relationship of the power consumption of the target interface for transmitting signals with different values of the target parameter. Optionally, since the SI margin can not only be used to determine whether the SI margins of the signals in each link of the first link group meet the requirements, the processing device can evaluate the power consumption of the target interface for transmitting signals according to the SI margins of each test signal. Or, the processing device can determine the power consumption of the target interface for transmitting signals according to a certain value of the target parameter through a table or a formula.

[0022] The present application does not limit the type of the one or more parameters. Optionally, the one or more parameters include at least one of the following parameters: driving ability parameter, transmitter equalization (EQ) parameter, on-die termination (ODT) parameter, and receiver equalization (EQ) parameter. Among them, the receiver equalization (EQ) parameter may include a linear continuous-time equalization (CTLE) parameter and / or a decision feedback equalizer (DFE) parameter. The above parameters can not only affect the SI margin of the signal in the link, but also affect the power consumption of the parallel interface. By differentially configuring the above parameters corresponding to the first link and the second link, it is beneficial to reduce the power consumption of the parallel interface while ensuring the communication quality of the parallel interface.

[0023] Optionally, the multiplexed signals are used to transmit data to be written into the one or more memories. Correspondingly, the processing device may control the first parallel interface to send the multiplexed signals to the second parallel interface through the at least two links. When the target interface is the first parallel interface, the one or more parameters may include transmission parameters (such as ODT parameter and / or transmitter equalization (EQ) parameter). When the target interface is the second parallel interface, the one or more parameters may include reception parameters (such as driving ability parameter and / or receiver equalization (EQ) parameter). When the target interface includes the first parallel interface and the second parallel interface, the one or more parameters may include transmission parameters and reception parameters, and the processing device may configure transmission parameters for the first parallel interface and reception parameters for the second parallel interface.

[0024] Optionally, the multiplexed signals are used to transmit data read from the one or more memories. Correspondingly, the processing device may control the first parallel interface to receive the multiplexed signals from the second parallel interface through the at least two links. When the target interface is the first parallel interface, the one or more parameters may include the above reception parameters. When the target interface is the second parallel interface, the one or more parameters may include the above transmission parameters. When the target interface includes the first parallel interface and the second parallel interface, the one or more parameters may include transmission parameters and reception parameters, and the processing device may configure transmission parameters for the second parallel interface and reception parameters for the first parallel interface.

[0025] In the optional solution introduced above, the processing device may configure one or more parameters adopted by the second parallel interface to transmit signals through the link. The present application does not limit the specific configuration method. For example, the electronic device and the memory may have a master-slave relationship, and the processing device may send a configuration signal to the parallel interface of the memory connected to the link. The configuration signal is used to transmit configuration information, the configuration information is used to determine the values of the one or more parameters, and the configuration signal is used to instruct the memory to configure the one or more parameters adopted by its own parallel interface to transmit signals through the link according to the values indicated by the configuration information.

[0026] Optionally, the one or more memories include non-volatile flash memory (Nand Flash) and / or double data rate synchronous dynamic random access memory (doubledata rate SDRAM, DDR SDRAM). Correspondingly, the first parallel interface and the second parallel interface may be a non-volatile flash memory interface (Nand Flash Interface, NFI) or a DDR SDRAM interface (abbreviated as DDR interface). Among them, "NAND" stands for "NOT AND", representing a NAND gate.

[0027] The present application does not limit the form of the memory. For example, multiple memories may be provided in a dual inline memory module (DIMM), and the DIMM is provided on the motherboard where the electronic device is located through a DIMM connector. Alternatively, the memory may be integrated with the electronic device on the same circuit board.

[0028] The present application does not limit the type of the processing device. For example, the processing device may be a device implemented in hardware. By way of example, the processing device may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. Alternatively, the processing device may be a device implemented in software.

[0029] The present application does not limit the function of the processing device. For example, the processing device may be a storage controller in a storage device, or, in addition to controlling the memory, the processing device may have other more functions, such as the processing device may also have at least one of functions such as a computing function and / or a communication function.

[0030] In a second aspect, the present application provides a processing device, which is applied to an electronic device. The first parallel interface of the electronic device is connected to the second parallel interface of one or more memories through multiple links. The processing device includes a configuration module and a communication module. The configuration module is configured to configure one or more parameters respectively adopted by a target interface to transmit signals through at least two of the multiple links. The target interface includes the first parallel interface and / or the second parallel interface. The at least two links include a first link and a second link. The one or more parameters include a target parameter. Moreover, after configuration, the values of the target parameter respectively adopted by the target interface to transmit signals through the first link and the second link are a first value and a second value. The communication module is configured to control the first parallel interface to transmit multiple signals to the second parallel interface through the at least two links.

[0031] Optionally, the at least two links include a first link group. The first link group includes the first link and other links, and the other links do not include the second link. After configuration, the value of the target parameter adopted by the target interface to transmit signals through the other links is the first value.

[0032] Optionally, the first link group is used to transmit signals in the same channel or signals in the same byte.

[0033] Optionally, the first link and the second link are used to transmit signals in different channels or signals in different bytes of the same channel.

[0034] Optionally, the configuration module is further configured to control the target interface to transmit test signals through the first link group respectively by using the target parameter with multiple different values, and then determine the first value from the multiple different values according to the signal integrity (SI) margin of the multiple transmitted test signals.

[0035] Optionally, the multiple different values include one or more values. The SI margin of the test signals respectively transmitted by the target interface by using the target parameter with the one or more values is not lower than a threshold. The one or more values include the first value. Moreover, among the one or more values, the power consumption of the target interface transmitting signals by using the target parameter with the first value is the smallest.

[0036] Optionally, the one or more parameters include at least one of the following parameters: driving ability parameter, transmitter equalization (EQ) parameter, on-chip termination (ODT) parameter, and receiver equalization (EQ) parameter.

[0037] Optionally, the multiplexed signals are used to transmit data to be written to the one or more memories, or to transmit data read from the one or more memories.

[0038] Optionally, the one or more memories include non-volatile flash memory and / or double data rate synchronous dynamic random access memory (DDR SDRAM).

[0039] Since the processing device provided in the second aspect can be used to execute the method provided in the first aspect, the technical effects that can be obtained by the processing device provided in the second aspect and the specific functions of each module can refer to the corresponding content of the foregoing first aspect, and will not be elaborated herein.

[0040] In a third aspect, the present application provides an electronic device, which includes a processing device and a parallel interface. The processing device is connected to the parallel interface, and the parallel interface is used to connect one or more memories. The processing device is used to execute the method according to the first aspect or any possible implementation manner of the first aspect.

[0041] Optionally, the processing device includes a processor and a memory. The memory stores instructions, and the processor is used to execute the instructions so that the processing device executes the method according to the first aspect or any possible implementation manner of the first aspect.

[0042] Optionally, the processing device includes a logic circuit, and the logic circuit is used to execute the method according to the first aspect or any possible implementation manner of the first aspect.

[0043] Optionally, the processing device is a chip. Optionally, the parallel interface and the processing device can be integrated on the same chip.

[0044] Optionally, the electronic device is a computer device or a storage device.

[0045] In a fourth aspect, the present application provides an electronic system, which includes a processing device and one or more memories. A first parallel interface of the processing device is connected to a second parallel interface of the one or more memories. The processing device is used to execute the method according to the first aspect or any possible implementation manner of the first aspect.

[0046] In a fifth aspect, the present application provides a computer-readable storage medium, including instructions, which, when running on a computer device, cause the computer device to execute the method according to the first aspect or any possible implementation manner of the first aspect.

[0047] In a sixth aspect, an embodiment of the present application further provides a computer program product, which, when running on a computer device, causes the computer device to execute the method described in the first aspect or any possible implementation manner of the first aspect.

[0048] Since each device can be used to execute the method provided in the first aspect, the technical effects that each device can obtain and the technical details for implementing the above method can refer to the corresponding content of the foregoing first aspect, and will not be elaborated here.

[0049] Based on the implementation manners provided in the above aspects of the present application, further combinations can be made to provide more implementation manners. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 Schematically showing an electronic system provided by the present application;

[0051] Figure 2-1 Schematically showing a storage device provided by the present application;

[0052] Figure 2-2 Schematically showing a computer device provided by the present application;

[0053] Figure 3-1 Showing a schematic diagram of the parallel interface of an electronic device connecting the parallel interfaces of multiple memory chips through a single channel;

[0054] Figure 3-2 Showing a schematic diagram of an electronic device connecting to memory chip 1-1;

[0055] Figure 3-3 Showing a schematic diagram of an electronic device connecting to memory chip 1-1 and memory chip 2-1 respectively through the same data bus L0;

[0056] Figure 4 Schematically showing a possible equivalent circuit diagram of a sending module and a receiving module;

[0057] Figure 5 Schematically showing the high-level equivalent circuits, high-level amplitudes, and high-level static power consumptions of three logic levels, namely SSTL / CTT, POD, and LVSTL / TTL;

[0058] Figure 6 Schematically showing the low-level equivalent circuits, low-level amplitudes, and low-level static power consumptions of three logic levels, namely SSTL / CTT, POD, and LVSTL / TTL;

[0059] Figure 7-1 Schematically showing the traces of a partial link between a processor and two DIMMs on a motherboard;

[0060] Figure 7-2Schematically shows the traces of a partial link between the host controller and two flash memory chips in an SSD;

[0061] Figure 8-1 Schematically shows the parameter configurations of the parallel interfaces in the host controller (referred to as the chip for short) and the flash memory chip (referred to as the die for short) in an SSD;

[0062] Figure 8-2 Schematically shows Figure 2-2 the parameter configurations of the parallel interfaces in the processor and the memory chip in;

[0063] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D respectively schematically show the possible processes of the method provided by this application;

[0064] Figure 10 and Figure 11 respectively schematically show the possible values of each parameter in the parallel interface;

[0065] Figure 12 Schematically shows the possible process of parameter training. Detailed implementation manners

[0066] First, the application scenarios of this application are introduced.

[0067] As Figure 1 shown, this application can be applied to any electronic system including an electronic device and one or more memories. The electronic device can be connected to one or more memories through a parallel interface. This application refers to the parallel interface of the electronic device as the first parallel interface and collectively refers to the parallel interfaces of one or more memories as the second parallel interface. Figure 1 Schematically shows Memory 1 and Memory 2. The electronic system can include a greater or lesser number of memories.

[0068] The first parallel interface and the second parallel interface are connected by multiple links. This application does not limit the number of links between the first parallel interface and the second parallel interface. This application refers to two of the multiple links as the first link and the second link respectively. Figure 1 Schematically shows the first link and the second link. This application does not limit the positional relationship between the first link and the second link.

[0069] This application refers to the port on the link used to connect the electronic device as the first port. The first port of the first link and the first port of the second link are connected to different pins of the first parallel interface for transmitting two signals.

[0070] The first parallel interface can be connected to the second parallel interface through multiple links. When the first parallel interface is connected to multiple memories, the second parallel interface can include the parallel interfaces of each memory. The first link and the second link can be connected to the parallel interfaces of the same memory or to the parallel interfaces of different memories.

[0071] In this application, the port used to connect a memory on a link is referred to as the second port. A single link can have one second port or multiple second ports, and different second ports can be used to connect the same memory or different memories.

[0072] This application does not limit the type of memory. The memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced synchronous DRAM. The memory can include not only all current mainstream high-speed memories but also future high-speed memories.

[0073] This application does not limit the type of parallel interface, as long as the two communicating parties communicate using the same parallel interface protocol. The above parallel interface can be a single-ended high-speed parallel bus interface. For example, the parallel interface can be the NFI interface, the SDR interface, the non-volatile double data rate (NV-DDR) interface, the NV-DDR2 interface, or the NV-DDR3 interface mentioned above.

[0074] The present application does not limit the form of the memory. For example, multiple memories can be provided in a dual inline memory module (DIMM), and the DIMM can be provided on the motherboard where the electronic device is located through a DIMM connector. Alternatively, the memory can be integrated on the motherboard where the electronic device is located.

[0075] As Figure 1 shown, the electronic device can include a processing device and a first parallel interface. The present application does not limit the type of the processing device. The processing device can be a device implemented by hardware. For example, the processing device can be a central processing unit (CPU), and the processor can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. Alternatively, the processing device can be a virtual device implemented by software. For example, the processing device can be a virtual device obtained when the processor executes instructions in the memory.

[0076] The present application does not limit the functions of the electronic device. For example, the electronic device is a storage controller, or in addition to controlling the memory, the electronic device can also have other more functions, such as computing functions and / or communication functions, etc.

[0077] The present application does not limit the type of the electronic system. For example, Figure 1 the electronic system shown can be a storage device, and the electronic device can be a storage controller in the storage device. The present application does not limit the type of the storage device. Taking the storage device as a solid-state drive (SSD) as an example, Figure 2-1 schematically shows a schematic diagram of the storage device.

[0078] An SSD is a storage device that mainly uses flash memory (NAND Flash) as the permanent memory. As Figure 2-1As shown, the SSD includes NAND flash memory and a host controller (referred to as the main controller for short). The NAND flash memory includes multiple flash memory chips for storing data. A flash memory chip is a package of one or more dies, and each die may include multiple panels, each panel may include multiple blocks, and each block may include one or more pages. The main controller is the brain center of the SSD and is responsible for some complex tasks such as managing data storage, maintaining the performance and service life of the SSD, etc. The main controller is an embedded microchip that includes a processor, whose function is like a command center, issuing all operation requests of the SSD. For example, the processor can execute functions such as reading / writing data, garbage collection, and wear leveling through the firmware in the buffer.

[0079] As Figure 2-1 shown, the SSD main controller also includes a host interface and a parallel interface. Among them, the host interface is used to communicate with the host. Here, the host can refer to any device such as a server, a personal computer, or an array controller. The parallel interface can have multiple channels. Through the multiple channels of the parallel interface, the main controller can operate multiple flash memory chips in parallel, thereby increasing the underlying bandwidth. Figure 2-1 Schematically shows 2 memory channels or simply channels between the main controller and the NAND flash memory. Through these 2 channels, the main controller can read and write data to 2 flash memory chips in parallel. The main controller can connect to the NAND flash memory through a larger number of channels.

[0080] In addition to the flash memory, the main controller can also be connected to other types of memories, such as Figure 2-1 the memory shown.

[0081] In Figure 2-1 the storage device shown, the main controller and the flash memory chips can be connected through a parallel interface, Figure 2-1 and the parallel interfaces of each flash memory chip are not specifically shown.

[0082] Optionally, Figure 1 the electronic device shown can be understood with reference to the main controller in Figure 2-1 , and Figure 1 the memory shown can be understood with reference to the flash memory chips in Figure 2-1 .

[0083] Or, for example, Figure 1 the electronic system shown can be a computer device, such as a server, a workstation, a smartphone, a personal computer (PC), or a laptop, or a communication device (such as a switch), etc. As Figure 2-2As shown, the computer device may include a motherboard, on which a processor is provided. The processor has two channels, and two DIMMs are provided in each channel. Specifically, the processor is respectively connected to DIMM 0 and DIMM 1 in channel 0 through channel 0, and is respectively connected to DIMM 0 and DIMM 1 in channel 1 through channel 1. A plurality of memory chips (or memory dies) are provided in the DIMM, and the memory chips may be double data rate synchronous dynamic random access memory (DDR SDRAM). A memory rank refers to a group of memory chips that can meet the data bit width requirements of the channel in parallel, and the memory chips in each DIMM can form one or more memory ranks. Figure 2-2 Schematically shows two memory ranks in each DIMM. In practical applications, fewer or more memory ranks can be set in the DIMM according to needs. When a single link has multiple second ports, different second ports can be connected to the memory chips in different memory ranks.

[0084] Figure 2-2 Taking the processor having two channels as an example, in practical applications, the processor may have more or fewer channels. Figure 2-2 Taking two DIMMs being provided in a single channel as an example, in practical applications, more or fewer DIMMs can be set in a single channel.

[0085] In Figure 2-2 the computer device shown, the processor and the memory chips can be connected through a parallel interface, Figure 2-2 and the parallel interface between the processor and the memory chips is not specifically shown.

[0086] Figure 1 The electronic device shown can be understood with reference to Figure 2-2 the processor shown, Figure 1 and the memory shown can be understood with reference to Figure 2-2 the memory chips or DIMMs shown.

[0087] The computer device may include more modules, such as Figure 2-2More processors can also be provided on the motherboard shown. Each processor can be connected to a greater or fewer number of DIMMs. The processor can also be connected to other forms of memories. In the foregoing, the memory chip is taken as an example of a DDR SDRAM chip. The type of the memory chip is not limited in this application. For example, the memory chip can be a single data rate synchronous dynamic random access memory (SDR SDRAM), or a compute express link (CXL) extended memory, or a storage class memory (SCM).

[0088] To ensure the bandwidth performance, as introduced above, the parallel interface can have multiple channels. Taking the NFI interface of a solid-state drive (SSD) as an example, the Hi18XX SSD controller has a total of 17 channels, and each channel has 1 byte. Taking the DDR interface as an example, each channel can have multiple bytes. Taking the DDR interface of the motherboard of a Kunpeng server as an example, the CPU controller has a total of 8 channels, and each channel has a total of 9 bytes. The following introduces the manner in which an electronic device accesses a memory through a single channel.

[0089] Figure 3-1 A schematic diagram showing that the parallel interface of an electronic device is connected to the parallel interfaces of multiple memory chips through a single channel is shown. Figure 3-1 The parallel interfaces are not specifically shown. It is assumed that the channel is Figure 2-2 the channel 0 shown. As Figure 3-1 shown, the channel 0 can include a control link ( Figure 3-1 represented by a dotted line with an arrow) for transmitting control signals and a data link ( Figure 3-1 represented by a solid line with an arrow) for transmitting data signals. The type of the link or transmission line is not limited in this application. For example, the link can be a bus. In the following, the link is taken as an example of a bus.

[0090] The control signal is used to carry control information. The type of the control signal is not limited in this application. For example, the control signal can include at least one of a configuration signal, a command signal, an address signal, and a clock signal. The channel 0 can include multiple control buses. For the simplicity of the drawings, Figure 3-1 a single dotted line is used to represent all the control buses.

[0091] The data signal is used to carry data. A single channel of the parallel interface has a certain bit width, and the bit width of the channel represents the bit width of the data that the parallel interface can transmit in parallel through a single channel. The bit width of a single channel is not limited in this application. Figure 3-1Taking the data bit width of channel 0 as 4 bytes (i.e., 32 bits) as an example, correspondingly, this channel includes at least 32 data buses to transmit 32-bit data in parallel. A byte refers to the bit width of one byte in the parallel bus interface, generally including 8 bits of data from DQ0 to DQ7. For the sake of simplicity of the drawings, Figure 3-1 In channel 0, 4 thick black solid lines are shown, respectively representing the data buses of 4 bytes. The data bus of byte 1 includes 8 data buses for transmitting the first byte of channel 0, the data bus of byte 2 includes 8 data buses for transmitting the second byte in channel 0, the data bus of byte 3 includes 8 data buses for transmitting the third byte in channel 0, and the data bus of byte 4 includes 8 data buses for transmitting the fourth byte in channel 0.

[0092] As introduced above, the processor can be connected to one or more memory blocks through a single channel respectively. Figure 3-1 Taking the example that the electronic device is connected to memory block 1 and memory block 2 through this channel 0 respectively. The present application does not limit the number of memory chips in the memory block. This number is generally related to the data bit width of the channel and the bit width of a single memory chip. The present application does not limit the bit width of a single memory chip. For example, the bit width of a single memory chip can be 4 bits, 8 bits or 16 bits. Assuming that the data bit width of the channel is 32 bits and the bit width of a single memory chip is 8 bits, then, a memory block includes at least 4 memory chips. A memory block can also include more memory chips. For example, for the data integrity of the memory and to recover memory errors, one or more memory chips can also be added to a memory block to store error correction code (ECC). For example, for a DRAM interface, a channel usually includes a bit width of 64 + 8 bits.

[0093] Assume Figure 3-1 The bit width of the shown memory chip 1-1 is 8 bits, and, the memory chip 1-1 is connected to the data bus of byte 1, Figure 3-2 A schematic diagram showing the connection of the electronic device to the memory chip 1-1 is shown. Figure 3-2 Data buses L0 to data bus L7 are schematically shown. Each data bus is used to transmit a data signal of one bit in byte 1. Figure 3-2 A control bus is also schematically shown. More other buses can also be connected between the electronic device and the memory chip. To transmit at least one of other types of signals other than data signals, such as configuration signals, clock signals, instruction signals and address signals.

[0094] Figure 3-2Take the case where the bit width of a single memory chip is equal to one byte. The bit width of a single memory chip can be less than 1 byte. In this case, the data bus connected to the single memory chip can be used to transmit data signals of a part of a single byte. Alternatively, the bit width of a single memory chip can be greater than 1 byte. In this case, the data bus connected to the single memory chip can be used to transmit data signals of multiple bytes.

[0095] Figure 3-2 The possible structures of the electronic device and the memory chip 1-1 are also schematically shown.

[0096] As Figure 3-2 shown, the processing device in the electronic device may include a configuration module and a communication module, and the configuration module and the communication module are respectively connected to the parallel interface. The configuration module can be used to configure the parameters of its own parallel interface and / or the parameters of the parallel interface of the connected memory. The communication module can be used to control the parallel interface to transmit signals through multiple connected links to access the connected memory, such as accessing the storage medium of the memory chip 1-1.

[0097] As Figure 3-2 shown, the memory chip may include a control device, a storage medium, and a parallel interface, and the control device includes a configuration module and a communication module. The configuration module can be used to configure the parameters of its own parallel interface and / or the parameters of the parallel interface of the connected processing device. The communication module can be used to control the parallel interface to transmit signals through multiple connected links to receive the data to be written into the storage medium sent by the electronic device or to send the data read from the storage medium to the electronic device.

[0098] This application does not limit the implementation manners of the modules in the control device. For example, the modules can be implemented in a software or hardware or a combination of software and hardware manner. Figure 3-2 Take the case where the control device and the parallel interface are independently arranged. Optionally, referring to Figure 3-3 , the control device can be integrated in the parallel interface.

[0099] As introduced above, a single link can have multiple second ports, and different second ports can be used to connect different memory chips. The electronic device can connect multiple memory chips through a single link. Assume Figure 3-1 that the memory chip 2-1 in the memory block 2 shown is connected to the same data bus L0 as the memory chip 1-1 in the memory block 1. Figure 3-3 The schematic diagram showing that the electronic device is respectively connected to the memory chip 1-1 and the memory chip 2-1 through the same data bus is shown. As Figure 3-3 shown, the electronic device can be respectively connected to the memory chip 1-1 and the memory chip 2-1 through the data bus L0. The memory chip 1-1 and the memory chip 2-1 can also be respectively connected to more data buses and control buses. For the sake of simplicity of the drawings, Figure 3-3Only a single data bus between the electronic device and the memory chip is schematically shown. Other data buses between the electronic device and the memory chip can be referred to Figure 3-3 .

[0100] The electronic device can also connect multiple memories through the same control bus. For example, different memory chips in the same memory block can be connected to the same control bus to receive the same control signals (such as chip select signals, etc.).

[0101] Input / output (IO) circuits can be set for each connected bus in the parallel interface. The IO circuit can include a transmission module and / or a reception module. The transmission module is used to send electrical signals to the bus, and the reception module is used to receive electrical signals from the bus. Figure 3-3 Schematically shown are the transmission module and the reception module set for the data bus L0 by each parallel interface. The controller can send a signal to L0 through the transmission module, and the memory chip 1-1 or the memory chip 2-1 can receive the signal from the data bus L0 through its own reception module. The memory chip 1-1 or the memory chip 2-1 can send a signal to the data bus L0 through its own transmission module, and the controller can receive the signal from the data bus L0 through its own reception module.

[0102] Since the parallel interface can connect more buses, therefore, Figure 3-3 the shown parallel interface can include more IO circuits.

[0103] Figure 4 Schematically shown is a possible equivalent circuit diagram of the transmission module and the reception module. As Figure 4As shown, the sending module may include a connected sending control unit and a sending unit, and the receiving module may include a connected receiving control unit and a receiving unit. The sending control unit is used to obtain the information to be sent and input a control instruction to the sending unit based on this information. The sending unit is used to input an electrical signal to the connected data bus L0 according to the control instruction. The parallel interface protocol specifies the types of logic levels of the signals transmitted between the two communicating parties, such as stub series terminated logic (SSTL) / center tapped termination (CTT), or pseudo open-drain (POD), or low voltage series terminated logic (LVSTL) / low tapped termination (LTT), etc. The receiving unit can receive the electrical signal from the data bus L0. The receiving control unit can sample the electrical signal received by the receiving unit according to the type of logic level, and make a decision on the sampled voltage (or level) based on the reference voltage (or called the decision level), so as to decode and obtain the information.

[0104] Figure 4 The sending module and the receiving module shown may be respectively arranged in Figure 3-3 the electronic device and a memory chip shown. In this way, the electronic device can write data to the memory. Or, Figure 4 the sending module and the receiving module shown are respectively arranged in Figure 3-3 a memory chip and an electronic device shown. In this way, the electronic device can read data from the memory.

[0105] Figure 3-3 and Figure 4 The IO circuit shown is a possible structure divided according to functions, rather than a limitation on the structure of the IO circuit. For example, the sending control unit of the sending module and the receiving control unit of the receiving module can be integrated into the same control unit (such as an interface control unit). Optionally, this control unit can integrate the sending control units and receiving control units in the IO circuits of each link. The IO circuit may include more units. For example, the IO circuit may further include one or more registers, and the registers can be used to store the parameter configurations of the parallel interface.

[0106] As Figure 4As shown, the transmission control unit can input a control instruction to port Ps based on the data to be transmitted. The control instruction can change the switching states of the PU switch and the PD switch, thereby changing the level of port Pr. The reception control unit can sample the electrical signal of port Pr according to the type of logic level, and make a decision on the sampled voltage (or level) based on a reference voltage (or decision level), thereby decoding the data.

[0107] For example, the transmission control unit turns on the PU switch and turns off the PD switch in the transmission unit, thereby generating a high level at port Pr2. The transmission control unit turns off the PU switch and turns on the PD switch in the transmission unit, thereby generating a low level at port Pr2.

[0108] Figure 4 The shown transmission module and reception module can be used to transmit electrical signals of the SSTL type. Different designs of the parallel interface can be used to generate different types of logic levels. Figure 5 Schematically showing the high-level equivalent circuit, high-level amplitude, and high-level static power consumption of three logic levels, namely SSTL / CTT, POD, and LVSTL / TTL Figure 6 Schematically showing the low-level equivalent circuit, low-level amplitude, and low-level static power consumption of these three logic levels. Refer to Figure 5 and Figure 6 , the transmission control unit can generate a high level at port Pr by controlling the instruction to turn on the branch where Ron_pu is located in the transmission unit and turn off the branch where Ron_pd is located; the transmission control unit can generate a low level at port Pr by controlling the instruction to turn off the branch where Ron_pu is located in the transmission unit and turn on the branch where Ron_pd is located.

[0109] As Figure 3-3 shown, a single data bus can be connected to the IO circuits of multiple memory chips. Correspondingly, the high and low level amplitudes will also be related to the parameters of the IO circuits of more memory chips.

[0110] This application does not limit the specific circuit design of the parallel interface. Figure 4 Only as an example. The ground level in the transmission unit and the reception unit can be replaced with other levels of magnitude. Figure 4 The shown single resistor can be implemented by one or more components. For example, Rodt can be implemented by an ODT circuit. This application does not limit the type of components, as long as the one or more components can be equivalent to a resistor.

[0111] An electronic system can optimize the signal integrity (SI) of signals in a link by adjusting the values of the parameters for transmitting signals through the link via a parallel interface, improve the SI margin of the electrical signals received at the receiving end, so as to ensure that the receiving end can correctly sample the electrical signals in the link.

[0112] The SI margin can include a voltage margin and / or a timing margin. Among them, the voltage margin refers to the extra voltage of the signal beyond the requirements of the high level and low level of the receiver. The timing margin refers to the extra time of the signal beyond the requirements of the setup time and hold time of the receiver.

[0113] For ease of description, this application refers to the parameters used by the parallel interface to transmit signals through the link as the interface parameters corresponding to the link. Since a link can connect multiple parallel interfaces (such as a first parallel interface and a second parallel interface), the interface parameters corresponding to the link can include the parameters of at least one parallel interface connected by the link, for example, including the parameters used by the target interface to transmit signals through the link, where the target interface can include the first parallel interface and / or the second parallel interface. The parameters used by the parallel interface to transmit signals through the link can include one or more parameters. Correspondingly, the interface parameters corresponding to the link can include one or more parameters of the parallel interface.

[0114] This application does not limit the specific types of the above parameters. For example, the parameters can include at least one of multiple parameters such as a driving ability parameter, a transmitter (Tx) equalization (EQ) parameter, an on-die termination (ODT) parameter, and a receiver (Rx) EQ parameter.

[0115] The following introduces each parameter.

[0116] The driving ability parameter can be used to determine the magnitude of the current of the electrical signal transmitted by the transmitting module. Since there are losses during the transmission of the electrical signal in the transmission line, if the driving ability is too small, the receiving end cannot correctly receive the signal. Optionally, the driving ability parameter can be used to indicate the magnitude of the resistance in the transmitting unit, for example, used to indicate Figure 4 Ron_pu and Ron_pd shown. This application does not limit the specific implementation manner and parameter configuration method of Ron. Hereinafter, an example is given where the driving ability parameter is used to indicate the magnitude of the resistance in the transmitting unit. Generally, by reducing the resistance indicated by the driving ability parameter, it is beneficial to increase the current of the electrical signal transmitted by the transmitting module, thereby enhancing the driving ability of the transmitting end, and further being beneficial to improving the SI of the link.

[0117] On-die termination (ODT), also known as on-die termination resistor, can improve signal integrity by reducing signal reflection between the transmitter and the receiver. The equivalent resistance of ODT can refer to Figure 4 the shown Rodt_pu and Rodt_Pd. This application does not limit the specific circuit design and parameter configuration method of ODT. ODT can reduce signal reflection by providing a termination resistor that matches the impedance of the transmission line. ODT parameters can be used to indicate the magnitude of the resistance of ODT, for example Figure 4 the shown Rodt_pu and Rodt_pd. Generally, by reducing the magnitude of the resistance indicated by the ODT parameters, it is beneficial to improve the SI of the link.

[0118] The equalization circuit is used to compensate for the non-ideality of the channel at the transmitter or receiver, eliminate inter-symbol interference, so that the eye diagram of the electrical signal received at the receiver re-opens. Understanding from the frequency domain, equalization compensates for the low-pass characteristic of the channel through a high-pass filter; understanding from the time domain, equalization reshapes the pulse response signal, limits its energy within a time interval, so as to avoid inter-symbol interference.

[0119] The transmission module can be provided with a Tx EQ circuit. The Tx EQ circuit can compensate for the attenuation difference between high and low frequencies through pre-emphasis or de-emphasis. Pre-emphasis is used to keep the low-frequency part of the electrical signal unchanged and boost the high-frequency part of the signal. De-emphasis is used to attenuate the low-frequency part of the signal and keep the high-frequency part unchanged. Both de-emphasis and pre-emphasis are applied at the transmitter end, and the purpose is to balance the high-frequency component and the low-frequency component as much as possible, and reduce the error code caused by the attenuation of the high-frequency component being greater than that of the low-frequency component in the transmission link. The Tx EQ parameter can be a pre-emphasis parameter or a de-emphasis parameter. The pre-emphasis parameter can include the enhancement amplitude and the enhancement time range of the edge where the signal flips. The de-emphasis parameter can include the attenuation amplitude and the attenuation time range of the signal. Generally, by increasing the enhancement amplitude and the time range indicated by the pre-emphasis parameter, it is beneficial to improve the SI of the link. By increasing the amplitude and the time range indicated by the de-emphasis parameter, it is beneficial to improve the SI of the link.

[0120] The receiving module may be provided with a receiving equalization circuit. The parameters of the receiving equalization circuit (i.e., Rx EQ) may include a continuous time linear equalization (CTLE) circuit and / or a decision feedback equalizer (DFE). Taking the CTLE circuit as an example, the CTLE circuit can compensate for the attenuation difference between high and low frequencies by amplifying high-frequency signals in the receiving module or by reducing low-frequency signals. Generally, when a high-speed digital signal is transmitted through a lossy channel, the CTLE circuit is used to enhance the high-frequency components of the signal to compensate for high-frequency channel losses. The CTLE parameters can be used to indicate the frequency range and / or amplification ratio for which the CTLE circuit amplifies the received electrical signal. Usually, by increasing the frequency range and / or amplification ratio indicated by the CTLE parameters, it is beneficial to improve the SI of the link. The DFE processes the error signal through the equalization of the feedback and forward paths to achieve signal recovery and optimization. Generally, the higher the order of the DFE, the better the SI.

[0121] A gear can be used to measure the value of the equalization parameter. Generally, the larger the gear, the larger the amplitude and / or range indicated by the pre-emphasis parameter or de-emphasis parameter.

[0122] The processing device can read a single configuration information 1 (denoted as configuration information 1) from the firmware, and then configure the interface parameters corresponding to each link according to the configuration information 1. Among them, the configuration information 1 is used to indicate the values of one or more parameters of the parallel interface.

[0123] Assume that a single link has a first port and a second port, and the interface parameters corresponding to the link include the parameters of the first parallel interface and the parameters of the second parallel interface. As an example, the configuration information 1 can be write process configuration information, and this configuration information 1 can indicate that the value of Ron of the first parallel interface is SOC_Ron1, and the value of ODT of the second parallel interface is Rodt1; or, the configuration information 1 can be read process configuration information, and this solution can indicate that the value of Ron of the second parallel interface is Ron1, and the value of ODT of the first parallel interface is SOC_Rodt1; or, the configuration information 1 can include the above write process configuration information and read process configuration information. SOC_Ron1 and Ron1 can be the same or different. When the two are the same, the configuration information 1 can indicate the values of the driving ability parameters of the sending end and the receiving end through Ron1. SOC_Rodt1 and Rodt1 can be the same or different. When the two are the same, the configuration information 1 can indicate the values of the ODT parameters of the sending end and the receiving end through Rodt1.

[0124] Assume that a single link has a first port and multiple second ports, and the interface parameters corresponding to the link include the parameters of the first parallel interface and the parameters of the second parallel interface. Taking the memory as a DDR memory as an example, Configuration Information 1 can be write process configuration information. This solution can indicate that the value of Ron of the first parallel interface is SOC_Ron1. The ODT of the second parallel interface includes 3 sub-parameters, which are respectively denoted as rtt_park, rtt_nom, and rtt_wr, and the values of these three sub-parameters are rtt_park1, rtt_nom1, and rtt_wr1 respectively; or, Configuration Information 1 can be read process configuration information. This solution can indicate that Ron of the second parallel interface is Ron1, the values of the three sub-parameters in ODT are rtt_park1 and rtt_nom1 respectively, and the ODT of the first parallel interface is SOC_Rodt1; or, Configuration Information 1 can include the above-mentioned write process configuration information and read process configuration information. As introduced above, SOC_Ron1 and Ron1 can be the same or different. The value of SOC_Rodt1 and any one of the sub-parameters in the ODT of the second parallel interface can be all different, or, the value of SOC_Rodt1 and at least one of the sub-parameters in the ODT of the second parallel interface is the same.

[0125] After the processing device obtains Configuration Information 1, it can configure the interface parameters corresponding to each link according to Configuration Information 1.

[0126] Next, taking the processing device as Figure 2-1 the processor in the SSD shown as an example, assume that the topology type of the SSD is H type, SOC_Ron1 indicated by Configuration Information 1 = 25, SOC_Rodt1 = 75, Ron1 = 37.5, Rodt = 50. Combining Figure 8-1 this, introduce the specific values of the interface parameters corresponding to each link configured by the processor according to Configuration Information 1 before reading or writing data.

[0127] Refer to Figure 8-1, before writing data, for each link, the processor can configure the Ron used by the first parallel interface to send data signals through this link to 25, and configure the Rodt used by the parallel interface of the flash memory chip (abbreviated as die) connected to this link to receive data signals through this link to 50. If a single link has multiple second ports, the second port for receiving data signals can be called the target second port, and the second port not used for receiving data signals can be called the non-target second port. The processor can configure the Rodt used by the parallel interface of the flash memory chip to receive data signals through the target second port to 50, or configure the Rodt used by the parallel interface of the flash memory chip to receive data signals through the non-target second port to 50, or configure the Rodt used by the parallel interface of the flash memory chip to receive data signals through the target second port and the non-target second port to 50 respectively.

[0128] Reference Figure 8-1 , before reading data, for each link, the processor can configure the Ron used by the parallel interface of the flash memory chip to send data signals through this link to 37.5, and configure the Rodt used by the first parallel interface to receive data signals through this link to 75. If a single link has multiple second ports, the second port for sending data signals can be called the target second port, and the second port not used for sending data signals can be called the non-target second port. The processor can configure the Rodt corresponding to the non-target second port in the parallel interface of the flash memory chip to 50, and turn off the Rodt corresponding to the target second port in the second parallel interface.

[0129] The following takes the processing device as Figure 2-2 the processor shown as an example. Assume that SOC_Ron1 = 34, SOC_Rodt1 = 60, Ron1 = 34, rtt_park1 = 60, rtt_nom1 = 240, rtt_wr1 = 240, combined with Figure 8-2 , introduce the specific values of the interface parameters corresponding to each link configured according to Configuration Information 1 before the processor reads or writes data.

[0130] As Figure 2-2 shown, since the processor connects 4 memory blocks through a single channel, therefore, a single link has at least four second ports, which are respectively called Second Port 1 to Second Port 4. Assume that Second Port 1 is connected to the memory chip in D1R0, Second Port 2 is connected to the memory chip in D1R1, Second Port 3 is connected to the memory chip in D0R0, and Second Port 4 is connected to the memory chip in D0R1.

[0131] Reference Figure 8-2The sub-table T1 corresponding to "the interface parameter configuration corresponding to each link during the D1R0 writing process". Before the processor writes data to D1R0, for each link, the processor can determine a set of configurations for the interface parameters corresponding to the link according to Configuration Information 1 (denoted as Configuration 1-1). The value of the parameter indicated by Configuration 1-1 can refer to the value indicated by the black dot in the sub-table T1. Then, when the processor configures the interface parameters of the link according to Configuration 1-1, it can configure the Ron value used by the first parallel interface to send signals through this link as SOC_Ron1 (i.e., 34), configure the Rodt (denoted as D1R0-Rodt) used by the second parallel interface to receive signals through the second port 1 of this link as rtt_wr1 (i.e., 240), configure the Rodt (denoted as D1R1-Rodt) used by the second parallel interface to receive signals through the second port 2 of this link as rtt_nom1 (i.e., 240), configure the Rodt (denoted as D0R0-Rodt) used by the second parallel interface to receive signals through the second port 3 of this link as rtt_park1 (i.e., 60), and configure the Rodt (denoted as D0R1-Rodt) used by the second parallel interface to receive signals through the second port 4 of this link as rtt_park1 (i.e., 60).

[0132] Similarly, before the processor writes data to D1R1, for each link, the processor can determine Configuration 1-2 for the interface parameters corresponding to the link according to Configuration Information 1, as Figure 8-2 indicated by the value of the black dot in the sub-table T2. Similarly, before the processor writes data to D1R0, for each link, the processor can determine Configuration 1-3 for the interface parameters corresponding to the link according to Configuration Information 1, as Figure 8-2 indicated by the value of the black dot in the sub-table T3. Similarly, before the processor writes data to D0R1, for each link, the processor can determine Configuration 1-4 for the interface parameters corresponding to the link according to Configuration Information 1, as Figure 8-2 indicated by the value of the black dot in the sub-table T4.

[0133] Refer to Figure 8-2The sub-table T5 corresponding to "the interface parameter configuration corresponding to each link during the D1R0 reading process". Before the processor reads data from D1R0, for each link, the processor can determine a set of configurations for the interface parameters corresponding to the link according to the configuration information 1 (denoted as configuration 1-5). The value of the parameter indicated by configuration 1-5 can refer to the value indicated by the black dot in the sub-table T5. Then, when the processor configures the interface parameters corresponding to the link according to configuration 1-5, it can configure the value of Rodt used by the first parallel interface to receive signals through this link as SOC_Rodt1 (i.e., 60), configure the Ron (denoted as D1R0-Ron) used by the second parallel interface to send signals through the second port 1 of this link as Ron1 (i.e., 34), configure the Rodt (denoted as D1R1-Rodt) used by the second parallel interface to receive signals through the second port 2 of this link as rtt_nom1 (i.e., 240), configure the Rodt (denoted as D0R0-Rodt) used by the second parallel interface to receive signals through the second port 3 of this link as rtt_park1 (i.e., 60), and configure the Rodt (denoted as D0R1-Rodt) used by the second parallel interface to receive signals through the second port 4 of this link as rtt_park1 (i.e., 60).

[0134] Similarly, before the processor reads data from D1R1, for each link, the processor can determine configuration 1-6 for the interface parameters corresponding to the link according to the configuration information 1, as Figure 8-2 the value indicated by the black dot in the sub-table T6 as shown. Similarly, before the processor reads data from D0R0, for each link, the processor can determine configuration 1-7 for the interface parameters corresponding to the link according to the configuration information 1, as Figure 8-2 the value indicated by the black dot in the sub-table T7 as shown. Similarly, before the processor reads data from D0R1, for each link, the processor can determine configuration 1-8 for the interface parameters corresponding to the link according to the configuration information 1, as Figure 8-2 the value indicated by the black dot in the sub-table T8 as shown.

[0135] With the development of information and communications technology (ICT), the computing power of the processor has been continuously enhanced, and higher requirements have been put forward for the signal transmission rate between the processor and the memory. In order to ensure the SI margin requirements, it is necessary to adjust the parameters of the parallel interface to optimize the SI of the signals in the link.

[0136] However, the parameters of the parallel interface not only affect the SI margin of the signals in the link, but also affect the power consumption of the parallel interface. Moreover, the parameter values that make the SI better tend to increase the power consumption of the parallel interface, and vice versa, the parameter values that make the SI worse tend to decrease the power consumption of the parallel interface.

[0137] Figure 5 and Figure 6 also respectively schematically show the static power consumption of the high and low levels of three logic levels, namely SSTL / CTT, POD, and LVSTL / TTL. As Figure 5 and Figure 6 shown, for any one of the logic levels, the smaller the Ron value, the greater the power consumption. Conversely, the larger the Ron value, the smaller the power consumption; the smaller the ODT value, the greater the power consumption. Conversely, the larger the ODT value, the smaller the power consumption.

[0138] The larger the value indicated by the pre-emphasis parameter (such as the enhancement amplitude and / or time range), the generally greater the power consumption. Conversely, the smaller the value indicated by the pre-emphasis parameter (such as the enhancement amplitude and / or time range), the generally smaller the power consumption.

[0139] The larger the value indicated by the CTLE parameter (such as the frequency range and / or amplification ratio), the generally greater the power consumption. Conversely, the smaller the value indicated by the CTLE parameter (such as the frequency range and / or amplification ratio), the generally smaller the power consumption.

[0140] Similarly, the larger the equalization order indicated by the DFE parameter, the generally greater the power consumption. Conversely, the smaller the equalization order indicated by the DFE parameter, the generally smaller the power consumption.

[0141] Through the above analysis, it is found that for different values of the same parameter, the value that makes the SI margin larger usually results in greater power consumption.

[0142] With the rapid development of semiconductor technology and the increase in the chip operating frequency, the power consumption of the chip and the system has increased rapidly. The increase in power consumption will lead to an increase in chip heat generation and a decrease in reliability. Therefore, low power consumption has become an important consideration in digital products. As a core component of digital products, the low-power design and application of memory are of great significance for reducing the power consumption of the entire digital product. In order to ensure the communication quality between the processing device and the memory, and to reduce the power consumption of the parallel interface, after configuring the interface parameters corresponding to each link according to Configuration Information 1, the SI thresholds of the signals transmitted in each link need to meet the requirements and the power consumption is the lowest.

[0143] However, with the continuous increase in the operating frequency and transmission rate of the parallel interface, the SI margin of the parallel bus continues to decrease. In order to ensure that the SI margin meets the requirements, the Ron and Rodt indicated by Configuration Information 1 continue to decrease, and the equalization parameters of the transmitter and / or receiver continue to increase. Correspondingly, the power consumption of the parallel interface continues to increase. The increase in power consumption will lead to an increase in chip heat generation and a decrease in reliability. Therefore, it is urgent to seek a solution to reduce the power consumption of the parallel interface while ensuring the communication quality.

[0144] Figure 7-1 Schematically shows a processor in a computer device and two DIMMs connected to the processor, and also schematically shows the routing and the length of part of the transmission lines between the processor and the DIMMs. Specifically, Figure 7-1 Schematically shows the routing of a transmission line in channel 0_byte1, the routing of a transmission line in channel 0_byte4, the routing of a transmission line in channel 1_byte1, and the routing of a transmission line in channel 1_byte4 respectively. The memory chips in the processor and the DIMMs can be connected through a DDR interface. Figure 7-2 Schematically shows a processor in a storage device and two flash memory chips, and also schematically shows the routing and the length of part of the transmission lines between the processor and the flash memory chips. Specifically, Figure 7-2 Schematically shows the routing of a transmission line in channel 0 and the routing of a transmission line in channel 16 respectively. The processor and the flash memory chips can be connected through an NFI interface. The implementation manner of the link in this application is not limited. For example, the link can be implemented through the routing in the circuit board and / or the connection lines outside the circuit board.

[0145] Such as Figure 7-1 and Figure 7-2 shown, there are generally large differences in the routing lengths of the transmission lines in different channels. Such as Figure 7-1 shown, there are generally also large differences in the routing lengths of the transmission lines in different bytes in the same channel. For example, as Figure 7-2 shown, the routing length of the transmission line in channel 0 is 2.1 inches, while the routing length of the transmission line in channel 16 is 5.9 inches. After configuring the interface parameters corresponding to each link according to configuration information 1 and transmitting signals through each link, it is found through experimental analysis that Figure 7-1 and Figure 7-2 the eye diagrams of the signals transmitted through the channels with longer routing lengths in Figure 7-1In the same channel, the eye diagram of the signal transmitted by the transmission line with a longer trace is worse than that of the signal transmitted by the transmission line with a shorter trace. Although the SI margin of the signals of each link is higher than the threshold, due to differences in trace conditions and other aspects among different links, the SI margins of different links may be different. For any two links configured according to the same configuration information, the present application refers to the link with better SI as the link with better trace condition, and the link with worse SI as the link with worse trace condition. For the link with better trace condition, by adjusting the value of the interface parameter (referred to as the target parameter) corresponding to it, it is possible to sacrifice a higher SI margin to reduce the power consumption of the parallel interface while ensuring that the SI margin is higher than the threshold. The target parameter may include one or more parameters of the parallel interface. That is to say, by differentially configuring the interface parameters corresponding to multiple links, it is beneficial to further reduce the power consumption of the parallel interface while ensuring that the SI margin of each link meets the requirements.

[0146] Based on the above analysis idea, the present application provides a method, which can be applied to Figure 1 the electronic system shown. By differentially configuring the interface parameters corresponding to different links, it is not only beneficial to make the links of each channel or each byte in the parallel interface meet the requirements of the SI margin, but also beneficial to reduce the power consumption of the parallel interface.

[0147] As introduced above, the interface parameter corresponding to the link may include the parameter used by the target interface to transmit the signal through the link. Correspondingly, before the processing device controls the first parallel interface to transmit multiple signals to the second parallel interface through at least two links among multiple links, the processing device may configure one or more parameters for the target interface to transmit the signal through at least two links. And among at least two links, there are at least two links (such as the first link and the second link), and the processing device differentially configures the interface parameters corresponding to these two links. In this way, it is not only beneficial to make the links of each channel or each byte in the parallel interface meet the requirements of the SI margin, but also beneficial to reduce the power consumption of the parallel interface. For example, the value configured for the target parameter used by the target interface to transmit the signal through the first link may be different from the value configured for the target parameter used by the target interface to transmit the signal through the second link.

[0148] After the processing device configures the interface parameters corresponding to a certain link according to a certain configuration information, and the SI margin of the signal transmitted by the link meets the requirements, this application refers to this configuration information as the alternative configuration information corresponding to the link. Among the multiple alternative configuration information corresponding to the link, this application refers to the alternative configuration information that minimizes the power consumption of the target interface transmitting signals through this link as the optimal configuration information corresponding to this link, and this minimum power consumption is referred to as the optimal power consumption corresponding to this link. This application also provides a method that can determine the configuration information corresponding to each link and configure the interface parameters corresponding to the corresponding link according to the configuration information corresponding to each link. In this way, it is beneficial to configure the corresponding link according to the optimal configuration information corresponding to each link, which is conducive to achieving the optimal power consumption corresponding to each link while ensuring that the SI margin requirements of each link are met, and thus conducive to achieving the optimal power consumption of the parallel interface.

[0149] For example, for three links with different routing situations (referred to as Link 1, Link 2, and Link 3), assuming that the routing situation of Link 1 is the worst and the routing situation of Link 3 is the best, it can be determined that the optimal configuration information corresponding to Link 1 is Configuration Information 1, the optimal configuration information corresponding to Link 2 is Configuration Information 2, and the optimal configuration information corresponding to Link 3 is Configuration Information 3. After that, the interface parameters corresponding to Link 1 can be configured according to Configuration Information 1, the interface parameters corresponding to Link 2 can be configured according to Configuration Information 2, and the interface parameters corresponding to Link 3 can be configured according to Configuration Information 3, which is conducive to achieving the optimal power consumption corresponding to each link while ensuring that the SI margin requirements of each link are met, and thus conducive to achieving the optimal power consumption of the parallel interface.

[0150] After the processing device configures the interface parameters corresponding to each link in a certain link group according to a certain configuration information, and the SI margins of the signals transmitted by each link in this link group all meet the requirements, this application refers to this configuration information as the alternative configuration information corresponding to this link group. Among the multiple alternative configuration information corresponding to the link group, this application refers to the alternative configuration information that minimizes the power consumption of the target interface transmitting signals through this link group as the optimal configuration information corresponding to this link group, and this minimum power consumption is referred to as the optimal power consumption corresponding to this link group. Through analysis, it is found that the optimal configuration information corresponding to the link group is the optimal configuration information corresponding to the link with the worst routing situation in the link group.

[0151] For the above three links, namely Link 1, Link 2, and Link 3, through further analysis, it is found that compared with configuring the interface parameters corresponding to Link 3 according to the optimal configuration information 1 corresponding to Link 1, when configuring the interface parameters corresponding to Link 3 according to the optimal configuration information 2 corresponding to Link 2, the power consumption of the target interface transmitting signals through Link 3 is closer to its corresponding optimal power consumption, that is, this power consumption is smaller.

[0152] Based on the above findings, the present application also provides a method, which can divide at least two links into multiple link groups, determine the configuration information corresponding to each link group respectively, and then configure the interface parameters corresponding to each link in the corresponding group according to the configuration information corresponding to each link group. In this way, it is beneficial to configure the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to the link with the worst routing situation in each link group.

[0153] The configuration information 1 introduced above, which makes the SI thresholds of the signals transmitted in each link meet the requirements and has the lowest power consumption, is actually the optimal configuration information corresponding to the link with the worst routing situation (the worst link) among multiple links. For a link group that does not include the worst link, since the routing situations of the links in this group are all better than that of the worst link, therefore, compared with configuring the interface parameters corresponding to each link in this group according to the configuration information 1, when configuring the interface parameters corresponding to each link in this group according to the optimal configuration information corresponding to this group, the power consumption of the target interface for transmitting signals through the links in this group is smaller. In this way, it is not only beneficial to ensure the communication quality and reduce the power consumption, but also beneficial to reduce the complexity of configuring the target interface.

[0154] As introduced above, the first parallel interface can have multiple channels. Through analysis, it is found that compared with the differences in the routing situations of the links in different channels, the differences in the routing situations of different links in the same channel are generally smaller. Optionally, the links in different channels can be divided into different link groups. The links in the same channel can be divided into one link group. Correspondingly, the optimal configuration information corresponding to each channel can be determined, and then the interface parameters corresponding to the links in the corresponding channel can be configured according to the optimal configuration information corresponding to each channel. As Figure 2-1 or Figure 2-2 shown, assuming that the first parallel interface has channel 0 and channel 1, the processing device can determine the optimal configuration information corresponding to channel 0 (denoted as CH0), determine the optimal configuration information corresponding to channel 1 (denoted as CH1), and then configure one or more interface parameters corresponding to each link in channel 0 according to CH0, and configure the interface parameters corresponding to each link in channel 1 according to CH1.

[0155] As introduced above, the bit width of a single channel of the first parallel interface can be multiple bytes. Through analysis, it is found that for different links in the same channel, compared with the differences in the routing situations of the links corresponding to different bytes, the differences in the routing situations of different links in the same byte are generally smaller. Optionally, the links corresponding to different bytes in the same channel can be divided into different link groups. The links in the same byte can be divided into one link group. Correspondingly, the optimal configuration information corresponding to each byte can be determined, and then the interface parameters corresponding to the links in the corresponding byte can be configured according to the optimal configuration information corresponding to each byte. As Figure 3-1As shown, assuming that the first parallel interface has Channel 0 and Channel 1, and the bit width of each channel is 4 bytes, the processing device can determine After that, configure the interface parameters corresponding to each link in Byte 1 of Channel 0 according to CH0B1, configure the interface parameters corresponding to each link in Byte 2 of Channel 0 according to CH0B2, …, configure the interface parameters corresponding to each link in Byte 4 of Channel 1 according to CH1B4.

[0156] The method for determining the optimal configuration information corresponding to the link group will be exemplified later and will not be elaborated here for the time being.

[0157] Through the above method, differential parameter configuration can be performed on the parallel bus interface, which is beneficial to enabling different channels and / or bytes of the parallel bus interface to select differential parameter configurations according to the actual routing conditions of the links (including routing length, impedance consistency, crosstalk, etc.), so as to fully exploit the SI margin of each channel and / or byte, reduce the power consumption of the signals transmitted on each channel or byte of the parallel interface, and thus reduce the overall power consumption of the parallel interface.

[0158] Taking the self-developed SSD XX platform as an example, the current optimal SI parameter configuration is Ron = 25Ω, ODT = 50Ω, and the overall static power consumption P of the NFI interface is P = 17ch * 12bit * 0.012W = 2.448W. According to the differential parameter scheme, on average, half of the channels have better routing conditions and can be configured as Ron = 25Ω, ODT = 100Ω, then the overall power consumption P = 8ch * 12bit * 0.012W + 9ch * 12bit * 0.006W = 1.8W, and the benefit of the overall static power consumption is 0.648W.

[0159] Assume that the multiple links between the first parallel interface and the second parallel interface include M control buses and N data buses, where M and N are positive integers greater than 1. The process of the electronic device accessing one or more memories will be exemplified later.

[0160] Assume that the target interface is the first parallel interface. The process of the electronic device writing data to one or more memories through the parallel interface will be introduced below. Figure 9A Schematically show a possible flow of the method. As Figure 9A shown, the method may include S901A to S904A.

[0161] S901A. The processing device determines multiple configuration information;

[0162] The processing device can determine multiple configuration information. Optionally, referring to Figure 3-2 , the configuration module in the processing device can determine multiple configuration information.

[0163] For example, the processing device may divide N data buses into P link groups. A single link group may include one or more links, and different link groups include different links. Then, the processing device may determine the configuration information corresponding to each link group, that is, determine P pieces of configuration information. Wherein, P is a positive integer less than or equal to N.

[0164] This application does not limit the way the processing device groups the N data buses. As described above, optionally, the processing device may divide the links in different channels into different link groups. Or, the processing device may divide the links in different channels into different link groups, and divide the links of different bytes in the same channel into different link groups. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link.

[0165] Optionally, the configuration information corresponding to the link group may be the optimal configuration information corresponding to the link group introduced above. As an example, assume that the first parallel interface has channel 0 and channel 1, and the processing device may determine CH0 and CH1 respectively. Assume that the first parallel interface has channel 0 and channel 1, and the bit width of each channel is 4 bytes. The processing device may determine CH0B1, CH0B2, CH0B3, CH0B4, CH1B1, CH1B2, CH1B3, and CH1B4 respectively.

[0166] As introduced above, the configuration information may be used to indicate the values of one or more parameters of the first parallel interface. For the process of writing data, the configuration information may at least include the write process configuration information introduced above. The write process configuration information may be used to indicate the parameters used by the first parallel interface to send signals through the link, for example, including the value of Ron (denoted as SOC_Ron) of the first parallel interface, and / or the value of Tx EQ (denoted as SOC_Tx EQ).

[0167] In this application, two link groups among multiple link groups are respectively called the first link group and the second link group. The configuration information corresponding to the first link group is called the first configuration information, and the configuration information corresponding to the second link group is called the second configuration information. Since the routing conditions of the links in different link groups generally vary greatly, the values of at least one parameter (called the target parameter) indicated by the first configuration information and the second configuration information may be different. For example, the first configuration information may indicate that SOC_Ron = 34 and the value of SOC_Tx EQ is gear 0, while the second configuration information may indicate that SOC_Ron = 40 and the value of SOC_TxEQ is gear 0. Accordingly, the target parameter is SOC_Ron.

[0168] S902A. The processing device configures one or more parameters used by the first parallel interface to send signals through the corresponding link group according to the values indicated by each configuration information;

[0169] After the processing device determines multiple configuration information, it can configure the interface parameters corresponding to the corresponding link group according to each configuration information. Optionally, referring to Figure 3-2 , S902A can be executed by the configuration module in the processing device.

[0170] For example, after the processing device determines P configuration information corresponding to P link groups, assuming that the configuration information i corresponds to the link group i, where i is a positive integer less than or equal to P, the processing device can configure the interface parameters corresponding to the link group 1 according to the value indicated by the configuration information 1, configure the interface parameters corresponding to the link group 2 according to the value indicated by the configuration information 2,..., and configure the interface parameters corresponding to the link group P according to the value indicated by the configuration information P.

[0171] The processing device configuring the interface parameters corresponding to the link group i according to the value indicated by the configuration information i can mean that for each link in the link group i, the processing device can configure one or more parameters used by the first parallel interface to send signals through the link according to the value indicated by the configuration information i. For example, for each link in the first link group, the processing device can configure Ron and Tx EQ used by the first parallel interface to send signals through the link to 34 and gear 0 respectively according to the value indicated by the first configuration information. For each link in the second link group, the processing device can configure Ron and Tx EQ used by the first parallel interface to send signals through the link to 40 and gear 0 respectively according to the second configuration information.

[0172] S903A. The processing device controls the configured first parallel interface to send N data signals to the second parallel interface through N data buses;

[0173] After the processing device configures the interface parameters corresponding to the N data buses, the processing device can control the first parallel interface to send N data signals to the second parallel interface through the N data buses, and the N data signals can carry data to be written into one or more memories. Optionally, referring to Figure 3-2 , S903A can be executed by the communication module in the processing device.

[0174] Assuming that the data bus j corresponds to a data signal j, the processing device can control the configured first parallel interface to send the data signal 1 to the second parallel interface through the data bus 1, control the configured first parallel interface to send the data signal 2 to the second parallel interface through the data bus 2,..., and control the configured first parallel interface to send the data signal N to the second parallel interface through the data bus N.

[0175] The configured first parallel interface can send a corresponding data signal to the first port of the link according to the interface parameters corresponding to the link. Suppose the first link group includes data bus 1, then the first parallel interface sends data signal 1 to the first port of data bus 1 with Ron having a value of 34 and Tx EQ in gear 0. Suppose the second link group includes data bus 2, then the first parallel interface sends data signal 2 to the first port of data bus 2 with Ron having a value of 40 and Tx EQ in gear 0. As Figure 5 and Figure 6 shown, the magnitude of Ron affects the signal level in the link. Therefore, the signal levels of data signal 1 and data signal 2 are different.

[0176] Refer to Figure 3-2 , suppose data bus 1 is Figure 3-2 L0 as shown, the processing device can control its own parallel interface to send data signal 1 to memory chip 1-1 through data bus 1.

[0177] S904A, one or more memories store the data transmitted by N data signals.

[0178] After the processing device controls the configured first parallel interface to send N data signals to the second parallel interface through N data buses, one or more memories can receive the N data signals through the second parallel interface, determine the data to be written by the processing device according to the N data signals, and write the data into its own storage medium.

[0179] Refer to Figure 3-2 , suppose data bus 1 is Figure 3-2 L0 as shown, the processing device can send data signal 1 to memory chip 1-1 through data bus 1. That one or more memories store the data carried by data signal 1 can mean that memory chip 1-1 receives data signal 1 through its own parallel interface and then writes the data carried by data signal 1 into its own storage medium. Optionally, refer to Figure 3-2 , the communication module in memory chip 1-1 can write the data into the storage medium.

[0180] The processing device configures one or more parameters for the first parallel interface to send signals through the corresponding link group according to the configuration information corresponding to each link group, which is beneficial to configuring the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to each link group. Then, the processing device controls the configured first parallel interface to send multiple data signals to the second parallel interface, which is beneficial to reducing the power consumption of the first parallel interface on the premise of ensuring the signal quality of the multiple data signals, thereby being beneficial to reducing the power consumption of the processing device and further reducing the power consumption of the electronic system.

[0181] Assume that the target interface is the first parallel interface. The following describes the process by which an electronic device reads data from one or more memories through the parallel interface. Figure 9B Schematically shows a possible flow of the method. As Figure 9B shown, the method may include S901B to S904B.

[0182] S901B. The processing device determines a plurality of configuration information;

[0183] The processing device may determine a plurality of configuration information. Optionally, referring to Figure 3-2 , the plurality of configuration information may be determined by a configuration module in the processing device.

[0184] Similar to S901A in the foregoing, for example, the processing device may divide N data buses into P link groups. Then, the processing device may determine the configuration information corresponding to each link group, that is, determine P configuration information. Wherein, P is a positive integer less than or equal to N. The present application does not limit the manner in which the processing device groups the N data buses. As described above, optionally, the processing device may divide the links in different channels into different link groups. Or, the processing device may divide the links in different channels into different link groups, and divide the links of different bytes in the same channel into different link groups. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. Optionally, the configuration information corresponding to the link group may be the optimal configuration information corresponding to the link group described above. As described above, the configuration information may be used to indicate the values of one or more parameters of the first parallel interface. In the present application, two link groups among the plurality of link groups are respectively referred to as a first link group and a second link group, the configuration information corresponding to the first link group is referred to as first configuration information, and the configuration information corresponding to the second link group is referred to as second configuration information. Since the routing conditions of the links in different link groups generally vary greatly, the values of at least one parameter (referred to as the target parameter) indicated by the first configuration information and the second configuration information may be different.

[0185] Different from S901A in the foregoing, for the data reading process, the configuration information may at least include the reading process configuration information described above. The reading process configuration information may be used to indicate the parameters used by the first parallel interface to receive signals through the link, for example, including the value of Rodt (denoted as SOC_Rodt) of the first parallel interface, and / or the value of Rx EQ (denoted as SOC_Rx EQ). For example, the first configuration information may indicate that SOC_Rodt = 60 and the value of SOC_Rx EQ is gear 0, while the second configuration information may indicate that SOC_Rodt = 120 and the value of SOC_Tx EQ is gear 0. Correspondingly, the target parameter is SOC_Rodt.

[0186] S902B. The processing device configures one or more parameters used by the first parallel interface to receive signals through the corresponding link group according to the values indicated by each configuration information;

[0187] Similar to S902A above, after the processing device determines multiple configuration information, it can configure the interface parameters corresponding to the corresponding link group according to each configuration information. Optionally, refer to Figure 3-2 , S902B can be executed by the configuration module in the processing device. For example, after the processing device determines the P configuration information corresponding to the P link groups, assuming that the configuration information i corresponds to the link group i, where i is a positive integer less than or equal to P, the processing device can configure the interface parameters corresponding to the link group 1 according to the value indicated by the configuration information 1, configure the interface parameters corresponding to the link group 2 according to the value indicated by the configuration information 2,..., and configure the interface parameters corresponding to the link group P according to the value indicated by the configuration information P.

[0188] For the read data process, different from S902A above, that the processing device configures the interface parameters corresponding to the link group i according to the value indicated by the configuration information i can mean that for each link in the link group i, the processing device can configure one or more parameters used by the first parallel interface to receive signals through this link according to the value indicated by the configuration information i. For example, for each link in the first link group, the processing device can configure the Rodt and Rx EQ used by the first parallel interface to receive signals through this link as 60 and gear 0 respectively according to the value indicated by the first configuration information. For each link in the second link group, the processing device can configure the Rodt and Rx EQ used by the first parallel interface to receive signals through this link as 120 and gear 0 respectively according to the second configuration information.

[0189] S903B. The processing device controls the configured first parallel interface to receive N data signals from the second parallel interface through N data buses;

[0190] After the processing device configures the interface parameters corresponding to the N data buses, one or more memories can, in response to the read data request of the processing device, control the second parallel interface to send N data signals to the first parallel interface through the N data buses, and the processing device can control the first parallel interface to receive N data signals from the second parallel interface through the N data buses, and the N data signals can carry the data read from one or more memories.

[0191] Assume that data bus j corresponds to a data signal j. The processing device can control the configured first parallel interface to receive data signal 1 from the second parallel interface through data bus 1, control the configured first parallel interface to receive data signal 2 from the second parallel interface through data bus 2, ……, control the configured first parallel interface to receive data signal N from the second parallel interface through data bus N.

[0192] The configured first parallel interface can receive a corresponding data signal from the first port of the link according to the interface parameters corresponding to the link. Assume that the first link group includes data bus 1. Then the first parallel interface receives data signal 1 from the first port of data bus 1 with a Rodt value of 60 and an Rx EQ at gear 0. Assume that the second link group includes data bus 2. Then the first parallel interface receives data signal 2 from the first port of data bus 2 with a Rodt value of 120 and an Rx EQ at gear 0. As Figure 5 and Figure 6 shown, the magnitude of Rodt affects the signal level in the link. Therefore, the signal levels of data signal 1 and data signal 2 are different.

[0193] Refer to Figure 3-2 , assume that data bus 1 is Figure 3-2 the L0 shown. Memory chip 1-1 (or Figure 3-2 the communication module in memory chip 1-1 shown) can send data signal 1 to L0 through the parallel interface according to the data stored in the storage medium. The processing device (or Figure 3-2 the communication module in the processing device shown) can receive data signal 1 from data bus 1 through the parallel interface.

[0194] S904B. The processing device obtains the data stored in one or more memories from the N data signals.

[0195] After the processing device controls the configured first parallel interface to receive N data signals from the second parallel interface through N data buses, the processing device can receive the N data signals through the first parallel interface, determine the data read from one or more memories according to the N data signals, and then process or transmit the data.

[0196] The processing device configures one or more parameters for the first parallel interface to receive signals through the corresponding link group according to the configuration information corresponding to each link group, which is beneficial to configuring the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to each link group. Then, the processing device controls the configured first parallel interface to receive multiplexed data signals from the second parallel interface to read data from one or more memories, which is beneficial to reducing the power consumption of the first parallel interface on the premise of ensuring the signal quality of the multiplexed data signals, thereby being beneficial to reducing the power consumption of the processing device and further reducing the power consumption of the electronic system.

[0197] Assume that the target interface is the second parallel interface. The following describes the process of the electronic device writing data to one or more memories through the parallel interface. Figure 9C Schematically shows a possible flow of the method. As Figure 9C shown, the method may include S901C to S904C.

[0198] S901C. The processing device determines multiple configuration information;

[0199] The processing device may determine multiple configuration information. Optionally, referring to Figure 3-2 , the configuration module in the processing device may determine multiple configuration information.

[0200] Similar to S901A in the previous text, for example, the processing device may divide N data buses into P link groups. Then, the processing device may determine the configuration information corresponding to each link group, that is, determine P configuration information. Wherein, P is a positive integer less than or equal to N. This application does not limit the way the processing device groups the N data buses. As mentioned above, optionally, the processing device may divide the links in different channels into different link groups. Or, the processing device may divide the links in different channels into different link groups and divide the links of different bytes in the same channel into different link groups. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. Optionally, the configuration information corresponding to the link group may be the optimal configuration information corresponding to the link group introduced above.

[0201] Different from S901A in the previous text, the configuration information may be used to indicate the values of one or more parameters of the second parallel interface. For the process of writing data, the configuration information may at least include the write process configuration information introduced above. The write process configuration information may be used to indicate the parameters adopted by the second parallel interface to receive signals through the link, for example, including the value of Rodt of the second parallel interface, and / or, the value of Rx EQ.

[0202] Similar to the previous S901A, in this application, two link groups among multiple link groups are respectively referred to as the first link group and the second link group, the configuration information corresponding to the first link group is referred to as the first configuration information, and the configuration information corresponding to the second link group is referred to as the second configuration information. Since the routing conditions of the links in different link groups generally vary greatly, the values of at least one parameter (referred to as the target parameter) indicated by the first configuration information and the second configuration information can be different.

[0203] Different from the previous S901A, for example, the first configuration information can indicate that Rodt = 34 and the value of Rx EQ is gear 0, while the second configuration information can indicate that Rodt = 48 and the value of Rx EQ is gear 0. Correspondingly, the target parameter is Rodt.

[0204] As introduced before, when a single link has multiple second ports, the ODT of the second parallel interface includes 3 sub-parameters, denoted as rtt_park, rtt_nom, and rtt_wr respectively. As an example, the values of rtt_park, rtt_nom, and rtt_wr indicated by the first configuration information can be 60, 240, and 240 respectively, and the values of rtt_park, rtt_nom, and rtt_wr indicated by the second configuration information can be 60, 120, and 120 respectively. Correspondingly, the target parameter can include rtt_park. Or, when the values of at least one of rtt_park, rtt_nom, and rtt_wr are different, it can be considered that the value of Rodt is different. Therefore, it can also be considered that the values of Rodt indicated by the first configuration information and the second configuration information are different.

[0205] S902C. The processing device configures one or more parameters used by the second parallel interface to receive signals through the corresponding link group according to the values indicated by each configuration information;

[0206] Similar to the previous S902A, after the processing device determines multiple configuration information, it can configure the interface parameters corresponding to the corresponding link group according to each configuration information. Optionally, referring to Figure 3-2 , S902C can be executed by the configuration module in the processing device.

[0207] After the processing device determines the P configuration information corresponding to the P link groups, assuming that the configuration information i corresponds to the link group i, where i is a positive integer less than or equal to P, the processing device can configure the interface parameters corresponding to the link group 1 according to the value indicated by the configuration information 1, configure the interface parameters corresponding to the link group 2 according to the value indicated by the configuration information 2,..., and configure the interface parameters corresponding to the link group P according to the value indicated by the configuration information P.

[0208] Regarding the configuration of the write process parameters of the second parallel interface, different from the above S902A, the processing device configures the interface parameters corresponding to the link group i according to the values ​​indicated by the configuration information i, which may refer to that for each link in the link group i, the processing device may configure one or more parameters used by the second parallel interface to receive signals through the link according to the values ​​indicated by the configuration information i. For example, for each link in the first link group, the processing device may configure the Rodt and Rx EQ used by the second parallel interface to receive signals through the link to 240 and gear 0, respectively, according to the values ​​indicated by the first configuration information. For each link in the second link group, the processing device may configure the Rodt and Rx EQ used by the second parallel interface to receive signals through the link to 120 and gear 0, respectively, according to the second configuration information.

[0209] The present application does not limit the manner in which the processing device configures one or more parameters used by the second parallel interface to receive signals through the link.

[0210] For example, the processing device may send the configuration signal described above to the memory connected to the second port of the link, and the configuration signal is used to indicate the value of one or more parameters adopted by the parallel interface of the memory to receive the signal through the link. Assuming that the processing device sends the configuration signal to the memory according to the first configuration information, the configuration signal may instruct the memory to configure the Rodt and Rx EQ of the parallel interface corresponding to the link to 240 and gear 0 respectively.

[0211] When the link has multiple second ports, the processing device may send a configuration signal to each memory connected to the second port of the link. Figure 8-2, assume that the link has second ports 1 to 4. The second port 1 is connected to the memory chip in D1R0, the second port 2 is connected to the memory chip in D1R1, the second port 3 is connected to the memory chip in D0R0, and the second port 4 is connected to the memory chip in D0R1. The processing device can respectively send configuration signals 1 to 4 to the memories connected to the second ports 1 to 4. Assume that the processing device sends the configuration signals 1 to 4 according to the first configuration information. The first configuration information indicates that the values of rtt_park, rtt_nom, and rtt_wr are 60, 240, and 240 respectively, the value of Rx EQ is gear 0, and the memory connected to the second port 1 is the memory to which data is to be written. Then, the configuration signal 1 can instruct the corresponding memory to configure the Rodt and Rx EQ corresponding to the parallel interface for this link as 240 and gear 0 respectively, the configuration signal 2 can instruct the corresponding memory to configure the Rodt and Rx EQ corresponding to the parallel interface for this link as 240 and gear 0 respectively, the configuration signal 3 can instruct the corresponding memory to configure the Rodt and RxEQ corresponding to the parallel interface for this link as 60 and gear 0 respectively, and the configuration signal 4 can instruct the corresponding memory to configure the Rodt and Rx EQ corresponding to the parallel interface for this link as 60 and gear 0 respectively.

[0212] S903C. The processing device controls the first parallel interface to send N data signals to the configured second parallel interface through N data buses;

[0213] After the processing device configures the parameters of the second parallel interface, the processing device can control the first parallel interface to send N data signals to the second parallel interface through N data buses. The N data signals can carry the data to be written into one or more memories.

[0214] Assume that data bus j corresponds to a data signal j. The processing device can control the first parallel interface to send data signal 1 to the configured second parallel interface through data bus 1, control the first parallel interface to send data signal 2 to the configured second parallel interface through data bus 2,..., control the configured first parallel interface to send data signal N to the configured second parallel interface through data bus N.

[0215] The configured second parallel interface can receive a corresponding data signal from the second port of the link according to the interface parameters corresponding to the link. Assume that the first link group includes data bus 1. Then, the second parallel interface can send data signal 1 from the second port of data bus 1 with a Rodt value of 240 and an Rx EQ of gear 0. Assume that the second link group includes data bus 2. Then, the first parallel interface receives data signal 2 from the second port of data bus 2 with a Rodt value of 120 and an Rx EQ of gear 0. As Figure 5and Figure 6 As shown, the size of Rodt affects the signal level in the link. Therefore, the signal levels of data signal 1 and data signal 2 are different.

[0216] Refer to Figure 3-2 , assuming that data bus 1 is L0 as shown in Figure 3-2 , the processing device (or the communication module in the processing device shown in Figure 3-2 ) can control its own parallel interface to send data signal 1 to memory chip 1-1 through data bus 1.

[0217] S904C, one or more memories store the data transmitted by N data signals.

[0218] After the processing device controls the first parallel interface to send N data signals to the configured second parallel interface through N data buses, one or more memories can receive the N data signals through the configured second parallel interface, determine the data to be written by the processing device according to the N data signals, and write the data into its own storage medium.

[0219] Refer to Figure 3-2 , assuming that data bus 1 is L0 as shown in Figure 3-2 , the processing device can send data signal 1 to memory chip 1-1 through data bus 1. That one or more memories store the data carried by data signal 1 can mean that memory chip 1-1 receives data signal 1 through its own parallel interface and then writes the data carried by data signal 1 into its own storage medium. Optionally, refer to Figure 3-2 , the data can be written into the storage medium by the communication module in memory chip 1-1.

[0220] The processing device configures one or more parameters for the second parallel interface to receive signals through each corresponding link group according to the configuration information corresponding to each link group, which is beneficial to configuring the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to each link group. Then, the processing device controls the first parallel interface to send multiple data signals to the configured second parallel interface, which is beneficial to reducing the power consumption of the second parallel interface on the premise of ensuring the signal quality of the multiple data signals, thereby being beneficial to reducing the power consumption of one or more memories and further reducing the power consumption of the electronic system.

[0221] Assuming that the target interface is the second parallel interface, the process of the electronic device reading data from one or more memories through the parallel interface is introduced below. Figure 9D Schematically shows a possible flow of the method. As shown in Figure 9D , the method may include S901D to S904D.

[0222] S901D, the processing device determines multiple configuration information;

[0223] The processing device may determine multiple configuration information. Figure 3-2 , multiple configuration information can be determined by a configuration module in the processing device.

[0224] Similar to the above S901A, for example, the processing device may divide N data buses into P link groups. Afterwards, the processing device may determine the configuration information corresponding to each link group, that is, determine P configuration information. Wherein, P is a positive integer less than or equal to N. The present application does not limit the manner in which the processing device groups the N data buses. As previously mentioned, optionally, the processing device may divide the links in different channels into different link groups. Alternatively, the processing device may divide the links in different channels into different link groups, and divide the links of different bytes in the same channel into different link groups. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. When P is equal to N, it can be considered that the processing device determines the configuration information corresponding to each link. Optionally, the configuration information corresponding to the link group may be the optimal configuration information corresponding to the link group introduced above.

[0225] Different from the above S901A, the configuration information can be used to indicate the values ​​of one or more parameters of the second parallel interface. For the process of reading data, the configuration information can at least include the read process configuration information introduced above, and the read process configuration information can be used to indicate the values ​​of the parameters used by the second parallel interface to send signals through the link, such as the value of Ron of the second parallel interface, and / or the value of Tx EQ.

[0226] Similar to the above S901A, the present application refers to two link groups in the multiple link groups as the first link group and the second link group, respectively, and refers to the configuration information corresponding to the first link group as the first configuration information, and refers to the configuration information corresponding to the second link group as the second configuration information. Since the routing conditions of the links in different link groups are generally quite different, the value of at least one parameter (referred to as the target parameter) indicated by the first configuration information and the second configuration information may be different.

[0227] Unlike the configuration information in S901A above indicating the parameters on the controller side, the configuration information may indicate the parameters on the memory side. For example, the first configuration information may indicate that Ron=34 on the memory side and the value of Tx EQ is gear 0, while the second configuration information may indicate that Ron=48 on the memory side and the value of Tx EQ is gear 0. Accordingly, the target parameter is Ron.

[0228] Optionally, the read process configuration information may also indicate the value of Rodt. As introduced above, when a single link has multiple second ports (such as second port 1 to second port 4), assuming that the processing device reads data from the memory connected to the second port 1, the processing device may also configure the Rodt corresponding to the links of the memories connected to other second ports. Correspondingly, the read process configuration information may also be used to indicate the values of rtt_park, rtt_nom, and rtt_wr respectively. As an example, the values of rtt_park, rtt_nom, and rtt_wr indicated by the first configuration information may be 60, 240, and 240 respectively, and the values of rtt_park, rtt_nom, and rtt_wr indicated by the second configuration information may be 60, 120, and 120 respectively. Correspondingly, the target parameter may include rtt_park. Alternatively, when the values of at least one of rtt_park, rtt_nom, and rtt_wr are different, it can be considered that the values of Rodt are different. Therefore, it can also be considered that the values of Rodt indicated by the first configuration information and the second configuration information are different.

[0229] S902D. The processing device configures one or more parameters used by the second parallel interface to send signals through the corresponding link group according to the values indicated by each configuration information;

[0230] Similar to S902A above, after the processing device determines multiple configuration information, it can configure the interface parameters corresponding to the corresponding link group according to each configuration information. Optionally, referring to Figure 3-2 , S902D can be executed by the configuration module in the processing device. For example, after the processing device determines the P configuration information corresponding to the P link groups, assuming that the configuration information i corresponds to the link group i, where i is a positive integer less than or equal to P, the processing device can configure the interface parameters corresponding to the link group 1 according to the value indicated by the configuration information 1, configure the interface parameters corresponding to the link group 2 according to the value indicated by the configuration information 2,..., and configure the interface parameters corresponding to the link group P according to the value indicated by the configuration information P.

[0231] For the read process parameters of the second parallel interface, which are different from those in S902A above, the processing device can configure the interface parameters corresponding to link group i according to the values indicated by the configuration information i, which can mean that for each link in link group i, the processing device can configure one or more parameters used by the second parallel interface to send signals through this link according to the values indicated by the configuration information i. For example, for each link in the first link group, the processing device can configure Ron and Tx EQ, which are used by the second parallel interface to send signals through this link, to 34 and gear 0 respectively according to the values indicated by the first configuration information. For each link in the second link group, the processing device can configure Rodt and Rx EQ, which are used by the second parallel interface to receive signals through this link, to 48 and gear 0 respectively according to the second configuration information.

[0232] This application does not limit the manner in which the processing device configures one or more parameters used by the second parallel interface to receive signals through the link.

[0233] Similar to S902C, for example, the processing device can send the above-mentioned configuration signal to the memory connected to the second port of this link, and this configuration signal is used to indicate the values of one or more parameters used by the parallel interface of the memory to send signals through this link. Assume that the processing device sends a configuration signal to the memory according to the first configuration information, and this configuration signal can indicate that the memory configures Ron and Tx EQ corresponding to this link of the parallel interface to 34 and gear 0 respectively.

[0234] When the link has multiple second ports, the processing device can send configuration signals to the memories connected to each second port of this link respectively. Continue to refer to Figure 8-2, assume that the link has second ports 1 to 4. The second port 1 is connected to the memory chips in D1R0, the second port 2 is connected to the memory chips in D1R1, the second port 3 is connected to the memory chips in D0R0, and the second port 4 is connected to the memory chips in D0R1. The processing device can respectively send configuration signals 1 to 4 to the memories connected to the second ports 1 to 4. Assume that the processing device sends the configuration signals 1 to 4 according to the first configuration information. The first configuration information indicates that Ron is 34, and the values of rtt_park, rtt_nom, and rtt_wr are 60, 240, and 240 respectively, and the value of Tx EQ is gear 0. And, the memory connected to the second port 1 is the memory to be read for data. Then, the configuration signal 1 can instruct the corresponding memory to configure the Ron and Rx EQ corresponding to the parallel interface of this link to 34 and gear 0 respectively, the configuration signal 2 can instruct the corresponding memory to configure the Rodt and RxEQ corresponding to the parallel interface of this link to 240 and gear 0 respectively, the configuration signal 3 can instruct the corresponding memory to configure the Rodt and Rx EQ corresponding to the parallel interface of this link to 60 and gear 0 respectively, and the configuration signal 4 can instruct the corresponding memory to configure the Rodt and Rx EQ corresponding to the parallel interface of this link to 60 and gear 0 respectively.

[0235] S903D. The processing device controls the first parallel interface to receive N data signals from the configured second parallel interface through N data buses;

[0236] After the processing device configures the parameters of the second parallel interface, one or more memories can, in response to the read data request of the processing device, control the configured second parallel interface to send N data signals to the first parallel interface through N data buses. The processing device can control the first parallel interface to receive N data signals from the second parallel interface through N data buses. The N data signals can carry the data read from one or more memories.

[0237] Assume that data bus j corresponds to a data signal j, where j is a positive integer less than or equal to N. The configured second parallel interface sends the data signal 1 to the first parallel interface through data bus 1, sends the data signal 2 to the first parallel interface through data bus 2,..., and sends the data signal N to the first parallel interface through data bus N.

[0238] The configured second parallel interface can send a corresponding data signal to the second port of the link according to the interface parameters corresponding to the link. Assuming that the first link group includes data bus 1, the second parallel interface can send data signal 1 to the second port of data bus 1 using Ron with a value of 34 and Tx EQ at gear 0. Assuming that the second link group includes data bus 2, the second parallel interface uses Ron with a value of 48 and Tx EQ at gear 0 to send data signal 2 to the second port of data bus 2. As Figure 5 and Figure 6 shown, the magnitude of Ron affects the signal level in the link. Therefore, the signal levels of data signal 1 and data signal 2 are different.

[0239] Refer to Figure 3-2 , assuming that data bus 1 is Figure 3-2 L0 shown, memory chip 1-1 (or Figure 3-2 the communication module in memory chip 1-1 shown) can send data signal 1 to L0 through the parallel interface according to the data stored in the storage medium, and the processing device (or Figure 3-2 the communication module in the processing device shown) can receive data signal 1 from data bus 1 through the parallel interface.

[0240] S904D. The processing device obtains the data stored in one or more memories from the N data signals.

[0241] After the processing device controls the first parallel interface to receive N data signals from the configured second parallel interface through N data buses, the processing device can receive the N data signals through the first parallel interface, determine the data read from one or more memories according to the N data signals, and then process or transmit the data.

[0242] The processing device configures one or more parameters for the second parallel interface to send signals through the corresponding link group according to the configuration information corresponding to each link group, which is beneficial to configuring the interface parameters corresponding to each link in the corresponding group according to the optimal configuration information corresponding to each link group. Then, the processing device controls the first parallel interface to receive multiple data signals from the configured second parallel interface, which is beneficial to reducing the power consumption of the second parallel interface on the premise of ensuring the signal quality of the multiple data signals, thereby being beneficial to reducing the power consumption of one or more memories and further reducing the power consumption of the electronic system.

[0243] In S902C and S902D above, the processing device may configure one or more parameters used by the memory connected to the link to transmit signals according to the configuration information. The processing device may send a configuration signal to the memory through the control bus connected to the memory, and the configuration signal is used to indicate the values of one or more parameters used by the memory to transmit signals through the link determined according to the configuration information.

[0244] Optionally, the processing device may send a configuration signal to the memory before each data read or write, and the configuration signal carries the values of the one or more parameters above.

[0245] Alternatively, in order to reduce the information length carried by the configuration signal, the processing device may send a first configuration signal to the memory, and the first configuration signal carries the values of the parameters indicated by the configuration information. For example, the first configuration signal carries the values of Ron, rtt_park, rtt_nom, and rtt_wr. Thereafter, the processing device may send a second configuration signal to the memory before each data read or write, and the second configuration signal is used to determine the values of at least one parameter from the values of the multiple parameters carried by the first configuration signal, and the memory may configure its parallel interface according to the values of the at least one parameter.

[0246] For example, continuing to refer to Figure 8-2 , before writing D1R0, the processor may send a second configuration signal to the memory chip in D1R0, and the second configuration signal instructs to configure Rodt according to the value of rtt_wr.

[0247] The parallel interface of the processor may send a configuration signal to a single memory chip through one or more pins, and these one or more pins may be connected to the control bus. When the parallel interface of the processor sends a configuration signal to the memory chip through multiple pins, optionally, one of the multiple pins may be used to transmit the signal of the above ODT field, and this pin may refer to Figure 8-2 the "ODT pin" shown. When the second configuration signal "0" sent by the first parallel interface through this pin, it may instruct the memory chip to configure ODT according to the value of rtt_park. When the second configuration signal "1" sent by the first parallel interface through this pin, it may instruct the memory chip to configure ODT according to the value of rtt_nom.

[0248] In S901A, S901B, S901C, and S901D above, the processing device may determine the configuration information corresponding to each link group in multiple link groups. The present application does not limit the manner in which the processing device determines the configuration information corresponding to the link group.

[0249] Optionally, the processing device may determine the configuration information corresponding to each link group by using a static configuration method. For example, the processing device may obtain the configuration information corresponding to each link group from the firmware (FW).

[0250] Taking the example of grouping multiple links by channel or byte, through simulation and testing in the R & D stage, the parameters of different channels or different bytes of each channel can be traversed, and a set of differential parameter combinations that meet the SI margin and have the optimal power consumption can be evaluated. Then, the differential parameter combinations are written into the firmware of the processing device. During the power-on initialization process, the processing device can obtain the values configured for the parameters of multiple links from the firmware and complete the configuration of the corresponding registers based on the obtained values.

[0251] Taking the example that the parallel interface of the processing device has m channels and each channel has n bytes, the multiple configuration information obtained by the processing device can be CHiBj represents the value of the parameter of the link in channel i byte j. Where m and n are positive integers greater than 1, i is a positive integer less than or equal to m, and j is a positive integer less than or equal to n.

[0252] Taking the example that the parallel interface of the processing device has m channels, the multiple configuration information obtained by the processing device can be Para = [CH1…CHm]. CHi represents the value of the parameter of the link in channel i. Where m is a positive integer greater than 1, and i is a positive integer less than or equal to m.

[0253] Taking the example that the parallel interface of the processing device has 1 channel and n bytes, the above differential parameter combination can be Para = [B1…Bn]. Bi represents the value of the parameter of the link in byte j. Where n is a positive integer greater than 1, and j is a positive integer less than or equal to n.

[0254] Alternatively, optionally, the processing device may use a dynamic configuration method to determine the configuration information corresponding to each link group. For example, the processing device may determine the configuration information corresponding to each link group through a parameter training program.

[0255] The processing device may optimize the configuration information corresponding to each link group through parameter training to determine its optimal configuration information. For example, the processing device may configure the parameters used by the target interface to transmit signals through the link group according to multiple different configuration information and transmit test signals through the configured target interface, and record the configuration information that makes the SI margin of the test signals transmitted by each link in the link group higher than the threshold as the alternative configuration information. Then, the processing device may select the alternative configuration information with the minimum power consumption from the multiple alternative configuration information as the optimal configuration information corresponding to the link group.

[0256] Taking the example that the parallel interface of the processing device has m channels and each channel has n bytes, after power-on, the processing device can optimize the configuration information corresponding to each byte in each channel through a training algorithm, and select a set of configuration information (i.e., the combination of parameter values) that meets the SI margin requirement and has the optimal power consumption for the link group of each byte. Then, based on the differentiated configuration information, the registers corresponding to the links in each byte of the target parallel interface are configured. The multiple configuration information obtained by the processing device through optimization can be All the links in the same byte can share the same parameter configuration. For example, the parameters of all the links in byte 1 of channel 1 can be configured as CH1B1.

[0257] Taking the example that the parallel interface of the processing device has m channels, after power-on, the processing device can optimize the configuration information corresponding to the links in each channel through a training algorithm, and select a set of configuration information (i.e., the combination of parameter values) that meets the SI margin requirement and has the optimal power consumption for the link group of each channel. Then, based on the differentiated configuration information, the registers corresponding to the links in each channel of the target parallel interface are configured. The multiple configuration information obtained by the processing device through optimization can be Para = [CH1…CHm]. All the links in the same channel can share the same parameter configuration. For example, the parameters of all the links in channel 1 can be configured as CH1.

[0258] Taking the example that the parallel interface of the processing device has 1 channel and n bytes, after power-on, the processing device can optimize the parameters of the links in each byte through a training algorithm, and select a set of configuration information (i.e., the combination of parameter values) that meets the SI margin requirement and has the optimal power consumption for the link group of each byte. Then, based on the differentiated configuration information, the registers corresponding to the links in each byte of the target parallel interface are configured. The multiple configuration information obtained by the processing device through optimization can be Para = [B1…Bn]. All the links in the same byte can share the same parameter configuration. For example, the parameters of all the links in byte 1 can be configured as B1.

[0259] The present application does not limit the way for the processing device to determine the power consumption. For example, the processing device can determine the power consumption corresponding to each configuration information through a table or a formula, or can predict the power consumption based on the size of the SI margin.

[0260] When the configuration information corresponding to the link group is used to indicate the value of each parameter among multiple parameters, the processing device can group the multiple parameters, and then optimize the multiple parameter combinations corresponding to the link group in sequence.

[0261] For example, assume that multiple parameters include Ron, ODT, transmitter pre-emphasis parameter, CTLE parameter, and DFE parameter. The processing device may divide the multiple parameters into two parameter combinations. The first parameter combination may include Ron and ODT, and the second parameter combination may include the transmitter pre-emphasis parameter, CTLE parameter, and DFE parameter.

[0262] The processing device may determine multiple value combinations for each parameter combination. The values of the parameters in the value combinations are the possible values of the parameter supported by the parallel interface configuration. The possible values of each parameter are specified in the protocol, and multiple value combinations can be determined according to the protocol. Taking the Figure 2-1 processor shown as an example, multiple value combinations of the parameter combination can be determined with reference to the relevant content of the NAND flash protocol. For example, the possible values of Ron and ODT can be determined with reference to Tables 4-11 and 4-56 in ONFI of the NAND flash protocol: ONFI. Taking the Figure 2-2 processor shown as an example, multiple value combinations of the parameter combination can be determined with reference to the relevant content of the DDR protocol. For example, the possible values of Ron and ODT can be determined with reference to Tables 136 and 110 in JESD79 of the DDR protocol: JESD79. Figure 10 and Figure 11 schematically show the possible values of the above respective parameters. In practical applications, the possible values of the parameters may be different from Figure 10 and Figure 11 . The multiple value combinations selected by the processing device may be all the value combinations determined according to the possible values of each parameter, or may be some preferred value combinations. For example, in the single-channel dual-DIMM (2DIMM per Channel, 2DPC) scenario of DDR2, the values of rtt_Wr and rtt_Nom can preferably be 240, and the value of rtt_Park can preferably be a value in the range of 120 to 40.

[0263] After the processing device determines multiple value combinations of the first parameter combination, it may scan the multiple value combinations of the first parameter combination corresponding to the link group to find and optimize the optimal value combination. The optimal value combination may refer to the value combination that enables the link group to meet the SI margin requirement and has the optimal power consumption. After setting the first parameter combination according to the optimal value combination of the first parameter combination, the optimal value combination can be scanned and determined from the multiple values of the second parameter combination. Thus, the processing device can determine the optimal value combination of the multiple parameters (i.e., Ron, ODT, transmitter pre-emphasis parameter, CTLE parameter, and DFE parameter) corresponding to the link group, that is, the optimal configuration information corresponding to the link group.

[0264] Next, in combination with Figure 12An example is given to introduce the method by which the processing device scans multiple different values of the target parameters of the target link and determines its optimal value. The target link can be a single uplink or downlink, and the target parameter can be a single parameter or a combination of single parameters of the target interface.

[0265] As Figure 12 shown, the method by which the processing device determines the optimal value combination of the target parameter combination corresponding to link group i through the parameter training process may include S1201 to S1208.

[0266] S1201. Determine the value combination sequence of the target parameter combination, where this value combination sequence includes multiple different value combinations of the target parameter combination;

[0267] Assume that this value combination sequence is {v1, v2,..., vn}, where n is a positive integer.

[0268] S1202. Select a value combination (denoted as vi) from the value combination sequence to make the value combination v of the target parameter combination equal to vi;

[0269] S1203. Configure the target interface with v, control the target interface to transmit a test signal through link group i, and detect the SI margin of the test signal;

[0270] S1204. Determine whether the SI margin meets the requirements. For example, determine whether the SI margin is not lower than the threshold. If so, execute S1205; if not, execute S1207;

[0271] S1205. Record the value of v;

[0272] S1206. Determine whether the value sequence has been traversed. If not, execute S1207; if so, execute S1208;

[0273] S1207. Select the next value combination (denoted as vi+1) from the value combination sequence to make the value combination v of the target parameter combination equal to vi+1, and trigger S1203;

[0274] S1208. Determine the value combination with the optimal power consumption from all the value combinations of the recorded v, that is, the optimal value combination of the target parameter combination corresponding to link group i.

[0275] This application does not limit the method by which the processing device determines the power consumption. For example, the processing device can determine the power consumption corresponding to each value combination through a table or formula, or can predict the power consumption based on the magnitude of the SI margin.

[0276] In the method introduced above, taking one or more parameters adopted by the processing device to configure the target interface to transmit signals through the corresponding link group according to the values indicated by each configuration information among multiple configuration information as an example, the present application does not limit the method for the processing device to differentially configure the interface parameters corresponding to different links or different link groups. For example, the processing device can call a machine learning model to configure one or more parameters respectively adopted by the target interface to transmit signals through at least two links. The machine learning model is used to predict the optimal configuration of the parameters adopted by the target interface to transmit signals through each link and configure the interface parameters corresponding to each link. Correspondingly, the processing device may not need to determine multiple configuration information.

[0277] Above, taking the parameters adopted by the processing device to configure the target interface to transmit data signals through the data bus as an example, optionally, the processing device can configure the parameters adopted by the target interface to transmit control signals through multiple control buses according to the above method, and the processing device configures different values for the interface parameters corresponding to at least two control buses. Then, the processing device can control the first parallel interface to transmit control signals to the second parallel interface through multiple control buses. The present application does not limit the specific type of the control signal. For example, the control signal may include at least one of an address signal, a chip select signal, a synchronization signal, and a configuration signal.

[0278] Above, taking the parameters of the target interface configured by the processing device through the interfaces corresponding to N data buses as an example, optionally, the processing device can configure the parameters of the target interface through a part of the N data buses among the N data buses. Then, optionally, the processing device can control the first parallel interface to transmit data signals to the second parallel interface through the configured part of the data buses.

[0279] Above, taking the processing device controlling the first parallel interface to send N data signals to N data buses or receive N data signals from N data buses as an example, optionally, the processing device can control the first parallel interface to send N1 data signals to N1 of the N data buses, and control the first parallel interface to receive N2 data signals from N2 of the N data buses. Wherein, N1 and N2 are positive integers, and N1 + N2 is less than or equal to N.

[0280] Assume the structure of the memory is as Figure 3-2 shown in memory chip 1-1, that is, the memory may include a control device, a parallel interface, and a storage medium. The control device can be respectively connected to the parallel interface and the storage medium. As introduced above, the configuration module in the control device is used to configure the parameters of the parallel interface, and the communication module controls the parallel interface to transmit signals to the first parallel interface of the processing device to send the data in the storage medium to the processing device, or receive the data to be written into the storage medium sent by the processing device.

[0281] In the method introduced above, the processing device configures the parameters of the parallel interface of the memory. Optionally, instead of the processing device configuring the parallel interface of the memory, the memory (or the configuration module in the memory) can configure its own parallel interface. Assuming that the parallel interface of the memory and the first parallel interface of the processing device are connected by multiple links, based on the above analysis ideas and solutions, the present application also provides a method. In this method, the memory (or the configuration module in the memory) can perform differential configuration on at least two of the multiple links. These at least two links can be all used for transmitting data signals or all used for transmitting control signals. For the specific solutions and effects, reference can be made to the content of the differential configuration solution executed by the processing device introduced above.

[0282] For example, before the processing device controls the first parallel interface to transmit multiplexed signals with the parallel interface of the memory through at least two of the multiple links, the memory can configure one or more parameters for transmitting signals through at least two of its own parallel interfaces. And, among the at least two links, there are at least two links (for example, the first link and the second link), and the memory performs differential configuration on the interface parameters corresponding to these two links.

[0283] For example, the memory can determine the configuration information corresponding to each link group, and configure the interface parameters corresponding to the corresponding link group according to the configuration information corresponding to each link group.

[0284] For example, the memory can divide at least two links into multiple link groups, respectively determine the configuration information corresponding to each link group, and then configure the interface parameters corresponding to each link in the corresponding group according to the configuration information corresponding to each link group.

[0285] For example, assuming that the multiple links correspond to multiple channels of the first parallel interface, the memory can determine the optimal configuration information corresponding to each channel, and then configure the interface parameters corresponding to the links in the corresponding channel according to the optimal configuration information corresponding to each channel.

[0286] For example, assuming that the multiple links correspond to one or more channels of the first parallel interface, and the bit width of a single channel is multiple bytes, the memory can determine the optimal configuration information corresponding to each byte, and then configure the interface parameters corresponding to the links in the corresponding byte according to the optimal configuration information corresponding to each byte.

[0287] For example, the memory can execute S901C and S902C instead of the processing device, and / or the memory can execute S901D and S902D instead of the processing device.

[0288] The above has introduced the method, apparatus, and device provided by the present application. The present application also provides a computer-readable medium, in which instructions are stored. When they run on an electronic device (such as a computer), the electronic device is caused to execute the methods described in the above aspects of the method.

[0289] The embodiments of the present application also provide a computer program product. When it runs on an electronic device (such as a computer), the electronic device (such as a computer) is caused to execute the methods described in the above aspects.

[0290] In addition, it should be noted that the embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separated. The modules mentioned in the present application may be hardware circuits, may also be modules in the form of software, or may be modules implemented by combining hardware circuits and software. The components shown as modules may or may not be physical modules, that is, they may be located in one place or may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the accompanying drawings of the apparatus embodiments provided by the present application, the connection relationships between the modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines.

[0291] The terms "first", "second", etc. in the specification, claims, and above-mentioned drawings of the present application are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0292] Those of ordinary skill in the art can understand that the aforementioned computer-readable storage media include: various non-transitory machine-readable media such as USB flash drives, external hard drives, magnetic disks, optical discs, RAM, SSDs, or non-volatile memories.

[0293] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them.

Claims

1. A signal transmission method, characterized in that, The method is applied to an electronic system, which includes an electronic device and one or more memories. The first parallel interface of the electronic device is connected to the second parallel interface of the one or more memories through multiple links. The method includes: Configuring one or more parameters respectively adopted by a target interface to transmit signals through at least two of the multiple links. The target interface includes the first parallel interface and / or the second parallel interface. The at least two links include a first link and a second link. The one or more parameters include a target parameter. And the values of the target parameter respectively adopted by the configured target interface to transmit signals through the first link and the second link are a first value and a second value; Controlling the first parallel interface to transmit multiple paths of signals to the second parallel interface through the at least two links.

2. The signal transmission method according to claim 1, characterized in that The at least two links include a first link group. The first link group includes the first link and other links. And the other links do not include the second link. The value of the target parameter adopted by the configured target interface to transmit signals through the other links is the first value.

3. The signal transmission method according to claim 2, characterized in that The first link group is used to transmit signals in the same channel or signals in the same byte.

4. The signal transmission method according to any one of claims 1-3, characterized in that The first link and the second link are used to transmit signals in different channels or signals in different bytes of the same channel.

5. The signal transmission method according to any one of claims 2-4, characterized in that, The method further includes: Controlling the target interface to transmit test signals through the first link group respectively by using the target parameter with multiple different values; Determining the first value from the multiple different values according to the signal integrity (SI) margin of the multiple transmitted test signals.

6. The signal transmission method according to claim 5, wherein, The multiple different values include one or more values. Among them, the SI margin of the test signals respectively transmitted by the target interface by using the target parameter with the one or more values is not lower than a threshold. And the one or more values include the first value. Among the one or more values, the power consumption of the target interface transmitting signals by using the target parameter with the first value is the smallest.

7. The signal transmission method according to any one of claims 1-6, characterized in that The one or more parameters include at least one of the following parameters: Drive capability parameter, transmitter equalization (EQ) parameter, on-chip termination (ODT) parameter, and receiver equalization (EQ) parameter.

8. The signal transmission method according to any one of claims 1-7, characterized in that, The multiple paths of signals are used to transmit data to be written into the one or more memories or data read from the one or more memories.

9. The signal transmission method according to any one of claims 1-8, characterized in that, The one or more memories include non-volatile flash memory and / or double data rate synchronous dynamic random access memory (DDR SDRAM).

10. A processing device, characterized in that, The processing device is applied to an electronic device. The first parallel interface of the electronic device is connected to the second parallel interface of one or more memories through multiple links. The processing device includes: A configuration module, configured to configure one or more parameters respectively adopted by a target interface for transmitting signals through at least two of the multiple links, where the target interface includes the first parallel interface and / or the second parallel interface, the at least two links include a first link and a second link, the one or more parameters include a target parameter, and after configuration, the values of the target parameter respectively adopted by the target interface for transmitting signals through the first link and the second link are a first value and a second value; A communication module, configured to control the first parallel interface to transmit multiple signals to the second parallel interface through the at least two links.

11. An electronic device, characterized in that, The electronic device includes a processing device and a parallel interface. The processing device is connected to the parallel interface. The parallel interface is used to connect to one or more memories. The processing device is configured to execute the method according to any one of claims 1-9.

12. The electronic device according to claim 11, characterized in that, The processing device includes a processor, and the processor is configured to execute instructions stored in a memory, so that the processing device executes the method according to any one of claims 1 to 9.

13. The electronic device according to claim 11, wherein The processing device includes a logic circuit, and the logic circuit is configured to execute the method according to any one of claims 1 to 9.

14. An electronic system, characterized in that, The electronic system includes an electronic device and one or more memories. The electronic device and the one or more memories are connected through a parallel interface. The electronic device is as described in any one of claims 11-13.

15. The electronic system according to claim 14, wherein The electronic system is a computer device or a storage device.

16. A computer-readable storage medium, characterized in that, Including instructions, when running on a computer device, causing the computer device to execute the method according to any one of claims 1 to 9.

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