Communication method and device, PCIe architecture, computer equipment and storage medium

Abstract

The invention relates to a communication method and device, a PCIe architecture, computer equipment and a storage medium. The method is used in a first processor in a PCIe architecture, the PCIe architecture comprises PCIe bridge equipment and a plurality of processors serving as main equipment, the plurality of processors are connected with the PCIe bridge equipment, the first processor is any one of the plurality of processors, and the method comprises the following steps: receiving first target data written into a first sending space, the first processor comprises a plurality of sending spaces, the plurality of sending spaces are in one-to-one correspondence with other processors except the first processor in the plurality of processors, and the first sending space is corresponding to a second processor; and mapping the address of the first sending space to obtain a first virtual address, and transmitting the first target data to a first receiving space, corresponding to the first virtual address, of the second processor through the PCIe bridge device based on the first virtual address. By adopting the method, the communication flexibility can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of data processing, and in particular, to a communication method, apparatus, PCIe architecture, computer device, storage medium, and computer program product. Background Art

[0002] In a traditional PCIe architecture, there is usually a unique master device RC and one or more terminal devices EP. The master device RC can actively request to read and write the EP, while the EP cannot actively request to read and write the RC. When such a PCIe architecture is used in an autonomous driving domain controller, each processor in the PCIe architecture needs to have the same power, that is, it can all be used as an RC.

[0003] In the prior art, there already exists a PCIe architecture with an interconnection between two RCs, and communication between the two RCs can be achieved based on a non-transparent bridge.

[0004] However, this communication method is only limited to communication between two RCs and cannot meet the requirements of a more complex autonomous driving domain controller, thereby resulting in lower communication flexibility. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a communication method, apparatus, PCIe architecture, computer device, computer-readable storage medium, and computer program product with relatively high flexibility.

[0006] In a first aspect, the present application provides a communication method for a first processor in a PCIe architecture. The PCIe architecture includes a PCIe bridge device and multiple processors acting as master devices. The multiple processors are all connected to the PCIe bridge device. The first processor is any one of the multiple processors, and the method includes:

[0007] Receiving first target data written to a first transmission space. The first processor includes multiple transmission spaces, and the multiple transmission spaces correspond one-to-one to other processors in the multiple processors except the first processor. The first transmission space corresponds to a second processor;

[0008] Performing mapping processing on the address of the first transmission space to obtain a first virtual address, and transmitting the first target data to a first reception space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address.

[0009] In one embodiment, the performing mapping processing on the address of the first transmission space includes: performing mapping processing on the address of the first transmission space based on a direct memory access (DMA) mapping method.

[0010] In one embodiment, the method for mapping the address of the first transmission space based on direct memory access (DMA) includes: mapping the address of the first transmission space based on the DMA mapping method by a first virtual peripheral, where the first virtual peripheral is a virtual peripheral corresponding to the first processor.

[0011] In one embodiment, the multiple transmission spaces are spaces shared by the first processor and the PCIe bridge device.

[0012] In one embodiment, the process of transferring the first target data to the first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address includes: transmitting the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first receiving space according to the first virtual address, and the PCIe bridge device obtains the first target data through the first transmission space to transfer the first target data to the first receiving space of the second processor.

[0013] In one embodiment, the PCIe bridge device includes multiple information interrupt regions, which respectively correspond to the multiple processors one by one. The method further includes: after the first processor goes online, broadcasting through the first information interrupt region in the PCIe bridge device to prompt other processors except the first processor among the multiple processors that the first processor has gone online and is in an online state, where the first information interrupt region is the information interrupt region corresponding to the first processor.

[0014] In one embodiment, before transferring the first target data to the first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address, the method further includes: determining whether the second processor is in an online state through the second information interrupt region corresponding to the second processor; and performing the step of transferring the first target data to the first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device when the second processor is in an online state.

[0015] In one embodiment, the PCIe bridge device includes multiple doorbell interrupt regions, which respectively correspond to the multiple processors one by one. The method further includes: triggering the second doorbell interrupt region in the PCIe bridge device to instruct the PCIe bridge device to send an interrupt event to the second processor, where the interrupt event is used to instruct the second processor to receive the first target data transmitted from the first processor, and the second doorbell interrupt region is the interrupt region corresponding to the second processor.

[0016] In one embodiment, the first processor includes a plurality of receiving spaces, which correspond one-to-one to other processors in the plurality of processors except the first processor. The method further includes: after the first processor receives an interrupt event sent by the PCIe bridge device, determining a third processor based on the interrupt event, where the third processor is the processor that sends the second target data; determining a second receiving space from the plurality of receiving spaces according to the third processor, and obtaining the second target data from the second receiving space, where the second receiving space is the receiving space corresponding to the third processor.

[0017] In one embodiment, the plurality of receiving spaces are spaces shared by the first processor and the PCIe bridge device.

[0018] In a second aspect, the present application further provides a communication device, including:

[0019] A receiving module, configured to receive first target data written to a first sending space. The first processor includes a plurality of sending spaces, which correspond one-to-one to other processors in the plurality of processors except the first processor. The first sending space corresponds to a second processor;

[0020] An execution module, configured to perform mapping processing on the address of the first sending space to obtain a first virtual address, and transmit the first target data to a first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address.

[0021] In one embodiment, the execution module is specifically configured to perform mapping processing on the address of the first sending space based on a direct memory access (DMA) mapping method.

[0022] In one embodiment, the execution module is specifically configured to perform mapping processing on the address of the first sending space through a first virtual peripheral based on the DMA mapping method, where the first virtual peripheral is a virtual peripheral corresponding to the first processor.

[0023] In one embodiment, the plurality of sending spaces are spaces shared by the first processor and the PCIe bridge device.

[0024] In one embodiment, the execution module is specifically configured to transmit the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first receiving space according to the first virtual address, and enables the PCIe bridge device to obtain the first target data through the first sending space, so as to transmit the first target data to the first receiving space of the second processor.

[0025] In one embodiment, the PCIe bridge device includes a plurality of information interruption regions, and the plurality of information interruption regions respectively correspond to the plurality of processors one by one. The execution module is specifically configured to, after the first processor goes online, broadcast through the first information interruption region in the PCIe bridge device to prompt other processors in the plurality of processors except the first processor that the first processor has gone online and is in an online state. The first information interruption region is the information interruption region corresponding to the first processor.

[0026] In one embodiment, the execution module is specifically configured to determine whether the second processor is in an online state through the second information interruption region corresponding to the second processor; in the case where the second processor is in an online state, execute the step of transmitting the first target data to the first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address.

[0027] In one embodiment, the PCIe bridge device includes a plurality of doorbell interruption regions, and the plurality of doorbell interruption regions respectively correspond to the plurality of processors one by one. The execution module is specifically configured to trigger the second doorbell interruption region in the PCIe bridge device to instruct the PCIe bridge device to send an interruption event to the second processor, and the interruption event is used to instruct the second processor to receive the first target data transmitted from the first processor. The second doorbell interruption region is the interruption region corresponding to the second processor.

[0028] In one embodiment, the first processor includes a plurality of receiving spaces, and the plurality of receiving spaces respectively correspond to other processors in the plurality of processors except the first processor one by one. The execution module is specifically configured to, after the first processor receives the interruption event sent by the PCIe bridge device, determine a third processor based on the interruption event, where the third processor is the processor that sends the second target data; determine a second receiving space from the plurality of receiving spaces according to the third processor, and obtain the second target data from the second receiving space, where the second receiving space is the receiving space corresponding to the third processor.

[0029] In one embodiment, the plurality of receiving spaces are spaces shared by the first processor and the PCIe bridge device.

[0030] In a third aspect, the present application further provides a PCIe architecture, and the PCIe architecture includes a PCIe bridge device and a plurality of processors serving as master devices; the plurality of processors are used to implement the steps of the method described in any one of claims 1 to 10, and the PCIe bridge device is used to implement data transmission between the plurality of processors.

[0031] Fourthly, the present application further provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the data transmission method described in any one of the first aspects above is implemented.

[0032] Fifthly, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the data transmission method described in any one of the first aspects above is implemented.

[0033] Sixthly, the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, the data transmission method described in any one of the first aspects above is implemented.

[0034] The above communication method, device, PCIe architecture, computer device, storage medium and computer program product. The method is used in a first processor in a PCIe architecture. The PCIe architecture includes a PCIe bridge device and multiple processors acting as master devices. The multiple processors are all connected to the PCIe bridge device. The first processor is any one of the multiple processors. The first processor receives first target data written to a first transmission space. The first processor includes multiple transmission spaces, and the multiple transmission spaces correspond one-to-one to other processors among the multiple processors except the first processor. The first transmission space corresponds to a second processor; perform mapping processing on the address of the first transmission space to obtain a first virtual address, and transmit the first target data to a first reception space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address. The communication method provided by the present application first receives target data in the first transmission space, determines the corresponding second processor according to the first transmission space, and performs mapping processing on the address of the first transmission space to obtain a first virtual address, so as to transmit the first target data to a first reception space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address. The communication method provided by the present application can meet the requirements of a relatively complex autonomous driving domain controller, that is, meet the communication between multiple processors acting as master devices in a multi-processor PCIe architecture, thereby effectively improving the flexibility of communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 Schematic flow diagram of a communication method in an embodiment;

[0037] Figure 2 Schematic flow diagram of a method before the first target data is transmitted to the first receiving space corresponding to the first virtual address of the second processor by the PCIe bridge device based on the first virtual address in an embodiment;

[0038] Figure 3 Schematic flow diagram of a method for a first processor to receive second target data in an embodiment;

[0039] Figure 4 Schematic flow diagram of a communication method in another embodiment;

[0040] Figure 5 Schematic diagram of a PCIe architecture in an embodiment;

[0041] Figure 6 Structural block diagram of a communication device in an embodiment;

[0042] Figure 7 Internal structure diagram of a computer device in an embodiment;

[0043] Figure 8 Internal structure diagram of a computer device in another embodiment. Detailed implementation manners

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] In a traditional PCIe architecture, there is usually a unique master device RC and one or more terminal devices EP. The master device RC can actively request to read and write the EP, while the EP cannot actively request to read and write the RC. When such a PCIe architecture is used in an autonomous driving domain controller, each processor in the PCIe architecture needs to have the same power, that is, it can all be used as an RC.

[0046] In the prior art, there already exists a PCIe architecture with an interconnection between two RCs, and communication between the two RCs can be achieved based on a non-transparent bridge.

[0047] However, this communication method is only limited to communication between two RCs and cannot meet the requirements of a more complex autonomous driving domain controller, thereby resulting in lower communication flexibility.

[0048] In view of this, the present application provides a communication method, which can meet the requirements of a relatively complex autonomous driving domain controller, thereby effectively improving the flexibility of communication.

[0049] The communication method provided by the present application can be used in a first processor in a PCIe architecture. The PCIe architecture includes a PCIe bridge device and multiple processors serving as master devices. The multiple processors are all connected to the PCIe bridge device, and the first processor is any one of the multiple processors.

[0050] In an exemplary embodiment, as Figure 1 shown, a communication method is provided, and the method includes the following steps:

[0051] Step 101: Receive first target data written to a first transmission space.

[0052] Among them, the first processor includes multiple transmission spaces, and the multiple transmission spaces correspond one-to-one to other processors in the multiple processors except the first processor, and the first transmission space corresponds to a second processor.

[0053] Optionally, the PCIe refers to a computer bus standard used to connect various hardware devices inside a computer. The PCIe architecture can transmit data through high-speed serial data channels, providing higher bandwidth and better performance.

[0054] In a possible implementation manner, the multiple processors may be GPUs. The GPU is a microprocessor specifically used for processing graphics and image calculations. It has a large number of parallel processing units and high computing power, making it excellent in processing large-scale data, graphics rendering, and compute-intensive tasks.

[0055] In another possible implementation manner, the multiple processors may also be Orin. Orin integrates multiple functional modules, including a processor, a graphics processor, a deep learning accelerator, and an embedded computing engine, etc. Orin has powerful computing power and high parallel processing ability, can process complex perception, decision-making, and control tasks in real time, and supports the input and processing of various sensor data, including cameras, radars, lidars, etc., and can achieve high-precision environmental perception and object recognition.

[0056] Optionally, the master device refers to the root complex (RC) in the PCIe architecture, and the RC has the power to actively access and read / write endpoint devices (EP).

[0057] In an optional embodiment of the present application, the multiple transmission spaces are spaces shared by the first processor and the PCIe bridge device.

[0058] In a possible implementation, assume that there are four processors in the PCIe architecture, namely the first processor, the second processor, the third processor, and the fourth processor. Taking the first processor as an example, there are three transmission spaces in the first processor, which can be represented as BAR2, BAR3, and BAR4. The BAR2 is the first transmission space and corresponds to the second processor. The BAR3 is the second transmission space and corresponds to the third processor. The BAR3 is the third transmission space and corresponds to the fourth processor. And the BAR2, BAR3, and BAR4 are the spaces shared by the first processor and the PCIe device bridge.

[0059] Optionally, the first processor refers to the sender of the first target data.

[0060] In a possible implementation, the user can write the first target data into the first transmission space of the first processor, so that the first processor receives the first target data in the first transmission space. As described above, since the first transmission space corresponds to the second processor, it can be determined that the first target data is to be sent to the second processor. If the user writes the first target data into the second transmission space, it can be determined that the first target data is to be sent to the third processor.

[0061] In another possible implementation, an external device can write the first target data into the first transmission space of the first processor, so that the first processor receives the first target data in the first transmission space. As described above, since the first transmission space corresponds to the second processor, it can be determined that the first target data is to be sent to the second processor. If the user writes the first target data into the third transmission space, it can be determined that the first target data is to be sent to the fourth processor.

[0062] Step 102: Perform mapping processing on the address of the first transmission space to obtain a first virtual address, and based on the first virtual address through the PCIe bridge device, transmit the first target data to the first receiving space corresponding to the second processor and the first virtual address.

[0063] Optionally, the mapping processing is used to implement the conversion between the logical address and the virtual address.

[0064] In a possible implementation, the address of the first transmission space can be mapped based on the direct memory access (DMA) mapping method to obtain the first virtual address.

[0065] In another possible implementation manner, the address of the first sending space may also be mapped based on a preset mapping relationship list or preset mapping relationship information to obtain the first virtual address.

[0066] In another possible implementation manner, the address of the first sending space may also be mapped based on a preset address mapping algorithm to obtain the first virtual address.

[0067] Optionally, the PCIe bridge device may be a PCIe Switch.

[0068] In one possible implementation manner, after obtaining the first virtual address, the first virtual address may be transmitted to the PCIe bridge device, so that the PCIe bridge device transmits the first target data to a first receiving space corresponding to the first virtual address of the second processor based on the first virtual address.

[0069] In another possible implementation manner, during the preparation stage, the addresses of multiple sending spaces of the first processor may be mapped to obtain multiple virtual addresses, and the virtual addresses are stored in the PCIe bridge device. During the usage stage, after the first target data is written into the first sending space of the first processor, since the first sending space is shared memory between the first processor and the PCIe bridge device, the PCIe bridge device will determine the corresponding first virtual address according to the first sending space, and transmit the first target data to a first receiving space corresponding to the first virtual address of the second processor based on the first virtual address.

[0070] The above communication method is used in a first processor in a PCIe architecture. The PCIe architecture includes a PCIe bridge device and multiple processors acting as master devices. All of the multiple processors are connected to the PCIe bridge device. The first processor is any one of the multiple processors. The first processor receives first target data written to a first transmission space. The first processor includes multiple transmission spaces, and the multiple transmission spaces correspond one-to-one to the other processors among the multiple processors except the first processor. The first transmission space corresponds to a second processor. The address of the first transmission space is mapped to obtain a first virtual address, and the first target data is transmitted to a first reception space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address. In the communication method provided in this application, the target data is first received in the first transmission space, the corresponding second processor is determined according to the first transmission space, and the address of the first transmission space is mapped to obtain a first virtual address, so that the first target data is transmitted to the first reception space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address. Using the communication method provided in this application can meet the requirements of a relatively complex autonomous driving domain controller, that is, it can meet the communication between multiple processors acting as master devices in a multi-processor PCIe architecture, thereby effectively improving the flexibility of communication.

[0071] In an optional embodiment of this application, the mapping process of the address of the first transmission space includes: mapping the address of the first transmission space based on a direct memory access (DMA) mapping method.

[0072] In an optional embodiment of this application, the mapping the address of the first transmission space based on the direct memory access (DMA) mapping method includes: mapping the address of the first transmission space based on the DMA mapping method through a first virtual peripheral, and the first virtual peripheral is a virtual peripheral corresponding to the first processor.

[0073] Optionally, the virtual peripheral refers to a technology implemented by software or hardware, which is used to simulate the functions and behaviors of physical peripherals and make them exist in a virtual form.

[0074] In a possible implementation manner, as described above, assuming that there are four processors in the PCIe architecture, then each processor corresponds to a virtual peripheral, that is, the first processor corresponds to a first virtual peripheral, the second processor corresponds to a second virtual peripheral, the third processor corresponds to a third virtual peripheral, and the fourth processor corresponds to a fourth virtual peripheral. The virtual peripheral can be used to map the address of the transmission space to a corresponding virtual address.

[0075] In an optional embodiment of the present application, the process of the PCIe bridge device transferring the first target data to the first receiving space corresponding to the first virtual address in the second processor based on the first virtual address includes: transmitting the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first receiving space according to the first virtual address, and enables the PCIe bridge device to obtain the first target data through the first sending space, in order to transfer the first target data to the first receiving space of the second processor.

[0076] In a possible implementation manner, as described above, assuming that there are four processors in the PCIe architecture, and there are three sending spaces in each processor, which correspond to the other three processors respectively, namely BAR2, BAR3, and BAR4. Based on the virtual peripherals corresponding to each processor, the addresses of the three sending spaces can be mapped to obtain virtual addresses, namely TRAN2, TRAN3, and TRAN4. The three virtual addresses correspond to the receiving spaces in the other three processors. Each processor also includes three receiving spaces, namely BASE2, BASE3, and BASE4, which correspond to the other three processors respectively. The specific corresponding relationships are shown in Table 1, Table 2, Table 3, and Table 4.

[0077] Table 1

[0078] BAR2 (sent to the second processor) TRAN2 BASE2 of the second processor BAR3 (sent to the third processor) TRAN3 BASE2 of the third processor BAR4 (sent to the fourth processor) TRAN4 BASE2 of the fourth processor

[0079] Taking the first processor as the data sender as an example, the corresponding relationship can be shown in Table 1. Specifically, if the first processor is in the first sending space, that is, BAR2 receives the first target data, it means that the first target data is to be sent to the second processor. Then, the first virtual peripheral corresponding to the first processor will map the address of BAR2 to obtain the first virtual address TRAN2, and TRAN2 corresponds to the first receiving space BASE2 in the second processor. Then, the PCIe bridge device can transfer the first target data in the first sending space to the first receiving space in the second processor based on the first virtual address. If the first processor is in the second sending space, that is, BAR3 receives the first target data, it means that the first target data is to be sent to the third processor. Then, the first virtual peripheral corresponding to the first processor will map the address of BAR3 to obtain the second virtual address TRAN3, and TRAN3 corresponds to the first receiving space BASE2 in the third processor. If the first processor is in the third sending space, that is, BAR4 receives the first target data, it means that the first target data is to be sent to the fourth processor. Then, the first virtual peripheral corresponding to the first processor will map the address of BAR4 to obtain the third virtual address TRAN4, and TRAN4 corresponds to the first receiving space BASE2 in the fourth processor.

[0080] Table 2

[0081] BAR2 (sent to the first processor) TRAN2 BASE2 of the first processor BAR3 (sent to the third processor) TRAN3 BASE3 of the third processor BAR4 (sent to the fourth processor) TRAN4 BASE3 of the fourth processor

[0082] Taking the second processor as the data sender as an example, the corresponding relationship can be shown in Table 2. Specifically, if the second processor is in the first transmission space, that is, BAR2 receives the first target data, it means that the first target data is to be sent to the first processor. Then, the second virtual peripheral corresponding to the second processor will map the address of BAR2 to obtain the first virtual address TRAN2, which corresponds to the first reception space BASE2 in the first processor. Then, the PCIe bridge device can transmit the first target data in the first transmission space to the first reception space in the first processor based on the first virtual address. If the second processor is in the second transmission space, that is, BAR3 receives the first target data, it means that the first target data is to be sent to the third processor. Then, the second virtual peripheral corresponding to the second processor will map the address of BAR3 to obtain the second virtual address TRAN3, which corresponds to the second reception space BASE3 in the third processor. If the second processor is in the third transmission space, that is, BAR4 receives the first target data, it means that the first target data is to be sent to the fourth processor. Then, the second virtual peripheral corresponding to the second processor will map the address of BAR4 to obtain the third virtual address TRAN4, which corresponds to the second reception space BASE3 in the fourth processor.

[0083] Table 3

[0084] BAR2 (sent to the first processor) TRAN2 BASE3 of the first processor BAR3 (sent to the second processor) TRAN3 BASE3 of the second processor BAR4 (sent to the fourth processor) TRAN4 BASE4 of the fourth processor

[0085] Among them, taking the third processor as the data sender as an example, the corresponding relationship can be shown in Table 3. Specifically, if the third processor is in the first sending space, that is, BAR2 receives the first target data, it means that the first target data is to be sent to the first processor. Then, the third virtual peripheral corresponding to the third processor will map the address of BAR2 to obtain the first virtual address TRAN2, and TRAN2 corresponds to the second receiving space BASE3 in the first processor. Then, the PCIe bridge device can transfer the first target data in the first sending space to the second receiving space in the first processor based on the first virtual address. If the third processor is in the second sending space, that is, BAR3 receives the first target data, it means that the first target data is to be sent to the second processor. Then, the third virtual peripheral corresponding to the third processor will map the address of BAR3 to obtain the second virtual address TRAN3, and TRAN3 corresponds to the second receiving space BASE3 in the second processor. If the third processor is in the third sending space, that is, BAR4 receives the first target data, it means that the first target data is to be sent to the fourth processor. Then, the third virtual peripheral corresponding to the third processor will map the address of BAR4 to obtain the third virtual address TRAN4, and TRAN4 corresponds to the third receiving space BASE4 in the fourth processor.

[0086] Table 4

[0087] BAR2 (sent to the first processor) TRAN2 BASE4 of the first processor BAR3 (sent to the second processor) TRAN3 BASE4 of the second processor BAR4 (sent to the third processor) TRAN4 BASE4 of the third processor

[0088] Taking the fourth processor as the data sender as an example, the corresponding relationship can be shown in Table 4. Specifically, if the fourth processor is in the first sending space, that is, BAR2 receives the first target data, it means that the first target data is to be sent to the first processor. Then, the fourth virtual peripheral corresponding to the fourth processor will map the address of BAR2 to obtain the first virtual address TRAN2, and TRAN2 corresponds to the third receiving space BASE4 in the first processor. Then, the PCIe bridge device can transfer the first target data in the first sending space to the third receiving space in the first processor based on the first virtual address. If the fourth processor is in the second sending space, that is, BAR3 receives the first target data, it means that the first target data is to be sent to the second processor. Then, the fourth virtual peripheral corresponding to the fourth processor will map the address of BAR3 to obtain the second virtual address TRAN3, and TRAN3 corresponds to the third receiving space BASE4 in the second processor. If the fourth processor is in the third sending space, that is, BAR4 receives the first target data, it means that the first target data is to be sent to the third processor. Then, the fourth virtual peripheral corresponding to the fourth processor will map the address of BAR4 to obtain the third virtual address TRAN4, and TRAN4 corresponds to the third receiving space BASE4 in the third processor.

[0089] In an optional embodiment of the present application, the PCIe bridge device includes multiple information interruption regions, and the multiple information interruption regions respectively correspond to the multiple processors one by one. The method further includes: after the first processor goes online, broadcasting through the first information interruption region in the PCIe bridge device to prompt other processors in the multiple processors except the first processor that the first processor has gone online and is in an online state. The first information interruption region is the information interruption region corresponding to the first processor.

[0090] In a possible implementation manner, as described above, assuming that there are four processors in the PCIe architecture, the doorbell register region of the PCIe bridge device can be partitioned to obtain four partitions, and each partition corresponds to each processor. The doorbell register is 64 bits in total, so each partition is 16 bits. Among them, the high 4 bits of each partition are the information interruption regions corresponding to each processor. After the first processor goes online, broadcasting can be performed through the first information interruption region corresponding to the first processor to prompt other processors in the multiple processors except the first processor that the first processor has gone online and is in an online state.

[0091] In an optional embodiment of the present application, when the first processor goes offline, it can also broadcast through the first information interruption area to prompt other processors in the multiple processors except the first processor that the first processor has gone offline and is in the offline state.

[0092] The above method of broadcasting through the first information interruption area in the PCIe bridge device after the first processor goes online to prompt other processors in the multiple processors except the first processor that the first processor has gone online and is in the online state can realize the function of multi-processor staggered online through the mechanism of the information interruption area, so as to prevent the preemption problem encountered when multiple processors start at the same time, and thus effectively improve the flexibility of communication.

[0093] In an exemplary embodiment, as Figure 2 shown, before the PCIe bridge device transfers the first target data to the first receiving space corresponding to the first virtual address of the second processor based on the first virtual address, the method further includes the following steps:

[0094] Step 201: Determine whether the second processor is in the online state through the second information interruption area corresponding to the second processor.

[0095] Step 202: When the second processor is in the online state, execute the step of transferring the first target data to the first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address.

[0096] In a possible implementation manner, after determining the recipient of the first target data, that is, the second processor, the state of the second processor can be determined through the second information interruption area corresponding to the second processor. Specifically, it can be determined whether the second processor is in the online state by determining whether an online broadcast or an offline broadcast from the second information interruption area is received. If the second processor is in the online state, then execute the step of transferring the first target data to the first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device.

[0097] The above method of determining whether the second processor is in the online state through the second information interruption area corresponding to the second processor and executing the step of transferring the first target data to the first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device when the second processor is in the online state can avoid the situation of still sending the first target data to the recipient when the recipient cannot receive the first target data, and effectively improve the flexibility of communication.

[0098] In an optional embodiment of the present application, the PCIe bridge device includes a plurality of doorbell interrupt regions, and the plurality of doorbell interrupt regions correspond to the plurality of processors one by one. The method further includes: triggering a second doorbell interrupt region in the PCIe bridge device to instruct the PCIe bridge device to send an interrupt event to the second processor, where the interrupt event is used to instruct the second processor to receive first target data transmitted from the first processor, and the second doorbell interrupt region is the interrupt region corresponding to the second processor.

[0099] In a possible implementation manner, as described above, assuming that there are four processors in the PCIe architecture, the doorbell register region of the PCIe bridge device can be partitioned to obtain four partitions, and each partition corresponds to each processor. The doorbell register is 64 bits in total, so each partition is 16 bits. Among them, the high 4 bits of each partition are the information interrupt regions corresponding to each processor, and the low 12 bits of each partition are the doorbell interrupt regions corresponding to each processor. When the first processor sends the first target data to the second processor, it can also trigger a specified region in the second doorbell interrupt region corresponding to the second processor to instruct the PCIe bridge device to send an interrupt event to the second processor, where the interrupt event is used to instruct the second processor to receive the first target data transmitted from the first processor, and the specified region can be preset by those skilled in the art.

[0100] The method of triggering the second doorbell interrupt region in the PCIe bridge device to instruct the PCIe bridge device to send an interrupt event to the second processor, where the interrupt event is used to instruct the second processor to receive the first target data transmitted from the first processor, can wake up the receiver before sending the first target data to the receiver, so as to wait for receiving the first target data, thereby effectively improving the flexibility of communication.

[0101] In an embodiment of an embodiment, as Figure 3 shown, the first processor includes a plurality of receiving spaces, and the plurality of receiving spaces correspond to the other processors except the first processor in the plurality of processors one by one. The method further includes the following steps:

[0102] Step 301, after the first processor receives the interrupt event sent by the PCIe bridge device, determine a third processor based on the interrupt event.

[0103] Wherein, the third processor is the processor that sends the second target data.

[0104] In a possible implementation manner, when the third processor sends the second target data to the first processor, it also triggers a specified position in the first doorbell interrupt region corresponding to the first processor to instruct the PCIe bridge device to send an interrupt event to the first processor. The interrupt event is used to instruct the first processor to receive the second target data transmitted from the third processor. After receiving the interrupt event, the first processor determines that the third processor is about to send the second target data to itself according to the interrupt event.

[0105] Step 302: Determine a second receiving space from the multiple receiving spaces according to the third processor, and obtain the second target data from the second receiving space.

[0106] Wherein, the second receiving space is the receiving space corresponding to the third processor.

[0107] In an optional embodiment of the present application, the multiple receiving spaces are spaces shared by the first processor and the PCIe bridge device.

[0108] In a possible implementation manner, the corresponding relationship between the sending space and the receiving space in each processor has been described in detail above, and will not be elaborated here. Only a simple description is given. There are multiple receiving spaces in the first processor, and the multiple receiving spaces correspond to each processor other than the first processor in the multiple processors one by one. Then, if it is determined according to the third processor that its corresponding receiving space is the second receiving space, the second target data can be obtained in the second receiving space.

[0109] In an exemplary embodiment, as Figure 4 shown, another communication method is provided for the first processor in the PCIe architecture. The PCIe architecture includes a PCIe bridge device and multiple processors acting as master devices. The multiple processors are all connected to the PCIe bridge device. The first processor is any one of the multiple processors. The method includes the following steps:

[0110] Step 401: Receive the first target data written to the first sending space. The first processor includes multiple sending spaces, and the multiple sending spaces correspond to each processor other than the first processor in the multiple processors one by one. The first sending space corresponds to the second processor;

[0111] Step 402: Perform mapping processing on the address of the first sending space through the first virtual peripheral based on the DMA mapping method. The first virtual peripheral is the virtual peripheral corresponding to the first processor to obtain a first virtual address.

[0112] Step 403: Determine whether the second processor is in an online state through the second information interruption area corresponding to the second processor;

[0113] Step 4041: When the second processor is in an online state, transmit the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first receiving space according to the first virtual address, and the PCIe bridge device obtains the first target data through the first sending space, so as to transmit the first target data into the first receiving space of the second processor.

[0114] Step 4042: Trigger the second doorbell interruption area in the PCIe bridge device to instruct the PCIe bridge device to send an interruption event to the second processor, and the interruption event is used to instruct the second processor to receive the first target data transmitted from the first processor, and the second doorbell interruption area is the interruption area corresponding to the second processor.

[0115] In an exemplary embodiment, a PCIe architecture is provided. The PCIe architecture includes: a PCIe bridge device and multiple processors serving as master devices. The multiple processors are used for the steps of the method in any one of the above embodiments, and the PCIe bridge device is used to implement data transmission between the multiple processors.

[0116] In a possible implementation manner, the PCIe architecture may be as Figure 5 shown. Among them, the PCIe architecture 500 includes a PCIe bridge device 505 and four processors serving as master devices, and the four processors are respectively a first processor 501, a second processor 502, a third processor 503, and a fourth processor 504.

[0117] It should be understood that although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0118] Based on the same inventive concept, an embodiment of the present application further provides a communication device for implementing the communication method involved above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the communication device provided below can refer to the limitations on the communication method in the above text, and will not be elaborated here.

[0119] In an exemplary embodiment, as Figure 6 shown, a communication device 600 is provided, including: a receiving module 601 and an execution module 602, where:

[0120] The receiving module 601 is configured to receive first target data written to a first transmission space. The first processor includes a plurality of transmission spaces, and the plurality of transmission spaces correspond one-to-one to other processors except the first processor among the plurality of processors. The first transmission space corresponds to a second processor;

[0121] The execution module 602 is configured to perform mapping processing on the address of the first transmission space to obtain a first virtual address, and based on the first virtual address through the PCIe bridge device, transmit the first target data to a first reception space corresponding to the first virtual address of the second processor.

[0122] In an embodiment, the execution module 602 is specifically configured to perform mapping processing on the address of the first transmission space based on a direct memory access (DMA) mapping method.

[0123] In an embodiment, the execution module 602 is specifically configured to perform mapping processing on the address of the first transmission space through a first virtual peripheral based on the DMA mapping method, and the first virtual peripheral is a virtual peripheral corresponding to the first processor.

[0124] In an embodiment, the plurality of transmission spaces are spaces shared by the first processor and the PCIe bridge device.

[0125] In an embodiment, the execution module 602 is specifically configured to transmit the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first reception space according to the first virtual address, and enables the PCIe bridge device to obtain the first target data through the first transmission space, so as to transmit the first target data to the first reception space of the second processor.

[0126] In one embodiment, the PCIe bridge device includes a plurality of information interruption regions, and the plurality of information interruption regions respectively correspond to the plurality of processors one by one. The execution module 602 is specifically configured to, after the first processor goes online, broadcast through the first information interruption region in the PCIe bridge device to prompt other processors in the plurality of processors except the first processor that the first processor has gone online and is in an online state. The first information interruption region is the information interruption region corresponding to the first processor.

[0127] In one embodiment, the execution module 602 is specifically configured to determine whether the second processor is in an online state through the second information interruption region corresponding to the second processor; in the case where the second processor is in an online state, execute the step of transmitting the first target data to the first receiving space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address.

[0128] In one embodiment, the PCIe bridge device includes a plurality of doorbell interruption regions, and the plurality of doorbell interruption regions respectively correspond to the plurality of processors one by one. The execution module 602 is specifically configured to trigger the second doorbell interruption region in the PCIe bridge device to instruct the PCIe bridge device to send an interruption event to the second processor, and the interruption event is used to instruct the second processor to receive the first target data transmitted from the first processor. The second doorbell interruption region is the interruption region corresponding to the second processor.

[0129] In one embodiment, the first processor includes a plurality of receiving spaces, and the plurality of receiving spaces respectively correspond to other processors in the plurality of processors except the first processor. The execution module 602 is specifically configured to, after the first processor receives the interruption event sent by the PCIe bridge device, determine a third processor based on the interruption event, where the third processor is the processor that sends the second target data; determine a second receiving space from the plurality of receiving spaces according to the third processor, and obtain the second target data from the second receiving space. The second receiving space is the receiving space corresponding to the third processor.

[0130] In one embodiment, the plurality of receiving spaces are spaces shared by the first processor and the PCIe bridge device.

[0131] Each module in the foregoing communication device can be implemented in whole or in part by software, hardware, and a combination thereof. The foregoing modules can be embedded in the processor in the computer device in a hardware form or be independent of the processor, or can be stored in the memory in the computer device in a software form, so as to facilitate the processor to call and execute the operations corresponding to the foregoing modules.

[0132] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structural diagram may be as shown in Figure 7 . The computer device includes a plurality of processors, a memory, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processors, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processors of the computer device are used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals through a network connection. When the computer program is executed by the processor, a communication method is implemented.

[0133] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structural diagram may be as shown in Figure 8 . The computer device includes a plurality of processors, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processors, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processors of the computer device are used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, a communication method is implemented.

[0134] Those skilled in the art can understand that Figure 7 or Figure 8 the structures shown in are only block diagrams of some structures related to the solution of the present application, and do not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0135] In an exemplary embodiment, a computer device is provided, including a memory and multiple processors. A computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented: receiving first target data written to a first sending space, where the first processor includes multiple sending spaces, and the multiple sending spaces correspond one-to-one to other processors among the multiple processors except the first processor, and the first sending space corresponds to a second processor; performing mapping processing on the address of the first sending space to obtain a first virtual address, and based on the first virtual address through the PCIe bridge device, transmitting the first target data to a first receiving space corresponding to the first virtual address in the second processor.

[0136] In an embodiment, when the processor executes the computer program, the following steps are further implemented: performing mapping processing on the address of the first sending space based on the direct memory access (DMA) mapping method.

[0137] In an embodiment, when the processor executes the computer program, the following steps are further implemented: performing mapping processing on the address of the first sending space through a first virtual peripheral based on the DMA mapping method, where the first virtual peripheral is a virtual peripheral corresponding to the first processor.

[0138] In an embodiment, the multiple sending spaces are spaces shared by the first processor and the PCIe bridge device.

[0139] In an embodiment, when the processor executes the computer program, the following steps are further implemented: transmitting the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first receiving space according to the first virtual address, and enables the PCIe bridge device to obtain the first target data through the first sending space, in order to transmit the first target data to the first receiving space of the second processor.

[0140] In an embodiment, the PCIe bridge device includes multiple information interruption regions, and the multiple information interruption regions correspond one-to-one to the multiple processors respectively. When the processor executes the computer program, the following steps are further implemented: after the first processor goes online, broadcasting through a first information interruption region in the PCIe bridge device to prompt other processors among the multiple processors except the first processor that the first processor has gone online and is in an online state, where the first information interruption region is an information interruption region corresponding to the first processor.

[0141] In one embodiment, when the processor executes the computer program, the following steps are further implemented: determining whether the second processor is in an online state through a second information interruption area corresponding to the second processor; and when the second processor is in an online state, executing the step of transmitting the first target data to a first receiving space corresponding to the first virtual address in the second processor based on the first virtual address through the PCIe bridge device.

[0142] In one embodiment, the PCIe bridge device includes a plurality of doorbell interruption areas, and the plurality of doorbell interruption areas correspond to the plurality of processors one by one. When the processor executes the computer program, the following steps are further implemented: triggering a second doorbell interruption area in the PCIe bridge device to instruct the PCIe bridge device to send an interruption event to the second processor, where the interruption event is used to instruct the second processor to receive the first target data transmitted from the first processor, and the second doorbell interruption area is the interruption area corresponding to the second processor.

[0143] In one embodiment, the first processor includes a plurality of receiving spaces, and the plurality of receiving spaces correspond to other processors in the plurality of processors except the first processor one by one. When the processor executes the computer program, the following steps are further implemented: after the first processor receives the interruption event sent by the PCIe bridge device, determining a third processor based on the interruption event, where the third processor is the processor that sends the second target data; determining a second receiving space from the plurality of receiving spaces according to the third processor, and obtaining the second target data from the second receiving space, where the second receiving space is the receiving space corresponding to the third processor.

[0144] In one embodiment, the plurality of receiving spaces are spaces shared by the first processor and the PCIe bridge device.

[0145] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0146] Receiving first target data written to a first sending space, where the first processor includes a plurality of sending spaces, and the plurality of sending spaces correspond to other processors in the plurality of processors except the first processor one by one, and the first sending space corresponds to a second processor; performing mapping processing on the address of the first sending space to obtain a first virtual address, and transmitting the first target data to a first receiving space corresponding to the first virtual address in the second processor based on the first virtual address through the PCIe bridge device.

[0147] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: performing mapping processing on the address of the first sending space based on a direct memory access (DMA) mapping method.

[0148] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: mapping the address of the first transmission space based on the DMA mapping method through a first virtual peripheral, where the first virtual peripheral is the virtual peripheral corresponding to the first processor.

[0149] In one embodiment, the multiple transmission spaces are spaces shared by the first processor and the PCIe bridge device.

[0150] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: transmitting the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first reception space according to the first virtual address, and the PCIe bridge device obtains the first target data through the first transmission space to transmit the first target data into the first reception space of the second processor.

[0151] In one embodiment, the PCIe bridge device includes multiple information interruption regions, and the multiple information interruption regions correspond to the multiple processors one by one. When the computer program is executed by a processor, the following steps are further implemented: after the first processor goes online, broadcasting through the first information interruption region in the PCIe bridge device to prompt other processors except the first processor among the multiple processors that the first processor has gone online and is in an online state, where the first information interruption region is the information interruption region corresponding to the first processor.

[0152] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented: determining whether the second processor is in an online state through the second information interruption region corresponding to the second processor; when the second processor is in an online state, executing the step of transmitting the first target data to the first reception space corresponding to the first virtual address of the second processor through the PCIe bridge device based on the first virtual address.

[0153] In one embodiment, the PCIe bridge device includes multiple doorbell interruption regions, and the multiple doorbell interruption regions correspond to the multiple processors one by one. When the computer program is executed by a processor, the following steps are further implemented: triggering the second doorbell interruption region in the PCIe bridge device to instruct the PCIe bridge device to send an interruption event to the second processor, where the interruption event is used to instruct the second processor to receive the first target data transmitted from the first processor, and the second doorbell interruption region is the interruption region corresponding to the second processor.

[0154] In one embodiment, the first processor includes a plurality of receiving spaces, which correspond one-to-one to other processors in the plurality of processors except the first processor. When the computer program is executed by the processor, the following steps are further implemented: after the first processor receives an interrupt event sent by the PCIe bridge device, determine a third processor based on the interrupt event, where the third processor is the processor that sends the second target data; determine a second receiving space from the plurality of receiving spaces according to the third processor, and obtain the second target data from the second receiving space, where the second receiving space is the receiving space corresponding to the third processor.

[0155] In one embodiment, the plurality of receiving spaces are spaces shared by the first processor and the PCIe bridge device.

[0156] In one embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by the processor, the following steps are implemented:

[0157] Receive first target data written to a first sending space, where the first processor includes a plurality of sending spaces, which correspond one-to-one to other processors in the plurality of processors except the first processor, and the first sending space corresponds to a second processor; perform mapping processing on the address of the first sending space to obtain a first virtual address, and transmit the first target data to a first receiving space corresponding to the first virtual address of the second processor based on the first virtual address through the PCIe bridge device.

[0158] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: perform mapping processing on the address of the first sending space based on the direct memory access (DMA) mapping method.

[0159] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: perform mapping processing on the address of the first sending space based on the DMA mapping method through a first virtual peripheral, where the first virtual peripheral is the virtual peripheral corresponding to the first processor.

[0160] In one embodiment, the plurality of sending spaces are spaces shared by the first processor and the PCIe bridge device.

[0161] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: transmit the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first receiving space according to the first virtual address, and enables the PCIe bridge device to obtain the first target data through the first sending space, so as to transmit the first target data to the first receiving space of the second processor.

[0162] In one embodiment, the PCIe bridge device includes a plurality of information interrupt regions, and the plurality of information interrupt regions correspond to the plurality of processors one by one. When the computer program is executed by the processor, the following steps are further implemented: after the first processor goes online, broadcast through the first information interrupt region in the PCIe bridge device to prompt other processors in the plurality of processors except the first processor that the first processor has gone online and is in an online state, and the first information interrupt region is the information interrupt region corresponding to the first processor.

[0163] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: determine whether the second processor is in an online state through the second information interrupt region corresponding to the second processor; when the second processor is in an online state, execute the step of transmitting the first target data to the first receiving space corresponding to the first virtual address in the second processor through the PCIe bridge device based on the first virtual address.

[0164] In one embodiment, the PCIe bridge device includes a plurality of doorbell interrupt regions, and the plurality of doorbell interrupt regions correspond to the plurality of processors one by one. When the computer program is executed by the processor, the following steps are further implemented: trigger the second doorbell interrupt region in the PCIe bridge device to instruct the PCIe bridge device to send an interrupt event to the second processor, and the interrupt event is used to instruct the second processor to receive the first target data transmitted from the first processor, and the second doorbell interrupt region is the interrupt region corresponding to the second processor.

[0165] In one embodiment, the first processor includes a plurality of receiving spaces, and the plurality of receiving spaces correspond to other processors in the plurality of processors except the first processor one by one. When the computer program is executed by the processor, the following steps are further implemented: after the first processor receives the interrupt event sent by the PCIe bridge device, determine a third processor based on the interrupt event, and the third processor is the processor that sends the second target data; determine a second receiving space from the plurality of receiving spaces according to the third processor, and obtain the second target data from the second receiving space, and the second receiving space is the receiving space corresponding to the third processor.

[0166] In one embodiment, the plurality of receiving spaces are spaces shared by the first processor and the PCIe bridge device.

[0167] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0168] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0169] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A communication method, characterized in that, In a first processor in a PCIe architecture, the PCIe architecture includes a PCIe bridge device and multiple processors acting as master devices, the multiple processors are all connected to the PCIe bridge device, the first processor is any one of the multiple processors, and the method includes: Receiving first target data written to a first transmission space, the first processor includes multiple transmission spaces, the multiple transmission spaces correspond one-to-one with other processors among the multiple processors except the first processor, and the first transmission space corresponds to a second processor; Performing mapping processing on the address of the first transmission space to obtain a first virtual address, and transmitting the first target data to a first reception space corresponding to the first virtual address of the second processor based on the first virtual address through the PCIe bridge device.

2. The method according to claim 1, wherein The performing mapping processing on the address of the first transmission space includes: Performing mapping processing on the address of the first transmission space based on a direct memory access (DMA) mapping method.

3. The method according to claim 2, wherein The performing mapping processing on the address of the first transmission space based on the DMA mapping method includes: Performing mapping processing on the address of the first transmission space based on the DMA mapping method through a first virtual peripheral, and the first virtual peripheral is a virtual peripheral corresponding to the first processor.

4. The method according to claim 1, wherein The multiple transmission spaces are spaces shared by the first processor and the PCIe bridge device.

5. The method according to claim 1, wherein The transmitting the first target data to a first reception space corresponding to the first virtual address of the second processor based on the first virtual address through the PCIe bridge device includes: Transmitting the first virtual address to the PCIe bridge device, so that the PCIe bridge device determines the first reception space according to the first virtual address, and enables the PCIe bridge device to obtain the first target data through the first transmission space to transmit the first target data to the first reception space of the second processor.

6. The method according to claim 1, wherein The PCIe bridge device includes multiple information interruption regions, the multiple information interruption regions correspond one-to-one with the multiple processors respectively, and the method further includes: After the first processor goes online, broadcasting through a first information interruption region in the PCIe bridge device to prompt other processors among the multiple processors except the first processor that the first processor has gone online and is in an online state, and the first information interruption region is the information interruption region corresponding to the first processor.

7. The method according to claim 6, wherein Before the transmitting the first target data to a first reception space corresponding to the first virtual address of the second processor based on the first virtual address through the PCIe bridge device, the method further includes: Determining whether the second processor is in an online state through a second information interruption region corresponding to the second processor; When the second processor is in an online state, execute the step of transmitting the first target data to the first receiving space corresponding to the first virtual address in the second processor based on the first virtual address through the PCIe bridge device.

8. The method according to claim 1, wherein The PCIe bridge device includes a plurality of doorbell interrupt regions, and the plurality of doorbell interrupt regions correspond to the plurality of processors one by one. The method further includes: Trigger the second doorbell interrupt region in the PCIe bridge device to instruct the PCIe bridge device to send an interrupt event to the second processor, where the interrupt event is used to instruct the second processor to receive the first target data transmitted from the first processor, and the second doorbell interrupt region is the interrupt region corresponding to the second processor.

9. The method according to claim 1, characterized in that, The first processor includes a plurality of receiving spaces, and the plurality of receiving spaces correspond to the other processors except the first processor in the plurality of processors one by one. The method further includes: After the first processor receives the interrupt event sent by the PCIe bridge device, determine a third processor based on the interrupt event, where the third processor is the processor that sends the second target data; Determine a second receiving space from the plurality of receiving spaces according to the third processor, and obtain the second target data from the second receiving space, where the second receiving space is the receiving space corresponding to the third processor.

10. The method according to claim 9, wherein The plurality of receiving spaces are spaces shared by the first processor and the PCIe bridge device.

11. A communication device, characterized in that, The device includes: A receiving module, configured to receive the first target data written to the first sending space. The first processor includes a plurality of sending spaces, and the plurality of sending spaces correspond to the other processors except the first processor in the plurality of processors one by one. The first sending space corresponds to the second processor; An execution module, configured to perform mapping processing on the address of the first sending space to obtain a first virtual address, and transmit the first target data to the first receiving space corresponding to the first virtual address in the second processor based on the first virtual address through the PCIe bridge device.

12. A PCIe architecture, characterized in that, The PCIe architecture includes a PCIe bridge device and a plurality of processors acting as master devices; The plurality of processors are configured to implement the steps of the method according to any one of claims 1 to 10, and the PCIe bridge device is configured to implement data transmission between the plurality of processors.

13. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 10.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 10.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 10.

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