A simulation method, device, equipment, medium and product

Abstract

The present invention discloses a simulation method, device, equipment, medium and product, which is applied to the field of integrated circuit design technology, and includes: receiving a bus transaction-level access request through a transaction-level shunting sub-module, where the bus transaction-level access request is an access request from an access-side simulation model process to a storage-side simulation model process; checking whether a first target address requested by the bus transaction-level access request is within the address range of a pre-configured shared memory; accessing the shared memory based on the first target address when the first target address is within the address range of the shared memory; otherwise, sending the bus transaction-level access request to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process can respond to the bus transaction-level access request. In this way, the communication efficiency across processes during simulation can be improved, thereby improving the simulation performance.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a simulation method, device, equipment, medium and product. Background Art

[0002] In the design of a chip (i.e., IC, Integrated Circuit) system simulation model, a simulation system is composed of two or more simulation model processes. Multiple simulation model processes are connected through a RemotePort (i.e., remote port) module to construct a complete physical simulation system, and cross-process access is achieved through the RemotePort module. However, when the amount of stored access data is large or the access is frequent, due to cross-process message communication and the transmission of TLM (i.e., Transaction-Level Modeling) messages through the RemotePort, a large amount of overhead and delay will be caused, resulting in an overly long simulation time.

[0003] Therefore, how to improve the cross-process communication efficiency during simulation and thus improve the simulation performance is a problem that those skilled in the art need to solve. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide a simulation method, device, equipment, medium and product, which can improve the cross-process communication efficiency during simulation and thus improve the simulation performance.

[0005] In a first aspect, the present application provides a simulation method, including: receiving a bus transaction-level access request through a transaction-level shunt sub-module, where the bus transaction-level access request is an access request from an access-side simulation model process to a storage-side simulation model process; the transaction-level shunt sub-module is attached to a remote port module in the access-side simulation model process; checking whether a first target address requested by the bus transaction-level access request is within the address range of a pre-configured shared memory; in the case where the first target address is within the address range of the shared memory, accessing the shared memory based on the first target address; in the case where the first target address is not within the address range of the shared memory, sending the bus transaction-level access request to a remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process can respond to the bus transaction-level access request.

[0006] Second aspect, the present application provides a simulation device, including an access-side simulation model process and a storage-side simulation model process. A transaction-level shunt sub-module is attached to the remote port module of the access-side simulation model process. The transaction-level shunt sub-module includes: a bus transaction-level access request receiving unit for receiving a bus transaction-level access request, where the bus transaction-level access request is an access request of the access-side simulation model process to the storage-side simulation model process; a first address detection unit for checking whether a first target address requested by the bus transaction-level access request is within the address range of a pre-configured shared memory; a first access shunt unit for accessing the shared memory based on the first target address when the first target address is within the address range of the shared memory; and when the first target address is not within the address range of the shared memory, sending the bus transaction-level access request to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process responds to the bus transaction-level access request.

[0007] Third aspect, the present application provides an electronic device, including: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the foregoing simulation method.

[0008] Fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the foregoing simulation method are implemented.

[0009] Fifth aspect, the present application provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the foregoing simulation method are implemented.

[0010] As can be seen from the above solutions, the present application provides a simulation method, including: receiving a bus transaction-level access request through a transaction-level shunt sub-module, where the bus transaction-level access request is an access request of the access-side simulation model process to the storage-side simulation model process; the transaction-level shunt sub-module is attached to the remote port module in the access-side simulation model process; checking whether a first target address requested by the bus transaction-level access request is within the address range of a pre-configured shared memory; accessing the shared memory based on the first target address when the first target address is within the address range of the shared memory; and when the first target address is not within the address range of the shared memory, sending the bus transaction-level access request to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process responds to the bus transaction-level access request.

[0011] It can be seen that the beneficial effects of the present application are as follows: The transaction-level shunt sub-module attached to the remote port module in the access-side simulation model process receives the bus transaction-level access request. When the target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory, the shared memory is accessed; otherwise, the bus transaction-level access request is sent to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process for the storage-side simulation model process to respond. In this way, by configuring the shared memory and attaching the transaction-level shunt sub-module to the remote port module in the access-side simulation model process, the shunt of cross-process access during the simulation is achieved. Through configuration, the corresponding cross-process bus transaction-level access is accelerated by accessing the shared memory instead of through the remote port module. In this way, the communication efficiency of cross-process during the simulation can be improved, thereby improving the simulation performance. Correspondingly, a simulation device, device, medium, and product provided by the present application also have the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a flowchart of a simulation method provided by an embodiment of the present application;

[0014] Figure 2 It is a block diagram of a simulation system provided by an embodiment of the present application;

[0015] Figure 3 It is a schematic diagram of a cross-process DMI module provided by an embodiment of the present application;

[0016] Figure 4 It is a schematic diagram of the initialization control of a simulation cross-process DMI module provided by an embodiment of the present application;

[0017] Figure 5 It is a schematic diagram of the data access of a simulation system cross-process DMI module provided by an embodiment of the present application;

[0018] Figure 6 It is a schematic diagram of the top-level initialization process of a CPU-side simulation process provided by an embodiment of the present application;

[0019] Figure 7 It is a schematic diagram of the initialization process of a peripheral chip simulation process provided by an embodiment of the present application;

[0020] Figure 8 Schematic diagram of the initialization process of a shared memory management sub-module provided by an embodiment of this application;

[0021] Figure 9 Initialization process of an access-side attachment control sub-module provided by an embodiment of this application;

[0022] Figure 10 Schematic diagram of the initialization process of a storage-side attachment control sub-module provided by an embodiment of this application;

[0023] Figure 11 Schematic diagram of the working process of a transaction-level shunt sub-module provided by an embodiment of this application;

[0024] Figure 12 Schematic diagram of the working process of a storage-side access sub-module provided by an embodiment of this application;

[0025] Figure 13 Schematic diagram of the structure of a simulation device provided by an embodiment of this application;

[0026] Figure 14 Structural diagram of an electronic device provided by an embodiment of this application. Detailed implementation manners

[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] The terms "including" and "having" in the specification of the present invention and any deformations related to "including" and "having" are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed. In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the drawings and specific implementation manners.

[0029] Next, a simulation method provided by an embodiment of the present invention will be introduced in detail. Figure 1 Flowchart of a simulation method provided by an embodiment of the present invention. This simulation method includes:

[0030] Step S11: Receive a bus transaction-level access request through the transaction-level shunt sub-module. Herein, the bus transaction-level access request is an access request from an access-side simulation model process to a storage-side simulation model process; the transaction-level shunt sub-module is attached to the remote port module in the access-side simulation model process.

[0031] Herein, the storage-side simulation model process is a simulation model process including a storage module, such as a CPU (i.e., Central Processing Unit) simulation model. The access-side simulation model process is a process for accessing the storage of the storage-side simulation model process, such as a peripheral chip simulation model. In the embodiment of the present application, the transaction-level shunt sub-module is attached to the remote port module in the access-side simulation model process to perform bus transaction-level access request shunting.

[0032] Step S12: Check whether the first target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory.

[0033] In the embodiment of the present application, it is possible to check whether the first target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory based on the bus address and memory size of the pre-configured shared memory.

[0034] Herein, the bus address of the shared memory is the starting bus address of the shared memory. The bus address and memory size determine the address range of the shared memory, and further check whether the first target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory.

[0035] Step S13: When the first target address is within the address range of the shared memory, access the shared memory based on the first target address.

[0036] In the embodiment of the present application, when the first target address is within the address range of the shared memory, a first offset address can be calculated based on the first target address and the bus address of the shared memory; the shared memory is accessed based on the first offset address and the logical address corresponding to the access-side simulation model process.

[0037] It can be understood that the bus address of the shared memory is the starting bus address of the shared memory. Based on this bus address and the first target address, an offset address is calculated to obtain the first offset address. Adding the first offset address to the logical address corresponding to the access-side simulation model process can achieve access to the shared memory, and moreover, access the shared memory based on the requested access size.

[0038] In an alternative embodiment, when the first target address is within the address range of the shared memory, the access-side shared memory configuration identifier may be checked; if the access-side shared memory configuration identifier is enabled, the shared memory is accessed based on the first target address. That is, in the embodiments of the present application, whether to access the shared memory can be controlled by enabling or the access-side shared memory configuration identifier. For example, when the access-side shared memory configuration identifier is 1, it indicates enabling, and when the access-side shared memory configuration identifier is 0, it indicates disabling.

[0039] Further, before receiving the bus transaction-level access request through the transaction-level shunt sub-module, it further includes: in the access-side simulation model process, generating a unique key value of the shared memory according to the shared memory name; obtaining an operation identifier of the shared memory based on the unique key value; if the operation identifier is normal, obtaining the logical address of the access-side simulation model process accessing the shared memory.

[0040] In an alternative embodiment, the shared memory management sub-module may generate a unique key value of the shared memory according to the shared memory name; obtain an operation identifier of the shared memory based on the unique key value; if the operation identifier is normal, obtain the logical address of the access-side simulation model process accessing the shared memory. If the operation identifier is abnormal, a shared memory is created, and the logical address of the access-side simulation model process accessing the shared memory is obtained.

[0041] Further, in the embodiments of the present application, the operation identifier of the shared memory obtained based on the unique key value may also be obtained in the access-side simulation model process; the bus address and memory size corresponding to the shared memory are configured; when the configuration is successful, it is determined whether the operation identifier is abnormal; if the operation identifier is normal, the access-side shared memory configuration identifier is enabled. In an alternative embodiment, the operation identifier of the shared memory may be obtained from the shared memory management sub-module; the bus address and memory size corresponding to the shared memory are configured through the access-side attachment control sub-module; wherein, the access-side attachment control sub-module is attached to the remote port module in the access-side simulation model process; when the configuration is successful, it is determined whether the operation identifier is abnormal; if the operation identifier is normal, the access-side shared memory configuration identifier is enabled. If the operation identifier is abnormal, the access-side shared memory configuration identifier is not enabled, and a parameter configuration error is reported, and the error code is printed.

[0042] In an alternative embodiment, before generating the unique key value of the shared memory by the shared memory management sub-module according to the shared memory name, the method further includes: passing the shared memory name to the shared memory management sub-module by the access side attachment control sub-module, triggering the step of generating the unique key value of the shared memory by the shared memory management sub-module according to the shared memory name.

[0043] Step S14: When the first target address is not within the address range of the shared memory, the bus transaction-level access request is sent to the remote port module of the storage side simulation model process through the remote port module in the access side simulation model process, so that the storage side simulation model process responds to the bus transaction-level access request.

[0044] That is, when the first target address is not within the address range of the shared memory, communication is performed through the remote port module. In an alternative embodiment, the bus storage request may also be received by the storage side access sub-module, where the storage side access sub-module is attached to the storage side simulation model process; checking whether the second target address requested by the bus storage request is within the address range of the pre-configured shared memory; when the second target address is within the address range of the shared memory, accessing the shared memory based on the second target address. When the second target address is not within the address range of the shared memory, accessing the corresponding local storage space. That is, a part of the requests on the storage side access the shared memory, and a part access the storage space of non-shared memory. In an alternative embodiment, the shared memory may be partitioned from the storage space of the storage side simulation model process.

[0045] In the embodiments of the present application, checking whether the second target address requested by the bus storage request is within the address range of the pre-configured shared memory includes: checking whether the second target address requested by the bus storage request is within the address range of the pre-configured shared memory based on the bus address and memory size of the pre-configured shared memory.

[0046] In the embodiments of the present application, when the second target address is within the address range of the shared memory, accessing the shared memory based on the second target address includes: when the second target address is within the address range of the shared memory, calculating a second offset address based on the second target address and the bus address of the shared memory; accessing the shared memory based on the second offset address and the logical address corresponding to the storage side simulation model process.

[0047] In the embodiment of the present application, when the second target address is within the address range of the shared memory, accessing the shared memory based on the second target address includes: when the second target address is within the address range of the shared memory, checking the storage-side shared memory configuration identifier; if the storage-side shared memory configuration identifier is enabled, accessing the shared memory based on the second target address.

[0048] In the embodiment of the present application, before receiving a bus storage request through the storage-side access sub-module, it may further include: in the storage-side simulation model process, generating a unique key value of the shared memory by the shared memory management sub-module according to the shared memory name; obtaining an operation identifier of the shared memory based on the unique key value; if the operation identifier is normal, obtaining the logical address for the storage-side simulation model process to access the shared memory; if the operation identifier is abnormal, creating a shared memory and obtaining the logical address for the storage-side simulation model process to access the shared memory.

[0049] Furthermore, the embodiment of the present application further includes: obtaining the operation identifier of the shared memory from the shared memory management sub-module; configuring the bus address and memory size corresponding to the shared memory through the storage-side attachment control sub-module; where the storage-side attachment control sub-module is attached to the storage-side simulation model process; judging whether the operation identifier is abnormal in the case of successful configuration; if the operation identifier is normal, enabling the storage-side shared memory configuration identifier; if the operation identifier is abnormal, the storage-side shared memory configuration identifier is not enabled, and a parameter configuration error is reported, and the error code is printed. For example, the storage-side shared memory configuration identifier being 1 indicates enabling, and the storage-side shared memory configuration identifier being 0 indicates not enabling. In a specific implementation manner, the storage-side attachment control sub-module may be attached to the storage module in the storage-side simulation model process.

[0050] It can be understood that the access-side simulation model process and the storage-side simulation model process share the shared memory for communication. One interaction scenario is: the access-side simulation model process accesses the shared memory, reads the data written by the storage-side simulation model process into the shared memory, then returns the calculation result corresponding to the data to the shared memory, and the storage-side simulation model process reads the calculation result from the shared memory again.

[0051] It can be seen that in the embodiment of the present application, the transaction-level shunt sub-module attached to the remote port module in the access-side simulation model process receives the bus transaction-level access request. When the target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory, the shared memory is accessed; otherwise, the bus transaction-level access request is sent to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process for the storage-side simulation model process to respond. In this way, by configuring the shared memory and attaching the transaction-level shunt sub-module to the remote port module in the access-side simulation model process, the shunt of cross-process access during the simulation is realized. Through configuration, the corresponding cross-process bus transaction-level access is accelerated by accessing the shared memory instead of through the remote port module to implement the cross-process bus transaction-level access. In this way, the communication efficiency of cross-process during the simulation can be improved, thereby improving the simulation performance.

[0052] Next, taking the access-side simulation model process as the CPU simulation model process and the storage-side simulation model process as the peripheral chip simulation model process as an example, the simulation solution provided by the present application will be further elaborated: For peripheral chip design, when building a system function model simulation environment, the CPU function model and other peripheral function models are usually separated. Since the CPU chip function simulation model is complex in function and rarely modified, the CPU model will be selected to run as an independent process. Since the peripheral simulation model needs to perform functional simulation modeling and will be frequently modified, the peripheral simulation model is usually separated from the CPU model to facilitate the rapid iterative development of the peripheral chip simulation model. Refer to Figure 2 as shown, Figure 2 is a block diagram of a simulation system provided by an embodiment of the present application. As Figure 2 shown, the CPU simulation model process includes a CPU simulation module, a bus simulation module, and a remote port module. The peripheral chip simulation model includes a peripheral chip simulation storage module, a peripheral chip simulation core module, a peripheral chip bus simulation module, and a remote port module. The present invention adds a cross-process DMI (i.e., Direct Memory Interface) module. Among them, the cross-process DMI module is connected to the CPU simulation model process on the left, and the cross-process DMI module is also connected to the peripheral chip simulation model on the right. Figure 2The accessed storage module is in the simulation model process on the right. The access is initiated by the CPU simulation model process on the left. Conversely, if the storage module is in the CPU simulation model process on the left, the access is initiated by the peripheral chip simulation model process on the right, based on the same principle. The present invention provides a method for constructing a SystemC (i.e., a library written in C++ for simulation modeling)-TLM cross-process DMI simulation model. Based on the SystemC-TLM framework, a cross-process DMI mechanism is established, and a transaction-level functional simulation model that supports cross-process access to the storage model is built using this cross-process DMI mechanism, to solve the problem of low efficiency in cross-process access to the storage model in the cross-process simulation model, save the resources consumed by the simulation system, and improve the performance of the simulation system.

[0053] Further, referring to Figure 3 as shown in Figure 3 FIG. is a schematic diagram of a cross-process DMI module provided by an embodiment of the present application. It includes a transaction-level shunt sub-module, a storage-side access sub-module, a shared memory management sub-module, a shared memory, an access-side attachment control sub-module, and a storage-side attachment control sub-module. Among them, the access-side attachment control sub-module, the storage-side attachment control sub-module, and the shared memory management sub-module are responsible for initializing and controlling related processes. Among them, the transaction-level shunt sub-module and the storage-side access sub-module are responsible for transaction-level shunt processing. The transaction-level shunt sub-module is responsible for transaction-level shunt processing of accessing the storage module of the remote process, and the storage-side access sub-module is responsible for transaction-level access shunt processing of the local storage module. The shared memory provides a shared memory processing function after shunting.

[0054] Referring to Figure 4 as shown in Figure 4 FIG. is a schematic diagram of initializing and controlling a simulation cross-process DMI module provided by an embodiment of the present application. As Figure 4 shown, it is the control relationship between the simulation system cross-process DMI module and each process of the simulation system during initialization. When the simulation system cross-process DMI module is initialized, the shared memory management sub-module is responsible for creating the shared memory, attaching the shared memory information to the RemotePort (i.e., remote port) module through the access-side attachment control sub-module, and attaching the shared memory information to the peripheral chip simulation storage module through the storage-side attachment control sub-module.

[0055] Referring to Figure 5 as shown in Figure 5 FIG. is a schematic diagram of data access of a simulation system cross-process DMI module provided by an embodiment of the present application. As Figure 5As shown, it is the data access relationship between the cross-process DMI module of the simulation system and each process of the simulation system. When the simulation system is running, when the CPU simulation model process on the left needs to perform cross-process access to the storage space of the peripheral chip simulation model process on the right, the transaction-level shunt sub-module inside the RemotePort module checks whether the accessed transaction hits the shared memory. If it hits, the access is shunted to the shared memory for processing through the transaction-level shunt sub-module and the transaction result of the access is returned. If it does not hit, the transaction-level access is still initiated to the remote process through the original transaction-level access path. When the simulation system is running, when the peripheral chip simulation model process on the right needs to access its own storage space, the peripheral chip bus simulation module inside the peripheral chip simulation model initiates an access to the storage module. After receiving the transaction request, the storage module calls the storage-side access sub-module to check whether the accessed transaction hits the shared memory. If it hits, the transaction is shunted to the shared memory and the transaction result of the access is returned. If it does not hit, the access to the memory inside the storage module is still initiated through the original transaction-level access path. That is, when the CPU simulation model process on the left needs to access the peripheral chip simulation storage module of the peripheral chip simulation model process on the right, the CPU simulation module accesses the RemotePort module of the peripheral chip simulation model process on the right through the bus simulation module, and the bus simulation module accesses the RemotePort module. Then, the peripheral chip bus simulation module on the right is used to access the peripheral chip simulation storage module.

[0056] Further, refer to Figure 6 as shown Figure 6 which is a schematic diagram of the top-level initialization process of the CPU-side simulation process provided by the embodiment of the present application. Figure 6This is the process of initializing the simulation process on the CPU side of the simulation system. When initializing the simulation process on the CPU side of the simulation system, the first part is the pre-initialization, including S1001: Initialization of the SystemC-TLM simulation basic library and initialization of the simulation system bus, that is, initializing the simulation basic library based on SystemC's TLM, initializing the system bus of the top-level module of the simulation system. The simulation system bus is responsible for connecting each simulation unit and processing bus requests and responses. It also includes S1002: Initializing other simulation devices to prepare for building the simulation process on the CPU side. The second part is S1003: Connecting the remote process simulation device, including creating a RemotePort port, creating a notification event, creating global variables, creating a transaction-level master access port of RemotePort, and a transaction-level slave access port. The third part, S1004: Calling the initialization of the attachment control sub-module on the access side. The attachment control sub-module on the access side will configure the name of the shared memory, the start address and end address of the transaction-level request corresponding to the shared memory. Call the shared memory management sub-module to initialize the shared memory. Finally, the top-level initialization of the simulation process on the CPU side of the simulation system is completed, and the simulation system runs.

[0057] Further, refer to Figure 7 as shown Figure 7 This is a schematic diagram of the initialization process of the peripheral chip simulation process provided by the embodiment of the present application. As Figure 7 shown, this is the process of initializing the simulation process of the peripheral chip of the simulation system. When initializing the simulation process of the peripheral chip of the simulation system, the first part is the pre-initialization, including S2001: Initialization of the SystemC-TLM simulation basic library and initialization of the simulation system bus, that is, initializing the simulation basic library based on SystemC's TLM, initializing the peripheral bus of the top-level module of the simulation system. The simulation system peripheral bus is responsible for connecting each simulation peripheral unit and processing bus requests and responses. It also includes S2002: Initializing other simulation peripheral devices to prepare for building the simulation process of the peripheral chip. The second part is S2003: Initializing the simulation storage device of the peripheral chip, including creating a storage unit, creating a notification event, creating global variables. It also includes S2004: Initialization of the attachment control sub-module on the storage side. The attachment control sub-module on the storage side will configure the name of the shared memory, the start address and end address of the transaction-level request corresponding to the shared memory. Call the shared memory management sub-module to initialize the shared memory. Perform a clearing operation on the storage unit, including clearing the shared memory unit. The third part, S2005: Connecting the remote process simulation device, that is, creating a transaction-level master access port and a transaction-level slave access port of RemotePort, and connecting them to the RemotePort port of the remote CPU-side simulation process. Finally, the top-level initialization of the simulation process of the peripheral chip of the simulation system is completed.

[0058] Further, refer toFigure 8 As shown Figure 8 This is a schematic diagram of the initialization process of a shared memory management sub-module provided by an embodiment of the present application. The initialization process of the shared memory management sub-module is as follows: S3001: Call the ftok (i.e., file-to-key conversion function) system function according to the shared memory name to generate a unique key value for the system. S3002: Call the shmget (i.e., shared memory get function) system function to obtain the shared memory operation identifier. Check the returned identifier. If it is normal, go to S3003; if it is abnormal, go to S3004. S3003: Call the shmat (i.e., shared memory attach function) system function to obtain the process logical address for accessing the shared memory. S3004: If the error code indicates that the shared memory does not exist, create the shared memory and call the shmat system function to obtain the process logical address for accessing the shared memory.

[0059] Further, refer to Figure 9 As shown Figure 9 This is an initialization process of an access-side attachment control sub-module provided by an embodiment of the present application. The initialization process of the access-side attachment control sub-module may include: S4001: Initialize the shared memory, and call the shared memory management sub-module to initialize the shared memory. S4002: Obtain the shared memory operation identifier. S4003: Configure the bus address and memory size of the memory corresponding to the shared memory. S4004: Check whether the configuration is successful. S4005: Judge the identifier returned by S4002; if it is normal, go to S4006; if it is abnormal, go to S4007. S4006: Enable the access-side shared memory configuration flag. S4007: Report a parameter configuration error, print the error code, and do not enable the access-side shared memory configuration flag.

[0060] Further, refer to Figure 10 As shown Figure 10 This is a schematic diagram of the initialization process of a storage-side attachment control sub-module provided by an embodiment of the present application. The initialization process of the storage-side attachment control sub-module may include: S5001: Initialize the shared memory, and call the shared memory management sub-module to initialize the shared memory. S5002: Obtain the shared memory operation identifier. S5003: Configure the bus address and memory size of the memory corresponding to the shared memory, where the bus address is the starting address. S5004: Check whether the configuration is successful. S5005: Judge the identifier returned by S5002; if it is normal, go to S5006; if it is abnormal, go to S5007. S5006: Enable the storage-side shared memory configuration flag. S5007: Report a parameter configuration error, print the error code, and do not enable the storage-side shared memory configuration flag.

[0061] Further, refer to Figure 11 As shown Figure 11A schematic diagram of the working process of a transaction-level shunt sub-module provided by an embodiment of the present application. The working process of the transaction-level shunt sub-module may include: S6001: The transaction-level shunt sub-module receives a cross-process bus transaction-level request. S6002: Check whether the requested address is shared memory. S6002 calls the specific method in S6003 for detection. S6003: By comparing the requested address with the bus address and memory size of the memory corresponding to the shared memory initialized and configured by the access-side attachment control sub-module, if the address is within the configured address range and the access-side shared memory configuration flag is enabled, proceed to S6004 for processing, otherwise proceed to S6005 for processing. S6004: Calculate the offset between the requested address and the bus address of the memory corresponding to the shared memory initialized and configured by the access-side attachment control sub-module, and access the shared memory through the offset and the requested access size. S6005: The original cross-process transaction-level access processing. Send a cross-process access transaction-level request message and receive a remote response message. S6006: Reply with a transaction-level response.

[0062] Further, refer to Figure 12 as shown in Figure 12 A schematic diagram of the working process of a storage-side access sub-module provided by an embodiment of the present application. The working process of the storage-side access sub-module may include: S7001: The storage-side access sub-module receives a bus storage request. S7002: Check whether the requested address is shared memory. S7003: By comparing the requested address with the bus address and memory size of the memory corresponding to the shared memory initialized and configured by the storage-side attachment control sub-module, if the address is within the configured address range and the storage-side shared memory configuration flag is enabled, proceed to S7004 for processing, otherwise proceed to S7005 for processing. S7004: Calculate the offset between the requested address and the bus address of the memory corresponding to the shared memory initialized and configured by the storage-side attachment control sub-module, and access the shared memory through the offset and the requested access size. S7005: Access the storage space corresponding to the original local storage. S7006: Reply with a transaction-level response.

[0063] Through the above method, a functional model supporting cross-process memory transaction accelerated access can be constructed in the simulation system. The software can build a simulation system based on this simulation model, perform program debugging and testing in the simulation system, and perform high-speed transaction-level access to the storage space of cross-process simulation devices, reducing the transaction-level access time for cross-process access to the simulation storage model and improving the efficiency of cross-process transaction access to the storage model.

[0064] The present invention proposes a method for constructing a cross-process DMI simulation model based on SystemC-TLM. Based on the SystemC framework, it performs transaction-level shunting on cross-process memory accesses, establishes a cross-process shared memory simulation system, and constructs a system in this way that can support fast access to the storage simulation model across processes, solving the problem of low performance in accessing the storage model across processes in the chip simulation function model during the chip R & D process. By adopting the modeling method based on SystemC-TLM, it uses the shared memory model to accelerate the simulation design of accessing the cross-process storage model and constructs a cross-process chip function simulation model. The newly constructed function simulation system can support fast access to the cross-process storage module.

[0065] The present invention uses the modeling method based on SystemC-TLM. The shared memory is attached to the simulation design of the simulation model, providing a method for configuring the shared memory of the TLM model based on SystemC, configuring the shared memory to be accessed, which facilitates subsequent shared memory access. Using the modeling method based on SystemC-TLM, for the simulation design of remote port transaction-level access shunting, when the cross-process function simulation model constructed based on the TLM model of SystemC runs and needs to initiate a cross-process storage access, according to the shared memory configuration of the remote port for cross-process communication, if the access falls within the address range of the shared memory, then this transaction-level access enters the processing of the shared memory, achieving fast access to the remote storage model. Using the modeling method based on SystemC-TLM, on the basis of transaction-level shunting, it uses the shared memory model to accelerate the simulation design of accessing the cross-process storage model. When constructing a cross-process function simulation system based on the TLM model of SystemC, the function simulation system can support frequent and fast access to the remote storage model, improving the overall performance of the function simulation system.

[0066] In this way, by adopting the modeling method based on SystemC-TLM, on the basis of transaction-level shunting, it uses the shared memory model to accelerate the access design of the cross-process storage model, accelerating the transaction-level access to the cross-process access storage simulation model. After adopting the above scheme, the access time for a single transaction-level access to the cross-process storage simulation model can be shortened. When the chip simulation system constructs a function model and frequently accesses the storage model across processes, it can shorten the simulation model running time of the entire function model system and improve the overall performance of the function simulation model.

[0067] Furthermore, the simulation functional model of the present invention consists of multiple processes to form a simulation system, and completes cross-process DMI access through shared memory. In this way, a transaction-level functional simulation model is built to solve the problem of low efficiency of cross-process access to the storage model during chip R & D. Although the described implementation of the present invention uses a design based on a cross-process DMI simulation model of SystemC-TLM, the method of building a functional simulation model system for cross-process DMI access using the above-mentioned SystemC-TLM-based transaction-level model is only for facilitating the understanding of the implementation manner of the present invention, and is not intended to limit the present invention. Any modifications and changes made without departing from the design and scope of the present invention, especially the modifications and changes to the relevant system schematic diagrams, mapping relationships, and relevant firmware frameworks, are within the protection scope of the present invention.

[0068] Furthermore, referring to Figure 13 As shown, a simulation device provided by an embodiment of the present application includes an access-side simulation model process and a storage-side simulation model process. A transaction-level shunt sub-module is attached to the remote port module of the access-side simulation model process. The transaction-level shunt sub-module includes:

[0069] A bus transaction-level access request receiving unit 11, configured to receive a bus transaction-level access request, where the bus transaction-level access request is an access request from the access-side simulation model process to the storage-side simulation model process;

[0070] A first address detection unit 12, configured to check whether a first target address requested by the bus transaction-level access request is within the address range of a pre-configured shared memory;

[0071] A first access shunt unit 13, configured to, when the first target address is within the address range of the shared memory, access the shared memory based on the first target address; and when the first target address is not within the address range of the shared memory, send the bus transaction-level access request to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process responds to the bus transaction-level access request.

[0072] Among them, the first address detection unit 12 may be configured to check whether the first target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory based on the bus address and memory size of the pre-configured shared memory.

[0073] The first access shunting unit 13 can be used to calculate a first offset address based on the first target address and the bus address of the shared memory when the first target address is within the address range of the shared memory; and access the shared memory based on the first offset address and the logical address corresponding to the access-side simulation model process.

[0074] The first access shunting unit 13 can be used to check the access-side shared memory configuration identifier when the first target address is within the address range of the shared memory; if the access-side shared memory configuration identifier is enabled, access the shared memory based on the first target address.

[0075] Further, the device further includes a shared memory management sub-module, which is used to generate a unique key value of the shared memory according to the shared memory name; obtain an operation identifier of the shared memory based on the unique key value; if the operation identifier is normal, obtain the logical address for the access-side simulation model process to access the shared memory. If the operation identifier is abnormal, create a shared memory and obtain the logical address for the access-side simulation model process to access the shared memory.

[0076] The remote port module in the access-side simulation model process further includes an access-side attachment control sub-module, which is used to obtain the operation identifier of the shared memory from the shared memory management sub-module; configure the bus address and memory size corresponding to the shared memory through the access-side attachment control sub-module; wherein, the access-side attachment control sub-module is attached to the remote port module in the access-side simulation model process; determine whether the operation identifier is abnormal in the case of successful configuration; if the operation identifier is normal, enable the access-side shared memory configuration identifier. If the operation identifier is abnormal, the access-side shared memory configuration identifier is not enabled, and a parameter configuration error is reported, and the error code is printed.

[0077] The access-side attachment control sub-module is further used to pass the shared memory name to the shared memory management sub-module through the access-side attachment control sub-module before the shared memory management sub-module generates the unique key value of the shared memory according to the shared memory name, triggering the step of generating the unique key value of the shared memory by the shared memory management sub-module according to the shared memory name.

[0078] Further, the storage - side simulation model process further includes a storage - side access sub - module. The storage - side access sub - module may include: a bus storage request receiving unit for receiving a bus storage request; a second address detection unit for checking whether a second target address requested by the bus storage request is within the address range of a pre - configured shared memory; and a second access shunting unit for accessing the shared memory based on the second target address when the second target address is within the address range of the shared memory, and accessing a corresponding local storage space when the second target address is not within the address range of the shared memory. Among them, the second address detection unit may be used to: check whether the second target address requested by the bus storage request is within the address range of the pre - configured shared memory based on the bus address and memory size of the pre - configured shared memory.

[0079] The second access shunting unit may be used to calculate a second offset address based on the second target address and the bus address of the shared memory when the second target address is within the address range of the shared memory; and access the shared memory based on the second offset address and the logical address corresponding to the storage - side simulation model process.

[0080] The second access shunting unit may be used to check the storage - side shared memory configuration identifier when the second target address is within the address range of the shared memory; if the storage - side shared memory configuration identifier is enabled, access the shared memory based on the second target address.

[0081] The shared memory management sub - module is further used to generate a unique key value of the shared memory according to the shared memory name in the storage - side simulation model process; obtain an operation identifier of the shared memory based on the unique key value; if the operation identifier is normal, obtain the logical address for the storage - side simulation model process to access the shared memory; if the operation identifier is abnormal, create a shared memory and obtain the logical address for the storage - side simulation model process to access the shared memory.

[0082] The storage - side simulation model process further includes a storage - side attachment control sub - module for obtaining the operation identifier of the shared memory from the shared memory management sub - module; configuring the bus address and memory size corresponding to the shared memory; where the storage - side attachment control sub - module is attached to the storage - side simulation model process; judging whether the operation identifier is abnormal in the case of successful configuration; if the operation identifier is normal, enabling the storage - side shared memory configuration identifier; if the operation identifier is abnormal, the storage - side shared memory configuration identifier is not enabled.

[0083] It can be seen that, in the embodiment of the present application, the transaction-level shunting sub-module attached to the remote port module in the access-side simulation model process receives the bus transaction-level access request. When the target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory, the shared memory is accessed; otherwise, the bus transaction-level access request is sent to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process for the storage-side simulation model process to respond. In this way, by configuring the shared memory and attaching the transaction-level shunting sub-module to the remote port module in the access-side simulation model process, the shunting of cross-process access during the simulation is achieved. Through configuration, the corresponding cross-process bus transaction-level access is accelerated by accessing the shared memory instead of implementing the cross-process bus transaction-level access through the remote port module. In this way, the communication efficiency of cross-process during the simulation can be improved, thereby enhancing the simulation performance.

[0084] Figure 13 For the description of the features in the corresponding embodiment, reference can be made to Figure 13 the relevant description of the corresponding embodiment, which will not be elaborated here one by one.

[0085] Figure 14 The following is a structural diagram of an electronic device provided by an embodiment of the present invention. As Figure 14 shown, the electronic device includes: a memory 20 for storing a computer program; a processor 21 for implementing the steps of the simulation method in the above embodiment when executing the computer program. Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may further include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0086] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may further include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices and flash memory storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201. After the computer program is loaded and executed by the processor 21, the relevant steps of the simulation method disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory 20 may further include an operating system 202 and data 203, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, stored data, etc. In some embodiments, the electronic device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26. Those skilled in the art can understand that Figure 14 the structure shown in

[0087] does not constitute a limitation on the electronic device, and may include more or fewer components than those shown in the figure. It can be understood that if the simulation method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The foregoing storage media include: USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, magnetic disks, or optical disks, etc., which can store program codes.

[0088] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be implemented: receiving a bus transaction-level access request through a transaction-level shunt sub-module, where the bus transaction-level access request is an access request from an access-side simulation model process to a storage-side simulation model process; the transaction-level shunt sub-module is attached to a remote port module in the access-side simulation model process; checking whether a first target address requested by the bus transaction-level access request is within the address range of a pre-configured shared memory; accessing the shared memory based on the first target address when the first target address is within the address range of the shared memory; and when the first target address is not within the address range of the shared memory, sending the bus transaction-level access request to a remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process can respond to the bus transaction-level access request.

[0089] It can be seen that in the embodiment of the present application, the transaction-level shunt sub-module attached to the remote port module in the access-side simulation model process receives the bus transaction-level access request. When the target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory, the shared memory is accessed; otherwise, the bus transaction-level access request is sent to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process can respond. In this way, by configuring the shared memory and attaching the transaction-level shunt sub-module to the remote port module in the access-side simulation model process, the shunt of cross-process access during the simulation is realized. Through configuration, the corresponding cross-process bus transaction-level access is accelerated by accessing the shared memory instead of through the remote port module. In this way, the communication efficiency of cross-process during the simulation can be improved, thereby improving the simulation performance.

[0090] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: checking whether a first target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory based on the bus address and memory size of the pre-configured shared memory.

[0091] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: when the first target address is within the address range of the shared memory, calculating a first offset address based on the first target address and the bus address of the shared memory; and accessing the shared memory based on the first offset address and the logical address corresponding to the access-side simulation model process.

[0092] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: When the first target address is within the address range of the shared memory, check the access-side shared memory configuration identifier; if the access-side shared memory configuration identifier is enabled, access the shared memory based on the first target address.

[0093] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: Generate a unique key value of the shared memory by the shared memory management sub-module according to the shared memory name; obtain an operation identifier of the shared memory based on the unique key value; if the operation identifier is normal, obtain a logical address for the access-side simulation model process to access the shared memory.

[0094] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: If the operation identifier is abnormal, create a shared memory and obtain a logical address for the access-side simulation model process to access the shared memory.

[0095] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: Obtain the operation identifier of the shared memory from the shared memory management sub-module; configure the bus address and memory size corresponding to the shared memory through the access-side attachment control sub-module; where the access-side attachment control sub-module is attached to the remote port module in the access-side simulation model process; determine whether the operation identifier is abnormal in the case of successful configuration; if the operation identifier is normal, enable the access-side shared memory configuration identifier.

[0096] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: After determining whether the operation identifier is abnormal in the case of successful configuration, if the operation identifier is abnormal, the access-side shared memory configuration identifier is not enabled, and a parameter configuration error is reported, and the error code is printed.

[0097] In this embodiment, when the processor executes the computer program stored in the memory, before generating the unique key value of the shared memory by the shared memory management sub-module according to the shared memory name, the following steps are further included: Pass the shared memory name to the shared memory management sub-module through the access-side attachment control sub-module, triggering the step of generating the unique key value of the shared memory by the shared memory management sub-module according to the shared memory name.

[0098] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: receiving a bus storage request through a storage-side access sub-module, where the storage-side access sub-module is attached to the storage-side simulation model process; checking whether a second target address requested by the bus storage request is within an address range of a pre-configured shared memory; and accessing the shared memory based on the second target address when the second target address is within the address range of the shared memory.

[0099] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: accessing a corresponding local storage space when the second target address is not within the address range of the shared memory.

[0100] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: checking whether a second target address requested by the bus storage request is within an address range of a pre-configured shared memory based on a bus address and a memory size of the pre-configured shared memory.

[0101] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: calculating a second offset address based on the second target address and the bus address of the shared memory when the second target address is within the address range of the shared memory; and accessing the shared memory based on the second offset address and a logical address corresponding to the storage-side simulation model process.

[0102] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: checking a storage-side shared memory configuration flag when the second target address is within the address range of the shared memory; and accessing the shared memory based on the second target address if the storage-side shared memory configuration flag is enabled.

[0103] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: in the storage-side simulation model process, generating a unique key value of the shared memory by a shared memory management sub-module according to a shared memory name; obtaining an operation identifier of the shared memory based on the unique key value; obtaining a logical address for the storage-side simulation model process to access the shared memory if the operation identifier is normal; and creating a shared memory and obtaining a logical address for the storage-side simulation model process to access the shared memory if the operation identifier is abnormal.

[0104] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: obtaining an operation identifier of the shared memory from the shared memory management sub-module; configuring a bus address and a memory size corresponding to the shared memory through the storage-side attachment control sub-module, where the storage-side attachment control sub-module is attached to the storage-side simulation model process; determining whether the operation identifier is abnormal in the case of successful configuration; if the operation identifier is normal, enabling the storage-side shared memory configuration identifier; if the operation identifier is abnormal, the storage-side shared memory configuration identifier is not enabled.

[0105] The following introduces a computer-readable storage medium provided by an embodiment of the present application. The computer-readable storage medium described below may be referred to each other with other embodiments described herein. An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above simulation method are implemented.

[0106] In this embodiment, the computer program executed by the processor may implement the following steps: receiving a bus transaction-level access request through the transaction-level shunt sub-module, where the bus transaction-level access request is an access request from the access-side simulation model process to the storage-side simulation model process; the transaction-level shunt sub-module is attached to the remote port module in the access-side simulation model process; checking whether a first target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory; accessing the shared memory based on the first target address in the case where the first target address is within the address range of the shared memory; in the case where the first target address is not within the address range of the shared memory, sending the bus transaction-level access request to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process responds to the bus transaction-level access request.

[0107] It can be seen that in the embodiment of the present application, the transaction-level shunt sub-module attached to the remote port module in the access-side simulation model process receives the bus transaction-level access request. When the target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory, the shared memory is accessed; otherwise, the bus transaction-level access request is sent to the remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process for the storage-side simulation model process to respond. In this way, by configuring the shared memory and attaching the transaction-level shunt sub-module to the remote port module in the access-side simulation model process, the shunt of cross-process access during the simulation is realized. Through configuration, the corresponding cross-process bus transaction-level access is accelerated by accessing the shared memory instead of through the remote port module. In this way, the communication efficiency of cross-process during the simulation can be improved, thereby improving the simulation performance.

[0108] Furthermore, the embodiment of the present application also provides a computer program product, including computer programs / instructions. When the computer programs / instructions are executed by a processor, the steps of the foregoing simulation method are implemented. For the specific process of the foregoing simulation method, reference may be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0109] The foregoing has introduced in detail a simulation method, apparatus, device, medium, and product provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and the key points of each embodiment are the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part. Professionals can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0110] The above has introduced in detail a simulation method, device, equipment, medium and product provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A simulation method, characterized in that, Including: Receiving a bus transaction-level access request through a transaction-level shunt sub-module, where the bus transaction-level access request is an access request from an access-side simulation model process to a storage-side simulation model process; the transaction-level shunt sub-module is attached to a remote port module in the access-side simulation model process; Checking whether a first target address requested by the bus transaction-level access request is within an address range of a pre-configured shared memory; When the first target address is within the address range of the shared memory, accessing the shared memory based on the first target address; When the first target address is not within the address range of the shared memory, sending the bus transaction-level access request to a remote port module of the storage-side simulation model process through the remote port module in the access-side simulation model process, so that the storage-side simulation model process responds to the bus transaction-level access request.

2. The simulation method according to claim 1, wherein Checking whether a first target address requested by the bus transaction-level access request is within an address range of a pre-configured shared memory includes: Checking whether the first target address requested by the bus transaction-level access request is within the address range of the pre-configured shared memory based on the bus address and memory size of the pre-configured shared memory.

3. The simulation method according to claim 2, wherein When the first target address is within the address range of the shared memory, accessing the shared memory based on the first target address includes: When the first target address is within the address range of the shared memory, calculating a first offset address based on the first target address and the bus address of the shared memory; Accessing the shared memory based on the first offset address and the logical address corresponding to the access-side simulation model process.

4. The simulation method according to claim 3, wherein When the first target address is within the address range of the shared memory, accessing the shared memory based on the first target address includes: When the first target address is within the address range of the shared memory, checking an access-side shared memory configuration identifier; If the access-side shared memory configuration identifier is enabled, accessing the shared memory based on the first target address.

5. The simulation method according to claim 4, wherein Before receiving the bus transaction-level access request through the transaction-level shunt sub-module, further including: Generating a unique key value of the shared memory by a shared memory management sub-module according to the shared memory name; Obtaining an operation identifier of the shared memory based on the unique key value; If the operation identifier is normal, obtaining the logical address for the access-side simulation model process to access the shared memory.

6. The simulation method according to claim 5, wherein Also including: If the operation identifier is abnormal, creating a shared memory and obtaining the logical address for the access-side simulation model process to access the shared memory.

7. The simulation method according to claim 6, wherein Also including: Obtaining the operation identifier of the shared memory from the shared memory management sub-module; Configuring the bus address and memory size corresponding to the shared memory through an access-side attachment control sub-module; where the access-side attachment control sub-module is attached to a remote port module in the access-side simulation model process; Judging whether the operation identifier is abnormal in the case of successful configuration; If the operation identifier is normal, enable the access-side shared memory configuration identifier.

8. The simulation method according to claim 7, wherein After determining whether the operation identifier is normal in the case of successful configuration, it further includes: If the operation identifier is abnormal, the access-side shared memory configuration identifier is not enabled, and a parameter configuration error is reported, and the error code is printed.

9. The simulation method according to claim 8, characterized in that, Before the shared memory management sub-module generates the unique key value of the shared memory according to the shared memory name, it further includes: The access-side attachment control sub-module passes the shared memory name to the shared memory management sub-module, triggering the step of generating the unique key value of the shared memory by the shared memory management sub-module according to the shared memory name.

10. The simulation method according to claim 1, characterized in that, It further includes: The storage-side access sub-module receives a bus storage request, where the storage-side access sub-module is attached to the storage-side simulation model process; Check whether the second target address requested by the bus storage request is within the address range of the pre-configured shared memory; In the case where the second target address is within the address range of the shared memory, access the shared memory based on the second target address.

11. The simulation method according to claim 10, wherein It further includes: In the case where the second target address is not within the address range of the shared memory, access the corresponding local storage space.

12. The simulation method according to claim 10, characterized in that, Checking whether the second target address requested by the bus storage request is within the address range of the pre-configured shared memory includes: Based on the bus address and memory size of the pre-configured shared memory, check whether the second target address requested by the bus storage request is within the address range of the pre-configured shared memory.

13. The simulation method according to claim 12, wherein In the case where the second target address is within the address range of the shared memory, accessing the shared memory based on the second target address includes: In the case where the second target address is within the address range of the shared memory, calculate the second offset address based on the second target address and the bus address of the shared memory; Access the shared memory based on the second offset address and the logical address corresponding to the storage-side simulation model process.

14. The simulation method according to claim 13, characterized in that, In the case where the second target address is within the address range of the shared memory, accessing the shared memory based on the second target address includes: In the case where the second target address is within the address range of the shared memory, check the storage-side shared memory configuration identifier; If the storage-side shared memory configuration identifier is enabled, access the shared memory based on the second target address.

15. The simulation method according to claim 14, wherein Before the storage-side access sub-module receives a bus storage request, it further includes: In the storage-side simulation model process, the shared memory management sub-module generates the unique key value of the shared memory according to the shared memory name; Obtain the operation identifier of the shared memory based on the unique key value; If the operation identifier is normal, obtain the logical address for the storage-side simulation model process to access the shared memory; If the operation identifier is abnormal, create a shared memory and obtain the logical address for the storage-side simulation model process to access the shared memory.

16. The simulation method according to claim 15, wherein It further includes: Obtain the operation identifier of the shared memory from the shared memory management sub-module; Configure the bus address and memory size corresponding to the shared memory through the storage - side attachment control sub - module; wherein, the storage - side attachment control sub - module is attached to the storage - side simulation model process; Judge whether the operation identifier is abnormal when the configuration is successful; If the operation identifier is normal, enable the storage - side shared memory configuration identifier; If the operation identifier is abnormal, the storage - side shared memory configuration identifier is not enabled.

17. A simulation device, characterized in that, It includes an access - side simulation model process and a storage - side simulation model process. The remote port module of the access - side simulation model process is attached with a transaction - level shunt sub - module, and the transaction - level shunt sub - module includes: A bus transaction - level access request receiving unit, which is used to receive a bus transaction - level access request. Among them, the bus transaction - level access request is an access request from the access - side simulation model process to the storage - side simulation model process; A first address detection unit, which is used to check whether the first target address requested by the bus transaction - level access request is within the address range of the pre - configured shared memory; A first access shunt unit, which is used to access the shared memory based on the first target address when the first target address is within the address range of the shared memory; when the first target address is not within the address range of the shared memory, send the bus transaction - level access request to the remote port module of the storage - side simulation model process through the remote port module in the access - side simulation model process, so that the storage - side simulation model process responds to the bus transaction - level access request.

18. An electronic device, characterized in that, It includes: A memory, which is used to store a computer program; A processor, which is used to execute the computer program to implement the steps of the simulation method according to any one of claims 1 to 16.

19. A computer-readable storage medium, characterized in that, A computer program is stored on the computer - readable storage medium, and when the computer program is executed by the processor, it implements the steps of the simulation method according to any one of claims 1 to 16.

20. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, it implements the steps of the simulation method according to any one of claims 1 to 16.

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