Analog chip design method and device

Abstract

The invention provides an analog chip design method and device, and the method comprises the steps: obtaining an analog layout constraint file which comprises an electrical constraint definition, a physical constraint definition, a layout design rule definition and an NDR definition; and generating an analog chip design file according to the layout constraint file, wherein the analog chip design file comprises a layout of analog design. According to the method provided by the invention, the design efficiency of the analog chip can be improved.

Description

Technical Field

[0001] This application relates to the field of chip design, and particularly to a method and device for analog chip design. Background Art

[0002] Digital chips are integrated circuits based on digital circuits, and analog chips are integrated circuits based on analog circuits. In recent years, the degree of automation and intelligence in digital chip design has become higher and higher, and digital design has been able to achieve automated design of high-frequency modules. However, there is still a large amount of manual intervention in the process of analog chip design, and the design efficiency is significantly lower than that of digital chip design.

[0003] In many high-value digital-analog hybrid chips, the design of analog chips has gradually become a bottleneck in chip design. Therefore, there is an urgent need for a new method for analog chip design to improve the design efficiency of analog chips. Summary of the Invention

[0004] This application provides a method and device for analog chip design, which can improve the design efficiency of analog chips.

[0005] In a first aspect, a method for analog chip design is provided. The method includes: obtaining an analog layout constraint file, where the analog layout constraint file includes electrical constraint definitions, physical constraint definitions, layout design rule definitions, and non-default routing rule (NDR) definitions; generating an analog chip design file according to the layout constraint file, where the analog chip design file includes the layout of the analog design.

[0006] This application provides a method for analog chip design, which can automatically generate an analog chip design file according to an analog layout constraint file including electrical constraint definitions, physical constraint definitions, layout design rule definitions, and NDR definitions input by a user, improving the design efficiency of analog chips.

[0007] Exemplarily, the electrical constraint definitions, physical constraint definitions, layout design rule definitions, and NDR definitions in the analog layout constraint file can be codes input through a domain specific language (DSL) or other programming languages. When running the code, the code can call the software development kit (SDK) interface to automatically generate an analog chip design file.

[0008] Exemplarily, a machine learning method can also be used to automatically generate an analog chip design file according to the electrical constraint definitions, physical constraint definitions, layout design rule definitions, and NDR definitions in the analog layout constraint file by using a trained neural network model.

[0009] Exemplarily, a mapping relation table may also be utilized to find corresponding design information in the mapping relation table according to the electrical constraint definition, physical constraint definition, layout design rule definition, and NDR definition in the analog layout constraint file, and automatically generate an analog chip design file.

[0010] In some possible application scenarios, the generated analog chip design file may be imported through the system or device implemented by the method provided in this application, combined with other analog chip design files to generate a more complex and large-scale analog chip design file, which is convenient for the reuse of analog chip design. Meanwhile, after the process design kit (PDK) is updated, the analog chip design may also be automatically updated through the method provided in this application to complete the automated porting design between different PDKs.

[0011] In combination with the first aspect, in some implementation manners of the first aspect, the obtaining of the analog layout constraint file includes: receiving the layout constraint information input by a user in a project engineering file in an integrated development environment (IDE) or a graphical user interface (GUI) to obtain the layout constraint file.

[0012] In some possible application scenarios, a user may use the system IDE or GUI to create a new project engineering file or import an old project engineering file, and input the layout constraint information in the project engineering file through the DSL text description provided by the system to obtain the layout constraint file.

[0013] This application provides an analog chip design method. A user may input layout constraint information in a project engineering file in an IDE or GUI to obtain a layout constraint file, and run the layout constraint file to automatically generate an analog chip design file, improving the design efficiency of the analog chip.

[0014] In combination with the first aspect, in some implementation manners of the first aspect, the electrical constraint definition includes a circuit trace related constraint definition and / or a circuit device related constraint definition.

[0015] The electrical constraint definition includes any one or more of a circuit trace related constraint definition and a circuit device related constraint definition. The circuit trace related constraint definition is used to define the relevant rules and requirements for traces in a circuit, and the circuit device related constraint definition is used to define the rules and requirements for setting devices in a circuit.

[0016] It should be understood that the electrical constraint definitions including circuit trace-related constraint definitions and / or circuit device-related constraint definitions are only examples, and the electrical constraint definitions may also include other definitions. This example should not be construed as a limitation to this application.

[0017] This application provides a method for analog chip design. Users can define electrical constraints in the analog layout constraint file according to design requirements, so that the layout of the generated analog design meets the requirements of the application scenario, improving the design efficiency of the analog chip.

[0018] In combination with the first aspect, in some implementation manners of the first aspect, the circuit trace-related constraint definitions include any one or more of differential signal matching definition, parasitic capacitance sensitivity definition, and parasitic resistance sensitivity definition.

[0019] Differential signal matching refers to the constraint that requires the trace lengths of a differential signal pair to be equal or very close in design. Parasitic capacitance sensitivity refers to the sensitivity to parasitic capacitance in analog chip design. Parasitic resistance sensitivity refers to the sensitivity to parasitic resistance in analog chip design.

[0020] It should be understood that the circuit trace-related constraint definitions including any one or more of differential signal matching definition, parasitic capacitance sensitivity definition, and parasitic resistance sensitivity definition are only examples, and the circuit trace-related constraint definitions may also include other definitions. This example should not be construed as a limitation to this application.

[0021] This application provides a method for analog chip design. Users can define circuit trace-related constraints in the analog layout constraint file according to design requirements, so that the layout of the generated analog design meets the requirements of the application scenario, improving the design efficiency of the analog chip.

[0022] In combination with the first aspect, in some implementation manners of the first aspect, the circuit device-related constraint definitions include any one or more of differential pair matching definition, current mirror matching definition, parasitic capacitance sensitive device definition, and parasitic resistance sensitive device definition.

[0023] Differential pair matching refers to the constraint that requires the second-order effects, parasitic parameters, process manufacturing deviations, etc. of two groups of devices to be consistent when they are laid out in design. Current mirror matching refers to the constraint that requires the second-order effects, parasitic parameters, process manufacturing deviations, etc. of multiple groups of devices with a multiple relationship of currents to be consistent when they are laid out in design. Parasitic capacitance sensitive devices refer to devices that are highly sensitive to the parasitic capacitance existing in the circuit. Parasitic resistance sensitive devices refer to devices that are highly sensitive to the parasitic resistance existing in the circuit.

[0024] It should be understood that the circuit device-related constraint definitions, including any one or more of the differential pair matching definition, current mirror matching definition, parasitic capacitance sensitive device definition, and parasitic resistance sensitive device definition, are only examples. The circuit device-related constraint definitions may also include other definitions, and this example should not be construed as a limitation to this application.

[0025] This application provides a method for designing an analog chip. Users can define circuit device-related constraints in the analog layout constraint file according to the design requirements, so that the layout of the generated analog design meets the requirements of the application scenario, improving the design efficiency of the analog chip.

[0026] In combination with the first aspect, in some implementation manners of the first aspect, the physical constraint definition includes a physical layout constraint definition and / or a physical routing constraint definition.

[0027] The physical layout constraint involves the position layout of circuit elements, and the physical routing constraint involves the rules and requirements for trace connections.

[0028] It should be understood that the physical constraint definition including the physical layout constraint definition and / or the physical routing constraint definition is only an example. The physical constraint definition may also include other definitions, and this example should not be construed as a limitation to this application.

[0029] This application provides a method for designing an analog chip. Users can define physical constraints in the analog layout constraint file according to the design requirements, so that the layout of the generated analog design meets the requirements of the application scenario, improving the design efficiency of the analog chip.

[0030] In combination with the first aspect, in some implementation manners of the first aspect, the physical layout constraint definition includes any one or more of a symmetric layout definition, an alignment layout definition, a proximity layout definition, a capacitor array layout definition, and a metal-oxide-semiconductor field-effect transistor (MOSFET) array layout definition.

[0031] The symmetric layout refers to using symmetric shapes and structures in the layout to achieve the symmetry of the layout. The alignment layout means aligning different components or structures of the layout according to certain rules or standards. The proximity layout means placing components or structures that are related or closely related to each other in the layout near each other. The capacitor array layout means connecting multiple capacitors together according to a certain rule or arrangement to form a whole. The MOSFET array layout means connecting multiple MOSFETs together according to a certain rule or arrangement to form a whole.

[0032] It should be understood that the physical layout constraint definition includes any one or more of symmetric layout definition, alignment layout definition, proximity layout definition, capacitor array layout definition, MOSFET array layout definition, etc. These are only examples, and the physical layout constraint definition can also include other definitions. This example should not be construed as a limitation to this application.

[0033] This application provides a method for analog chip design. Users can define physical layout constraints in the analog layout constraint file according to design requirements, so that the layout of the generated analog design meets the requirements of the application scenario, improving the design efficiency of the analog chip.

[0034] In combination with the first aspect, in some implementation manners of the first aspect, the physical wiring constraint definition includes any one or more of symmetric wiring definition, shielded wire wiring definition, bus (BUS) wire group definition, and routing track definition.

[0035] Symmetric wiring means that the signal lines or power lines in the wiring are required to be symmetric in a specific direction or position. Shielded wire wiring means that some signal lines or power lines in the wiring are required to be surrounded by a shielding layer or metal layer to reduce the influence of external electromagnetic interference on these signals. The BUS wire group is used to transmit multiple signals or data bits, such as an address bus, a data bus, or a control bus. A routing track refers to a specific area or channel reserved for routing in the analog chip layout.

[0036] It should be understood that the physical wiring constraint definition includes any one or more of symmetric wiring definition, shielded wire wiring definition, BUS wire group definition, and routing track definition. These are only examples, and the physical wiring constraint definition can also include other definitions. This example should not be construed as a limitation to this application.

[0037] This application provides a method for analog chip design. Users can define physical wiring constraints in the analog layout constraint file according to design requirements, so that the layout of the generated analog design meets the requirements of the application scenario, improving the design efficiency of the analog chip.

[0038] In combination with the first aspect, in some implementation manners of the first aspect, the layout design rule definition includes any one or more of process grid point design rule definition, interval design rule definition between layout layers of the layout, width range design rule definition of layout layers of the layout, area design rule definition of layout layers of the layout, and device attribute design rule definition.

[0039] A process grid, also known as a layout grid or layout mesh, is a fundamental unit in the layout process. It divides the layout space into regular grid-like regions for positioning and aligning circuit components, routing tracks, and other layout objects. Device attribute design rules refer to the consideration of different types of devices, process reliability, and circuit design intentions, etc., to attach additional attributes to devices and define design rules such as mutual exclusivity and space between devices.

[0040] It should be understood that the layout design rule definitions include any one or more of the process grid design rule definitions, the space design rule definitions between layout layers, the width range design rule definitions of layout layers, the area design rule definitions of layout layers, and the device attribute design rule definitions are only examples. The layout design rule definitions can also include other definitions. This example should not be construed as a limitation on this application.

[0041] This application provides a method for designing an analog chip. Users can define layout design rules in an analog layout constraint file according to design requirements, so that the generated layout of the analog design meets the requirements of the application scenario, improving the design efficiency of the analog chip.

[0042] In combination with the first aspect, in some implementation manners of the first aspect, the NDR definition includes a routing pattern defined according to the metal hierarchy of the analog chip.

[0043] Exemplarily, the NDR definition includes various different routing patterns such as width, pitch, and space defined according to the metal hierarchy.

[0044] This application provides a method for designing an analog chip. Users can define the NDR in an analog layout constraint file according to design requirements, so that the generated layout of the analog design meets the requirements of the application scenario, improving the design efficiency of the analog chip.

[0045] In combination with the first aspect, in some implementation manners of the first aspect, the analog chip design file is in a compressed and / or encrypted format.

[0046] Users can select the format and encryption form of the analog chip design file. Exemplarily, users can configure the layout to output in a graphic design system (GDS) format, a library exchange format (LEF), or a design exchange format (DEF), etc.

[0047] Exemplarily, the user can pack the analog chip design file into a compressed format and / or an encrypted format, such as ZIP format or RAR format, using a packing command. Subsequently, it can be re-imported into the system for use. The imported design can be part of other designs, or a new process configuration can be re-specified for transplantation to scenarios adapted to the new process.

[0048] This application provides an analog chip design method. The user can select the format of the generated analog chip design file according to requirements to suit different application scenarios.

[0049] In a second aspect, a computer device is provided. The device includes: an acquisition module for acquiring an analog layout constraint file, where the analog layout constraint file includes electrical constraint definitions, physical constraint definitions, layout design rule definitions, and non-default routing rule NDR definitions; a processing module for generating an analog chip design file according to the layout constraint file, where the analog chip design file includes the layout of the analog design.

[0050] In combination with the second aspect, in certain implementation manners of the second aspect, the acquisition module is specifically configured to: receive the layout constraint information input by the user in the project engineering file on the IDE or GUI to obtain the layout constraint file.

[0051] In combination with the second aspect, in certain implementation manners of the second aspect, the electrical constraint definitions include circuit trace-related constraint definitions and / or circuit device-related constraint definitions.

[0052] In combination with the second aspect, in certain implementation manners of the second aspect, the circuit trace-related constraint definitions include any one or more of differential signal matching definitions, parasitic capacitance sensitivity definitions, and parasitic resistance sensitivity definitions.

[0053] In combination with the second aspect, in certain implementation manners of the second aspect, the circuit device-related constraint definitions include any one or more of differential pair matching definitions, current mirror matching definitions, parasitic capacitance sensitive device definitions, and parasitic resistance sensitive device definitions.

[0054] In combination with the second aspect, in certain implementation manners of the second aspect, the physical constraint definitions include physical layout constraint definitions and / or physical routing constraint definitions.

[0055] In combination with the second aspect, in certain implementation manners of the second aspect, the physical layout constraint definitions include any one or more of symmetric layout definitions, alignment layout definitions, proximity layout definitions, capacitor array layout definitions, and MOSFET array layout definitions.

[0056] In combination with the second aspect, in some implementations of the second aspect, the physical wiring constraint definition includes any one or more of a symmetric wiring definition, a shielded wire wiring definition, a bus BUS wire group definition, and a wiring track definition.

[0057] In combination with the second aspect, in some implementations of the second aspect, the layout design rule definition includes any one or more of a process grid design rule definition, an interval design rule definition between layout layers, a width range design rule definition of layout layers, an area design rule definition of layout layers, and a device attribute design rule definition.

[0058] In combination with the second aspect, in some implementations of the second aspect, the NDR definition includes a wiring pattern defined according to the metal layer of the analog chip.

[0059] In combination with the second aspect, in some implementations of the second aspect, the layout constraint file is in a compressed and / or encrypted format.

[0060] The beneficial effects of the second aspect and any possible implementation of the second aspect correspond to those of the first aspect and any possible implementation of the first aspect, and thus will not be elaborated herein.

[0061] In a third aspect, an embodiment of the present application provides a computer device, which includes a processor for coupling with a memory, reading, and executing instructions and / or program codes in the memory to execute the first aspect or any possible implementation of the first aspect.

[0062] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing program codes, which when run on a computer, cause the computer to execute the first aspect or any possible implementation of the first aspect.

[0063] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes computer program codes, which when run on a computer, cause the computer to execute the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 is an exemplary flowchart of a method for designing an analog chip provided by an embodiment of the present application.

[0065] Figure 2 is a schematic diagram of a DHT provided by an embodiment of the present application.

[0066] Figure 3It is a schematic structural diagram of a simulation chip design system provided by an embodiment of the present application.

[0067] Figure 4 It is an exemplary flowchart of another simulation chip design method provided by an embodiment of the present application.

[0068] Figure 5 It is an exemplary flowchart of another simulation chip design method provided by an embodiment of the present application.

[0069] Figure 6 It is an exemplary flowchart of a user creating a project through an IDE provided by an embodiment of the present application.

[0070] Figure 7 It is an exemplary structural diagram of circuit definition provided by an embodiment of the present application.

[0071] Figure 8 It is an exemplary structural diagram of layout definition provided by an embodiment of the present application.

[0072] Figure 9 It is the module generation process and control points of a simulation chip provided by an embodiment of the present application.

[0073] Figure 10 It is an exemplary flowchart of another simulation chip design method provided by an embodiment of the present application.

[0074] Figure 11 It is an exemplary structural diagram of a computer device provided by an embodiment of the present application.

[0075] Figure 12 It is an exemplary structural diagram of another computer device provided by an embodiment of the present application.

[0076] Figure 13 It is an example diagram of a computer program product provided by an embodiment of the present application. Detailed implementation manners

[0077] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0078] In the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of the word "exemplary" is intended to present concepts in a specific manner.

[0079] The business scenarios described in the embodiments of this application are for more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those of ordinary skill in the art will know that with the emergence of new business scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems.

[0080] References to "one embodiment" or "some embodiments" etc. described in this specification mean that specific features, structures, or characteristics described in connection with that embodiment are included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "include", "comprise", "have" and their variants all mean "include but not limited to", unless otherwise specifically emphasized in another way.

[0081] In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: including the case where A exists alone, where A and B exist simultaneously, and where B exists alone, where A and B can be singular or plural. The character " / " generally means that the associated objects before and after are in an "or" relationship. "At least one (item)" or similar expressions thereof refer to any combination of these items, including any combination of single item (s) or plural items (s). For example, at least one (item) of a, b, or c can mean: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c can be single or multiple.

[0082] To facilitate the understanding of the embodiments of this application, some definitions involved in this application are briefly described first.

[0083] 1. Product part number: The number of the product produced by the enterprise.

[0084] 2. Discrete device: Generally refers to all basic circuit elements with a single function, such as transistors, diodes, resistors, capacitors, inductors, etc.

[0085] 3. Grid: Refers to the grid system in the chip layout, used for dividing and positioning the chip surface. The grid usually consists of regular square or rectangular units, and is used to position and align each element in the layout.

[0086] 4. Pitch: It represents the distance between adjacent elements in the chip layout, which can be the horizontal and vertical distances, and is used to define the distance between elements.

[0087] 5. Space: It refers to the gap or void between elements in the layout, which represents the unused area or the blank area between elements.

[0088] 6. Length: It represents the length in the chip layout, which can be the length of a circuit, a wire, or other elements.

[0089] 7. Via: In the chip layout, a via (or simply called a hole) is used to connect circuits at different levels. The via provides an electrical connection in the vertical direction, enabling signals to be transmitted between different layers.

[0090] 8. Semiconductor Intellectual Property (IP): It refers to an integrated circuit module that has been verified, reusable, and has specific functions in integrated circuit design.

[0091] 9. Common Building Block (CBB): It refers to those components, modules, technologies, and other related design achievements that can be shared among different products and systems.

[0092] 10. Simulator: It is used to simulate and verify the circuit behavior and performance. It can simulate the operation of the circuit under different input conditions to evaluate the performance of the circuit in terms of functional correctness, timing requirements, power consumption, noise, etc.

[0093] 11. Design Hierarchy Tree (DHT): A multi - branch tree generated based on the simulated chip design information, which carries the logical information, physical information, and constraint information of the circuit according to the design hierarchy.

[0094] Digital chips are integrated circuits based on digital circuits, and analog chips are integrated circuits based on analog circuits. In recent years, the degree of automation and intelligence in digital chip design has been getting higher and higher, and digital design can already achieve the automated design of high - frequency modules. However, there is still a large amount of manual intervention in the process of analog chip design, and the design efficiency is significantly lower than that of digital chip design.

[0095] Compared with digital chip design technology, analog chip design faces many challenges, including but not limited to the following aspects: (1) Although the types of analog semiconductor IP are limited, the design index range is very wide, and different specifications need to be designed for different usage scenarios; (2) Analog design requires weighing various indicators; (3) Engineers need to design different circuit structures based on experience; (4) Engineers need to iteratively adjust circuit parameters based on experience and the process design kit (PDK); (5) Engineers need to customize the layout design based on experience and PDK.

[0096] In many high-value digital-analog hybrid chips, analog chip design has gradually become the bottleneck of chip design. Therefore, there is an urgent need for new analog chip design methods to improve the efficiency of analog chip design. In the field of discrete analog devices, the product part number is one of the key indicators to measure an analog chip company. Creating a more advanced analog design system can help users enrich the analog chip part numbers.

[0097] This application provides an analog chip design method and device, which can automatically design analog chips according to the needs of users, support the realization of a fully controllable automation system from analog circuits to layout, and also support the rapid transplantation of the current existing implementation to different processes.

[0098] Figure 1 It is an exemplary flowchart of an analog chip design method provided by an embodiment of this application.

[0099] 110. Obtain an analog layout constraint file.

[0100] The analog layout constraint file includes electrical constraint definitions, physical constraint definitions, layout design rule definitions, and non-default routing rule (NDR) definitions.

[0101] Exemplarily, the electrical constraint definitions, physical constraint definitions, layout design rule definitions, and NDR definitions in the analog layout constraint file can be codes input through a domain specific language (DSL) or other programming languages.

[0102] In some possible application scenarios, the system or device can obtain the layout constraint file by receiving the layout constraint information input by the user in the project engineering file on the IDE or GUI.

[0103] Among them, the electrical constraint definitions include circuit trace-related constraint definitions and / or circuit device-related constraint definitions. The circuit trace-related constraint definitions include any one or more of differential signal matching definitions, parasitic capacitance sensitivity definitions, and parasitic resistance sensitivity definitions. The circuit device-related constraint definitions include any one or more of differential pair matching definitions, current mirror matching definitions, parasitic capacitance sensitive device definitions, and parasitic resistance sensitive device definitions. The physical constraint definitions include physical layout constraint definitions and / or physical routing constraint definitions. The physical layout constraint definitions include any one or more of symmetric layout definitions, alignment layout definitions, proximity layout definitions, capacitor array layout definitions, and MOSFET array layout definitions. The physical routing constraint definitions include any one or more of symmetric routing definitions, shielded wire routing definitions, BUS line group definitions, and routing track definitions. The layout design rule definitions include any one or more of process grid design rule definitions, spacing design rule definitions between layout layers of the layout, width range design rule definitions of the layout layers of the layout, area design rule definitions of the layout layers of the layout, and device attribute design rule definitions. The NDR definitions include routing patterns defined according to the metal layers of the analog chip.

[0104] 120, generate an analog chip design file.

[0105] The analog chip design file includes the layout of the analog design. The analog chip design file can be in a compressed and / or encrypted format.

[0106] Exemplarily, when running the layout constraint file, the code in the layout constraint file can call the software development kit (SDK) interface to automatically generate an analog chip design file.

[0107] The user can select the format and encryption form for exporting the analog chip design file. Exemplarily, the user can configure the layout to output in the graphic design system (GDS) format, library exchange format (LEF), or design exchange format (DEF), etc.

[0108] Exemplarily, the user can use a packaging command to package the analog chip design file into a compressed format and / or an encrypted format, such as the ZIP format or the RAR format. Subsequently, it can be re-imported into the system for use. The imported design can be used as part of other designs, or a new process configuration can be re-specified for transplantation to a scenario adapted to a new process.

[0109] Figure 2 It is a schematic diagram of a DHT provided by an embodiment of the present application.

[0110] The DHT is a multi - way tree generated according to the analog chip design information. A, B, and C represent different levels of the multi - way tree. For example, A1 is the first node of the first level of the multi - way tree, B1 is the first node of the second level of the multi - way tree, C1 is the first node of the third level of the multi - way tree, C2 is the second node of the third level of the multi - way tree, and C3 is the third node of the third level of the multi - way tree.

[0111] The standard cell is the basic unit in the DHT. It is a pre - designed logical and physical unit, such as logic gates (e.g., AND gate, OR gate), flip - flops (e.g., D flip - flop, JK flip - flop), etc. The standard cell has fixed functions and characteristics and can be reused in circuit design. The standard cell provides an abstraction at the logical level of the circuit, simplifying the circuit design and verification process. The macro cell is a logical unit composed of multiple standard cells and is used to represent a higher - level circuit structure. The macro cell can contain multiple standard cells and other macro cells, forming a logical combination. By using standard cells and macro cells, the DHT provides a hierarchical design method, enabling the circuit design to be decomposed and organized at different levels, thus improving the flexibility, scalability, and maintainability of the design. At the same time, the use of standard cells and macro cells also promotes the modularity and reuse of the design, reducing development time and cost.

[0112] Figure 3 It is a schematic diagram of the architecture of an analog chip design system provided by an embodiment of the present application.

[0113] The analog chip design system provided by this application mainly includes four layers: user interface, application service, domain service, and domain model. Each layer provides a series of modules for related function processing, and there are dependency relationships in sequence. The user interface layer includes a standardized interface module, a file management module, a scheduling management module, a data access module, a tool management module, and an IDE, where the IDE can also be replaced by a GUI. The application service layer includes a CBB component management module, a CBB test management module, a user CBB management module, a process management module, a constraint management module, a design rule checking (DRC) verification module, a circuit structure selection module, a circuit module management module, a global layout and routing module, and a group layout and routing module. The domain service layer includes a circuit analysis algorithm, a group placer and router (P&R) algorithm, a global P&R algorithm, a circuit automatic design algorithm, a DRC parsing and checking algorithm, a device standardization service, a process abstraction service, and a constraint management service. The domain model module provides a standardized device model, and the standardized device model includes DHT. DHT carries the logical information, physical information, and constraint information of the circuit. The standardized device model is used to uniformly standardize the expression of circuit devices such as resistors or capacitors in different processes.

[0114] The analog chip design method provided by this application can provide users with automated design capabilities through the IDE and / or GUI. This application defines a set of domain specific language (DSL) suitable for analog design, provides a set of coded software development kit (SDK) interfaces, can interact with computing and storage systems, supports users to generate coded analog design modules through the IDE or GUI, constructs the code into an analog circuit and / or analog layout through this system, combines the design constraint information provided by the PDK, and the controllable automatic layout and routing of the layout to generate an analog chip design file. The analog chip design file includes any one or more of the designed circuit, layout, and design-related code.

[0115] The generated analog chip design file can be imported through this system, combined with other analog chip design files to generate more complex and large-scale analog chip design files, which is convenient for the reuse of analog design. At the same time, after the PDK is updated, the system can also automatically update the analog chip design to complete the automated porting design between different PDKs.

[0116] The following describes in detail several key modules in the analog chip design system provided by this application.

[0117] (1) Analog chip design DSL:

[0118] The analog chip design DSL includes two parts: circuit definition information and layout constraint information, which are used to control the automatic generation of analog circuits and layouts.

[0119] The circuit definition information includes: (1) Module interface definition, including the definitions of circuit module name, type, input ports, output ports, control ports, and power ports; (2) Definition of the process name compatible with the module; (3) Definition of the module circuit netlist file, which is an optional part; (4) Determination of the circuit parameters provided by the module according to the process, which is an optional part; (5) Definition of the module simulation excitation file (TestBench), including various connections between various excitation sources of the analog circuit and the ports of the circuit module; (6) Module index definition, defining the specifications (SPEC) that the module can achieve in the front-end simulation under a certain process, using the standardized naming of the system, such as the loop gain and phase margin of the operational amplifier circuit.

[0120] The layout constraint information includes: (1) Electrical constraint definition, which includes circuit routing-related constraint definitions and / or circuit device-related constraint definitions. The circuit routing-related constraint definitions include any one or more of differential signal matching definition, parasitic capacitance sensitivity definition, and parasitic resistance sensitivity definition. The circuit device-related constraint definitions include any one or more of differential pair matching definition, current mirror matching definition, parasitic capacitance sensitive device definition, and parasitic resistance sensitive device definition; (2) Physical constraint definition, which includes physical layout constraint definition and / or physical routing constraint definition. The physical layout constraint definition includes any one or more of symmetric layout definition, alignment layout definition, proximity layout definition, capacitor array layout definition, and MOSFET array layout definition. The physical routing constraint definition includes any one or more of symmetric routing definition, shielded wire routing definition, BUS line group definition, and routing track definition; (3) Layout design rule definition, which includes any one or more of process grid design rule definition, interval design rule definition between layout layers, width range design rule definition of layout layers, area design rule definition of layout layers, and device attribute design rule definition; (4) NDR definition, which includes the routing mode defined according to the metal layer of the analog chip; (5) Special constraint definition, which includes analog-customized logic units and is an optional definition.

[0121] In some possible implementation manners, the user can input the layout constraint information in the project engineering file on the IDE or GUI to obtain the layout constraint file. The user can input the circuit definition information in the project engineering file on the IDE or GUI to obtain the circuit definition file.

[0122] (2) SDK Interface Module:

[0123] The SDK provided by this application defines a series of interfaces, which can conveniently control the generation of circuit modules and layout modules, mainly including interfaces related to circuit generation and interfaces related to layout generation.

[0124] The interfaces related to circuit generation can support setting preferences for circuit generation-related architecture selection, circuit optimization algorithm preferences, simulator settings, etc.

[0125] The interfaces related to layout generation can perform the following operations: (1) query or set a series of parameters used for layout generation, including process parameters and constraints, etc.; (2) operate the underlying database that stores layout data; (3) can use the Graphics Application Programming Interface (API) for specific graphic design of the layout; (4) can control the Placer algorithm for manual row and column layout; (5) can control the Router algorithm for power network planning, signal line planning, symmetric routing, Bus connection, etc.; (6) can call other generation modules or existing modules of other users for splicing.

[0126] (3) Standardized Device Model:

[0127] The standardized device model provides all the basic object unit structures for analog chip design, and serves as a general interface for upper-layer use. This object is process-independent. The objects abstracted at the implementation level include basic units such as resistors (Res), capacitors (Cap), metal-oxide-semiconductor (MOS), bipolar junction transistors (BJT), taps (Tap), fillers (Filler), etc., digital standard cells such as inverters (INV), NAND gates (NAND), etc., excitation signals such as positive power supply voltage (VDD), negative power supply voltage (VSS), and logical units such as differential pairs, current mirrors, loads, biases, power domains (PD).

[0128] (4) Algorithm Module:

[0129] The algorithm module includes circuit analysis algorithms, Placer&Router (P&R) algorithms, global P&R algorithms, automatic circuit design algorithms, DRC parsing and checking algorithms.

[0130] The algorithm module provides a series of basic algorithms, and each algorithm provides a set of standard SDK interfaces externally to support the generation from circuit to layout. The implementation includes providing algorithms and interfaces for automatic circuit structure generation and optimization, and providing algorithms and related interfaces for netlist analysis, process integration, cell generation, placement, routing, and effect evaluation.

[0131] (5) Process abstraction module:

[0132] The process abstraction module extracts the standard design rules and design constraints used by the PDK extraction system, and at the same time provides query and setting interfaces for the related constraints abstracted by the process externally.

[0133] Figure 4 It is an exemplary flowchart of another analog chip design method provided by an embodiment of the present application.

[0134] 410. The user inputs chip design information through the IDE or GUI.

[0135] The user can use the system IDE to create a new project engineering file or import an old project engineering file. Through the DSL text description provided by the system, circuit definition and layout constraint definition are carried out in the project engineering file to be compiled. Exemplarily, the user can input the PDK file, PDK metal options, analog chip application scenarios, and / or other optional parameters according to the prompts. The system creates an executable project engineering file by virtue of the capabilities provided by the DSL and SDK. The user can input circuit definition information and layout constraint information in the generated project engineering file using the DSL according to the design requirements.

[0136] Optionally, the way of user text input can also be encapsulated on the GUI, and GUI operations (such as clicking and dragging) are converted into DSL text descriptions.

[0137] 420. Compilation.

[0138] The system converts the project engineering file into an analog circuit and an analog layout through a compiler.

[0139] 425. Abstract design rules and constraints.

[0140] The PDK is a collection of data files and script files of a specific foundry in the chip design process. The main components of the PDK are models, symbols, process files, parameterized cells (PCells), and rule files. The PDK is created by the foundry for simulating the manufacturing process of integrated circuits and extracting characteristic parameters, defines some certain process specifications of the foundry process, and passes them to the user for use in the design process. The user can redesign the PDK to make it adapt to a specific design style and scenario.

[0141] Different PDKs represent the process specifications of different factories. Users input the selected PDK files into the system according to their needs. For example, PDK files can be imported into the system from the local, or PDKs can be selected in the system. The system can abstract the corresponding standard design rules and constraints based on the PDKs input by the users.

[0142] 430, Model Management.

[0143] The system manages the models of analog chip designs by combining the compilation and the output of design rules and constraints.

[0144] 440, Automatic Optimization.

[0145] According to the automatic optimization algorithms provided by the system, such as automatic placement and / or routing algorithms, the analog chip design is automatically optimized in terms of placement and routing.

[0146] 450, Implementation.

[0147] The system converts the analog chip design into a legal and reusable analog chip design file according to the process requirements. The analog chip design file includes any one or more of the designed circuits, layouts, and design-related codes. In some possible application scenarios, the analog chip design file can also be referred to as an application (APP). The system provided in this application supports the reuse of the generated APP. Exemplarily, users can re-enter the previously generated APP2 or APP3 into the system for editing and modification, and compile to generate a new APP for use, improving the generation efficiency of analog chip designs and reducing the time cost.

[0148] Figure 5 It is an exemplary flowchart of another analog chip design method provided by the embodiments of this application.

[0149] 510, IDE Creates a Project.

[0150] Users can use the system IDE to create a new project. Exemplarily, Figure 6 It is an exemplary flowchart of a user creating a project through the IDE provided by the embodiments of this application, Figure 6 Corresponding to step 510.

[0151] The user can create a command for a project through the management interface or the command-line interface (CLI), and an executable project engineering file can be automatically generated in combination with the user configuration information. Exemplarily, the user inputs configuration parameters such as the PDK file, PDK metal options, analog chip application scenarios, and / or other optional parameters according to the prompts, and the system automatically creates an executable project engineering file. The project engineering file may include a process-related file main.py, configuration-related files config.yaml, tech_constraint.yaml, models.py, and constraint-related files constraint.py, user_constraint.py. The user can directly use relevant environments such as the python environment in the IDE to run this project engineering file.

[0152] In some possible implementation scenarios, the user can also directly import an old project engineering file into the system, modify the relevant content of the circuit definition information and / or layout constraint information in the project engineering file, and improve the design efficiency of the analog chip.

[0153] 520. Input circuit definition information.

[0154] Exemplarily, the user can use the DSL provided by the system to input circuit definition information in the configuration-related file of the project engineering file to meet the requirements of the application scenario. Figure 7 It is an exemplary structural diagram for circuit definition provided by an embodiment of the present application. Figure 7 Corresponding to step 520.

[0155] Circuit definition includes module interface definition, process information definition, simulation stimulus file definition, and metric definition. Optionally, it may also include netlist file definition and circuit parameter definition. Among them, the module interface definition includes the definition of the circuit module name, type, input port, output port, control port, and power port. The process information definition includes the definition of the process name compatible with the module; the simulation stimulus file (TestBench) definition includes various connections between various stimulus sources in the analog circuit and the ports of the circuit module; the metric definition includes the specifications (SPEC) metrics that the module can achieve in the front-end simulation under a certain process, using the standardized naming of the system, such as the loop gain and phase margin of the operational amplifier circuit; the netlist file definition includes the path definition of the circuit netlist file; the circuit parameter definition includes the determined values of the circuit parameters provided by the module according to the process.

[0156] In some possible implementation manners, the user can input circuit definition information in the project engineering file to obtain a circuit definition file, and run the circuit definition file to generate the circuit of the analog design.

[0157] 530, Input the layout constraint information.

[0158] Users can use the DSL provided by the system to define the layout constraints to meet the requirements of the application scenario. Figure 8 It is an exemplary structural diagram for layout definition provided by an embodiment of the present application, Figure 8 corresponding to step 530.

[0159] The layout constraints define electrical constraints definition, physical constraints definition, design rule definition, and NDR definition. Optionally, it can also include special constraint definition. The electrical constraints definition includes circuit routing related constraint definition and / or circuit device related constraint definition. The circuit routing related constraint definition includes any one or more of differential signal matching definition, parasitic capacitance sensitivity definition, and parasitic resistance sensitivity definition. The circuit device related constraint definition includes any one or more of differential pair matching definition, current mirror matching definition, parasitic capacitance sensitive device definition, and parasitic resistance sensitive device definition. The physical constraints definition includes physical layout constraint definition and / or physical routing constraint definition. The physical layout constraint definition includes any one or more of symmetric layout definition, alignment layout definition, proximity layout definition, capacitor array layout definition, and MOSFET array layout definition. The physical routing constraint definition includes any one or more of symmetric routing definition, shield wire routing definition, BUS wire group definition, and routing track definition. The layout design rule definition includes any one or more of process grid design rule definition, interval design rule definition between layout layers, width range design rule definition of layout layers, area design rule definition of layout layers, and device attribute design rule definition. The NDR definition includes the routing mode defined according to the metal layer of the analog chip. The special constraint definition includes analog-customized logic units.

[0160] In some possible implementation manners, users can input the layout constraint information in the project engineering file to obtain the layout constraint file, and running this layout constraint file can generate the layout of the analog design.

[0161] It should be understood that the circuit definition file and the layout constraint file can be run simultaneously or not simultaneously, and the circuit definition file and the layout constraint file can be located in one code file or belong to two different code files.

[0162] 540, Use the SDK to control the model operation.

[0163] Users can use the SDK provided by the system to control the operation and generation of the modules of the analog chip. Figure 9It is the module generation process and control points of the analog chip provided by the embodiments of the present application. The module generation process includes circuit analysis, circuit optimization, group placement, group routing, global placement, and global routing. Circuit analysis includes processing nodes such as circuit structure identification, constraint extraction, signal flow analysis, and device grouping. Group placement includes processing nodes such as group size estimation, device generation, matrix generation, and ring generation. Group routing includes processing nodes such as trunk routing and detail routing. Global placement includes processing nodes such as FloorPlan, pre-placement, global placement DRC, and legalization. Global routing includes processing nodes such as Pin Assignment, pre-routing, overall wiring planning, and routing. Among them, trunk routing is used for overall planning, and detail routing is the specific implementation. Trunk routing is fast and concise, while detail routing is meticulous and complex. The purpose of FloorPlan is to determine the module size, position, shape, and the placement of macro cells.

[0164] During the entire module operation, the system can provide an SDK interface at all processing nodes to control relevant processing parameters. Users can customize the processing rules of the corresponding node data of the processing nodes in the project engineering file or select the desired algorithm parameters.

[0165] 550, use the SDK to control module generation and packaging.

[0166] The system can output an analog chip design file. The analog chip design file includes any one or more of the circuits, layouts, and design-related codes of the analog design. Users can also select the format and encryption form of the exported content. Exemplarily, users can configure the layout to output in the graphic design system (GDS) format, library exchange format (LEF), or design exchange format (DEF), etc.

[0167] Users can use the packaging command to package the analog chip design file into a compressed format, such as the ZIP format or RAR format. Subsequently, it can be re-imported into the system for use. The imported module can be used as part of other designs or can be re-specified with a new process configuration to be transplanted to a scenario adapted to the new process.

[0168] The present application provides an end-to-end analog chip design system that can go from circuit design to generating a circuit layout. Users can describe the analog chip design to be implemented through the IDE and the DSL provided by the system, and can constrain the analog chip design objectives and implementation process to ensure that the automatically generated analog circuit modules meet the user's expectations. Through engineering management, the system provides a set of customized SDK interfaces, combines the design constraint information provided by the PDK, and the controllable automatic layout and routing of the layout, enabling users to control the overall process from analog chip design to automatic layout implementation. At the same time, the system supports users to package the generated analog chip design files for subsequent module reuse or future transplantation to new processes for use.

[0169] Figure 10 It is an exemplary flowchart of another analog chip design method provided by an embodiment of the present application.

[0170] 610, the GUI creates a project.

[0171] The present application also provides a set of GUI, which encapsulates the user's text input method on the interface. Exemplarily, users can create project engineering files on the interface in the form of list selection or dragging.

[0172] Exemplarily, users input configuration parameters such as PDK files, PDK metal options, analog chip application scenarios, and / or other optional parameters in the GUI, and the system automatically creates an executable project engineering file. The project engineering file includes process-related files main.py, configuration-related files config.yaml, tech_constraint.yaml, models.py, and constraint-related files constraint.py, user_constraint.py.

[0173] In some possible implementation scenarios, users can also directly import the old project engineering file into the system through the GUI, and modify the relevant content of the circuit definition information and / or layout constraint information in the project engineering file to improve the design efficiency of the analog chip.

[0174] 620, code conversion from GUI operations to DSL.

[0175] The system can convert the input in the form of list or drag in the user's GUI operations into DSL code in text format.

[0176] 630 - 660, this step is the same as Figure 5 the steps 520 - 550, and the present application will not repeat them.

[0177] The present application provides an end-to-end analog chip design system that can go from circuit design to generating a circuit layout. Users can describe the required analog chip design through GUI operations, and can constrain the analog chip design objectives and implementation processes to ensure that the automatically generated analog circuit modules meet user expectations. Through engineering management, the system provides a set of customized SDK interfaces, combines the design constraint information provided by the PDK, and performs controllable automatic layout and routing of the layout, enabling users to control the overall process from analog chip design to automated implementation. At the same time, the system supports users to package the generated analog chip design files for subsequent module reuse or future transplantation to new processes for use.

[0178] The above describes the analog chip design method according to the embodiments of the present application. The following will separately describe the apparatus and device according to the embodiments of the present application in combination with Figure 11 and Figure 12 respectively.

[0179] The embodiments of the present application also provide a computer storage medium. Program instructions are stored in the computer storage medium, and when the program instructions are executed, they may include some or all of the steps of the analog chip design method in the corresponding embodiments such as Figure 1 and Figures 3 to 10 respectively.

[0180] Figure 11 FIG. 18 is a structural schematic diagram of a computer device 1000 provided by an embodiment of the present application. The computer device 1000 includes an acquisition module 1010 and a processing module 1020. The acquisition module 1010 and the processing module 1020 can be implemented by software, hardware, or a combination of both.

[0181] Among them, the acquisition module 1010 is used to acquire an analog layout constraint file to execute Figure 1 step 110 in the method.

[0182] The processing module 1020 is used to generate an analog chip design file according to the layout constraint file and execute some or all of the steps in the methods of Figure 1 and Figures 3 to 10 respectively.

[0183] Figure 12 FIG. 34 is a structural schematic diagram of another computer device 1300 provided by an embodiment of the present application. The computer device 1300 includes a processor 1302, a communication interface 1303, and a memory 1304. An example of the computer device 1300 is a computing device.

[0184] The method disclosed in the embodiments of the present application described above can be applied to or implemented by the processor 1302. The processor 1302 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. In the implementation process, the steps of the above method may be completed by the integrated logic circuit in the hardware of the processor 1302 or by instructions in the form of software. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or may be executed and completed by a combination of hardware and software modules in the decoding processor.

[0185] The memory 1304 can be a volatile memory, a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory of the methods described herein is intended to include but not be limited to these and any other suitable types of memory.

[0186] Communication can occur between the processor 1302, the memory 1304, and the communication interface 1303 via a bus. Executable code is stored in the memory 1304, and the processor 1302 reads the executable code in the memory 1304 to execute the corresponding method. Other software modules required for other running processes, such as an operating system, can also be included in the memory 1304. The operating system can be LINUX TM , UNIX TM , WINDOWS TM , etc.

[0187] For example, the executable code in the memory 1304 is used to implement Figure 1 , Figures 3 to 10 the methods shown. The processor 1302 reads the executable code in the memory 1304 to execute Figure 1 , Figures 3 to 10 the methods shown.

[0188] In some embodiments of the present application, the disclosed method may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or encoded on other non-transitory media or articles. Figure 13 A conceptual partial view of an example computer program product arranged in accordance with at least some of the embodiments presented herein is schematically shown. The example computer program product includes a computer program for performing a computer process on a computing device. In one embodiment, the example computer program product 1400 is provided using a signal-bearing medium 1401. The signal-bearing medium 1401 may include one or more program instructions 1402 that, when run by one or more processors, may provide the functions or portions of the functions described above for Figure 1 , Figures 3 to 10 the methods described. Thus, for example, with reference to the embodiments shown in Figure 1 , Figures 3 to 10 , one or more of the features therein may be carried out by one or more instructions associated with the signal-bearing medium 1401.

[0189] In some examples, the signal-bearing medium 1401 may include a computer-readable medium 1403, such as but not limited to, a hard disk drive, a compact disk (CD), a digital video disk (DVD), a digital tape, a memory, a read-only memory (ROM), or a random access memory (RAM), and so on. In some embodiments, the signal-bearing medium 1401 may include a computer-recordable medium 1404, such as but not limited to, a memory, a read / write (R / W) CD, an R / W DVD, and so on. In some embodiments, the signal-bearing medium 1401 may include a communication medium 1405, such as but not limited to, a digital and / or analog communication medium (e.g., an optical fiber cable, a waveguide, a wired communication link, a wireless communication link, and so on). Thus, for example, the signal-bearing medium 1401 may be conveyed by a wireless form of the communication medium 1405 (e.g., a wireless communication medium compliant with the IEEE 802.11 standard or other transmission protocols). One or more program instructions 1402 may be, for example, computer-executable instructions or logic implementation instructions. In some examples, the foregoing computing device may be configured to provide various operations, functions, or actions in response to the program instructions 1402 communicated to the computing device via one or more of the computer-readable medium 1403, the computer-recordable medium 1404, and / or the communication medium 1405. It should be understood that the arrangements described herein are for illustrative purposes only. Thus, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and groups of functions, etc.) can be used instead, and some elements may be omitted altogether depending on the desired results. Additionally, many of the elements described can be implemented as discrete or distributed components, or as functional entities combined with other components in any suitable combination and location.

[0190] Those of ordinary skill in the art can realize that the units and method steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0191] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the devices and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0192] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0193] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0194] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0195] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0196] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for simulating chip design, characterized in that, Including: Obtain a simulation layout constraint file, where the simulation layout constraint file includes electrical constraint definitions, physical constraint definitions, layout design rule definitions, and non-default routing rule (NDR) definitions; Generate a simulation chip design file according to the layout constraint file, where the simulation chip design file includes the layout of the simulation design.

2. The method according to claim 1, wherein The obtaining of the simulation layout constraint file includes: Receive the layout constraint information input by the user in the project engineering file on the integrated development environment (IDE) or the graphical user interface (GUI) to obtain the layout constraint file.

3. The method according to claim 1 or 2, characterized in that, The electrical constraint definitions include circuit trace-related constraint definitions and / or circuit device-related constraint definitions.

4. The method according to claim 3, characterized in that, The circuit trace-related constraint definitions include any one or more of differential signal matching definitions, parasitic capacitance sensitivity definitions, and parasitic resistance sensitivity definitions.

5. The method according to claim 3 or 4, characterized in that The circuit device-related constraint definitions include any one or more of differential pair matching definitions, current mirror matching definitions, parasitic capacitance sensitive device definitions, and parasitic resistance sensitive device definitions.

6. The method according to any one of claims 1 to 5, characterized in that, The physical constraint definitions include physical layout constraint definitions and / or physical routing constraint definitions.

7. The method according to claim 6, wherein The physical layout constraint definitions include any one or more of symmetric layout definitions, alignment layout definitions, proximity layout definitions, capacitor array layout definitions, and metal-oxide-semiconductor field-effect transistor (MOSFET) array layout definitions.

8. The method according to claim 6 or 7, characterized in that, The physical routing constraint definitions include any one or more of symmetric routing definitions, shield wire routing definitions, bus (BUS) line group definitions, and trace track definitions.

9. The method according to any one of claims 1 to 8, characterized in that, The layout design rule definitions include any one or more of process grid design rule definitions, interval design rule definitions between layout layers, width range design rule definitions of layout layers, area design rule definitions of layout layers, and device attribute design rule definitions.

10. The method according to any one of claims 1 to 9, characterized in that The NDR definition includes a routing pattern defined according to the metal layer of the simulation chip.

11. The method according to any one of claims 1 to 10, characterized in that, The simulation chip design file is in a compressed and / or encrypted format.

12. A computer device, characterized in that, Including: An obtaining module for obtaining a simulation layout constraint file, where the simulation layout constraint file includes electrical constraint definitions, physical constraint definitions, layout design rule definitions, and non-default routing rule (NDR) definitions; A processing module for generating a simulation chip design file according to the layout constraint file, where the simulation chip design file includes the layout of the simulation design.

13. The device according to claim 12, wherein, The obtaining module is specifically used for: Receive the layout constraint information input by the user in the project engineering file on the integrated development environment (IDE) or the graphical user interface (GUI) to obtain the layout constraint file.

14. The device according to claim 12 or 13, characterized in that, The electrical constraint definitions include circuit trace-related constraint definitions and / or circuit device-related constraint definitions.

15. The device according to claim 14, wherein The circuit trace-related constraint definitions include any one or more of differential signal matching definitions, parasitic capacitance sensitivity definitions, and parasitic resistance sensitivity definitions.

16. The device according to claim 14 or 15, characterized in that, The circuit device-related constraint definitions include any one or more of differential pair matching definitions, current mirror matching definitions, parasitic capacitance sensitive device definitions, and parasitic resistance sensitive device definitions.

17. The device according to any one of claims 12 to 16, characterized in that, The physical constraint definitions include physical layout constraint definitions and / or physical routing constraint definitions.

18. The device according to claim 17, wherein, The physical layout constraint definition includes any one or more of a symmetric layout definition, an alignment layout definition, a proximity layout definition, a capacitor array layout definition, and a metal oxide semiconductor field effect transistor (MOSFET) array layout definition.

19. The device according to claim 17 or 18, characterized in that, The physical routing constraint definition includes any one or more of a symmetric routing definition, a shielded wire routing definition, a bus (BUS) line group definition, and a routing track definition.

20. The device according to any one of claims 12 to 19, characterized in that The layout design rule definition includes any one or more of a process grid design rule definition, an interval design rule definition between layout layers of a layout, a width range design rule definition of layout layers of a layout, an area design rule definition of layout layers of a layout, and a device attribute design rule definition.

21. The device according to any one of claims 12 to 20, characterized in that, The NDR definition includes a routing pattern defined according to the metal levels of an analog chip.

22. The device according to any one of claims 12 to 21, characterized in that, The analog chip design file is in a compressed and / or encrypted format.

23. A computer device, characterized in that, Comprising: A processor, which is used to be coupled with a memory, read and execute instructions and / or program codes in the memory to execute the method according to any one of claims 1-11.

24. A computer-readable medium, characterized in that, The computer-readable medium stores computer program codes, which, when running on a computer, cause the computer to execute the method according to any one of claims 1-11.

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