GOA driving circuit and method, cascade circuit and display panel

Abstract

The invention discloses a GOA driving circuit and method, a cascade circuit and a display panel. The driving circuit comprises a forward scanning starting unit, a reverse scanning starting unit, a first pull-down unit, a second pull-down unit and an output unit. The output end of the forward scanning starting unit is connected with the output end of the reverse scanning starting unit, the first pull-down unit, the second pull-down unit and the output unit; the second pull-down unit is used for carrying out primary pull-down on the level of the input end of the output unit of the nth row of gate line when the (n + 1) th row of gate line drives and outputs; and the first pull-down unit is used for carrying out secondary pull-down on the level of the input end of the output unit of the nth row of gate line when the (n + 2) th row of gate line drives and outputs. The two pull-down units are arranged in the GOA driving circuit, and the current GOA driving circuit is pulled down twice in the subsequent two rows of driving, so that the problem of abnormal display caused by incomplete pull-down of the level of the input end of the output unit of the GOA driving circuit is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of display panel driving, and particularly to a GOA driving circuit and method, a cascading circuit, and a display panel. Background Art

[0002] The gate driving circuit GOA technology (gate on array) refers to integrating a gate driving circuit on an array substrate. It uses the same process as thin-film transistors to fabricate a line scanning driving circuit on a glass substrate. By directly making the circuit for controlling the gate on the TFT-LCD panel, the driving and display of the panel are realized. It saves the traditional gate driving circuit (COF) and improves the process yield of the module.

[0003] The gate driving circuit GOA technology is favored by consumers because it can reduce the border of the display screen. However, since the GOA technology arranges the gate driving circuit on the display screen, when the display screen is in a low-temperature environment, the GOA circuit driving is insufficient, the transistor current decreases, affecting the output of the gate circuit Gout; or when electrostatic (ESD) acts on the display screen, the output of the gate circuit may also output abnormally; or when external stress such as the display screen is subjected to external pressure and the display screen is mechanically deformed, the characteristics of the TFT of the GOA circuit may also change, affecting the output of the display screen Gout; or when the display screen is subjected to external disturbances and signal interferences, it may also affect the output of the display screen Gout, causing the display screen to have abnormal display, affecting the display effect, and reducing the experience of consumers.

[0004] In summary, there is a need for a method that can avoid the abnormal output of the gate Gout, thereby improving the display quality of the display screen and enhancing the product competitiveness. Summary of the Invention

[0005] In the prior art, when the display panel is affected by the external environmental temperature, electrostatic influence, external signal interference or mechanical deformation, the output of the GOA driving circuit is abnormal, thereby causing abnormal display.

[0006] To solve the above problems, a GOA driving circuit and method, a cascading circuit, and a display panel are proposed. By setting two pull-down units in the GOA driving circuit and performing two pull-down operations on the current GOA driving circuit in the subsequent two-line driving, the problem that the input terminal level of the output unit of the GOA driving circuit is not pulled down completely is avoided, and the problem that the display panel in the prior art has abnormal display when affected by the external environmental temperature, electrostatic influence, external signal interference or mechanical deformation is solved. In a first aspect, a GOA driving circuit for driving a corresponding nth row gate line includes: A forward scan start unit, a reverse scan start unit, a first pull-down unit, a second pull-down unit, and an output unit; The output terminal of the forward scan start unit is commonly connected to the output terminal of the reverse scan start unit, the first pull-down unit, the second pull-down unit, and the output unit; The first pull-down unit is also electrically connected to the second pull-down unit, and the second pull-down unit is also electrically connected to the output unit; The second pull-down unit is electrically connected to the output terminal of the output unit of the (n + 1)-th row gate line, and is used for pulling down the input terminal level of the output unit of the n-th row gate line once when the (n + 1)-th row gate line drives an output; The first pull-down unit is electrically connected to the output terminal of the output unit of the (n + 2)-th row gate line, and is used for pulling down the input terminal level of the output unit of the n-th row gate line twice when the (n + 2)-th row gate line drives an output; Wherein, n is a natural number.

[0007] Combined with the GOA driving circuit described in the first aspect of the present invention, in the first possible implementation manner, the forward scan start unit and the reverse scan start unit respectively include: A first transistor and a second transistor; The gates of the first transistor and the second transistor are electrically connected to the start signal line and the reset signal line respectively. The drain of the first transistor is electrically connected to the forward scan signal line, and the source of the second transistor is electrically connected to the reverse scan signal line. The source of the first transistor and the drain of the second transistor are commonly connected.

[0008] Combined with the first possible implementation manner of the first aspect of the present invention, in the second possible implementation manner, the output unit includes: A third transistor and a first capacitor; The gate of the third transistor, the first end of the first capacitor, the source of the first transistor, and the drain of the second transistor are commonly connected to a first common point; The second end of the first capacitor and the source of the third transistor are commonly connected to a second common point; The drain of the third transistor is electrically connected to the clock signal line.

[0009] Combined with the second possible implementation manner of the first aspect of the present invention, in the third possible implementation manner, the first pull-down unit includes a fourth transistor; The first end of the second pull-down unit and the drain of the fourth transistor are commonly connected to the first common point; The gate of the fourth transistor is electrically connected to the output terminal of the output unit of the (n + 2)-th row gate line; The source of the fourth transistor is electrically connected to the second end of the second pull-down unit; The third end of the second pull-down unit is commonly connected to the second common point.

[0010] In a second aspect, a cascaded circuit includes a plurality of GOA driving circuits and GOA signal line units described in the first aspect, and each of the GOA driving circuits is electrically connected to a corresponding clock signal line, a forward scan signal line, a reverse scan signal line, and a low-level signal line of the GOA signal line unit; The gate of the forward scan start unit transistor of the GOA driving circuit corresponding to the first row of gate lines is electrically connected to the start signal line, the output end of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the gate of the forward scan start unit transistor of the GOA driving circuit corresponding to the (n + 1)th row, the second pull-down unit of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the output end of the GOA driving circuit corresponding to the (n + 1)th row, and the first pull-down unit of the GOA driving circuit corresponding to the nth row of gate lines is electrically connected to the output end of the GOA driving circuit corresponding to the (n + 2)th row.

[0011] In a third aspect, a GOA driving method using the cascaded circuit described in the second aspect includes: Step 100: Start the GOA driving circuit of the nth row, output a driving signal to the nth row of gate lines, and input a high-level start signal to the GOA driving circuit of the (n + 1)th row to start the GOA driving circuit of the (n + 1)th row; Step 200: The GOA driving circuit of the (n + 1)th row outputs a driving signal, inputs a high-level start signal to the GOA driving circuit of the (n + 2)th row, and performs a first pull-down on the GOA driving circuit of the nth row; Step 300: The GOA driving circuit of the (n + 2)th row outputs a driving signal, inputs a high-level start signal to the GOA driving circuit of the (n + 3)th row, and performs a second pull-down on the GOA driving circuit of the nth row; where n is a natural number.

[0012] Combined with the GOA driving method described in the third aspect of the present invention, in a first possible implementation manner, the step 100 includes: Step 110: When the gate line of the GOA driving circuit of the nth row is the initial row, the gate of the forward scan start unit transistor of the GOA driving circuit of the nth row is electrically connected to the start signal line to obtain a high-level start signal; Step 120: The output unit of the GOA driving circuit of the nth row outputs a high-level signal to the gate of the forward scan start unit transistor of the GOA driving circuit of the (n + 1)th row to input a high-level start signal.

[0013] Combined with the first possible implementation manner of the third aspect of the present invention, in a second possible implementation manner, the step 200 includes: Step 210: The output terminal of the output unit of the (n + 1)-th row GOA driving circuit inputs a high-level start signal to the gate of the transistor of the positive scan start unit of the (n + 2)-th row GOA driving circuit, and at the same time, the second pull-down unit of the n-th row GOA driving circuit performs a pull-down on the n-th row GOA driving circuit once.

[0014] Combined with the first possible implementation manner of the third aspect of the present invention, in the second possible implementation manner, the step 300 includes: Step 310: The output terminal of the output unit of the (n + 2)-th row GOA driving circuit inputs a high-level start signal to the gate of the transistor of the positive scan start unit of the (n + 3)-th row GOA driving circuit, and at the same time, the first pull-down unit of the n-th row GOA driving circuit performs a secondary pull-down on the n-th row GOA driving circuit.

[0015] Fourth aspect, a display panel includes the cascade circuit described in the second aspect.

[0016] Implementing the GOA driving circuit and method, cascade circuit and display panel of the present invention, by setting two pull-down units in the GOA driving circuit and performing two pull-downs on the current GOA driving circuit in the subsequent two-row driving, it avoids the incomplete pull-down of the input terminal level of the output unit of the GOA driving circuit, and solves the problem of abnormal display of the display panel in the prior art when affected by external environmental temperature, static electricity, external signal interference or mechanical deformation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0018] Figure 1 is a schematic diagram of a GOA driving circuit in the prior art; Figure 2 is a schematic diagram of a cascade circuit in the prior art; Figure 3 is a schematic diagram of a GOA driving circuit in the present application; Figure 4 is a schematic diagram of a cascade circuit in the present application; Figure 5 is a driving timing diagram of the cascade circuit in the present application; Figure 6 is a module connection diagram of the GOA driving circuit in the present application; Figure 7It is a schematic flow chart of a specific embodiment of the GOA driving method in the present application; Figure 8 It is Figure 7 a schematic flow chart of a specific embodiment of step 100 in Specific embodiments

[0019] Next, the technical solutions in the present invention will be clearly and completely described in conjunction with the accompanying drawings in the invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments in the present invention, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0021] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0022] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application.

[0023] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0024] In the prior art, when the display panel is affected by the external environmental temperature, static electricity, external signal interference or mechanical deformation, the GOA driving circuit outputs abnormally, thereby causing display abnormalities, such as Figure 1 andFigure 2 , Figure 1 is a schematic diagram of a GOA driving circuit in the prior art, Figure 2 is a schematic diagram of a cascade circuit in the prior art; when the Gout output in the GOA driving circuit is abnormal, usually the potential of the first common contact point is not pulled down completely, so that the subsequent clock signal (CK signal) passes through the third transistor T3 of the output unit, and the output Gout of the output unit of the GOA driving circuit outputs abnormally, affecting normal display. For example, when the display screen is in the forward scan (the forward scan signal line FW is at a high level and the reverse scan signal line BW is at a low level), after the output Gout1 of the GOA driving circuit of the first row outputs a high level, Gout1 will simultaneously input the start signal STV of the GOA driving circuit GOA2 of the second row as the start signal. When the next CK signal is input to the drain of T3 of GOA2, at this time Gout2 will output a high level, and this high level is also connected to the RST position of GOA1, that is Figure 1 the gate of the second transistor T2, and the low level BW passes through T2 to reach the first common contact point, so that the P point of GOA1 is pulled down, that is, at this time the gate of the third transistor T3 is at a low level, turning off T3 to prevent the subsequent CK from passing through T3 and causing the Gout1 output to be abnormal. However, when the display screen is in a special environment (such as low temperature, ESD, external stress, external disturbance, signal coupling, etc.), the potential of the P point is not pulled down completely, or the abnormal output of Gout of the previous stage may cause the potential of the P point not to be pulled to a low level, affecting the normal display of the subsequent Gout.

[0025] In view of the above problems, a GOA driving circuit and method, a cascade circuit and a display panel are proposed.

[0026] In a first aspect, a GOA driving circuit, as shown in Figure 5 and Figure 6 , Figure 5 is a schematic diagram of the driving timing of the cascade circuit in the present application, Figure 6It is a schematic diagram of module connections of the GOA driving circuit in the present application; it is used to drive the corresponding nth row gate line, and includes a forward scan start unit, a reverse scan start unit, a first pull-down unit, a second pull-down unit, and an output unit; the output end of the forward scan start unit is commonly connected to the output end of the reverse scan start unit, the first pull-down unit, the second pull-down unit, and the output unit; the first pull-down unit is also electrically connected to the second pull-down unit, and the second pull-down unit is also electrically connected to the output unit; the second pull-down unit is electrically connected to the output end of the output unit of the (n + 1)th row gate line, and is used to perform a first pull-down on the input end level of the output unit of the nth row gate line when the (n + 1)th row gate line drives and outputs; the first pull-down unit is electrically connected to the output end of the output unit of the (n + 2)th row gate line, and is used to perform a second pull-down on the input end level of the output unit of the nth row gate line when the (n + 2)th row gate line drives and outputs; where n is a natural number. By setting two pull-down units in the GOA driving circuit and performing two pull-downs on the current GOA driving circuit in the subsequent two-row driving, it avoids the incomplete pull-down of the input end level of the output unit of the GOA driving circuit, and solves the problem of abnormal display of the display panel in the prior art when affected by the external ambient temperature, static electricity, external signal interference, or mechanical deformation.

[0027] As Figure 3 , Figure 3 As shown in, the forward scan start unit and the reverse scan start unit of the GOA driving circuit schematic diagram in the present application respectively include a first transistor T1 and a second transistor T2; the gates of the first transistor T1 and the second transistor T2 are respectively electrically connected to the start signal line and the reset signal line, the drain of the first transistor T1 is electrically connected to the forward scan signal line FW, the source of the second transistor T2 is electrically connected to the reverse scan signal line BW, and the source of the first transistor T1 and the drain of the second transistor T2 are commonly connected.

[0028] As Figure 3 As shown in, the output unit includes a third transistor T3 and a first capacitor C; the gate of the third transistor T3, the first end of the first capacitor C, the source of the first transistor T1, and the drain of the second transistor T2 are commonly connected to the first common point P; the second end of the first capacitor C and the source of the third transistor T3 are commonly connected to the second common point; the drain of the third transistor T3 is electrically connected to the clock signal line CK.

[0029] As Figure 3 As shown in, the first pull-down unit includes a fourth transistor; the first end of the second pull-down unit and the drain of the fourth transistor are commonly connected to the first common point P; the gate of the fourth transistor is electrically connected to the output end of the output unit of the (n + 2)th row gate line; the source of the fourth transistor is electrically connected to the second end of the second pull-down unit; the third end of the second pull-down unit is commonly connected to the second common point.

[0030] In a second aspect, a cascaded circuit, as Figure 4 ,Figure 4 It is a schematic diagram of a cascaded circuit in the present application; it includes multiple GOA driving circuits and GOA signal line units of the first aspect. Each GOA driving circuit is electrically connected to the corresponding clock signal line CK, forward scan signal line FW, reverse scan signal line BW, and low-level signal line VGL of the GOA signal line unit. The gate of the forward scan start unit transistor of the GOA driving circuit GOA1 corresponding to the first row of gate lines is electrically connected to the start signal line. The output end of the GOA driving circuit GOAn corresponding to the nth row of gate lines is electrically connected to the gate of the forward scan start unit transistor of the GOA driving circuit GOAn+1 corresponding to the (n + 1)th row. The second pull-down unit of the GOA driving circuit GOAn corresponding to the nth row of gate lines is electrically connected to the output end of the GOA driving circuit GOAn+1 corresponding to the (n + 1)th row. The first pull-down unit of the GOA driving circuit GOAn corresponding to the nth row of gate lines is electrically connected to the output end of the GOA driving circuit GOAn+2 corresponding to the (n + 2)th row.

[0031] Such as Figure 4 , the first pull-down unit is like Figure 4 RST2 in Figure 4 , the second pull-down unit is like

[0032] In the third aspect, a GOA driving method, such as Figure 7 , Figure 7It is a schematic flow diagram of a specific embodiment of the GOA driving method in the present application; adopting the cascaded circuit of the second aspect, including: Step 100, start the n-th row GOA driving circuit, output a driving signal to the n-th row gate line, and input a high-level start signal to the (n + 1)-th row GOA driving circuit to start the (n + 1)-th row GOA driving circuit; Step 200, the (n + 1)-th row GOA driving circuit outputs a driving signal, inputs a high-level start signal to the (n + 2)-th row GOA driving circuit, and performs a first pull-down on the n-th row GOA driving circuit; Step 300, the (n + 2)-th row GOA driving circuit outputs a driving signal, inputs a high-level start signal to the (n + 3)-th row GOA driving circuit, and performs a second pull-down on the n-th row GOA driving circuit; where n is a natural number.

[0033] Preferably, as Figure 8 , Figure 8 is Figure 7 a schematic flow diagram of a specific embodiment of Step 100. Step 100 includes: Step 110, when the gate line of the n-th row GOA driving circuit is the initial row, the gate of the positive-scan start unit transistor of the n-th row GOA driving circuit is electrically connected to the start signal line STV to obtain a high-level start signal; Step 120, the output unit of the n-th row GOA driving circuit outputs a high-level signal to the gate of the positive-scan start unit transistor of the (n + 1)-th row GOA driving circuit to input a high-level start signal.

[0034] Preferably, Step 200 includes: Step 210, the output terminal of the output unit of the (n + 1)-th row GOA driving circuit inputs a high-level start signal to the gate of the positive-scan start unit transistor of the (n + 2)-th row GOA driving circuit, and at the same time performs a first pull-down on the n-th row GOA driving circuit through the second pull-down unit of the n-th row GOA driving circuit.

[0035] Preferably, Step 300 includes: Step 310, the output terminal of the output unit of the (n + 2)-th row GOA driving circuit inputs a high-level start signal to the gate of the positive-scan start unit transistor of the (n + 3)-th row GOA driving circuit, and at the same time performs a second pull-down on the n-th row GOA driving circuit through the first pull-down unit of the n-th row GOA driving circuit.

[0036] Fourth aspect, a display panel, including the cascaded circuit of the second aspect.

[0037] The GOA driving circuit and method, cascading circuit and display panel for implementing the present invention set two pull-down units in the GOA driving circuit, and perform two pull-down operations on the current GOA driving circuit in the subsequent two-line driving, avoiding incomplete pull-down of the input terminal level of the output unit of the GOA driving circuit, and solving the problem of abnormal display of the display panel in the prior art when affected by external environmental temperature, electrostatic influence, external signal interference or mechanical deformation.

[0038] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A GOA driving circuit, for driving a corresponding row gate line, characterized in that: include: A forward scanning start unit, a reverse scanning start unit, a first pull-down unit, a second pull-down unit and an output unit; The output end of the forward scanning start unit is connected with the output end of the reverse scanning start unit, the first pull-down unit, the second pull-down unit and the output unit; The first pull-down unit is also electrically connected to the second pull-down unit, and the second pull-down unit is also electrically connected to the output unit; The second pull-down unit is electrically connected to the output end of the output unit of the n+1th row of gate lines, and is used to pull down the input end level of the output unit of the nth row of gate lines when the n+1th row of gate lines is driven and output; The first pull-down unit is electrically connected to the output end of the output unit of the n+2th row of gate lines, and is used to perform a secondary pull-down on the input end level of the output unit of the nth row of gate lines when the n+2th row of gate lines is driven and output; Wherein, n is a natural number.

2. The GOA driving circuit according to claim 1, characterized in that: The forward scanning start unit and the reverse scanning start unit respectively include: a first transistor and a second transistor; The gate of the first transistor and the gate of the second transistor are electrically connected to the start signal line and the reset signal line respectively, the drain of the first transistor is electrically connected to the forward scan signal line, the source of the second transistor is electrically connected to the reverse scan signal line, and the source of the first transistor is connected to the drain of the second transistor in common.

3. The GOA driving circuit according to claim 2, characterized in that: The output unit comprises: a third transistor and a first capacitor; The gate of the third transistor, the first end of the first capacitor, the source of the first transistor, and the drain of the second transistor are connected to a first common point; The second end of the first capacitor and the source of the third transistor are connected to a second common point; A drain of the third transistor is electrically connected to a clock signal line.

4. The GOA driving circuit according to claim 3, characterized in that: The first pull-down unit includes a fourth transistor; The first end of the second pull-down unit and the drain of the fourth transistor are commonly connected to the first common point; The gate of the fourth transistor is electrically connected to the output end of the output unit of the (n+2)th row of gate lines; The source of the fourth transistor is electrically connected to the second end of the second pull-down unit; The third ends of the second pull-down units are commonly connected to the second common point.

5. A cascade circuit, characterized in that: The method comprises a plurality of GOA drive circuits and GOA signal line units according to any one of claims 1 to 4, wherein each of the GOA drive circuits is electrically connected to a clock signal line, a forward scan signal line, a reverse scan signal line and a low level signal line corresponding to the GOA signal line unit; The gate of the positive scan start unit transistor of the GOA drive circuit corresponding to the first row of gate lines is electrically connected to the start signal line, the output end of the GOA drive circuit corresponding to the nth row of gate lines is electrically connected to the gate of the positive scan start unit transistor of the GOA drive circuit corresponding to the n+1th row, the second pull-down unit of the GOA drive circuit corresponding to the nth row of gate lines is electrically connected to the output end of the GOA drive circuit corresponding to the n+1th row, and the first pull-down unit of the GOA drive circuit corresponding to the nth row of gate lines is electrically connected to the output end of the GOA drive circuit corresponding to the n+2th row.

6. A GOA driving method, using the cascade circuit of claim 5, characterized in that: include: Step 100, starting the GOA driving circuit of the nth row, outputting a driving signal to the gate line of the nth row, and inputting a high level starting signal to the GOA driving circuit of the n+1th row to start the GOA driving circuit of the n+1th row; Step 200, the GOA driving circuit of the n+1th row outputs a driving signal, inputs a high level start signal to the GOA driving circuit of the n+2th row, and pulls down the GOA driving circuit of the nth row once; Step 300, the GOA driving circuit of the n+2th row outputs a driving signal, inputs a high level start signal to the GOA driving circuit of the n+3th row, and performs a secondary pull-down on the GOA driving circuit of the nth row; Wherein, n is a natural number.

7. The GOA driving method according to claim 6, characterized in that: The step 100 comprises: Step 110, when the gate line of the GOA driving circuit in the nth row is the initial row, the gate of the positive scan start unit transistor of the GOA driving circuit in the nth row is electrically connected to the start signal line to obtain a high level start signal; Step 120: the output unit of the GOA driving circuit of the nth row outputs a high level signal to the gate of the positive scan start unit transistor of the GOA driving circuit of the n+1th row to input the high level start signal.

8. The GOA driving method according to claim 7, characterized in that: The step 200 comprises: Step 210: the output end of the output unit of the n+1th row GOA driving circuit inputs a high-level start signal to the gate of the positive scan start unit transistor of the n+2th row GOA driving circuit, and simultaneously pulls down the nth row GOA driving circuit through the second pull-down unit of the nth row GOA driving circuit.

9. The GOA driving method according to claim 8, characterized in that: The step 300 includes: Step 310: the output end of the output unit of the GOA driving circuit of the n+2th row inputs a high-level start signal to the gate of the positive scan start unit transistor of the GOA driving circuit of the n+3th row, and simultaneously pulls down the GOA driving circuit of the nth row for the second time through the first pull-down unit of the GOA driving circuit of the nth row.

10. A display panel, characterized in that: Includes the cascade circuit described in claim 5.

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