Memory Controller and 3D Stacked Memory

Abstract

The present invention provides a memory controller and a three-dimensional stacked memory. The trimming configuration parameter information of each memory die in the memory stack can be stored by the EFUSE control logic module in the trimming system of the memory controller into the EFUSE memory of the memory die. After power-on, the trimming configuration parameter information stored in the EFUSE memory of each memory die can be read by the EFUSE control logic module, and output as multi-stage pipelined signals through pipeline control and broadcast to several storage control modules. Thus, the trimming configuration parameter information can be reliably written to the storage units of the main memory of the memory die, and the writing of the trimming configuration parameter information and power-on are both completed in the memory controller and the memory stack without an off-chip memory, thereby simplifying the system architecture and the writing process of the trimming configuration parameter information during power-on.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and particularly to a memory controller and a three-dimensional stacked memory. Background Art

[0002] DRAM (Dynamic Random Access Memory) has the advantages of high speed, high density, and low cost, and is currently widely used in fields such as artificial intelligence.

[0003] In existing DRAM chips, trimming logics such as built-in self-test (BIST) logic are integrated into the memory controller logic die of the DRAM chip, and the trimming configuration parameter information (such as redundancy repair information, etc.) generated by the trimming logic is stored in an off-chip memory such as an additional nor flash memory or a nand flash memory through the memory controller logic die. After the DRAM chip is powered on, the corresponding trimming configuration parameter information needs to be loaded from the off-chip memory into the memory controller logic die to implement trimming, which brings a great overhead to the memory controller logic die and also requires an additional off-chip memory, which is very unfriendly in applications such as mobile phones and wearables. Summary of the Invention

[0004] The purpose of the present invention is to provide a memory controller and a three-dimensional stacked memory, which can eliminate the off-chip memory for storing the trimming configuration parameter information (such as bad point addresses, etc.) of the memory and improve reliability.

[0005] To achieve the above purpose, the present invention provides a memory controller, which is coupled to and controls a corresponding memory stack. The memory stack includes a plurality of memory dies, each memory die includes a main memory and an EFUSE memory. The main memory has a plurality of memory cells. The memory controller has a trimming system, and the trimming system includes:

[0006] A trimming logic module, configured to obtain the trimming configuration parameter information of the main memory of at least one of the memory dies;

[0007] An EFUSE control logic module, coupled to the trimming logic module and each of the EFUSE memories, and configured to write the trimming configuration parameter information of each memory die obtained by the trimming logic module into the corresponding EFUSE memory of the memory die, and, when powered on, read out the trimming configuration parameter information in each of the EFUSE memories, output the read trimming configuration parameter information as a plurality of levels of pipeline signals, and select an appropriate level of pipeline signal from the plurality of levels of pipeline signals for broadcasting, or broadcast all of the plurality of levels of pipeline signals;

[0008] A plurality of memory control modules are coupled to the EFUSE control logic module in parallel. Each memory control module is coupled to a plurality of the memory cells in the memory stack, and is configured to, after power-on, receive the appropriate first-stage pipeline signal or receive the plurality of stages of pipeline signals and select the appropriate first-stage pipeline signal therefrom, and then extract the corresponding trimming configuration parameter information from the appropriate first-stage pipeline signal received or selected by it for latching.

[0009] Optionally, the plurality of memory dies are j + 1, and the number of memory cells coupled by each memory control module and bonded by the same through-silicon via path is (j + 1) / l pieces, and the number of memory cells coupled by each memory control module and belonging to the same-layer memory die is k + 1, where 0 < l ≤ j + 1, and j and k are integers greater than or equal to 0; wherein, each memory control module includes (j + 1) / l *(k + 1) groups of latches, and each group of latches is configured to latch the trimming configuration parameter information of each of the memory cells in the corresponding-layer memory die respectively.

[0010] Optionally, the EFUSE control logic module includes:

[0011] An EFUSE write control logic unit, coupled to the trimming logic module and each of the EFUSE memories, and configured to write the trimming configuration parameter information obtained by the trimming logic module into the corresponding EFUSE memory;

[0012] An EFUSE read control logic unit, coupled to each of the EFUSE memories, and configured to read the trimming configuration parameter information in each of the EFUSE memories after power-on;

[0013] A pipeline logic unit, coupled to the EFUSE read control logic unit, and configured to read the trimming configuration parameter information in each of the EFUSE memories, and perform pipeline control on the read result to convert it into a plurality of stages of pipeline signals;

[0014] A pipeline signal selection unit, coupled to the pipeline logic unit, and configured to select an appropriate first-stage pipeline signal from the plurality of stages of pipeline signals and broadcast it to each of the memory control modules;

[0015] Wherein, each of the memory control modules synchronously receives the appropriate first-stage pipeline signal.

[0016] Optionally, the signal transmission paths between the plurality of storage control modules and the output end of the pipeline signal selection unit are of different lengths. The longer the signal transmission path is, the greater the routing delay generated thereby is. The appropriate number of stages of the first-level pipeline signal is determined by the routing delay generated on the longest signal transmission path.

[0017] Optionally, the EFUSE control logic module includes:

[0018] An EFUSE write control logic unit, coupled to the trimming logic module and each of the EFUSE memories, and configured to write the trimming configuration parameter information obtained by the trimming logic module into the corresponding EFUSE memory;

[0019] An EFUSE read control logic unit, coupled to each of the EFUSE memories, and configured to read the trimming configuration parameter information in each of the EFUSE memories after power-on;

[0020] A pipeline logic unit, coupled to the EFUSE read control logic unit, and configured to read the trimming configuration parameter information in each of the EFUSE memories, convert the read result into a plurality of stages of pipeline signals through pipeline control, and broadcast the plurality of stages of pipeline signals to the plurality of storage control modules;

[0021] Wherein, each of the storage control modules includes a pipeline signal selection unit. The pipeline signal selection unit is coupled to the pipeline logic unit, and is configured to receive the plurality of stages of pipeline signals, and select an appropriate stage of pipeline signal therefrom to latch the corresponding trimming configuration parameter information in the appropriate stage of pipeline signal.

[0022] Optionally, the signal transmission paths between the plurality of storage control modules and the output end of the pipeline signal selection unit are of different lengths. The longer the signal transmission path is, the greater the routing delay generated thereby is. The smaller the number of stages of the pipeline signal selected by the pipeline signal selection unit is, so that the latches in each of the storage control modules can latch the corresponding trimming configuration parameter information synchronously.

[0023] Optionally, the pipeline logic unit includes a plurality of cascaded pipeline units. Each stage of the pipeline unit outputs a corresponding stage of pipeline signal, and the pipeline signal output by the previous stage of the pipeline unit is the input of the next stage of the pipeline unit; and / or, the contents of the stages of pipeline signals in the plurality of stages of pipeline signals are the same. Each group of latches in each of the storage control modules latches the corresponding trimming configuration parameter information of the corresponding storage unit in the same layer to which it is coupled.

[0024] Optionally, the pipeline unit includes a register, and / or the number of stages of the pipeline unit is equal to the number of the storage control modules.

[0025] Optionally, the pipeline signal selection unit includes:

[0026] A selection signal generator is used to provide a required selection signal;

[0027] The multiplexer is coupled to the selection signal generator and the plurality of pipeline signals and is used to select an appropriate first-stage pipeline signal from the plurality of pipeline signals for output according to the selection signal.

[0028] Optionally, the selection signal provided by the selection signal generator can be adaptively adjusted to dynamically adjust the number of levels of the appropriate first-level pipeline signal selected by the multiplexer to ensure that each storage control module receives the corresponding first-level pipeline signal in time synchronization.

[0029] Optionally, the selection signal generator includes at least one of the following (1) to (3):

[0030] (1) a configuration register for configuring a corresponding value, and the selection signal is adaptively adjusted as the value configured in the configuration register changes;

[0031] (2) a temperature detection circuit, configured to detect a corresponding temperature, wherein the selection signal is adaptively adjusted as the temperature detected by the temperature detection circuit changes;

[0032] (3) A voltage detection circuit, configured to detect a corresponding voltage, wherein the selection signal is adaptively adjusted as the voltage detected by the voltage detection circuit changes.

[0033] Optionally, the trimming configuration parameter information includes at least one of bad pixel information, timing trimming information and voltage trimming information.

[0034] Optionally, the trimming logic module includes a built-in self-test unit for performing a built-in self-test on the memory stack to detect bad pixels in the memory stack.

[0035] Optionally, each of the storage units includes a main storage unit structure and a redundant storage unit structure, and each of the storage control modules further includes a latch and a redundant matching unit, wherein:

[0036] The latch is used to capture the bad pixel address from the appropriate first-level pipeline signal received or selected by the storage control module and latch it;

[0037] The redundant matching unit is coupled to the latch and is used to extract the bad point address from the latch and perform analysis to determine the storage unit hit by the bad point address, and then replace the bad point address in the main storage unit structure with the address of the corresponding redundant storage unit structure in the storage unit.

[0038] Optionally, the memory controller further includes a plurality of master device interfaces for communicating with the master device. Each master device interface is a multi-IO parallel interface, and the trimming logic module obtains the trimming configuration parameter information through the master device interface.

[0039] Based on the same inventive concept, the present invention further provides a three-dimensional stacked memory, which includes a memory stack and the memory controller as described in the present invention. The memory controller is disposed on a buffer die. The memory stack includes multiple layers of memory dies stacked three-dimensionally. The multiple layers of memory dies and between them and the buffer die are bonded by through-silicon via hybrid bonding.

[0040] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0041] 1. The trimming configuration parameter information of each memory die in the memory stack can be stored by the EFUSE control logic module in the trimming system of the memory controller into the EFUSE memory of the memory die. After power-on, the trimming configuration parameter information stored in the EFUSE memory of each memory die can be read by the EFUSE control logic module and converted into several levels of pipeline signals through pipeline control. Several storage control modules receive or select a suitable level of pipeline signal in a broadcast manner and latch the trimming configuration parameter information therein. The rewriting and power-on of the trimming configuration parameter information are completed in the memory controller and the memory stack without an off-chip memory, thus simplifying the system architecture and the trimming configuration parameter information writing process during power-on.

[0042] 2. The EFUSE control logic module performs pipeline control output on the trimming configuration parameter information read after power-on, which can improve reliability.

[0043] 3. It is possible to dynamically adjust the number of levels of the appropriate first-level pipeline signal broadcast by the EFUSE control logic module or selected by each storage control module, so that each storage control module synchronously receives the pipeline signal or synchronously extracts the trimming configuration parameter information, thereby ensuring the reliability of the trimming configuration parameter information latched by each storage control module. Description of the Drawings

[0044] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0045] Figure 1 is a schematic structural diagram of a memory controller and a three-dimensional stacked memory according to the first embodiment of the present invention.

[0046] Figure 2 is a schematic structural diagram of an EFUSE control logic module in the memory controller according to the first embodiment of the present invention.

[0047] Figure 3 is a schematic structural diagram of a pipeline logic unit and a pipeline signal selection unit in the EFUSE control logic module of the memory controller according to the first embodiment of the present invention.

[0048] Figure 4 is a schematic structural diagram of the package structure of the memory controller and the three-dimensional stacked memory according to the first embodiment of the present invention.

[0049] Figure 5 is a schematic cell-level structure diagram of a storage unit unit in the memory controller and the three-dimensional stacked memory according to the first embodiment of the present invention.

[0050] Figure 6 is a schematic example diagram of the memory controller according to the first embodiment applied to the built-in test and redundancy repair scenario.

[0051] Figure 7 is a schematic structural diagram of a memory controller and a three-dimensional stacked memory according to the second embodiment of the present invention.

[0052] Figure 8 is a schematic structural diagram of an EFUSE control logic module in the memory controller according to the second embodiment of the present invention.

[0053] Figure 9 is a schematic structural diagram of a storage control module and a pipeline logic unit in the EFUSE control logic module of the memory controller according to the second embodiment of the present invention.

[0054] Figure 10 is a schematic example diagram of the memory controller according to the second embodiment applied to the built-in test and redundancy repair scenario. Detailed implementation manners

[0055] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0056] First Embodiment

[0057] Please refer to Figure 1 , this embodiment provides a memory controller 2, which is coupled between a master device (Master, i.e., a device accessing the memory) 1 and a memory stack 3. The memory controller 2 can perform interface conversion to convert commands such as read and write issued by the master device 1 into signals recognizable by the memory stack 3, and complete the conversion of address decoding and data format (such as data bit width) between the master device 1 and the memory stack 3, thereby realizing the necessary control for accessing the memory stack 3 (which includes the control of address signals, data signals, and various command signals).

[0058] The memory controller 2 can be integrated with the memory stack 3 to form a system-level memory chip, or can be independent of the chip of the memory stack 3 as a separate logic chip, or can be integrated with the master device 1 to form a logic chip, or the memory controller 2, the master device 1, and the memory stack 3 can be integrated together to form a system-level logic chip. The present invention does not make specific limitations on this.

[0059] Among them, the master device 1 may include any type of processor device with computing and processing capabilities, such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), a field programmable gate array (FPGA), a dedicated processor, etc. The processor device may be configured to execute instructions or software (including code, operating system, or application programs, etc.), firmware, or a combination thereof that can be executed by one or more computers.

[0060] Please refer to Figure 1 and Figure 4 、 Figure 5 , the memory stack 3 includes j + 1 memory dies 300 to 30j, where j ≥ 1 and is an integer. The j + 1 memory dies 300 to 30j can be three-dimensionally stacked together by through-silicon via (TSV) hybrid bonding. In other examples, the j + 1 memory dies 300 to 30j can also be integrated on the same plane. Each memory die can be any suitable type of memory die structure of DRAM. Among them, DRAM can be any one of, for example, synchronous DRAM (SDRAM), wide I / O DRAM, etc. The memory stack 3 can be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc.

[0061] Further optionally, please refer to Figure 4 , the memory stack 3 includes j + 1 stacked memory dies (such as DRAM dies), the memory controller 2 is disposed in the buffer die 200, and the master device 1 is disposed in the logic die 100. In one example, any suitable packaging technology, such as chip-on-wafer (COW) packaging technology, wafer-on-wafer (WOW) packaging, or chip-on-chip (COC) packaging technology, can be used to package the memory stack 3 and the buffer die 200 together to form a three-dimensional stacked memory.

[0062] For example, memory dies in different layers in the memory stack 3 and between them and the buffer die 200 are stacked together using through-silicon vias (TSVs) and hybrid bonding, which on one hand expands the capacity of the memory stack 3 managed by the memory controller 2 and reduces the chip area. On the other hand, after power-on, calibration configuration parameter information or information such as data to be written is loaded into each memory control module IP1 in the memory controller 2, and then directly and independently loaded into each memory cell unit (such as the latch module of the memory cell) through the through-silicon vias (TSVs), so as to solve the problem of a large number of occupied line tracks when loading calibration configuration parameter information (trim bit) or information such as data to be written into each memory cell through a dedicated trace (EFUSE bus line) in the prior art.

[0063] In another example, any suitable advanced packaging technology such as chip-on-wafer (COW) packaging technology, wafer-on-wafer (WOW) packaging, or chip-on-chip (COC) packaging technology is used to package the memory stack 3, the buffer die 200, and the logic die 100 together to form a three-dimensional stacked memory. For example, the logic die 100 is stacked on the substrate 400, the buffer die 200 is stacked on the logic die 100 using through-silicon vias (TSVs) and hybrid bonding technology, the memory die 300 is stacked on the buffer die 200 through through-silicon vias (TSVs), and the remaining upper-layer memory dies are stacked on the lower-layer memory dies through through-silicon vias (TSVs). In the memory stack 3, the memory dies 300 to 30j in the j+1 layer are vertically stacked together, which has great advantages in terms of the connection lines, bandwidth, and latency of the memory stack 3. It not only saves space, can bring a shorter chip pitch, and thus shorten the signal transmission path and latency. It uses through-silicon vias (TSVs) technology to perforate the edges or specific positions of the memory dies, and uses these holes as paths for wiring to complete the vertical interconnection between memory dies and between them and the buffer die 200, as well as the vertical interconnection between the buffer die 200 and the logic die 100, etc.

[0064] In this embodiment, each memory die includes a main memory 3a and an EFUSE memory. Specifically, in the memory die 300, there is an EFUSE memory EFUSE0 and a corresponding main memory 3a, in the memory die 301, there is an EFUSE memory EFUSE1 and a corresponding main memory 3a, in the memory die 302, there is an EFUSE memory EFUSE2 and a corresponding main memory 3a, and so on. In the memory die 30j-1, there is an EFUSE memory EFUSEj-1 and a corresponding main memory 3a, and in the memory die 30j, there is an EFUSE memory EFUSEj and a corresponding main memory 3a.

[0065] Each main memory 3a includes a plurality of storage units unit. In the memory stack 3, each storage unit unit includes a plurality of cells (memory cells) determined by the intersection of a plurality of word lines WL and a plurality of bit lines BL. Each cell corresponds to a storage address. A cell address can be a 1-bit storage address and is determined by a corresponding word line WL and a bit line BL of the memory stack 3. A bad cell is a bad point. Each storage unit unit in the memory stack 3 has a plurality of storage addresses. The memory controller 2 can manage the access to the memory stack 3 from the cell (memory cell) level to the storage unit unit level. Each storage unit unit can be any suitable management unit at a level higher than the cell level, such as a storage block (block), a sector (sector), or a page (page) of the memory stack 3. Among them, a page contains a plurality of bytes (whose address range can be determined by a plurality of word lines and a plurality of bit lines), a sector contains a plurality of pages, and a storage block contains a plurality of sectors.

[0066] Please refer to Figure 1 , the memory controller 2 of this embodiment includes a trimming system 21 and m main device interfaces 20_0 to 20_m-1, where m≥2 and is an integer.

[0067] Among them, the main device interfaces 20_0 to 20_m-1 are used for communication connection with the main device 1 to implement interface conversion between the main device 1 and the memory stack 3, receive commands from the main device 1 and data to be written into the memory, and return the data read by the main device 1, etc., so as to achieve high bandwidth. The main device interfaces 20_0 to 20_m-1 can be any suitable parallel high-speed communication protocol interface that supports multiple IOs, such as an AXI (Advanced eXtensible Interface) interface or the like. The AXI interface is an on-chip bus interface for a master-slave architecture oriented to high performance, high bandwidth, and low latency. Its address, instruction, and data phases are separated, supports unaligned data transmission, and in burst transmission, only the first address is required. At the same time, the separated read and write data channels support Outstanding (number of unfinished transactions) transmission access and out-of-order access, and are more easily time-convergent, suitable for high-speed memory access. It should be noted that although the AXI protocol is shown in the specification drawings, the present invention is not limited thereto. The main device interfaces 20_0 to 20_m-1 can also adopt any other suitable high-bandwidth interface protocol, such as the AHB (Advanced High-performance Bus) protocol or the CHI (Coherent Hub Interface) protocol, etc.

[0068] The trimming system 21 is coupled to the m master device interfaces 20_0 to 20_m-1, and includes a trimming logic module 210, an EFUSE control logic module 211, and n + 1 storage control module IP1_0 to IP1_n, where n is an integer.

[0069] The trimming logic module 210 is configured to obtain trimming configuration parameter information (trim bit) of the main memory 3a of at least one of the memory dies 300 to 30j, and the trimming configuration parameter information includes at least one of bad point information, timing trimming information (timing), and voltage trimming information.

[0070] The EFUSE control logic module 211 is coupled to the trimming logic module 210 and each of the EFUSE memories EFUSE0 to EFUSEj, and is configured to write the trimming configuration parameter information of each memory die obtained by the trimming logic module 210 into the corresponding EFUSE memory of the memory die, and, when powering on, read out the trimming configuration parameter information in each of the EFUSE memories EFUSE0 to EFUSEj, and output the read trimming configuration parameter information as a plurality of levels of pipeline signals Pipe0 to Pipen, and select a suitable one of the plurality of levels of pipeline signals Pipe0 to Pipe n for broadcasting.

[0071] The plurality of storage control modules IP1_0 to IP1_n are coupled to the EFUSE control logic module 211 in parallel, and each of the storage control modules IP1_0 to IP1_n is respectively coupled to corresponding multiple storage units in the memory stack 3, and is configured to, after powering on, receive a suitable one of the pipeline signals Pipe i, and then extract and latch the corresponding trimming configuration parameter information from the received suitable one of the pipeline signals Pipe i.

[0072] In this embodiment, each of the above modules in the trimming system 21 may adopt any suitable architecture design or circuit design, and the present invention does not make specific limitations thereto.

[0073] For example, please refer to Figure 2 , the EFUSE control logic module 211 includes an EFUSE write control logic unit 211a, an EFUSE read control logic unit 211b, a pipeline logic unit 211c, and a pipeline signal selection unit 211d.

[0074] Among them, the EFUSE write control logic unit 211a is coupled to the trimming logic module 210 and the EFUSE memories EFUSE0 to EFUSEj in the memory die 300 to 30j, and is used to write the trimming configuration parameter information of each memory die 300 to 30j obtained by the trimming logic module 210 into the EFUSE memory of the memory die. For example, the EFUSE write control logic unit 211a writes the trimming configuration parameter information of the memory die 300 into the EFUSE memory EFUSE0 of the memory die 300, writes the trimming configuration parameter information of the memory die 301 into the EFUSE memory EFUSE1 of the memory die 301, writes the trimming configuration parameter information of the memory die 302 into the EFUSE memory EFUSE2 of the memory die 302, and so on, writes the trimming configuration parameter information of the memory die 30j into the EFUSE memory EFUSEj of the memory die 30j.

[0075] The EFUSE read control logic unit 211b is coupled to the EFUSE memories EFUSE0 to EFUSEj in the memory die 300 to 30j, and is used to read out the trimming configuration parameter information in each EFUSE memory EFUSE0 to EFUSEj when powering on.

[0076] The pipeline logic unit 211c is coupled to the EFUSE read control logic unit 211b and the pipeline signal selection unit 211d. The pipeline logic unit 211c is used to control the trimming configuration parameter information read by the EFUSE read control logic unit 211b through a pipeline (Pipeline), and convert it (i.e., output it) into n + 1 levels of pipeline signals Pipe0 to Pipe n. Among them, the latter-stage pipeline signal has a delay relative to the former-stage pipeline signal, but the content of each stage of pipeline signal is the same.

[0077] In an example, the number of pipeline signals output by the pipeline logic unit 211c is equal to the number of storage control modules IP1, both of which are n + 1. For example, please refer to Figure 3, the pipelined logic unit 211c includes corresponding delay chains, which include cascaded first-stage pipeline units 211_0, second-stage pipeline units 211_1... nth-stage pipeline units 211_n-1, and (n + 1)th-stage pipeline units 211_n. Each stage of the pipeline unit outputs a corresponding stage of pipeline signal. The first-stage pipeline unit 211_0 outputs the first-stage pipeline signal Pipe0, the second-stage pipeline unit 211_1 outputs the second-stage pipeline signal Pipe1, the third-stage pipeline unit 211_2 outputs the third-stage pipeline signal Pipe2, and so on. The nth-stage pipeline unit 211_n-1 outputs the nth-stage pipeline signal Pipe n-1, and the (n + 1)th-stage pipeline unit 211_n outputs the (n + 1)th-stage pipeline signal Pipe n. Among them, the output of the previous-stage pipeline unit is the input of the next-stage pipeline unit, and the next-stage pipeline unit delays the received previous-stage pipeline signal and outputs the next-stage pipeline signal.

[0078] Among them, the pipeline unit can adopt any suitable design, such as including registers or logic gates, etc.

[0079] The pipeline signal selection unit 211d is coupled to the pipelined logic unit 211c, and according to the current requirement (which can be the currently configured register value, etc.), selects a suitable stage of pipeline signal Pipei from the (n + 1) stages of pipeline signals Pipe0~Pipe n and broadcasts it to each storage control module IP1_0~IP_n.

[0080] Each storage control module block IP1_0~IP_n is coupled to the pipeline signal selection unit 211d of the EFUSE control logic module 211 in parallel. Each storage control module block IP1_0~IP_n can receive a suitable stage of pipeline signal Pipe i broadcast by the pipeline signal selection unit 211d when powered on, and extracts the trimming configuration parameter information of the corresponding storage unit unit of the same layer to which it is coupled from the pipeline signal Pipe i for latching. And each storage control module IP1_0~IP_n synchronously receives the suitable stage of pipeline signal Pipe i.

[0081] Among them, please combine Figure 1 and Figures 4 to 5 , the memory stack 3 has j + 1 layers of memory dies 300~30j, and are stacked together in turn by the way of through-silicon via hybrid bonding. The number of storage units coupled to each storage control module IP1 and bonded by the same through-silicon via path is (j + 1) / l, and the number of storage units coupled to each storage control module IP1 and belonging to the same layer of memory die is k + 1, 0 < l ≤ j + 1 ( Figure 1 In the embodiment l= 2, and of course it can also be equal to 1 or other integers less than or equal to j + 1), j and k, l are both integers, and both j and k are greater than or equal to 0; each storage control module IP1 includes (j + 1) / l *(k + 1) groups of latches 212a, and each group of latches 212a in each storage control module IP1 is correspondingly set with each storage unit coupled to the storage control module IP1 (that is to say, the total number of storage units unit coupled to each storage control module IP1 is (j + 1) / l *(k + 1)), and each group of the latches is used to latch the trimming configuration parameter information of each storage unit in the memory die cores 300~30j of the corresponding layer.

[0082] Exemplarily, the pipeline signal selection unit 211d includes a selection signal generator 211d1 and a multiplexer 211d2. Among them, the selection signal generator 211d1 is used to provide the required selection signal SEL <q:0>, the multiplexer 211d2 is coupled to the selection signal generator 211d1, the n+1-stage pipelined signals Pipe0 to Pipe n, and each memory control module IP1_0 to IP1_n. Each memory control module IP1 is coupled to k+1 memory cells U0 to Uk of each memory die in the memory stack 3 (i.e., each memory control module IP1 is coupled to a total of (j+1) / l *(k+1) memory cells unit). The multiplexer 211d2 is used to select according to the selection signal SEL provided by the selection signal generator 211d1 <q:0>, selecting an appropriate one-level pipelined signal from the n+1-level pipelined signals Pipe0 to Pipe n for broadcasting. Among them, q≥0 and is an integer.

[0083] In an example, the selection signal SEL provided by the selection signal generator 211d1 <q:0>It can be adaptively adjusted to dynamically adjust the number of stages of the pipelined signal selected by the multiplexer 211d2. Thereby ensuring that each memory control module IP1 can synchronously receive the pipelined signal Pipe and latch the trimming configuration parameters required by the memory cells it manages) from it, thereby ensuring the reliability of the trimming configuration parameter signals latched by each memory control module.

[0084] Optionally, the selection signal generator 211d1 includes at least one of the following (1) to (3):

[0085] (1) A configuration register for configuring a corresponding value, the selection signal SEL <q:0>Adaptive adjustment is made according to the change of the configuration parameter value in the configuration register;

[0086] (2)A temperature detection circuit for detecting the corresponding temperature and selecting signal SEL <q:0>Adaptive adjustment is made according to the temperature change detected by the temperature detection circuit;

[0087] (3) A voltage detection circuit for detecting the corresponding voltage and the selection signal SEL <q:0>It is adaptively adjusted according to the voltage change detected by the voltage detection circuit.

[0088] In this embodiment, the number of storage control module IP1s is relatively large, and the signal transmission paths between each storage control module IP1 and the output end of the multiplexer 211d2 are of different lengths. Therefore, the wiring delays generated on these signal transmission paths are also different. The longer the signal transmission path, the greater the wiring delay generated. In this embodiment, the appropriate number of levels of the first-stage pipelined signal selected by the multiplexer 211d2 can be determined by the wiring delay generated on the longest signal transmission path. Thus, after each storage control module IP1 waits for the same time simultaneously, it can synchronously receive the pipelined signal broadcast by the multiplexer 211d2, and further ensure the reliability of all information reaching the storage control module IP1.

[0089] Please refer to Figure 6 , in the prior art, there is a DRAM chip that integrates the built-in self-test (BIST) logic into the buffer die 200 where the memory controller of the DRAM chip is located, and stores the bad point information obtained from the BIST test (which can also be referred to as "repair information", and is a kind of trimming configuration parameter information of the present invention) generated by the buffer die 200 and stores it in an off-chip storage body such as a nor flash memory or a nand flash memory added outside the buffer die 200. It is required that the user loads the corresponding bad point information from the off-chip storage body outside the buffer die 200 into the buffer die 200 after the DRAM chip is powered on, which brings a great overhead to the buffer die 200 and also requires an additional off-chip storage body, which is very unfriendly in applications such as mobile phones and wearables.

[0090] Based on this, the memory controller 2 provided in this embodiment can be applied to this scenario. Please refer to Figure 1 and Figure 6 , the memory controller 2 includes the above-mentioned master device interfaces 20_0~20_m and the trimming system 21. The trimming system 21 includes a trimming logic module 210, an EFUSE control logic module 211, and several storage control module IP1s. In this application scenario: (1) The trimming logic module 210 includes a built-in self-test (BIST) unit 210a, which is used to perform a built-in self-test on the memory stack 3 to detect bad points (error cells / bits) in the memory stack 3; (2) Each storage unit unit of each main memory 3a of each storage unit has a main storage unit structure 31 and a redundant storage unit structure 32. Each storage control module IP1 includes a redundant matching unit 212b in addition to a latch 212a. Figure 6 For the sake of simplicity of the picture, only a set of latches and a redundant matching unit are shown in one memory control module IP1. When one memory control module IP1 manages x memory cells, there can be x sets of latches and x redundant matching units in this memory control module IP1.

[0091] Among them, the master device 1 writes the corresponding test instructions and related test items into the built-in self-test (BIST) unit 210a through the master device interface. Thereby, the built-in self-test unit 210a starts the test process to realize real-time or intermittent bad point checking, improve the performance of the three-dimensional stacked memory, and meet the requirements of complex application scenarios. Optionally, the built-in self-test unit 210a can support incremental update of the content of the EFUSE memory after multiple tests, without having to update the content of the EFUSE memory after each test, thereby improving the efficiency of the three-dimensional stacked memory.

[0092] In this application scenario, the main memory cell structure 31 in each memory cell unit is a memory array composed of corresponding several word lines WL and several bit lines BL. Each memory address (i.e., each cell) of the main memory cell structure 31 is determined by one word line WL and one bit line BL. The redundant memory cell structure 32 is a redundant array composed of several redundant word lines redundancy WL and several redundant bit lines redundancy BL. Each redundant address of the redundant memory cell structure 32 is determined by one redundant word line and one redundant bit line.

[0093] Each group of latches 212a in each memory control module IP1 is coupled to the pipelined signal selection unit 211d in the EFUSE control logic module 211, and is used to receive the appropriate first-level pipelined signal pipe i broadcast by the pipelined signal selection unit 211d, and latch the bad point information (i.e., the bad point address, which is also the memory address where read / write errors occur in the main memory cell structure 31) of the corresponding memory cell therefrom.

[0094] The redundant matching unit 212b is coupled to the corresponding group of latches 212a, and is used to analyze the remaining resources of the redundant memory cell structure 32 in the memory cell hit by the bad point address according to the bad point address latched by this group of latches 212a, and judge whether there are still remaining redundant addresses in the memory cell hit by the bad point address. If so, replace the bad point address in the main memory cell structure 31 in the memory cell hit by the redundant address corresponding to the redundant memory cell structure 32 in this hit memory cell to complete the redundant repair of this bad point address.

[0095] It should be noted that, in this embodiment, the buffer die 200 can also be referred to as an interface die or a base die. The memory controller 2 is only a part of the buffer die 200 and includes a master device interface and a trimming system 21. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, as an interface between the logic die 100 and the stacked DRAM die 300, the buffer die 200 may further include an input / output (IO) circuit, a circuit for performing a refresh operation on the memory, a circuit for error correction of the memory (such as ECC correction), a circuit for implementing timing constraint rules (such as a phase-locked loop PLL), a circuit for managing power consumption and temperature, a first-in-first-out queue register (fifo), and any other required circuits. These circuits may be integrated in the trimming system 21 or independent of the trimming system. Moreover, these circuits are not the focus of the present invention, so they will not be elaborated herein. The EFUSE memory may also store information other than repair information, such as chip information (including chip voltage fields, chip version numbers, chip production dates, and other information).

[0096] In one example, the trimming system 21 is further configured to allocate and map the address ranges of good memory cells in the corresponding area of the memory stack 3 to the master device interfaces 20_0 to 20_m-1 in a balanced or unbalanced manner.

[0097] In addition, in the embodiments of the present invention, the memory stack 3 may be divided into multiple memory areas. Each memory area serves as a sub-storage system and corresponds to a set of master device interfaces (i.e., m + 1 master device interfaces 20_0 to 20_m) and a trimming system 21, thereby enabling a memory controller 2 to perform trimming on the sub-systems of the memory stack 3 by using multiple trimming systems 21. Alternatively, the memory stack 3 is divided into multiple memory areas. Each memory area serves as a sub-storage system and is correspondingly provided with a memory controller 2 of this embodiment as shown in Figure 1 FIG. Each memory controller 2 has a set of master device interfaces (i.e., m + 1 master device interfaces 20_0 to 20_m) and a trimming system 21, thereby enabling multiple memory controllers 2 to manage the sub-systems of the memory stack 3.

[0098] It should also be noted that the division of the master device interfaces 20_0 to 20_m-1, the trimming system 21, and the various modules inside the trimming system 21 in the memory controller 2 of this embodiment is illustrative and mainly a logical function division. There can be other division methods in actual implementation. Each module or unit in the embodiments of this application can be integrated in a processing module, or each module or unit can exist physically alone, or two or more modules or units can be integrated in a module. The above-mentioned integrated modules or units can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as an SSD), etc.

[0099] Please refer to Figures 1 to 6 , this embodiment also provides a three-dimensional stacked memory, which includes a memory stack 3 and the memory controller 2 as described in the present invention. The memory controller 2 is disposed on a buffer die 200. The memory stack 3 includes j + 1 layers of memory dies 300 to 30j stacked three-dimensionally. Among the j + 1 layers of memory dies 300 to 30j and between them and the buffer die 200, through-silicon via (TSV) hybrid bonding is used.

[0100] In summary, for the memory controller and the 3D stacked memory provided in this embodiment, the trimming configuration parameter information of each memory die in the memory stack can be stored by the EFUSE control logic module in the trimming system of the memory controller into the EFUSE memory of the memory die. After the system is powered on, the trimming configuration parameter information stored in the EFUSE memory of each memory die can be read by the EFUSE control logic module and converted into several levels of pipelined signals through pipeline control, and an appropriate level of signal can be selected from the several levels of pipelined signals and broadcast to several memory control modules, and then the corresponding trimming configuration parameter information is supplemented and latched in the memory control module. The supplementation and power-on of the trimming configuration parameter information are completed in the memory controller and the memory stack, without an off-chip memory, thus simplifying the system architecture and the write process of the trimming configuration parameter information during power-on.

[0101] Furthermore, the EFUSE control logic module performs pipeline control output on the trimming configuration parameter information read after power-on, which can improve reliability.

[0102] Moreover, the EFUSE control logic module can dynamically adjust the number of levels of the pipelined signal it selects, thereby ensuring the reliability of the trimming configuration parameter information latched in each memory control module.

[0103] Second Embodiment

[0104] Please refer to Figures 7 to 10 , this embodiment provides a memory controller, which is coupled to and controls a corresponding memory stack 3. The memory stack includes j + 1 memory dies 300 to 30j. Each memory die includes a main memory 3a and EFUSE memories EFUSE0 to EFUSEj. The main memory 3a in each memory die has k + 1 storage units unit. The memory controller 2 includes a trimming system 21 and m main device interfaces 20_0 to 20_m-1. The trimming system 21 also includes a trimming logic module 210, an EFUSE control logic module 211, and n + 1 memory control modules IP1_0 to IP1_n. Among them, the trimming logic module 210 is used to obtain the trimming configuration parameter information of the main memory of at least one memory die; the EFUSE control logic module 211 is coupled to the trimming logic module 210 and each of the EFUSE memories EFUSE0 to EFUSEj, and is used to write the trimming configuration parameter information of each memory die obtained by the trimming logic module 210 into the corresponding EFUSE memory of the memory die, and, when powered on, read the trimming configuration parameter information in each EFUSE memory, and output the read trimming configuration parameter information as several levels of pipelined signals Pipe0 to Pipe n through pipeline control.

[0105] The difference between the memory controller 2 of this embodiment and that of the first embodiment lies in: (1) After power-on, the EFUSE control logic module 211 broadcasts the read n+1-stage pipeline signals Pipe0 to Pipe n to each memory control module IP1_0 to IP1_n; (2) Each memory control module IP1 is configured to receive the n+1-stage pipeline signals Pipe0 to Pipe n after power-on, select a suitable one of the pipeline signals therefrom, and then latch the corresponding trimming configuration parameter information extracted from the selected pipeline signal.

[0106] In one example, please refer to Figure 8 , the EFUSE control logic module 211 includes an EFUSE write control logic unit 211a, an EFUSE read control logic unit 211b, and a pipeline logic unit 211c. The EFUSE write control logic unit 211a is coupled to the trimming logic module 211 and each EFUSE memory, and is configured to write the trimming configuration parameter information obtained by the trimming logic module 210 into the corresponding EFUSE memory. The EFUSE read control logic unit 211b is coupled to each EFUSE memory, and is configured to read the trimming configuration parameter information in each EFUSE memory after power-on. The pipeline logic unit 211c is coupled to the EFUSE read control logic unit 211b, and is configured to read the trimming configuration parameter information in each EFUSE memory, convert the read result into n+1-stage pipeline signals Pipe0 to Pipe n through pipeline control, and broadcast the n+1-stage pipeline signals Pipe0 to Pipe n to each memory control module IP1_0 to IP1_n. Among them, the pipeline logic unit 211c can adopt the same design as that of the first embodiment, that is, it includes cascaded first-stage pipeline unit 211_0, second-stage pipeline unit 211_1... nth-stage pipeline unit 211_n-1 and n+1th-stage pipeline unit 211_n, and each stage of the pipeline unit outputs a corresponding stage of pipeline signal. The first-stage pipeline unit 211_0 outputs the first-stage pipeline signal Pipe0, the second-stage pipeline unit 211_1 outputs the second-stage pipeline signal Pipe1, the third-stage pipeline unit 211_2 outputs the first-stage pipeline signal Pipe2, and so on. The nth-stage pipeline unit 211_n-1 outputs the nth-stage pipeline signal Pipe n-1, and the n+1th-stage pipeline unit 211_n outputs the n+1th-stage pipeline signal Pipe n. And the output of the previous-stage pipeline unit is the input of the next-stage pipeline unit. Thus, the next-stage pipeline unit delays the previous-stage pipeline signal and outputs the next-stage pipeline signal.

[0107] Please refer to Figure 9 , in this embodiment, each of the storage control module IP1s includes a pipelined signal selection unit 212c and a latch 212a (although not shown, it can be understood that the number of storage units unit managed by each storage control module IP1 is x, and correspondingly, each storage control module IP1 includes x groups of latches). The pipelined signal selection unit 212c is coupled to the pipelined logic unit 211c in the EFUSE control logic module 211 and is configured to receive n + 1 levels of pipelined signals Pipe0 to Pipen to select an appropriate level of pipelined signal therefrom. The group of latches 212a fetches and latches the corresponding trimming configuration parameter information from the level of pipelined signal selected by the pipelined signal selection unit 212c.

[0108] Among them, when the number of memory dies is j + 1, the number of storage units coupled to each storage control module IP1 and bonded by the same through-silicon via path is (j + 1) / l pieces, the number of storage units coupled to each storage control module IP1 and belonging to the same layer of memory dies is k + 1, and each group of latches 212a is used to latch the trimming configuration parameter information of each storage unit in the corresponding layer of memory dies respectively.

[0109] In this embodiment, the circuit of the pipelined signal selection unit 212c can adopt the same design as that of the first embodiment, for example, including a selection signal generator and a multiplexer, which will not be elaborated here. In addition, in an example, in each storage control module IP1, the selection signal SEL provided by the selection signal generator in its pipelined signal selection unit 212c <q:0>It can be adaptively adjusted to dynamically adjust the number of stages of the pipeline signal selected by the multiplexer in the pipeline signal selection unit 212c. Thus, it is ensured that the latches in each memory control module IP1 can synchronously receive the corresponding first-stage pipeline signal Pipe and extract the trimming configuration parameters required by the storage unit Unit it manages for latching, thereby ensuring the reliability of the trimming configuration parameter signals latched by each memory control module.

[0110] Optionally, in each memory control module IP1, the selection signal generator in its pipeline signal selection unit 212c includes at least one of the following (1) to (3):

[0111] (1) A configuration register for configuring the corresponding value, the selection signal SEL <q:0>Adaptive adjustment is made according to the change of the configuration parameter value in the configuration register;

[0112] (2) A temperature detection circuit for detecting the corresponding temperature and selecting signal SEL <q:0>It is adaptively adjusted according to the temperature change detected by the temperature detection circuit;

[0113] (3) A voltage detection circuit for detecting the corresponding voltage and the selection signal SEL <q:0>Adapting and adjusting accordingly with the voltage variation detected by the voltage detection circuit.

[0114] Optionally, in this embodiment, the signal transmission path lengths between each of the storage control modules IP1_0 to IP1_n and the output terminal of the pipeline logic unit 211c in the EFUSE control logic module 211 are different. The longer the signal transmission path, the greater the wiring delay generated. The smaller the number of stages of the pipeline signal selected by the pipeline signal selection unit in each of the storage control modules IP1_0 to IP1_n. Thus, for each of the storage control modules IP1_0 to IP1_n, the sum of the delay of the selected pipeline signal and the wiring delay on its signal transmission path is basically the same, thereby enabling the latches 212a in each of the storage control modules IP1_0 to IP1_n to synchronously latch the corresponding trimming configuration parameter information. In addition, the content of each stage of the pipeline signals Pipe0 to Pipe n is the same, and each group of latches 212a in each of the storage control modules IP1 captures the trimming configuration parameter information of the storage cells in the same layer to which it is coupled for latching.

[0115] In one example, the number of stages and the delay of the n + 1 - stage pipeline signals Pipe0 to Pipe n output by the pipeline logic unit 211c in the EFUSE control logic module 211 increase sequentially, and the signal transmission paths between the storage control modules IP1_0 to IP1_n and the output terminal of the pipeline logic unit 211c become longer sequentially. At this time, the pipeline signal selection unit in the storage control module IP1_0 selects the (n + 1) - th stage pipeline signal Pipe n and outputs it to the latch in the storage control module IP1_0. The pipeline signal selection unit in the storage control module IP1_1 selects the n - th stage pipeline signal Pipe n - 1 and outputs it to the latch in the storage control module IP1_1, and so on. The pipeline signal selection unit in the storage control module IP1_n selects the 1 - st stage pipeline signal Pipe 0 and outputs it to the latch of the storage control module IP1_n.

[0116] It should also be noted that the division of the master device interfaces 20_0 to 20_m - 1, the trimming system 21, and each module inside the trimming system 21, etc. in the memory controller 2 of this embodiment is illustrative and mainly a logical function division. There may be other division methods in actual implementation. Each module or unit in the embodiments of the present application can be integrated in a processing module, or each module or unit can exist physically alone, or two or more modules or units can be integrated in a module. The above - integrated modules or units can be implemented in whole or in part through software, hardware, firmware, or any combination thereof.

[0117] Please refer to Figure 10 , the memory controller 2 of this embodiment can also be used in the techniques of built-in self-test and redundant repair based on the results of the built-in self-test. In this example, the trimming logic module 210 in the memory controller 2 includes a built-in self-test (BIST) unit 210a, which is used to perform a built-in self-test on the memory stack 3 to detect bad points (error cells / bits) in the memory stack 3; each storage unit unit of the main memory 3a of each memory die has a main storage unit structure 31 and a redundant storage unit structure 32. Each storage control module IP1 includes a redundant matching unit 212b in addition to a latch 212a and a pipelined signal selection unit 212c. A redundant matching unit 212b is coupled to a corresponding group of latches 212a, and is used to analyze the remaining resources of the redundant storage unit structure 32 in the storage unit hit by the bad point address latched by the latches 212a to which it is coupled, and determine whether there are still remaining redundant addresses in the storage unit hit by the bad point address. If so, the bad point address in the main storage unit structure 31 of the hit storage unit is replaced with the corresponding redundant address in the redundant storage unit structure 32 of the hit storage unit to complete the redundant repair of the bad point address.

[0118] Please refer to Figures 7 to 10 and Figures 4 to 5 , this embodiment also provides a three-dimensional stacked memory, which includes a memory stack 3 and the memory controller 2 as described in the present invention. The memory controller 2 is disposed on a buffer die 200. The memory stack 3 includes j + 1 layers of memory dies 300~30j stacked three-dimensionally, and the j + 1 layers of memory dies 300~30j and between them and the buffer die 200 are hybrid-bonded through through-silicon vias TSVs.

[0119] In summary, the memory controller and the three-dimensional stacked memory of this embodiment can also achieve the effect that the writing and power-on of the trimming configuration parameter information are completed in the memory controller and the memory stack through its trimming system, without an off-chip memory, thereby simplifying the system architecture and the writing process of the trimming configuration parameter information during power-on. Moreover, its EFUSE control logic module can also perform pipeline control output on the trimming configuration parameter information read after power-on, which can improve reliability. In addition, each storage control module can dynamically adjust the appropriate number of stages of the first-stage pipelined signal it selects, so that each storage control module synchronously captures and latches the trimming configuration parameter information, thereby ensuring the reliability of the trimming configuration parameter information latched by each storage control module.

[0120] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the technical solutions of the present invention.

Claims

1. A memory controller, coupled to and controlling a corresponding memory stack, the memory stack including a plurality of memory dies, each memory die including a main memory and an EFUSE memory, the main memory having a plurality of memory cells, the memory controller having a trimming system, characterized in that, The trimming system includes: A trimming logic module for obtaining trimming configuration parameter information of the main memory of at least one of the memory dies; An EFUSE control logic module coupled to the trimming logic module and each of the EFUSE memories, and configured to write the trimming configuration parameter information of each of the memory dies obtained by the trimming logic module into the EFUSE memory corresponding to the memory die, and, when powering on, read the trimming configuration parameter information in each of the EFUSE memories, output the read trimming configuration parameter information as several levels of pipeline signals, and select a suitable level of pipeline signal from the several levels of pipeline signals for broadcasting, or broadcast all of the several levels of pipeline signals; A plurality of storage control modules coupled to the EFUSE control logic module in parallel, each of the storage control modules coupled to a plurality of the storage units in the memory stack, and configured to, after powering on, receive the suitable level of pipeline signal or receive the several levels of pipeline signals and select a suitable level of pipeline signal therefrom, and then extract the corresponding trimming configuration parameter information from the suitable level of pipeline signal received or selected by it for latching.

2. The memory controller according to claim 1, wherein The multiple memory dies are j + 1 in number, and the memory cells coupled to each of the memory control modules and bonded by the same through-silicon via path are (j + 1) / l in number, and the memory cells coupled to each of the memory control modules and belonging to the same layer of memory dies are k + 1 in number, where 0 < l ≤ j + 1, and j, k, l are all integers, and both j and k are greater than or equal to 0; wherein, each of the memory control modules includes (j + 1) / l *(k + 1) groups of latches, and each group of the latches is used to latch the trimming configuration parameter information of each of the memory cells in the corresponding layer of the memory dies respectively.

3. The memory controller according to claim 1, wherein The EFUSE control logic module includes: An EFUSE write control logic unit coupled to the trimming logic module and each of the EFUSE memories, and configured to write the trimming configuration parameter information obtained by the trimming logic module into the corresponding EFUSE memory; An EFUSE read control logic unit coupled to each of the EFUSE memories, and configured to read the trimming configuration parameter information in each of the EFUSE memories after powering on; A pipeline logic unit coupled to the EFUSE read control logic unit, and configured to read the trimming configuration parameter information in each of the EFUSE memories and perform pipeline control on the read result to convert it into several levels of pipeline signals; A pipeline signal selection unit coupled to the pipeline logic unit, and configured to select a suitable level of pipeline signal from the several levels of pipeline signals for broadcasting to each of the storage control modules; Wherein, each of the storage control modules synchronously receives the suitable level of pipeline signal.

4. The memory controller according to claim 3, wherein The signal transmission path lengths between the plurality of storage control modules and the output end of the pipeline signal selection unit are different. The longer the signal transmission path, the greater the routing delay generated by it; the number of levels of the suitable level of pipeline signal is determined by the routing delay generated on the longest signal transmission path.

5. The memory controller according to claim 1, characterized in that, The EFUSE control logic module includes: An EFUSE write control logic unit coupled to the trimming logic module and each of the EFUSE memories, and configured to write the trimming configuration parameter information obtained by the trimming logic module into the corresponding EFUSE memory; An EFUSE read control logic unit coupled to each of the EFUSE memories, and configured to read the trimming configuration parameter information in each of the EFUSE memories after powering on; A pipeline logic unit, coupled to the EFUSE read control logic unit, for reading the trimming configuration parameter information in each of the EFUSE memories, and converting the read result into several levels of pipeline signals through pipeline control, and broadcasting the several levels of pipeline signals to the several memory control modules; Wherein, each of the memory control modules includes a pipeline signal selection unit, and the pipeline signal selection unit is coupled to the pipeline logic unit for receiving the several levels of pipeline signals and selecting a suitable level of pipeline signal therefrom.

6. The memory controller according to claim 5, wherein, The signal transmission path lengths between the several memory control modules and the output end of the pipeline signal selection unit are different. The longer the signal transmission path, the greater the routing delay generated. The smaller the level of the pipeline signal selected by the pipeline signal selection unit, so that the latches in each of the memory control modules can synchronously latch the corresponding trimming configuration parameter information.

7. The memory controller according to any one of claims 3-6, characterized in that The pipeline logic unit includes several cascaded pipeline units, and each pipeline unit outputs a corresponding level of pipeline signal, and the pipeline signal output by the previous pipeline unit is the input of the next pipeline unit; and / or, the content of each level of pipeline signal in the several levels of pipeline signals is the same, and each group of latches in each of the memory control modules fetches and latches the trimming configuration parameter information of the corresponding memory unit in the same layer to which it is coupled.

8. The memory controller according to claim 7, wherein The pipeline unit includes a register, and / or, the number of levels of the pipeline unit is equal to the number of memory control modules.

9. The memory controller according to any one of claims 3-6 or 8, characterized in that, The pipeline signal selection unit includes: A selection signal generator for providing the required selection signal; A multiplexer, coupled to the selection signal generator and the several levels of pipeline signals, and for selecting a suitable level of pipeline signal from the several levels of pipeline signals for output according to the selection signal.

10. The memory controller according to claim 9, wherein The selection signal provided by the selection signal generator can be adaptively adjusted to dynamically adjust the level of the suitable level of pipeline signal selected by the multiplexer, so as to ensure that the time when each of the memory control modules receives the corresponding level of pipeline signal is synchronized.

11. The memory controller according to claim 9, wherein The selection signal generator includes at least one of the following (1) to (3): (1) A configuration register for configuring a corresponding value, and the selection signal is adaptively adjusted as the value configured in the configuration register changes; (2) A temperature detection circuit for detecting a corresponding temperature, and the selection signal is adaptively adjusted as the temperature detected by the temperature detection circuit changes; (3) A voltage detection circuit for detecting a corresponding voltage, and the selection signal is adaptively adjusted as the voltage detected by the voltage detection circuit changes.

12. The memory controller according to any one of claims 1 or 3-6 or 8 or 10, characterized in that, The trimming configuration parameter information includes at least one of bad point information, timing trimming information, and voltage trimming information.

13. The memory controller according to claim 12, wherein The trimming logic module includes a built-in self-test unit for performing a built-in self-test on the memory stack to detect bad points in the memory stack.

14. The memory controller according to claim 12, wherein Each of the storage units includes a main storage unit structure and a redundant storage unit structure, and each of the storage control modules further includes a latch and a redundancy matching unit, where: The latch is configured to latch a bad point address extracted from the appropriate first-stage pipelined signal received or selected by the storage control module; The redundancy matching unit is coupled to the latch and is configured to extract the bad point address from the latch and perform analysis to determine the storage unit hit by the bad point address, and then replace the bad point address in the main storage unit structure with the address of the corresponding redundant storage unit structure in the storage unit.

15. The memory controller according to any one of claims 1-6, 8, 10-11 or 13-14, characterized in that, It further includes a plurality of main device interfaces for communicating with the main device, where each main device interface is a multi-IO parallel interface, and the trimming logic module obtains the trimming configuration parameter information via the main device interface.

16. A three-dimensional stacked memory, characterized in that, It includes a memory stack and a memory controller according to any one of claims 1-15, the memory controller is disposed on a buffer die, the memory stack includes a plurality of three-dimensionally stacked memory dies, and the plurality of memory dies are hybrid-bonded to each other and to the buffer die through through-silicon vias.

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