Repackage structure

Abstract

The invention discloses a repackaging structure. The repackaging structure comprises a substrate, at least one chip, a dielectric body, an electrical element and at least one conductive column, the substrate comprises a plate body, a plurality of mounting pads and a plurality of corresponding pads. The corresponding pad and the mounting pad are arranged on two opposite surfaces of the plate body. The corresponding pad corresponds to the mounting pad. The chip is mounted on the substrate. The chip comprises a plurality of chip pins. The chip pins are mounted on the mounting pads. The dielectric covers the chip. The electrical element is disposed on the dielectric body. The conductive column is electrically connected with the electrical element and the substrate.

Description

Technical Field

[0001] The present invention relates to a repackaging structure, and particularly to a repackaging structure for a chip. Background Art

[0002] With the development of the semiconductor industry, the density of active components on semiconductor chips has begun to approach the physical limit, and it has become increasingly difficult to make breakthroughs. In this situation, manufacturers have developed various packaging solutions, hoping to have more functions in a limited repackaging structure.

[0003] In recent years, there has been a solution for packaging semiconductor chips using a high density interconnection substrate. However, the price of the high density interconnection substrate is relatively expensive. Moreover, manufacturers also need to consider the requirements for mechanical bonding reliability and functions such as heat dissipation of such a substrate in the repackaging structure. Summary of the Invention

[0004] An object of the present invention is to provide a repackaging structure that improves the performance of a chip in a repackaging manner and maintains a small volume.

[0005] An embodiment of the present invention provides a repackaging structure, which includes: a substrate, at least one chip, a dielectric, an electrical component, and at least one conductive pillar. The substrate includes a plate body, a plurality of mounting pads, and a plurality of corresponding pads. The corresponding pads and the mounting pads are disposed on opposite surfaces of the plate body. The corresponding pads correspond to the mounting pads. The chip is mounted on the substrate. The chip includes a plurality of chip pins. The chip pins are mounted on the mounting pads. The dielectric covers the chip. The electrical component is disposed on the dielectric. The conductive pillar electrically connects the electrical component and the substrate.

[0006] According to the repackaging structure of an embodiment of the present invention, the performance is improved in a repackaging manner and a small volume is maintained. By mounting the chip on a substrate where the corresponding pads correspond to the mounting pads, and disposing an electrical component electrically connected to the substrate above the dielectric covering the chip, functions of the additional electrical component can be added to the repackaging structure while maintaining the original input / output state of the chip. Moreover, the electrical component itself also has a heat dissipation effect.

[0007] The above description of the content of the present invention and the following description of the embodiments are used to illustrate and explain the spirit and principle of the present invention, and provide a further explanation of the scope of the patent application of the present invention. Brief Description of the Drawings

[0008] Figure 1 is a schematic side cross-sectional view of a repackaging structure according to an embodiment of the present invention;

[0009] Figure 2Schematic side cross-sectional view of the repackaging structure of another embodiment of the present invention;

[0010] Figure 3 Schematic side cross-sectional view of the repackaging structure of another embodiment of the present invention;

[0011] Figure 4 Along Figure 3 Schematic top cross-sectional view of the cross-section along line A-A;

[0012] Figure 5 Schematic side cross-sectional view of the repackaging structure of another embodiment of the present invention;

[0013] Figure 6 Schematic side cross-sectional view of the repackaging structure of another embodiment of the present invention;

[0014] Figure 7 Along Figure 6 Schematic top cross-sectional view of the cross-section along line B-B;

[0015] Figure 8 Schematic side cross-sectional view of the repackaging structure of another embodiment of the present invention;

[0016] Figure 9 Schematic side cross-sectional view of the repackaging structure of another embodiment of the present invention;

[0017] Figure 10 For Figure 9 Schematic top cross-sectional view of the repackaging structure shown;

[0018] Figure 11 For Figure 9 Schematic diagram of the application description of the repackaging structure shown;

[0019] Figure 12 Schematic side cross-sectional view of the repackaging structure of another embodiment of the present invention.

[0020] Symbol description

[0021] 100, 100’, 200, 200’, 300, 400, 500, 600: Repackaging structure

[0022] 11, 11’, 21, 21’, 31, 41, 51, 61: Substrate

[0023] 111, 211, 311, 411, 511: Plate body

[0024] 111a, 211a, 311a, 411a, 511a: Lower surface

[0025] 111b, 211a, 311a, 411a, 511a: Upper surface

[0026] 1111, 2111, 3111, 4111, 5111: First dielectric layer

[0027] 1112, 2112, 3112, 4112: Ground layer

[0028] 1113, 2113, 3113, 4113, 5113: Second dielectric layer

[0029] 112, 212, 312, 412, 512: Corresponding pad

[0030] 113, 213, 313, 413, 513: Mounting pad

[0031] 114, 214, 314, 414, 514: Ground pad

[0032] 115a, 115b, 115c, 215a, 215b, 215c, 315a, 315b, 315d, 315e, 415a, 415b, 415d, 415e, 515a, 515f, 515g: Conductive via connection structure

[0033] 116, 117, 217: Additional pad

[0034] 12, 22, 32, 42, 52, 62: Chip

[0035] 121, 221, 321, 421, 521: Chip pin

[0036] 13, 13’, 23, 33, 43, 53, 63: Buffer connection layer

[0037] 131, 231, 331, 431, 531: Conductive solder block

[0038] 132: Underfill

[0039] 14, 14’, 24, 34, 44, 54, 64: Dielectric

[0040] 15, 25, 65: Conductive pillar

[0041] 16, 26, 36, 46, 56, 66: Electrical component

[0042] 161, 261: Conductive layer

[0043] 17, 171, 172, 27, 272, 37, 47, 57, 67: Conductive solder block

[0044] 3114, 4114: Power layer

[0045] 3115, 4115: The third dielectric layer

[0046] 318, 418: Power supply pads

[0047] 351, 451, 551: Ground conductive posts

[0048] 352, 452: Power supply conductive posts

[0049] 362: The first conductive layer

[0050] 363: Insulating layer

[0051] 364: The second conductive layer

[0052] 46a, 46b: Electrodes

[0053] 5116: Hybrid layer

[0054] 5116a: Ground layer

[0055] 5116b: Signal layer

[0056] 519: Signal pads

[0057] 553: Signal conductive posts

[0058] 565: Conductive layer

[0059] 566: Insulating layer

[0060] 567: Trace layer

[0061] 568: Additional chip

[0062] 569: Conductive solder block

[0063] 9: Main central processing unit

[0064] R1: Dielectric top view area

[0065] R2: Chip top view area Detailed implementation manners

[0066] In the following implementation manners, the detailed features and advantages of the embodiments of the present invention are described in detail. The content is sufficient for any person with ordinary knowledge in the art to understand the technical content of the embodiments of the present invention and implement them accordingly. According to the content disclosed in this specification, the claims and the drawings, any person with ordinary knowledge in the art can easily understand the related purposes and advantages of the present invention. The following embodiments further illustrate the content of the present invention in detail, but do not limit the scope of the present invention in any way.

[0067] In the so-called schematic diagrams of this specification, for the purpose of illustration, there may be exaggerated situations such as dimensions, proportions, and angles, but it is not intended to limit the present invention. Various changes can be made without departing from the gist of the present invention. The up, down, front, and back orientations mentioned in the description of the embodiments and the drawings are for illustration purposes and not intended to limit the present invention.

[0068] Please refer to Figure 1 。 Figure 1 FIG. 1 is a schematic side cross-sectional view of a repackaging structure according to an embodiment of the present invention. As Figure 1 shown, the repackaging structure 100 includes a substrate 11, a chip 12, a buffer connection layer 13, a dielectric 14, a conductive pillar 15, and an electrical component 16.

[0069] The substrate 11 includes a board body 111, a plurality of corresponding pads 112, a plurality of mounting pads 113, a ground pad 114, and a plurality of conductive via connection structures 115a, 115b. The board body 111 can be a redistribution layer (RDL). The board body 111 includes a first dielectric layer 1111, a ground layer 1112, and a second dielectric layer 1113. The board body 111 has an opposite lower surface 111a and an upper surface 111b. The corresponding pads 112 are disposed on the lower surface 111a of the board body 111. The lower surface 111a is located in the first dielectric layer 1111. The ground layer 1112 is stacked on the first dielectric layer 1111. The second dielectric layer 1113 is stacked on the ground layer 1112 and the first dielectric layer 1111. The upper surface 111b is located in the second dielectric layer 1113. The mounting pads 113 are disposed on the upper surface 111b of the board body 111. The mounting pads 113 are electrically connected to the corresponding pads 112 through the conductive via connection structures 115a, 115b passing through the second dielectric layer 1113 and the first dielectric layer 1111. The ground layer 1112 is patterned such that the conductive via connection structure 115a is electrically insulated from the ground layer 1112, and the conductive via connection structure 115b is electrically connected to the ground layer 1112. Each corresponding pad 112 is vertically corresponding and electrically connected to each mounting pad 113 via each conductive via connection structure 115a, 115b. The ground pad 114 is disposed on the upper surface 111b of the board body 111 and is electrically connected to the ground layer 1112. The conductive via connection structures 115a, 115b are structures formed by stacking a plurality of conductive vias.

[0070] The chip 12 is mounted on the substrate 11 via a buffer connection layer 13. In this embodiment, the chip 12 is a packaged structure with the die preliminarily packaged, but it is not limited thereto. In other embodiments, the chip 12 can also be an unpackaged die. In this embodiment, the buffer connection layer 13 includes a plurality of conductive solder bumps 131. The chip 12 includes a plurality of chip pins 121. The chip pins 121 are connected to the mounting pads 113 via the conductive solder bumps 131. The number of chip pins 121 is equal to the number of conductive solder bumps 131, and the number of conductive solder bumps 131 is equal to the number of mounting pads 113. The pitch between the chip pins 121 is substantially equal to the pitch between the mounting pads 113. The number of mounting pads 113 is equal to the number of corresponding pads 112. The pitch between the mounting pads 113 is substantially equal to the pitch between the corresponding pads 112. Thus, the mounting pads 113 correspond to the corresponding pads 112 in a one-to-one manner. The mounting pads 113 can include a plurality of signal mounting pads 113 and a plurality of non-signal mounting pads 113, and the corresponding pads 112 can include a plurality of signal corresponding pads 112 and a plurality of non-signal corresponding pads 112. Among them, the number of the plurality of signal mounting pads 113 is the same as the number of the plurality of signal corresponding pads 112. The non-signal mounting pads 113 and the non-signal corresponding pads 112 can be used for various non-signal functions such as grounding and power supply, and the number is not limited, but the total number of the non-signal mounting pads 113 is the same as the total number of the non-signal corresponding pads 112. In addition, when the repackaging structure 100 is impacted, the buffer connection layer 13 can provide a buffering function for the chip 12, and thus the chip 12 can be prevented from being damaged due to the impact.

[0071] In this embodiment, the number of the mounting pads 113 is equal to the number of the corresponding pads 112, but it is not limited thereto. In other embodiments, the number of the mounting pads 113 can also be greater than the number of the corresponding pads 112, such that some of the plurality of chip pins 121 are combined to correspond to one corresponding pad 112. Or in other embodiments, the corresponding pads 112 correspond to some of the plurality of mounting pads 113, and the remaining mounting pads 113 do not have corresponding pads 112 corresponding thereto. The chip pins 121 include a plurality of signal pins and at least one other pin. The signal pins are mounted on some of the mounting pads 113 corresponding to the corresponding pads 112, and the other pins are mounted on the mounting pads 113 that do not have corresponding pads 112 corresponding thereto, such that the other pins do not correspond to any corresponding pads 112. For example, the number of the corresponding pads 112 / the number of the mounting pads 113 = 50% - 100%. The mounting pads 113 can include a plurality of signal mounting pads 113 and a plurality of non-signal mounting pads 113, and the corresponding pads 112 can include a plurality of signal corresponding pads 112 and a plurality of non-signal corresponding pads 112. Among them, the number of the plurality of signal mounting pads 113 is the same as the number of the plurality of signal corresponding pads 112. The non-signal mounting pads 113 and the non-signal corresponding pads 112 can be used for various non-signal functions such as grounding and power supply, but the total number of the non-signal mounting pads 113 is greater than the total number of the non-signal corresponding pads 112.

[0072] In this embodiment, the spacing between the mounting pads 113 is substantially equal to the spacing between the corresponding pads 112, but this is not limiting. In other embodiments, the spacing between the corresponding pads 112 may also be greater than 100% of the spacing between the mounting pads 113 and less than or equal to 150% of the spacing between the mounting pads 113. In other embodiments, the spacing between the corresponding pads 112 may also be greater than 100% of the spacing between the mounting pads 113 and less than or equal to 120% of the spacing between the mounting pads 113.

[0073] When the spacing between the mounting pads 113 is substantially equal to the spacing between the corresponding pads 112, a chip socket or circuit board (not shown) originally designed to match the chip 12 can be directly applied to the repackaging structure 100. Alternatively, when the spacing between the corresponding pads 112 is an integer multiple of the spacing between the mounting pads 113, a chip socket or circuit board originally matching the chip 12 can also be directly applied to the repackaging structure 100.

[0074] In this embodiment, the dielectric 14 covers part of the surfaces of the chip 12 and the substrate 11. A part of the dielectric 14 is located between the conductive solder blocks 131. In this embodiment, the dielectric 14 is formed by molding, but this is not limiting. In other embodiments, the dielectric can also be formed in other ways. In this embodiment, the electrical component 16 includes a conductive layer 161. The conductive layer 161 is disposed on the dielectric 14. The conductive posts 15 are electrically connected to the ground pads 114 of the substrate 11 and the conductive layer 161 while avoiding the chip 12. Specifically, after forming the dielectric 14 covering the chip 12, a through hole (i.e., the surface of the conductive posts 15 in the figure) is formed through the dielectric 14 while avoiding the chip 12 to reach the ground pads 114 of the substrate 11. Next, conductive posts 15 are formed in this through hole, and a conductive layer 16 is further formed on the dielectric 14. As described above, the conductive posts 15 can be formed by forming conductive vias. In other words, it can also be said that the conductive posts 15 and the ground pads 114 together penetrate the dielectric 14. Moreover, the conductive posts 15 are electrically connected to the ground pads 114 of the substrate 11, and the conductive layer 161 is electrically connected to the conductive posts 15.

[0075] Since the conductive layer 161 is electrically connected to the ground pads 114 via the conductive posts 15, the conductive layer 161 is also grounded. Since there is a grounded conductive layer 161 above the chip 12 and a grounded ground layer 1112 below the chip 12, the chip 12 can be protected from external electromagnetic waves through the electromagnetic interference shielding (EMI shielding) effect. The conductive layer 161 can also have a heat dissipation function. Although the above-grounding forms the electromagnetic shielding effect in this embodiment, this is not limiting. In other embodiments, the grounding can also be changed to a specific potential.

[0076] In this embodiment, a top-view area R1 of the dielectric 14 is greater than 100% and less than or equal to 150% of a top-view area R2 of the chip 12, but is not limited thereto. In other embodiments, the top-view area R1 of the dielectric 14 may also be greater than 100% and less than or equal to 120% of the top-view area R2 of the chip 12.

[0077] The repackaging structure 100 may further include a plurality of conductive solder bumps 17 disposed on corresponding pads 112. The repackaging structure 100 may be mounted and electrically connected to other chip carriers or circuit boards through the corresponding pads 112 and the conductive solder bumps 17.

[0078] Please refer to Figure 2 。 Figure 2 FIG. is a schematic side cross-sectional view of a repackaging structure according to another embodiment of the present invention. In this embodiment, the repackaging structure 100' is similar to Figure 1 the repackaging structure 100 shown, and the same or similar elements are denoted by the same reference numerals as those in the Figure 1 repackaging structure 100, and repeated descriptions are adaptively omitted.

[0079] As Figure 2 shown, in this embodiment, the repackaging structure 100' includes a substrate 11', a chip 12, a buffer connection layer 13', a dielectric 14', a conductive pillar 15, and an electrical component 16. The substrate 11' includes a board body 111, a plurality of corresponding pads 112, a plurality of mounting pads 113, a ground pad 114, a plurality of conductive via connection structures 115a, 115b, 115c, and a plurality of additional pads 116, 117. The board body 111 includes a first dielectric layer 1111, a ground layer 1112, and a second dielectric layer 1113 stacked in sequence. The corresponding pads 112, the additional pads 116, and the additional pads 117 are disposed on the lower surface 111a of the board body 111 and are in contact with the first dielectric layer 1111. The additional pads 116 and 117 are located around the array formed by the corresponding pads 112. The additional pad 116 is electrically connected to the ground layer 1112. The mounting pads 113 and the ground pad 114 are disposed on the upper surface 111b of the board body 111 and are in contact with the second dielectric layer 1113. The ground pad 114 is electrically connected to the additional pad 117 through the conductive via connection structure 115c passing through the second dielectric layer 1113 and the first dielectric layer 1111. The conductive via connection structure 115c may further be electrically connected to the ground layer 1112.

[0080] The chip 12 is mounted on the substrate 11' via a buffer connection layer 13'. The buffer connection layer 13' includes a plurality of conductive solder blocks 131 and an underfill 132. The chip pins 121 are connected to the mounting pads 113 via the conductive solder blocks 131. The underfill 132 is disposed between and around the conductive solder blocks 131. Thus, the dielectric 14' does not lie between the conductive solder blocks 131.

[0081] The conductive layer 161 of the electrical component 16, the conductive posts 15, the ground pads 114, the conductive via connection structure 115c, the additional pads 117, the ground layer 1112, and the additional pads 116 are all grounded. The repackaging structure 100' may further include a plurality of conductive solder blocks 17, 171, 172. The conductive solder block 17 is disposed on the corresponding pad 112. The conductive solder block 171 is disposed on the additional pad 116. The conductive solder block 172 is disposed on the additional pad 117. The repackaging structure 100' can be mounted and electrically connected to other chip carriers or circuit boards (not shown) via the conductive solder blocks 17, 171, 172. The chip carrier or circuit board can ground the conductive solder block 171 and the conductive solder block 172 to ground the additional pad 116 and the additional pad 117, and thus can protect the chip 12 from external electromagnetic wave interference through the electromagnetic shielding effect caused by the conductive layer 161 and the ground layer 1112. The conductive layer 161 can also have a heat dissipation function.

[0082] In this embodiment, the number of the mounting pads 113 is less than the sum of the number of the corresponding pads 112 plus the number of the additional pads 116, 117. Moreover, the additional pads 116, 117 are used for various non-signal functions. In addition, the mounting pads 113 may include a plurality of signal mounting pads 113 and a plurality of non-signal mounting pads 113, and the corresponding pads 112 may include a plurality of signal corresponding pads 112 and a plurality of non-signal corresponding pads 112. Among them, the number of the plurality of signal mounting pads 113 is the same as the number of the plurality of signal corresponding pads 112. The non-signal mounting pads 113 and the non-signal corresponding pads 112 can also be used for various non-signal functions such as grounding and power supply, but the total number of the non-signal mounting pads 113 is less than the total number of the non-signal corresponding pads 112.

[0083] Please refer to Figure 3 and Figure 4 . Figure 3 FIG. shows a side cross-sectional schematic view of a repackaging structure according to another embodiment of the present invention. Figure 4 FIG. shows a top cross-sectional schematic view of a cross-section along the line A-A of Figure 3 . In this embodiment, the repackaging structure 200 is similar to the repackaging structure 100 shown in Figure 1 . The following elements with the same or similar functions are labeled with similar element symbols, and the repeated descriptions are adaptively omitted.

[0084] As shown in Figure 3and Figure 4 As shown in Figure 4 , in this embodiment, the re - encapsulation structure 200 includes a substrate 21, a chip 22, a buffer connection layer 23, a dielectric 24, a plurality of conductive pillars 25, and an electrical component 26. The substrate 21 includes a plate body 211, a plurality of corresponding pads 212, a plurality of mounting pads 213, a plurality of ground pads 214, and a plurality of conductive via connection structures 215a, 215b. The plate body 211 includes a first dielectric layer 2111, a ground layer 2112, and a second dielectric layer 2113 stacked in sequence. The corresponding pads 212 are disposed on the lower surface 211a of the plate body 211 and are in contact with the first dielectric layer 2111. The mounting pads 213 and the ground pads 214 are disposed on the upper surface 211b of the plate body 211 and are in contact with the second dielectric layer 2113. The ground pads 214 are located around the array formed by the mounting pads 213. The mounting pads 213 are electrically connected to the corresponding pads 212 through the conductive via connection structures 215a, 215b passing through the second dielectric layer 2113 and the first dielectric layer 2111. The conductive via connection structure 215b is electrically connected to the ground layer 2112. The ground pads 214 are electrically connected to the ground layer 2112.

[0085] The chip 22 is mounted on the substrate 21 via the buffer connection layer 23. The buffer connection layer 23 includes a plurality of conductive solder bumps 231. The chip pins 221 are connected to the mounting pads 213 via the conductive solder bumps 231. The dielectric 24 covers the chip 22. A part of the dielectric 24 is located between the conductive solder bumps 231. The conductive pillars 25 penetrate through the dielectric 24 while avoiding the chip 22. The conductive pillars 25 are electrically connected to the ground pads 214 of the substrate 21. The conductive pillars 25 are located around the chip 22. As Figure 4 shown in Figure 4 , the plurality of conductive pillars 25 are arranged in a manner surrounding the chip 22.

[0086] As Figure 3 and Figure 4 shown in Figure 3 and Figure 4 , a conductive layer 261 of the electrical component 26 is disposed on the dielectric 24. The conductive layer 261 is electrically connected to the conductive pillars 25. The conductive layer 261 is electrically connected to the ground pads 214 via the conductive pillars 25. The conductive layer 261 of the electrical component 26, the conductive pillars 25, the ground pads 214, and the ground layer 2112 are all grounded. Since there is a grounded conductive layer 261 above the chip 22, a grounded ground layer 2112 below the chip 22, and grounded conductive pillars 25 around the chip 22, the chip 22 can be protected from external electromagnetic waves through the electromagnetic shielding effect. The conductive layer 261 and the conductive pillars 25 can also have a heat dissipation function.

[0087] The re - encapsulation structure 200 may further include a plurality of conductive solder bumps 27. The conductive solder bumps 27 are disposed on the corresponding pads 212. The re - encapsulation structure 200 can be mounted and electrically connected to other chip sockets or circuit boards (not shown) via the conductive solder bumps 27.

[0088] Please refer to Figure 5 。 Figure 5 A side cross-sectional schematic view showing a repackaging structure according to another embodiment of the present invention. In this embodiment, the repackaging structure 200' is similar to Figure 3 the repackaging structure 200 shown, and the same or similar elements use the element symbols shown in the Figure 3 repackaging structure 200, and repetitive descriptions are adaptively omitted.

[0089] As Figure 5 shown, in this embodiment, the repackaging structure 200' includes a substrate 21', a chip 22, a buffer connection layer 23, a dielectric 24, a plurality of conductive pillars 25, and an electrical component 26. The substrate 21' includes a plate body 211, a plurality of corresponding pads 212, a plurality of mounting pads 213, a plurality of ground pads 214, a plurality of conductive via connection structures 215a, 215b, 215c, and a plurality of additional pads 217. The plate body 211 includes a first dielectric layer 2111, a ground layer 2112, and a second dielectric layer 2113 stacked in sequence. The corresponding pads 212 and the additional pads 217 are disposed on the lower surface 211a of the plate body 211 and are in contact with the first dielectric layer 2111. The additional pads 217 are located around the array formed by the corresponding pads 212. The mounting pads 213 and the ground pads 214 are disposed on the upper surface 211b of the plate body 211 and are in contact with the second dielectric layer 2113. The ground pads 214 are located around the array formed by the mounting pads 213. The ground pads 214 are electrically connected to the additional pads 217 through the conductive via connection structures 215c passing through the second dielectric layer 2113 and the first dielectric layer 2111. The conductive via connection structures 215c can also be further electrically connected to the ground layer 2112.

[0090] The chip pins 221 of the chip 22 are mounted and connected to the mounting pads 213 of the substrate 21' via the conductive solder bumps 231 of the buffer connection layer 23. The dielectric 24 covers the chip 22 and the conductive solder bumps 231. The conductive pillars 25 penetrate through the dielectric 24 while avoiding the chip 22 and are electrically connected to the ground pads 214. The conductive pillars 25 are located around the chip 22. A conductive layer 261 of the electrical component 26 is disposed on the dielectric 24 and is electrically connected to the conductive pillars 25. The conductive layer 261 is electrically connected to the ground pads 214 via the conductive pillars 25.

[0091] The conductive layer 261, conductive posts 25, ground pads 214, conductive via connection structures 215c, additional pads 217, and ground layer 2112 of the electrical component 26 are all grounded. The repackaging structure 200' may further include a plurality of conductive solder blocks 27, 272. The conductive solder block 27 is disposed on the corresponding pad 212. The conductive solder block 272 is disposed on the additional pad 217. The repackaging structure 200' can be mounted and electrically connected to other chip carriers or circuit boards (not shown) through the conductive solder blocks 27, 272. The chip carrier or circuit board can ground the conductive solder block 272 and the additional pad 217, and thus, through the electromagnetic shielding effect, protect the chip 22 from external electromagnetic wave interference. The conductive layer 261 and the conductive posts 25 can also have a heat dissipation function.

[0092] Figure 6 FIG. shows a schematic side cross-sectional view of a repackaging structure according to another embodiment of the present invention. Figure 7 FIG. shows Figure 6 a schematic top cross-sectional view taken along line B-B of. In this embodiment, the repackaging structure 300 is similar to the repackaging structure 100 shown in Figure 1 FIG.. The same or similar elements are labeled with similar element symbols hereinafter, and repeated descriptions are adaptively omitted.

[0093] As shown in Figure 6 and Figure 7 FIG., in this embodiment, the repackaging structure 300 includes a substrate 31, a chip 32, a buffer connection layer 33, a dielectric 34, a plurality of ground conductive posts 351, a plurality of power conductive posts 352, and an electrical component 36. The substrate 31 includes a board body 311, a plurality of corresponding pads 312, a plurality of mounting pads 313, a plurality of ground pads 314, a plurality of conductive via connection structures 315a, 315b, 315d, 315e, and a plurality of power pads 318. The board body 311 includes a first dielectric layer 3111, a power layer 3114, a third dielectric layer 3115, a ground layer 3112, and a second dielectric layer 3113 stacked in sequence. The corresponding pads 312 are disposed on the lower surface 311a of the board body 311 and are in contact with the first dielectric layer 3111. The mounting pads 313, ground pads 314, and power pads 318 are disposed on the upper surface 311b of the board body 311 and are in contact with the second dielectric layer 3113. The ground pads 314 and power pads 318 are located around the array formed by the mounting pads 313. The mounting pads 313 are electrically connected to the corresponding pads 312 through the conductive via connection structures 315a, 315b, 315d passing through the second dielectric layer 3113, the third dielectric layer 3115, and the first dielectric layer 3111. The ground pads 314 are electrically connected to the ground layer 3112. The power pads 318 are electrically connected to the power layer 3114 through the conductive via connection structures 315e passing through the second dielectric layer 3113 and the third dielectric layer 3115.

[0094] The ground layer 3112 and the power supply layer 3114 are patterned. Thus, the conductive via connection structure 315a is electrically insulated from the ground layer 3112 and the power supply layer 3114. The conductive via connection structure 315b is electrically connected to the ground layer 3112 and is electrically insulated from the power supply layer 3114. The conductive via connection structure 315d is electrically connected to the power supply layer 3114 and is electrically insulated from the ground layer 3112. The conductive via connection structure 315e is electrically insulated from the ground layer 3112.

[0095] The chip pins 321 of the chip 32 are mounted and connected to the mounting pads 313 of the substrate 31 via the conductive solder bumps 331 of the buffer connection layer 33. The dielectric 34 covers the chip 32 and the conductive solder bumps 331. The ground conductive posts 351 and the power supply conductive posts 352 penetrate through the dielectric 34 while avoiding the chip 32. The ground conductive posts 351 are electrically connected to the ground pads 314. The power supply conductive posts 352 are electrically connected to the power supply pads 318. The ground conductive posts 351 and the power supply conductive posts 352 are located around the chip 32. As Figure 7 shown, the ground conductive posts 351 and the power supply conductive posts 352 are arranged in a manner surrounding the chip 32. Among them, the ground conductive posts 351 are arranged on both sides of each power supply conductive post 352. In this embodiment, the number of the power supply conductive posts 352 and the number of the conductive via connection structures 315e are both multiple, but it is not limited thereto. In other embodiments, the number of the power supply conductive posts 352 and the number of the conductive via connection structures 315e may also be both one.

[0096] As Figure 6 and Figure 7 shown, in this embodiment, the electrical component 36 includes a first conductive layer 362, an insulating layer 363, and a second conductive layer 364. The first conductive layer 362 is disposed between the dielectric 34 and the insulating layer 363. The insulating layer 363 is disposed between the first conductive layer 362 and the second conductive layer 364. The first conductive layer 362 is electrically connected to the power supply pad 318 via the power supply conductive post 352. The second conductive layer 364 is electrically connected to the ground pad 314 via the ground conductive post 351. The grounded second conductive layer 364, the first conductive layer 362 connected to the power supply layer 3114, and the insulating layer 363 in between can form a capacitor. The second conductive layer 364 of the electrical component 36, the ground conductive posts 351, the ground pads 314, and the ground layer 3113 are all grounded. Since the second conductive layer 364 above the chip 32 is grounded, the ground layer 3112 below the chip 32 is grounded, and the ground conductive posts 351 are grounded around the front, back, left, and right of the chip 32, the chip 32 can be protected from external electromagnetic waves through the electromagnetic shielding effect. The second conductive layer 364, the ground conductive posts 351, and the power supply conductive posts 352 can also have a heat dissipation function.

[0097] The repackaging structure 300 may further include a plurality of conductive solder blocks 37. The conductive solder blocks 37 are disposed on corresponding pads 312. The repackaging structure 300 may be mounted and electrically connected to other chip carriers or circuit boards (not shown) through the conductive solder blocks 37.

[0098] Figure 8 FIG. shows a schematic side cross-sectional view of a repackaging structure according to another embodiment of the present invention. In this embodiment, the repackaging structure 400 is similar to Figure 1 the repackaging structure 100 shown. The same or similar elements are labeled with similar element symbols hereinafter, and repeated descriptions are adaptively omitted.

[0099] As Figure 8 shown, in this embodiment, the repackaging structure 400 includes a substrate 41, a chip 42, a buffer connection layer 43, a dielectric 44, a plurality of ground conductive posts 451, a plurality of power conductive posts 452, and an electrical component 46. The substrate 41 includes a board body 411, a plurality of corresponding pads 412, a plurality of mounting pads 413, a plurality of ground pads 414, a plurality of conductive via connection structures 415a, 415b, 415d, 415e, and a plurality of power pads 418. The board body 411 includes a first dielectric layer 4111, a power layer 4114, a third dielectric layer 4115, a ground layer 4112, and a second dielectric layer 4113 stacked in sequence. The corresponding pads 412 are disposed on the lower surface 411a of the board body 411 and are in contact with the first dielectric layer 4111. The mounting pads 413, the ground pads 414, and the power pads 418 are disposed on the upper surface 411b of the board body 411 and are in contact with the second dielectric layer 4113. The chip pins 421 of the chip 42 are mounted and connected to the mounting pads 413 via the conductive solder blocks 431 of the buffer connection layer 43.

[0100] In this embodiment, the electrical component 46 is disposed on the dielectric 44. The electrical component 46 is at least one capacitive element, at least one resistive element, or other passive elements. The electrodes 46a and 46b of the electrical component 46 are electrically connected to the ground conductive posts 451 and the power conductive posts 452, respectively. The electrical component 46 is electrically connected to the substrate 41 via the ground conductive posts 451 and the power conductive posts 452. In this embodiment, the ground pads 414 and the power pads 418 may be capacitive pads for connecting capacitive elements and having different potentials.

[0101] The electrical component 46, the ground conductive posts 451, the ground pads 414, and the ground layer 4113 are all grounded. Since the electrical component 46 above the chip 42 is grounded, the ground layer 4112 below the chip 42 is grounded, and the ground conductive posts 451 are grounded around the chip 42, the chip 42 can be protected from external electromagnetic waves through the electromagnetic shielding effect. The electrical component 46, the ground conductive posts 451, and the power conductive posts 452 may also have a heat dissipation function.

[0102] The repackage structure 400 may further include a plurality of conductive solder bumps 47. The conductive solder bumps 47 are disposed on corresponding pads 412. The repackage structure 400 may be mounted and electrically connected to other chip holders or circuit boards (not shown) through the conductive solder bumps 47.

[0103] Please refer to Figures 9 to 11 . Figure 9 A schematic side cross-sectional view of a repackaging structure according to another embodiment of the present invention is shown. Figure 10 Draw Figure 9 A top cross-sectional schematic diagram of the repackaging structure shown, and Figure 9 Is the drawing along Figure 10 Schematic diagram of the side view of the C-C line section. Figure 11 Draw Figure 9 In this embodiment, the repackaging structure 500 and Figure 1 The repackaging structure 100 shown is similar. In the following, the same or similar elements are marked with the same reference numerals, and repeated descriptions are omitted as appropriate.

[0104] like Figures 9 to 10 As shown, in this embodiment, the repackaging structure 500 includes a substrate 51, a chip 52, a buffer connection layer 53, a dielectric body 54, a plurality of ground conductive pillars 551, a plurality of signal conductive pillars 553 and an electrical element 56. The substrate 51 includes a board 511, a plurality of corresponding pads 512, a plurality of mounting pads 513, a plurality of ground pads 514, a plurality of conductive through-hole connection structures 515a, 515f, 515g and a plurality of signal pads 519. The board 511 includes a first dielectric layer 5111, a mixed layer 5116 and a second dielectric layer 5113 stacked in sequence. The corresponding pad 512 is disposed on the lower surface 511a of the board 511 and contacts the first dielectric layer 5111. The mounting pad 513, the ground pad 514 and the signal pad 519 are disposed on the upper surface 511b of the board 511 and contact the second dielectric layer 5113.

[0105] The ground pad 514 and the signal pad 519 are located around the array formed by the mounting pad 513. The mounting pad 513 is electrically connected to the corresponding pad 512 through the conductive via connection structure 515a, 515f, 515g through the second dielectric layer 5113 and the first dielectric layer 5111. The mixed layer 5116 is patterned and divided into a ground layer 5116a and a signal layer 5116b located on the same layer. The ground pad 514 is electrically connected to the ground layer 5116a. The signal pad 519 is electrically connected to the signal layer 5116b.

[0106] The conductive via connection structure 515a is electrically insulated from the ground layer 5116a and the signal layer 5116b. The conductive via connection structure 515f is electrically connected to the ground layer 5116a and is electrically insulated from the signal layer 5116b. The conductive via connection structure 515g is electrically connected to the signal layer 5116b and is electrically insulated from the ground layer 5116a.

[0107] The chip pins 521 of the chip 52 are mounted and connected to the mounting pads 513 via the conductive solder bumps 531 of the buffer connection layer 53. The dielectric 54 covers the chip 52 and the conductive solder bumps 531. The ground conductive posts 551 and the signal conductive posts 553 penetrate through the dielectric 54 while avoiding the chip 52. The ground conductive posts 551 are electrically connected to the ground pads 514. The signal conductive posts 553 are electrically connected to the signal pads 519. The ground conductive posts 551 and the signal conductive posts 553 are located around the chip 52. As Figure 10 shown, the ground conductive posts 551 and the signal conductive posts 553 are arranged in a manner surrounding the chip 52. Among them, the ground conductive posts 551 are arranged on both sides of each signal conductive post 553. In this embodiment, the number of the signal conductive posts 553 and the number of the signal pads 519 are both multiple, but this is not limiting. In other embodiments, the number of the signal conductive posts 553 and the number of the signal pads 519 may also both be one.

[0108] In this embodiment, the electrical component 56 is disposed on the dielectric 54. The electrical component 56 includes a conductive layer 565, an insulating layer 566, a trace layer 567, an additional chip 568, and a plurality of conductive solder bumps 569.

[0109] The conductive layer 565 is disposed between the dielectric 54 and the insulating layer 566. The insulating layer 566 is disposed between the conductive layer 565 and the trace layer 567. The conductive layer 565 is electrically connected to the ground pad 514 via the ground conductive post 551. The trace layer 567 is electrically connected to the signal pad 519 via the signal conductive post 553. The additional chip 568 is mounted on the trace layer 567 via the conductive solder bumps 569. The conductive layer 565 is patterned such that the conductive layer 565 is electrically insulated from the signal conductive posts 553.

[0110] The conductive layer 565, the ground conductive posts 551, the ground pads 514, and the ground layer 5116a of the electrical component 56 are all grounded. Since there is the conductive layer 565 grounded above the chip 52, the ground layer 5116a grounded below the chip 52, and the ground conductive posts 551 grounded around the front, back, left, and right of the chip 52, the chip 52 can be protected from external electromagnetic wave interference through the electromagnetic shielding effect. The conductive layer 565 can also prevent the chip 52 and the additional chip 568 from interfering with each other. The conductive layer 565, the ground conductive posts 551, and the signal conductive posts 553 can also have a heat dissipation function.

[0111] As Figure 9and Figure 11 As shown, the repackaging structure 500 may further include a plurality of conductive solder blocks 57. The conductive solder blocks 57 are disposed on corresponding pads 512. The repackaging structure 500 may be mounted and electrically connected to other chip carriers or circuit boards (not shown) through the conductive solder blocks 57, and is further electrically connected to the main central processing unit 9( Figure 11 ).

[0112] As Figure 11 shown, the main central processing unit 9 may input a first signal to the chip 52 (right thick dashed arrow) via the conductive solder block 57, the corresponding pad 512, the conductive via connection structure 515a, the mounting pad 513, the conductive solder block 531, and the chip pin 521. The chip 52 may perform operations on this signal. After the chip 52 performs operations, a second signal is output from another chip pin 521. The second signal is input to the additional chip 568 (left thick dashed arrow) via the solder block 531, the mounting pad 513, the conductive via connection structure 515g, the signal layer 5116b, the signal pad 519, the signal conductive post 553, the trace layer 567, and the conductive solder block 569.

[0113] When the second signal passes through the conductive via connection structure 515g and the signal layer 5116b, power lines (thin solid arrows) are generated toward the ground layer 5116a. When the second signal passes through the signal pad 519, power lines (thin solid arrows) are generated toward the ground pad 514. When the second signal passes through the signal conductive post 553, power lines (thin solid arrows) are generated toward the ground conductive post 551. When the second signal passes through the trace layer 567, power lines (thin solid arrows) are generated toward the conductive layer 565. Thus, the impedances of the conductive via connection structure 515g, the signal layer 5116b, the signal pad 519, the signal conductive post 553, and the trace layer 567 through which the second signal passes can be made to match each other, and thus the second signal can be made stable and have less loss.

[0114] Please refer to Figure 12 . Figure 12 FIG. shows a side cross-sectional schematic view of a repackaging structure according to another embodiment of the present invention. In this embodiment, the repackaging structure 600 is similar to Figure 1 the repackaging structure 100 shown. The same or similar elements are labeled with similar element symbols below, and repeated descriptions are adaptively omitted.

[0115] As Figure 12As shown, in this embodiment, the repackaging structure 600 includes a substrate 61, a plurality of chips 62, a buffer connection layer 63, a dielectric 64, a plurality of conductive posts 65, and an electrical component 66. The chips 62 are mounted on the substrate 61 via the buffer connection layer 63. The dielectric 64 covers the chips 62. The conductive posts 65 penetrate the dielectric 64 while avoiding the chips 62. The conductive posts 65 are located between the chips 62 and surround the periphery of the chips 62. The conductive posts 65 are electrically connected to the substrate 61.

[0116] The electrical component 66 is disposed on the dielectric 64. The electrical component 66 is electrically connected to the conductive posts 65. The electrical component 66 is electrically connected to the substrate 61 via the conductive posts 65. The electrical component 66, the conductive posts 65, the ground pad 614, and the substrate 61 are all grounded. Since the electrical component 66 is grounded above the chips 62, the substrate 61 is grounded below the chips 62, and the conductive posts 65 are grounded around the front, back, left, and right of each chip 62, the chips 62 can be protected from external electromagnetic waves through the electromagnetic shielding effect, and mutual interference between the chips 62 can be avoided. The electrical component 66 and the conductive posts 65 can also have a heat dissipation function. In this embodiment, some of the conductive posts 65 are located between the chips 62, but this is not limiting. In other embodiments, the conductive posts 65 may not be provided between the chips 62.

[0117] In this embodiment, the repackaging structure 600 may further include a plurality of conductive solder blocks 67. The conductive solder blocks 67 are disposed on the substrate 61. The repackaging structure 600 can be mounted and electrically connected to other chip carriers or circuit boards (not shown) through the conductive solder blocks 67.

[0118] In summary, in the repackaging structure of an embodiment of the present invention, by mounting the chips on a substrate corresponding to the mounting pads and providing an electrical component electrically connected to the substrate above the dielectric covering the chips, the functions of the electrical component can be added while maintaining the original input / output state of the chips. When the electrical component is a grounded conductive layer, the chips can be protected from external electromagnetic waves through the electromagnetic shielding effect. In addition, when the electrical component includes an additional chip and a grounded conductive layer, the repackaging structure can add the functions of the additional chip, and the grounded conductive layer can also avoid interference between the chips and the additional chip. When the conductive posts connecting the electrical component and the substrate are located around the chips and grounded, the chips can also be protected from external electromagnetic waves around through the electromagnetic shielding effect. Moreover, the electrical component itself has a heat dissipation effect. Furthermore, by including a first conductive layer connected to the power layer, a second conductive layer grounded, and an insulating layer in between in the electrical component, the electrical component can form a capacitor, enabling the repackaging structure to have the functions provided by the capacitor.

Claims

1. A repackaging structure, comprising: A substrate, comprising a plate body, a plurality of mounting pads and a plurality of corresponding pads, wherein the corresponding pads and the mounting pads are arranged on two opposite surfaces of the plate body, and the corresponding pads correspond to the mounting pads; At least one chip is mounted on the substrate, the at least one chip includes a plurality of chip pins, and the chip pins are mounted on the mounting pads; A dielectric body covering the at least one chip; An electrical element is disposed on the dielectric body; and At least one conductive column electrically connects the electrical element and the substrate. 2 . The repackaging structure as claimed in claim 1 , wherein the corresponding pads respectively correspond vertically to the mounting pads. 3 . The repackaging structure as claimed in claim 1 , wherein the number of the chip pins is equal to the number of the mounting pads, and the number of the mounting pads is equal to the number of the corresponding pads. 4 . The repackaging structure as claimed in claim 1 , wherein the number of the chip pins is equal to the number of the mounting pads, and the number of the mounting pads is greater than the number of the corresponding pads. 5 . The repackage structure as claimed in claim 4 , wherein the chip pins include a plurality of signal pins and at least one other pin, and the signal pins are mounted on portions of the mounting pads corresponding to the corresponding pads. 6 . The repackage structure as claimed in claim 1 , further comprising a buffer connection layer, wherein the at least one chip is mounted on the substrate via the buffer connection layer. 7 . The repackage structure of claim 6 , wherein the buffer connection layer comprises a plurality of conductive solder bumps. 8 . The repackage structure as claimed in claim 7 , wherein a portion of the dielectric body is located between the conductive solder bumps. 9 . The repackaging structure as claimed in claim 7 , wherein the buffer connection layer further comprises a primer surrounding the conductive solder bumps. 10 . The repackaging structure as claimed in claim 1 , wherein the substrate further comprises at least one ground pad, the electrical element comprises a conductive layer, the conductive layer is disposed on the dielectric body, and the conductive layer is electrically connected to the at least one ground pad via the at least one conductive column. 11 . The repackage structure as claimed in claim 10 , wherein the substrate further comprises a ground layer, and the at least one ground pad is electrically connected to the ground layer. 12 . The repackaging structure as claimed in claim 10 , wherein the number of the at least one conductive pillar is plural, the number of the at least one grounding pad is plural, the conductive pillars are electrically connected to the grounding pads, and the conductive pillars are located around the at least one chip.

13. The repackaging structure as described in claim 1, wherein the substrate further includes at least one power pad and at least one ground pad, the electrical element includes a first conductive layer, an insulating layer and a second conductive layer, the at least one conductive column includes at least one ground conductive column and at least one power conductive column, the first conductive layer is arranged between the dielectric and the insulating layer, the insulating layer is arranged between the first conductive layer and the second conductive layer, the first conductive layer is electrically connected to the at least one power pad via the at least one power conductive column, and the second conductive layer is electrically connected to the at least one ground pad via the at least one ground conductive column. 14 . The repackage structure as claimed in claim 13 , wherein the substrate further comprises a ground layer, and the at least one ground pad is electrically connected to the ground layer.

15. The repackaging structure as described in claim 13, wherein the number of the at least one power conductive pillar is multiple, the number of the at least one power pad is multiple, the power conductive pillars are electrically connected to the power pads, the number of the at least one grounding conductive pillar is multiple, the number of the at least one grounding pad is multiple, the grounding conductive pillars are electrically connected to the grounding pads, the power conductive pillars and the grounding conductive pillars are located around the at least one chip, and two of the grounding conductive pillars are arranged on both sides of each of the power conductive pillars. 16 . The repackage structure as claimed in claim 1 , wherein the electrical element is at least one capacitor element, the at least one conductive pillar is in a plurality, and the at least one capacitor element is electrically connected to the substrate via the conductive pillars. 17 . The repackage structure as claimed in claim 1 , wherein the substrate further comprises at least one additional pad disposed on the same surface of the board as the corresponding pads.

18. The repackage structure of claim 17, wherein the at least one additional pad is electrically connected to a power source or a ground.

19. The repackaging structure as described in claim 1, wherein the substrate further includes at least one signal pad and at least one ground pad, the electrical element includes a conductive layer, an insulating layer, a trace layer and an additional chip, the at least one conductive column includes at least one ground conductive column and at least one signal conductive column, the conductive layer is arranged between the dielectric and the insulating layer, the insulating layer is arranged between the conductive layer and the trace layer, the conductive layer is electrically connected to the at least one ground pad via the at least one ground conductive column, the trace layer is electrically connected to the at least one signal pad via the at least one signal conductive column, and the additional chip is mounted on the trace layer. 20 . The repackage structure as claimed in claim 19 , wherein the substrate further comprises a ground layer, and the at least one ground pad is electrically connected to the ground layer.

21. The repackaging structure as described in claim 19, wherein the number of the at least one signal conductive pillar is multiple, the number of the at least one signal pad is multiple, the signal conductive pillars are electrically connected to the signal pads, the number of the at least one grounding conductive pillar is multiple, the number of the at least one grounding pad is multiple, the grounding conductive pillars are electrically connected to the grounding pads, the signal conductive pillars and the grounding conductive pillars are located around the at least one chip, and two of the grounding conductive pillars are arranged on both sides of each of the signal conductive pillars. 22 . The repackage structure of claim 1 , wherein a dielectric top-view area of ​​the dielectric is greater than 100% of a chip top-view area of ​​the at least one chip and less than or equal to 150% of the chip top-view area. 23 . The repackage structure as claimed in claim 1 , wherein the substrate further comprises a plurality of conductive via connection structures, and each of the corresponding pads vertically corresponds to and is electrically connected to each of the mounting pads via each of the conductive via connection structures.

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