Semiconductor chip, semiconductor packaging structure and preparation method of semiconductor packaging structure

Abstract

The invention provides a semiconductor chip, a semiconductor packaging structure and a preparation method of the semiconductor packaging structure, and relates to the technical field of semiconductors. The semiconductor chip comprises a central region and a peripheral region, and further comprises a substrate; a first structure over the substrate in the central region, the first structure including a plurality of layers of metal patterns and a plurality of insulating layers, the metal patterns including test pads; the second structure is positioned above the first structure and is also positioned in the peripheral area of the semiconductor chip; a front pad layer over the second structure, the front pad layer including a plurality of first pads and a plurality of second pads; wherein the first bonding pad is located in the central area, the second bonding pad is located in the peripheral area, and the metal pattern density of the first structure is larger than that of the second structure. According to the embodiment of the invention, the packaging reliability of the semiconductor chip can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor chip, a semiconductor packaging structure, and a method for preparing the semiconductor packaging structure. Background Art

[0002] With the rapid development of semiconductor technology, advanced packaging technology has been widely used in high-performance computing, artificial intelligence, memory and other fields. In particular, the hybrid bonding stacking technology of multi-layer wafers has gradually become mainstream. However, with the rise of multi-layer wafer hybrid bonding technology, the wafer dicing process faces new challenges, especially for DRAM chips. The wafer dicing problem after hybrid bonding has become increasingly prominent.

[0003] In semiconductor manufacturing, wafer dicing is a key process for dividing the finished wafer into independent chips. Traditional wafer dicing methods are mainly optimized for single-layer wafers, including laser dicing, mechanical dicing (blade dicing), and plasma dicing. However, with the application of multi-layer hybrid bonded wafers, especially multi-layer hybrid bonded wafers containing Low-K materials, the limitations of existing dicing methods have gradually become apparent.

[0004] Therefore, with the widespread application of multi-layer hybrid bonded wafers in advanced packaging, the limitations of existing cutting methods have become increasingly prominent, especially the cutting problem of multi-layer hybrid bonded wafers containing Low-K materials needs to be solved urgently.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The present disclosure provides a semiconductor chip, a semiconductor packaging structure and a method for preparing the semiconductor packaging structure, which can improve the packaging reliability of the semiconductor chip.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, there is provided a semiconductor chip, comprising a central region and a peripheral region, and further comprising:

[0009] substrate;

[0010] A first structure, located above the substrate in the central area, the first structure comprising a multi-layer metal pattern and a multi-layer insulation layer, the metal pattern comprising a test pad;

[0011] A second structure, located above the first structure and also within the peripheral region of the semiconductor chip;

[0012] A front pad layer, located above the second structure, the front pad layer includes a plurality of first pads and a plurality of second pads;

[0013] Among them, the first pads are located within the central region, the second pads are located within the peripheral region, and the metal pattern density of the first structure is greater than that of the second structure.

[0014] In one embodiment, the dielectric constant of the second structure is greater than that of the insulating layer.

[0015] In one embodiment, the coefficient of thermal expansion of the second structure is less than that of the first structure.

[0016] In one embodiment, the metal pattern density of the second structure located in the peripheral region is zero.

[0017] In one embodiment, the top surface of the substrate located in the central region is higher than the top surface of the substrate located in the peripheral region.

[0018] In one embodiment, the second structure also covers the sidewall of the substrate located in the central region.

[0019] In one embodiment, the second structure includes a first dielectric layer and a second dielectric layer, the first dielectric layer covers the sidewall and the top surface of the first structure and is also located within the peripheral region.

[0020] In one embodiment, the front pad layer located in the peripheral region further includes a first alignment mark.

[0021] In one embodiment, the size of the first pads is substantially the same as the size of the second pads, and the pitch of the first pads is substantially the same as the pitch of the second pads; and / or

[0022] The first pads include a first virtual pad and a first bonding pad, the test pad is electrically connected to a part of the first bonding pad, the first virtual pad is electrically insulated from the metal pattern, and the second pad is electrically insulated from the substrate.

[0023] In one embodiment, the first structure further includes a passivation layer, located on the top surface of the first structure and exposing the test pad.

[0024] In one embodiment, the first structure is also located within a partial region of the peripheral region, and the first structure located in the peripheral region includes a second alignment mark.

[0025] In one embodiment, the semiconductor chip further includes a back pad layer located on the surface of the semiconductor chip facing away from the front pad layer. The second pad layer includes a plurality of third pads and a plurality of fourth pads. The third pads are located in the central region, and the fourth pads are located in the peripheral region. The sizes of the third pads are substantially the same as those of the fourth pads, and the pitches of the third pads are substantially the same as those of the fourth pads. The fourth pads are electrically insulating substrates.

[0026] In one embodiment, the back pad layer covers the substrate located in the central region and the second structure located in the peripheral region.

[0027] According to another aspect of the present disclosure, there is provided a semiconductor package structure, including:

[0028] A plurality of the above-mentioned semiconductor chips;

[0029] Among them, a plurality of the above-mentioned semiconductor chips are stacked in a hybrid bonding manner.

[0030] According to still another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor package structure, including:

[0031] Provide a first wafer, the first wafer includes an initial substrate and an initial first structure. The initial first structure is located above the initial substrate, and the initial first structure includes multiple metal patterns and multiple insulating layers. The metal patterns include test pads;

[0032] Cut the initial first structure to form a groove in the dicing channel region of the first wafer;

[0033] Form an initial second structure in the groove and above the initial first structure;

[0034] Form an initial front pad layer above the initial second structure;

[0035] Hybrid bond a plurality of first wafers to obtain a stacked wafer, and thin the back surface of the first wafer to form an initial back pad layer, and obtain a multi-layer wafer to be diced;

[0036] Cut the multi-layer wafer to be diced along the groove to obtain a semiconductor package structure, and the semiconductor package structure includes a plurality of the above-mentioned semiconductor chips.

[0037] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. Description of the Drawings

[0038] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0039] Figure 1 Top view of the semiconductor chip provided by the embodiment of the present disclosure; Figure 2 For the embodiment of the present disclosure along Figure 1 Cross-sectional view of the semiconductor chip along the a-a direction; Figure 3 Top view of the first wafer provided by the embodiment of the present disclosure; Figure 4 For the embodiment of the present disclosure Figure 3 Enlarged view of area A; Figure 5 For the embodiment of the present disclosure along Figure 1 Cross-sectional view of another semiconductor chip along the a-a direction; Figure 6 Top view of another semiconductor chip provided by the embodiment of the present disclosure; Figure 7 For the embodiment of the present disclosure along Figure 6 Cross-sectional view of another semiconductor chip along the b-b direction; Figure 8 Schematic structural diagram of a semiconductor packaging structure provided by the embodiment of the present disclosure; Figure 9 Schematic structural diagram of another semiconductor packaging structure provided by the embodiment of the present disclosure; Figures 10 - 18 Schematic structural diagram during the preparation process of a semiconductor packaging structure provided by the embodiment of the present disclosure; Detailed implementation manners

[0040] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant accompanying drawings. The preferred embodiments of the present disclosure are given in the accompanying drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure content of the present disclosure more thorough and comprehensive.

[0041] With the rapid development of semiconductor technology, advanced packaging technology has been widely used in fields such as high-performance computing, artificial intelligence, and memory. In particular, the hybrid bonding stacking technology of multi-layer wafers has gradually become the mainstream. However, with the rise of the multi-layer wafer hybrid bonding technology, the wafer dicing process has faced new challenges, especially the problem of wafer dicing after hybrid bonding of DRAM chips has become increasingly prominent.

[0042] In semiconductor manufacturing, wafer dicing is a critical process for dividing a completed wafer into individual chips. Traditional wafer dicing methods are mainly optimized for single-layer wafers, including techniques such as laser dicing, mechanical dicing (blade dicing), and plasma dicing. However, with the application of multi-layer hybrid-bonded wafers, especially those containing Low-K materials, the limitations of existing dicing methods are gradually emerging.

[0043] Due to its low dielectric constant characteristics, Low-K materials are widely used in advanced process DRAMs to reduce signal delay and crosstalk. However, the high porosity and relatively low mechanical strength of Low-K materials make them vulnerable to mechanical stress during the dicing process, resulting in problems such as chip detachment and cracking. Especially during mechanical dicing (blade dicing), the high-speed movement and cutting force of the blade may cause local stress concentration in the Low-K material, leading to material breakage, seriously affecting the dicing yield and product quality. In addition, a large number of metal pattern structures are widely used in the dicing lane area of advanced process wafers, and these structures pose limitations to plasma dicing during the dicing process. Due to the presence of metal pattern structures, traditional plasma dicing methods cannot effectively cut, resulting in a significant decrease in dicing yield and efficiency.

[0044] In view of this, embodiments of the present disclosure provide a semiconductor chip, a semiconductor packaging structure, and a method for preparing a semiconductor packaging structure. By removing the metal patterns in the wafer dicing lane area and filling them with a second structure, and simultaneously forming a front pad layer that can be hybrid-bonded above the second structure, damage to the semiconductor chip during wafer dicing is ensured, and at the same time, the packaging reliability of the semiconductor chip is improved.

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] Figure 1 A top view of the semiconductor chip provided by the embodiment of the present disclosure; Figure 2 For the embodiment of the present disclosure along Figure 1 a-a direction cross-sectional view of the semiconductor chip; Figure 3 A top view of the first wafer provided by the embodiment of the present disclosure; Figure 4 For the embodiment of the present disclosure providedFigure 3 Enlarged view of area A; Figure 5 For the present disclosure embodiment, it is a cross-sectional view of another semiconductor chip along the Figure 1 a-a direction; Figure 6 For the present disclosure embodiment, it is a top view of another semiconductor chip; Figure 7 For the present disclosure embodiment, it is a cross-sectional view of another semiconductor chip along the Figure 6 b-b direction;

[0047] Referring to Figures 1 - 2 As shown, in one embodiment, the semiconductor chip 100 includes a central region I and a peripheral region II, and further includes:

[0048] Substrate 110;

[0049] The first structure 120 is above the substrate 110 located in the central region I. The first structure 120 includes a multi-layer metal pattern 121 and a multi-layer insulating layer 122, and the metal pattern 121 includes a test pad 1212;

[0050] The second structure 130 is above the first structure 120 and is also within the peripheral region II of the semiconductor chip 100;

[0051] The front pad layer 140 is above the second structure 130. The front pad layer 140 includes a plurality of first pads 141 and a plurality of second pads 142;

[0052] Among them, the first pads 141 are within the central region I, the second pads 142 are within the peripheral region II, and the metal pattern density of the first structure 120 is greater than that of the second structure 130.

[0053] Referring to Figures 1 - 2 , the above semiconductor chip 100 will be described in detail.

[0054] The semiconductor chip 100 includes a central region I and a peripheral region II. The central region I can be the region where storage devices exist in the semiconductor chip 100, such as mainly used for placing DRAM memory cells, logic circuits, and other key functional modules. The peripheral region II can be within the scribe line region, that is, the scribe line region that is not cut and remains when the first wafer after front-end and back-end processes is cut. Referring to Figure 3 and Figure 4 , before the first wafer 200 is cut, it includes a scribe line region III and an actual cutting region V. The peripheral region II is the region that is not cut and remains when the first wafer 200 is cut, that is, referring to the II region in Figure 4 . That is to say, the peripheral region II is within the scribe line region III of the first wafer 200. The first wafer 200 is cut along the actual cutting region V to obtain the semiconductor chip 100.

[0055] The substrate 110 can be located in the central region I and the peripheral region II of the semiconductor chip 100. As shown in the reference Figure 2 figure, or it can be only located in the central region I of the semiconductor chip 100, as shown in the reference Figure 5 figure. The main material of the substrate 110 can be silicon, Silicon-on-Insulator (SOI), gallium arsenide (GaAs), gallium nitride (GaN), etc. The substrate 110 located in the central region I can include storage devices, such as those mainly used for placing DRAM memory cells, logic circuits, and other key functional modules. The substrate 110 also includes through-silicon via structures 160 for signal transmission.

[0056] The first structure 120 is above the substrate 110 located in the central region I. The first structure 120 includes multiple metal patterns 121 and multiple insulating layers 122. The metal pattern 121 includes test pads 1212. The first structure 120 is above the substrate 110 located in the central region I, that is to say, the first structure 120 covers the substrate 110 located in the central region I. The metal pattern 121 is actually a metal interconnect layer that connects components such as transistors, capacitors, and resistors inside the chip through wires and vias to form a complete circuit function. It is numbered as Metal 1 to Metal 5 (M1 - M5) according to the hierarchy. The specific hierarchy is as follows: M1 (Metal 1): The bottommost metal, directly connecting the source / drain or gate of the transistor. M2 - M4: Intermediate metal layers, responsible for local signal routing and power / ground distribution. M5 (or higher layer): The top metal layer, usually used for global signal transmission, power network, and high-density interconnection. The multiple insulating layers 122 are made of Low-K (low dielectric constant) materials, mainly used for electrical isolation between metal interconnect layers (such as M1 - M5) to reduce the interlayer capacitance, signal crosstalk, and power consumption. The Low-K (low dielectric constant) materials can be medium Low-K materials (k = 2.7 - 3.0), such as fluorine-doped silicon oxide (SiOF), carbon-doped silicon oxide (SiOCH), or ultra-low Low-K (k < 2.5) materials, such as porous SiCOH, organic polymers (polyimide), etc. The metal pattern 121 includes test pads 1212, that is to say, the M5 layer metal of the metal pattern 121 includes test pads 1212. The test pads 1212 are contacted by a probe card before wafer dicing, used to complete chip function tests (such as read / write verification of DRAM memory cells, leakage current detection, etc.), and screen out defective chips to improve the packaging yield. The test pads 1212 are usually made of aluminum (Al) or aluminum-copper alloy (Al - Cu). Additionally, the aluminum surface can be plated with a nickel / palladium / gold (Ni / Pd / Au) layer to enhance the welding performance and corrosion resistance.

[0057] The second structure 130 is located above the first structure 120 and is also located within the peripheral region II of the semiconductor chip 100; that is, the second structure 130 covers the first structure 120, and at the same time, the second structure 130 is also located within the peripheral region II of the semiconductor chip 100.

[0058] The front pad layer 140 is located above the second structure 130. The front pad layer 140 includes a plurality of first pads 141 and a plurality of second pads 142. That is, the front pad layer 140 covers the second structure 130. Moreover, the front pad layer 140 is above the test pad 1212. That is, the front pad layer 140 for hybrid bonding needs to be re-prepared, and the test pad 1212 is not required for hybrid bonding, which can avoid the bonding quality of hybrid bonding being affected by the damage of the test pad 1212 after testing. The front pad layer 140 includes a plurality of first pads 141, a plurality of second pads 142, a first interface layer 143, and a second interface layer 144. The plurality of first pads 141 and the plurality of second pads 142 may include at least one selected from, for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au) for hybrid bonding; the material of the first interface layer 143 may be silicon carbonitride, and the material of the second interface layer 144 may be silicon oxide. The high hardness and diffusion barrier ability of silicon carbonitride (SiCN) ensure the stable connection between the pad and the underlying medium, while the excellent insulation and passivation properties of silicon oxide (SiO2) provide long-term protection for the pad.

[0059] Among them, the first pads 141 are located within the central region I, the second pads 142 are located within the peripheral region II, and the metal pattern density of the first structure 120 is greater than that of the second structure 130. By providing the second pads 142 in the peripheral region II, the bonding strength of the semiconductor chip 100 can be improved. At the same time, the metal pattern density of the first structure 120 is greater than that of the second structure 130. That is, the metal pattern density of the second structure 130 is less than that of the first structure 120, which can avoid the problem that when the first wafer 200 is cut to obtain the semiconductor chip 100, due to the presence of a high-density metal pattern, it cannot be effectively cut, resulting in a significant decrease in the cutting yield and efficiency. That is, since the metal pattern density of the second structure 130 is less than that of the first structure 120, the cutting yield and efficiency can be improved when the first wafer 200 is cut.

[0060] In one embodiment, the dielectric constant of the second structure 130 is greater than the dielectric constant of the insulating layer 122. The second structure 130 is located above the first structure 120 and is also located in the peripheral region II of the semiconductor chip 100; the material of the second structure 130 is a high dielectric constant material, which generally has a high mechanical strength and a low porosity. This material property enables the second structure 130 to withstand greater mechanical stress during the cutting process. In the process of cutting the first wafer 200 to obtain the semiconductor chip 100, the second structure 130 can absorb and disperse part of the cutting stress, reduce the concentration of stress in the insulating layer 122 material, and thus reduce the probability of chipping and cracking.

[0061] In one embodiment, the thermal expansion coefficient of the second structure 130 is smaller than that of the first structure 120. Since the thermal expansion coefficient of the second structure 130 is smaller than that of the first structure 120, in the process of cutting the first wafer 200 to obtain the semiconductor chip 100, although a large amount of heat will be generated due to friction, the thermal expansion coefficient of the second structure 130 is smaller, and its thermal deformation is smaller, which can protect the first structure 120 and avoid unnecessary thermal stress in the first structure 120, thereby avoiding the risk of crack initiation in the first structure 120 during the cutting process. At the same time, the local warping caused by cutting heat can be suppressed, so that the straightness deviation of the cutting path is reduced, and the cutting accuracy is improved.

[0062] In one embodiment, the metal pattern density of the second structure 130 located in the peripheral area II is zero. That is, the second structure 130 located in the peripheral area II does not contain a metal pattern, eliminating metal interference such as metal scattering during the cutting process, so that the cutting energy is fully applied to the cutting area, thereby improving the cutting yield and efficiency.

[0063] In one embodiment, the top surface of the substrate 110 located in the central region I is higher than the top surface of the substrate 110 located in the peripheral region II. That is, the bottom surface of the first structure 130 is lower than the bottom surface of the second structure 120. In this way, during the cutting process, the cutting order may be the front pad layer 140 first, the second structure 120 second, and the substrate 110 last, or the cutting order may be the substrate 110 first, the second structure 120 second, and the front pad layer 140 last. In other words, in the process of cutting the first wafer 200 to obtain the semiconductor chip 100, the first structure 120 is not cut as much as possible, thereby reducing the probability of chipping and cracking due to the presence of a large number of metal patterns in the first structure 120 and the Low-K material when cutting.

[0064] See also Figure 5As shown, in one embodiment, the second structure 130 also covers the sidewalls of the substrate 110 located in the central region I. That is to say, the substrate 110 is only located in the central region I of the semiconductor chip 110. Thus, during the dicing process, the dicing sequence can be the front pad layer 140 first, followed by the second structure 130, or the dicing sequence can be the second structure 130 first, followed by the front pad layer 140. That is, during the dicing process, it is not necessary to dice the substrate 110, which makes it easier to dice and can improve the dicing yield and efficiency.

[0065] In one embodiment, the second structure 130 includes a first dielectric layer 131 and a second dielectric layer 132. The first dielectric layer 131 covers the sidewalls and the top surface of the first structure 120 and is also located within the peripheral region II. The first dielectric layer 131 can be a nitride such as silicon nitride, etc., and the second dielectric layer 132 can be an oxide such as silicon oxide, etc.; the first dielectric layer 131 is deposited by a linear deposition (linear dep) method, which can serve as a protective layer and can prevent contamination or damage when filling the second dielectric layer 132 such as an oxide in the dicing channel region. After filling the second dielectric layer 132 such as an oxide, the first dielectric layer 131 such as a nitride can provide better insulation performance.

[0066] In one embodiment, the step coverage of the first dielectric layer 131 is higher than that of the second dielectric layer 132. Step Coverage is an important indicator to measure the deposition uniformity of a dielectric layer on a vertical or inclined surface (such as steps, trenches, etc.). The higher the step coverage, the more uniform the deposition of the dielectric layer in these regions and the better the coverage effect. Since the sidewalls or step regions of the first structure 120 are relatively complex, therefore, it is necessary to deposit the first dielectric layer 131 with a high step coverage first, and then fill the second dielectric layer 132 with a low step coverage. In this way, the filling effect of the second dielectric layer 132 can be improved, avoiding the generation of holes, etc. during the filling process, and thus improving the dicing effect of the first wafer.

[0067] In one embodiment, the front pad layer 140 located in the peripheral region II further includes a first alignment mark 170. The first alignment mark 170 can be a bonding alignment mark for precise positioning during chip packaging to ensure accurate alignment between the wire bonder and the chip pads; the first alignment mark 170 can be a registration alignment mark in the lithography process for pattern alignment between different process layers; the first alignment mark 170 is provided on the front pad layer 140 located in the peripheral region II, that is, in the full clearance area in the dicing channel region. Thus, due to no obstruction by the first structure 120, the alignment effect of the first alignment mark 170 is more excellent.

[0068] In one embodiment, the size of the first pad 141 is substantially the same as the size of the second pad 142, and the pitch of the first pad 141 is substantially the same as the pitch of the second pad 142; the shape of the first pad 141 or the second pad 142 can be circular, polygonal, elliptical, etc. The size of the first pad 141 is substantially the same as the size of the second pad 142, that is, the orthographic projection of the first pad 141 and the orthographic projection of the second pad 142 completely overlap, and the pitch of the first pad 141 is substantially the same as the pitch of the second pad 142. That is to say, the pitch between any two first pads is substantially the same as the pitch between any two second pads 142. The same size and pitch of the first pad 141 and the second pad 142 result in a high degree of symmetry on the wafer surface during the polishing process. This symmetry helps to evenly distribute the polishing pressure and the flow of the polishing liquid, thereby avoiding local over-polishing or under-polishing. The symmetric design can reduce stress concentration caused by non-uniform structure during the polishing process, thereby reducing the risk of wafer warping.

[0069] and / or,

[0070] The first pad 141 includes a first dummy pad 1412 and a first bonding pad 1411. The test pad 1212 is electrically connected to a part of the first bonding pad 1411. The first dummy pad 1412 is electrically insulated from the metal pattern 121, and the second pad 142 is electrically insulated from the substrate 110. That is to say, a part of the first bonding pad 1411 is electrically connected to the test pad 1212 in the metal pattern 121, and the first dummy pad 1412 is electrically insulated from the metal pattern 121. By adding the first dummy pad 1412, the first dummy pad 1412 and the first bonding pad 1411 together form a uniform polishing surface in the central region I, and the thickness non-uniformity after CMP is controlled within ±3 nm.

[0071] In one embodiment, the first structure 120 further includes a passivation layer 123, which is located on the top surface of the first structure 120 and exposes the test pad 1212. The material of the passivation layer 123 can be silicon nitride, which protects the wafer surface, prevents the wafer from being physically or chemically damaged during the testing process, and avoids contamination and scratches. The excellent dielectric properties of silicon nitride help to isolate the circuit, prevent signal interference, and ensure the accuracy of the test. In a high-temperature test environment, the thermal stability of the passivation layer 123 ensures the stability of the test process and prevents performance fluctuations caused by temperature changes. The excellent dielectric properties of the passivation layer 123 help to isolate the circuit, prevent signal interference, and ensure the accuracy of the test.

[0072] In one embodiment, the first structure 120 is also located in a partial area of the peripheral region II, and the first structure located in the peripheral region includes a second alignment mark 180. See Figure 3As shown, the first wafer 200 further includes an alignment mark region 210. When the first wafer 200 is cut along the actual cutting region V and the alignment mark region 210 is cut, the semiconductor chip 100 structure as shown in Figure 7 is obtained. Among them, due to the existence of the alignment mark region 210, a part of the first structure 120 is also located in the peripheral region II, and the first structure located in the peripheral region includes a second alignment mark 180. The structure of the second alignment mark 180 includes a cross type, a bar code type, and a multi-layer stacked type. The material of the second alignment mark 180 is metal. The position of the second alignment mark 180 can be on the same metal layer as the test pad 1212, that is, both are on the M5 layer. A part of the first structure 120 is also located in the peripheral region II, that is, the first structure 120 at the alignment mark region 210 is not replaced by the second structure 130. Thus, the processing of the first alignment mark 170 can be omitted, which can ensure the alignment during the bonding process of the first wafer 200. At the same time, since the area of the alignment mark region 210 is small, it will not affect the improvement of the yield of the subsequent cutting process of the first wafer 200.

[0073] In one embodiment, continue to refer to Figure 2 . The semiconductor chip further includes a backside pad layer 150. The backside pad layer is located on the surface of the substrate 110 facing away from the front side pad layer 140. The second pad layer 150 includes a plurality of third pads 151 and a plurality of fourth pads 152. The third pads 151 are located in the central region I, and the fourth pads 152 are located in the peripheral region II. Among them, the third pad 151 further includes a third bonding pad 1511 and a third dummy pad 1512. The third bonding pad 1511 can be electrically connected to the through-silicon via structure 160, and the third dummy pad 1512 is electrically insulated from the through-silicon via structure 160. The backside pad layer 150 further includes a third interface layer 153 and a fourth interface layer 154. The plurality of third pads 151 and the plurality of fourth pads 152 can include at least one selected from, for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au) for hybrid bonding. The material of the third interface layer 153 can be silicon carbonitride, and the material of the fourth interface layer 154 can be silicon oxide. The high hardness and diffusion barrier ability of silicon carbonitride (SiCN) ensure the stable connection between the pad and the underlying dielectric, while the excellent insulation and passivation properties of silicon oxide (SiO2) provide long-term protection for the pad. Continue to refer to Figure 2, the size of the third pad 151 is substantially the same as that of the fourth pad 152, and the pitch of the third pad 151 is substantially the same as that of the fourth pad 152. The fourth pad 152 is an electrically insulating substrate 110. Additionally, the shape of the third pad 151 or the fourth pad 152 can be circular, polygonal, elliptical, etc. The size of the third pad 151 is substantially the same as that of the fourth pad 152, that is, the orthographic projection of the third pad 151 and the orthographic projection of the fourth pad 152 completely overlap. The pitch of the third pad 151 is substantially the same as that of the fourth pad 152, that is to say, the pitch between any two third pads 151 is substantially the same as the pitch between any two fourth pads 152. Additionally, the sizes of the first pad 141, the second pad 142, the third pad 151, and the fourth pad 152 are substantially the same, and the pitches of the first pad 141, the second pad 142, the third pad 151, and the fourth pad 152 are substantially the same. Thus, the bonding difficulty of the semiconductor chip 100 can be reduced.

[0074] In one embodiment, continue to refer to Figure 5 , the back pad layer 150 covers the substrate 110 located in the central region I and the second structure 130 located in the peripheral region II. That is to say, the substrate 110 is only located in the central region I of the semiconductor chip 110. Thus, during the dicing process, the dicing sequence can be the front pad layer 140 first, then the second structure 130, and finally the back pad layer 150, or the dicing sequence can be the back pad layer 150 first, then the second structure 130, and finally the front pad layer 140. That is, during the dicing process, it is not necessary to dice the substrate 110. Thus, it is easier to dice, and the dicing yield and efficiency can be improved.

[0075] Based on the above embodiments, the embodiments of the present disclosure further provide a semiconductor packaging structure. The following provides a detailed description of the semiconductor packaging structure.

[0076] Figure 8 shows a schematic structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0077] Figure 9 shows a schematic structural diagram of another semiconductor packaging structure provided by an embodiment of the present disclosure;

[0078] Refer to Figure 8 As shown, in one embodiment, a semiconductor packaging structure 300 is provided, including:

[0079] A plurality of the above semiconductor chips 100;

[0080] Among them, a plurality of the above semiconductor chips 100 are stacked in a hybrid bonding manner.

[0081] In one embodiment, refer to Figure 9, two semiconductor chips 100 are face-to-face hybrid bonded to obtain a stacked unit 310, and multiple stacked units 310 are stacked by hybrid bonding to obtain a semiconductor package structure 300. The so-called face-to-face hybrid bonding means that the active surfaces (including transistors or circuit layers) of two semiconductor chips 100 are relatively bonded, and pad-to-pad bonding and dielectric-to-dielectric bonding are performed.

[0082] Based on the above embodiments, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor package structure. The following will describe in detail the method for manufacturing a semiconductor package structure.

[0083] Figures 10 - 18 Shows a schematic structural diagram in the manufacturing process of a semiconductor package structure provided by an embodiment of the present disclosure;

[0084] Refer to Figures 10 - 16 As shown, in one embodiment, a semiconductor package structure 300 is provided, including:

[0085] See Figure 10 As shown, a first wafer 200 is provided. The first wafer 200 includes an initial substrate 210 and an initial first structure 220. The initial first structure 220 is located above the initial substrate 210. The initial first structure 220 includes multiple metal patterns 121 and multiple insulating layers 122. The metal pattern includes test pads 1212;

[0086] The metal pattern 121 is actually a metal interconnect layer that connects components such as transistors, capacitors, and resistors inside the chip through wires (Lines) and vias to form a complete circuit function. It is numbered as Metal 1 to Metal 5 (M1 - M5) according to the hierarchy, and the specific hierarchy division is as follows: M1 (Metal1): The bottom - layer metal, directly connecting to the source / drain or gate of the transistor. M2 - M4: Intermediate - layer metals, responsible for local signal routing and power / ground distribution. M5 (or higher layer): The top - layer metal, usually used for global signal transmission, power network, and high - density interconnection. The multi - layer insulating layer 122 uses Low - K (low dielectric constant) materials, mainly for electrical isolation between metal interconnect layers (such as M1 - M5) to reduce inter - layer capacitance, signal crosstalk, and power consumption. The Low - K (low dielectric constant) material can be a medium Low - K material (k = 2.7 - 3.0): such as fluorinated silicon oxide (SiOF), carbon - doped silicon oxide (SiOCH), or an ultra - low Low - K (k < 2.5) material: such as porous SiCOH, organic polymers (polyimide), etc. The metal pattern 121 includes test pads 1212. That is to say, the M5 - layer metal of the metal pattern 121 includes test pads 1212. The test pads 1212 are contacted by a probe card before wafer dicing, used to complete chip function tests (such as read - write verification of DRAM memory cells, leakage current detection, etc.), and defective chips are screened out to improve the packaging yield. The test pads 1212 usually use aluminum (Al) or aluminum - copper alloy (Al - Cu). Additionally, the aluminum surface can be plated with a nickel / palladium / gold (Ni / Pd / Au) layer to enhance welding performance and corrosion resistance.

[0087] That is to say, the initial first structure 220 is still within the scribe lane region III. Thus, the dicing problem of the first wafer 200 needs to be solved urgently.

[0088] See Figure 4 and Figure 11 As shown, the initial first structure 220 is diced to form a groove 400 within the scribe lane region III of the first wafer 200; See Figure 4 As shown, the width of the groove 400 is Figure 4 the region IV in, that is, the width of the groove 400 is less than the width of the scribe lane region III. Here, the depth of the groove 400, preferably, needs to be greater than the depth of the initial first structure 220, that is, the groove 400 will cut into the initial substrate 210; or, the bottom surface of the groove 400 is lower than the bottom surface of the initial first structure 220 and lower than the bottom surface of the device layer of the initial substrate 210.

[0089] It should be noted that, see Figures 3 - 4As shown, when the alignment mark area 210 is further included in the scribe lane area III, the alignment mark area 210 does not need to be cut to form a groove, that is, the initial first structure 220 below the alignment mark area 210 does not need to be cut to form a groove. In this way, the bonding alignment of the first wafer can be ensured.

[0090] Alternatively, when the alignment mark area 210 is further included in the scribe lane area III, the alignment mark area 210 also needs to be cut to form a groove. In this way, the alignment marks in the alignment mark area 210 are damaged and the first alignment marks 170 need to be re-fabricated in the peripheral area II.

[0091] See Figure 12 As shown, an initial second structure 230 is formed within the groove 400 and above the initial first structure 220;

[0092] In some embodiments, the metal pattern density of the initial second structure 230 is less than that of the initial first structure 220. In some embodiments, the dielectric constant of the initial second structure 230 is greater than that of the insulating layer 122. In some embodiments, the coefficient of thermal expansion of the initial second structure 230 is less than that of the initial first structure 220.

[0093] The initial second structure 230 includes a first dielectric layer 131 and a second dielectric layer 132. The first dielectric layer 131 covers the sidewalls and the top surface of the initial first structure 220. That is to say, the first dielectric layer 131 covers the sidewalls and the top surface of the groove 400. The second dielectric layer 132 is used to fill the groove 400. The first dielectric layer 131 may be a nitride such as silicon nitride, etc. The second dielectric layer 132 may be an oxide such as silicon oxide, etc. The first dielectric layer 131 is deposited by a linear deposition (linear dep) method and can be used as a protection layer to prevent contamination or damage when filling the second dielectric layer 132 such as an oxide in the scribe lane area. After filling the second dielectric layer 132 such as an oxide, the first dielectric layer 131 such as a nitride can provide better insulation performance.

[0094] See Figure 13 As shown, an initial front pad layer 240 is formed above the initial second structure 230;

[0095] The initial front pad layer 240 includes a plurality of first pads 141, a plurality of second pads 142, a first interface layer 143, and a second interface layer 144. The plurality of first pads 141 and the plurality of second pads 142 may include at least one selected from, for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au) for hybrid bonding; the material of the first interface layer 143 may be silicon carbonitride, and the material of the second interface layer 144 may be silicon oxide. The high hardness and diffusion barrier ability of silicon carbonitride (SiCN) ensure a stable connection between the pads and the underlying dielectric, while the excellent insulation and passivation properties of silicon oxide (SiO2) provide long-term protection for the pads. The second interface layer 144 may be deposited and prepared simultaneously with the second dielectric layer 132.

[0096] See Figure 14 As shown, a plurality of first wafers 200 are hybrid-bonded to obtain a stacked wafer 201. See Figures 15 - 16 , the back surface of the first wafer 200 is thinned to form an initial back pad layer 250, and a multi-layer wafer 202 to be cut is obtained; the initial back pad layer 250 includes a plurality of third pads 151, a plurality of fourth pads 152, a third interface layer 153, and a fourth interface layer 154. The plurality of third pads 151 and the plurality of fourth pads 152 may include at least one selected from, for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au) for hybrid bonding; the material of the third interface layer 153 may be silicon carbonitride, and the material of the fourth interface layer 154 may be silicon oxide. The high hardness and diffusion barrier ability of silicon carbonitride (SiCN) ensure a stable connection between the pads and the underlying dielectric, while the excellent insulation and passivation properties of silicon oxide (SiO2) provide long-term protection for the pads. It should be emphasized that the thinning depth of the back surface of the first wafer 200 can be thinned to expose the initial second structure 230, so that the subsequent cutting difficulty can be reduced.

[0097] See Figures 8 - 9 As shown, the multi-layer wafer 202 to be cut is cut along the groove 400 to obtain a semiconductor package structure 300, and the semiconductor package structure 300 includes a plurality of the above semiconductor chips 100. See Figure 4 As shown, the width of the groove 400 is Figure 4 the IV region in, and the actual cutting region is the V region. That is to say, the width of the actual cutting region V is smaller than the width of the groove 400, and the II region is the uncut IV region retained after actual cutting.

[0098] Since the metal pattern density of the initial second structure 230 is less than that of the initial first structure 220, it is possible to avoid the problem that when the multi-layer wafer 202 to be cut is cut to obtain the semiconductor package structure 300, due to the presence of high-density metal patterns, effective cutting cannot be performed, resulting in a significant decrease in cutting yield and efficiency. That is, since the metal pattern density of the initial second structure 230 is less than that of the initial first structure 220, the cutting yield and efficiency can be improved when the multi-layer wafer 202 to be cut is cut.

[0099] In one embodiment, referring to Figures 17 - 18 , two first wafers 200 are face-to-face hybrid bonded to obtain a stacked wafer unit 203, and multiple stacked wafer units 203 are stacked by hybrid bonding to obtain a multi-layer wafer 202 to be cut. The so-called face-to-face hybrid bonding means that the active surfaces (including transistors or circuit layers) of two first wafers 200 are relatively bonded, and are bonded by pad-to-pad bonding and dielectric-to-dielectric bonding.

[0100] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure.

[0101] In the description of the present disclosure, it should be understood that the terms "including" and "having" used herein and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices.

[0102] Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, and can be the connection inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor chip comprising a central region and a peripheral region, characterized in that: include: substrate; A first structure, above the substrate located in the central area, the first structure comprising a multi-layer metal pattern and a multi-layer insulation layer, the metal pattern comprising a test pad; a second structure located above the first structure and also located within the peripheral region of the semiconductor chip; A front pad layer, located above the second structure, the front pad layer comprising a plurality of first pads and a plurality of second pads; The first pad is located in the central area, the second pad is located in the peripheral area, and the metal pattern density of the first structure is greater than the metal pattern density of the second structure.

2. The semiconductor chip according to claim 1, characterized in that The dielectric constant of the second structure is greater than the dielectric constant of the insulating layer.

3. The semiconductor chip according to claim 1, characterized in that The second structure has a thermal expansion coefficient that is smaller than a thermal expansion coefficient of the first structure.

4. The semiconductor chip according to claim 1, characterized in that The metal pattern density of the second structure located in the peripheral area is zero.

5. The semiconductor chip according to claim 1, characterized in that The top surface of the substrate located in the central area is higher than the top surface of the substrate located in the peripheral area.

6. The semiconductor chip according to claim 1, characterized in that The second structure also covers the sidewalls of the substrate located in the central area.

7. The semiconductor chip according to claim 1, characterized in that The second structure includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the sidewalls and the top surface of the first structure and is also located in the peripheral area.

8. The semiconductor chip according to claim 1, characterized in that The front side pad layer located in the peripheral area further includes a first alignment mark.

9. The semiconductor chip according to claim 1, characterized in that The size of the first pad is substantially the same as the size of the second pad, and the spacing between the first pads is substantially the same as the spacing between the second pads; and / or The first pad includes a first dummy pad and a first bonding pad, the test pad is electrically connected to a portion of the first bonding pad, the first dummy pad is electrically insulated from the metal pattern, and the second pad is electrically insulated from the substrate.

10. The semiconductor chip according to claim 1, characterized in that The first structure further includes a passivation layer located on a top surface of the first structure and exposing the test pad.

11. The semiconductor chip according to claim 1, characterized in that The first structure is also located in a partial area of ​​the peripheral region, and the first structure located in the peripheral region includes a second alignment mark.

12. The semiconductor chip according to claim 1, characterized in that The semiconductor chip also includes a back side pad layer, which is located on the surface of the semiconductor chip away from the front side pad layer. The second pad layer includes a plurality of third pads and a plurality of fourth pads. The third pads are located in the central area, and the fourth pads are located in the peripheral area. The size of the third pads is substantially the same as the size of the fourth pads, the spacing between the third pads is substantially the same as the spacing between the fourth pads, and the fourth pads are electrically insulating the substrate.

13. The semiconductor chip according to claim 12, characterized in that The backside pad layer covers the substrate located in the central area and the second structure located in the peripheral area.

14. A semiconductor packaging structure, characterized in that: include A plurality of semiconductor chips as claimed in any one of claims 1 to 13; Among them, multiple semiconductor chips are stacked using a hybrid bonding method.

15. A method for preparing a semiconductor packaging structure, characterized in that: include Providing a first wafer, the first wafer comprising an initial substrate and an initial first structure, the initial first structure being located above the initial substrate, the initial first structure comprising a multi-layer metal pattern and a multi-layer insulation layer, the metal pattern comprising a test pad; cutting the initial first structure to form grooves in the dicing street area of ​​the first wafer; forming an initial second structure in the groove and above the initial first structure; forming an initial front side pad layer over the initial second structure; Mixing and bonding the plurality of the first wafers to obtain a stacked wafer, and thinning the back side of the first wafer to form an initial back side pad layer, and obtaining a multi-layer wafer to be cut; The multi-layer wafer to be cut is cut along the groove to obtain a semiconductor packaging structure, wherein the semiconductor packaging structure includes a plurality of semiconductor chips as described in any one of claims 1 to 13.

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