Inverter i-type three-level drive logic protection circuit and inverter

Abstract

The application discloses an inverter I type three-level drive logic protection circuit and an inverter, and the circuit comprises a triode push-pull component, an input end of which is connected with an inner tube input signal; a logic gate component, a first input end of which is connected with an outer tube input signal, and a second input end of which is connected with an output end of the triode push-pull component; and a delay protection module, which comprises a resistor, a first diode and a capacitor, one end of the resistor is connected with the output end of the triode push-pull component, the other end of the resistor is connected with one end of the capacitor, the other end of the capacitor is grounded, and the two ends of the first diode are connected with the two ends of the resistor respectively; wherein the output end of the logic gate component is used for outputting an outer tube output signal, and the output end of the delay protection module is used for outputting an inner tube output signal, and the application can realize effective protection of a power device through the cooperative work of the logic gate component and the delay protection module on the hardware level, thereby ensuring stable operation of the system.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a type I three-level drive logic protection circuit for an inverter and an inverter. Background Technology

[0002] Currently, in the Type I three-level circuit of inverters, the power devices operate in series, with each device only needing to withstand half of the system voltage. Therefore, the turn-on and turn-off logic of the drive switching transistors becomes particularly important. It is necessary to ensure the correct switching sequence of the internal and external transistors. Once the drive logic is incorrect, it is very likely to cause overvoltage damage to the power devices, leading to serious consequences such as malfunctions or even equipment destruction.

[0003] Traditional drive logic protection for type I three-level topologies mainly relies on software implementation, lacking effective protection measures for power devices at the hardware level. Summary of the Invention

[0004] The purpose of this invention is to at least solve one of the technical problems existing in the prior art, and to provide an inverter type I three-level drive logic protection circuit and an inverter, which can effectively protect power devices at the hardware level through the coordinated work of logic gate components and delay protection modules, thereby ensuring the stable operation of the system.

[0005] In a first aspect, embodiments of the present invention provide a type I three-level drive logic protection circuit for an inverter, comprising: a transistor push-pull assembly with its input terminal connected to the input signal of the inner transistor; a logic gate assembly with its first input terminal connected to the input signal of the outer transistor and its second input terminal connected to the output terminal of the transistor push-pull assembly; and a delay protection module comprising a resistor, a first diode, and a capacitor, wherein one end of the resistor is connected to the output terminal of the transistor push-pull assembly, the other end is connected to one end of the capacitor, the other end of the capacitor is grounded, and the two ends of the first diode are respectively connected to the two ends of the resistor; wherein the output terminal of the logic gate assembly is used to output the output signal of the outer transistor, and the output terminal of the delay protection module is used to output the output signal of the inner transistor.

[0006] In some embodiments, the logic gate component is an AND gate component, the end of the resistor closest to the capacitor is connected to the output terminal of the delay protection module, the first diode is forward-biased, the positive terminal is connected to the output terminal of the transistor push-pull component, and the negative terminal is connected to the output terminal of the delay protection module.

[0007] In some embodiments, the delay protection module further includes a second diode, which is disposed between the output terminal of the transistor push-pull assembly and the resistor. The second diode is configured in reverse, with its positive terminal connected to the resistor and its negative terminal connected to the output terminal of the transistor push-pull assembly.

[0008] In some embodiments, the delay protection module further includes a second diode, which is disposed between the resistor and the output terminal of the delay protection module. The second diode is configured in reverse, with its positive terminal connected to the output terminal of the delay protection module and its negative terminal connected to the resistor.

[0009] In some embodiments, a high-level signal is used to turn on the corresponding switch, and a low-level signal is used to turn off the corresponding switch; when the input signal of the outer tube is a high-level signal and the input signal of the inner tube is a low-level signal, both the output signal of the outer tube and the output signal of the inner tube are low-level signals; when both the input signal of the outer tube and the input signal of the inner tube change from high-level signals to low-level signals, the output signal of the outer tube changes from high-level signals to low-level signals, and the output signal of the inner tube changes from high-level signals to low-level signals after the capacitor has discharged.

[0010] In some embodiments, the logic gate component is an OR gate component, the end of the resistor closest to the capacitor is connected to the output terminal of the delay protection module; the first diode is reverse-biased, with its positive terminal connected to the output terminal of the delay protection module and its negative terminal connected to the output terminal of the transistor push-pull component.

[0011] In some embodiments, the delay protection module further includes a second diode, which is disposed between the resistor and the output terminal of the delay protection module. The second diode is forward-biased, with its positive terminal connected to the resistor and its negative terminal connected to the output terminal of the delay protection module.

[0012] In some embodiments, the delay protection module further includes a second diode, which is disposed between the output terminal of the transistor push-pull assembly and the resistor. The second diode is forward-biased, with its positive terminal connected to the output terminal of the transistor push-pull assembly and its negative terminal connected to the resistor.

[0013] In some embodiments, a low-level signal is used to turn on the corresponding switch, and a high-level signal is used to turn off the corresponding switch; when the input signal of the outer tube is low and the input signal of the inner tube is high, both the output signal of the outer tube and the output signal of the inner tube are high; when both the input signal of the outer tube and the input signal of the inner tube change from low to high, the output signal of the outer tube changes from low to high, and the output signal of the inner tube changes from low to high after the capacitor is fully charged.

[0014] In a second aspect, embodiments of the present invention provide an inverter, including an inverter type I three-level drive logic protection circuit as described in any embodiment of the first aspect.

[0015] According to embodiments of the present invention, an inverter type I three-level drive logic protection circuit and an inverter are provided, which have at least the following beneficial effects: The present invention provides an inverter type I three-level drive logic protection circuit, which improves the stability and reliability of the system by introducing a transistor push-pull component and a delay protection module; specifically, the inverter type I three-level drive logic protection circuit includes a transistor push-pull component, a logic gate component, and a delay protection module. The first input terminal of the logic gate component is connected to the input signal of the external transistor, and the second input terminal is connected to the output terminal of the transistor push-pull component. This means that the logic gate component will only output a high-level signal to control the external transistor to conduct when both input signals are high at the same time. At the same time, the transistor push-pull component enhances the driving capability of the internal transistor input signal and transmits it to the delay protection module. Due to the existence of the delay protection module, the output signal of the internal transistor will change only after an appropriate time delay; it can be understood that the resistor, the first diode, and the capacitor in the delay protection module together constitute an RC delay circuit. When the output signal of the transistor push-pull component changes, the capacitor charges or discharges through the resistor, generating a delay effect. This invention ensures correct switching timing and avoids overvoltage damage caused by timing issues. In summary, the inverter type I three-level drive logic protection circuit and inverter provided in this invention can effectively protect power devices at the hardware level through the coordinated operation of logic gate components and delay protection modules, thereby ensuring stable system operation.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0017] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments;

[0019] Figure 1 This is a schematic diagram of the inverter type I three-level circuit provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of an AND gate component in the inverter type I three-level drive logic protection circuit provided in this embodiment of the invention.

[0021] Figure 3This is a schematic diagram of an inverter type I three-level drive logic protection circuit provided in an embodiment of the present invention, wherein the logic gate component is an AND gate component and the second diode is reverse-biased.

[0022] Figure 4 This is another schematic diagram of the inverter type I three-level drive logic protection circuit provided in the embodiment of the present invention, in which the logic gate component is an AND gate component and the second diode is reverse-biased;

[0023] Figure 5 This is a schematic diagram of an OR gate component in the inverter type I three-level drive logic protection circuit provided in an embodiment of the present invention.

[0024] Figure 6 This is a schematic diagram of an inverter type I three-level drive logic protection circuit provided in an embodiment of the present invention, wherein the logic gate component is an OR gate component and the second diode is forward-biased.

[0025] Figure 7 This is another schematic diagram of the inverter type I three-level drive logic protection circuit provided in the embodiment of the present invention, in which the logic gate component is an OR gate component and the second diode is forward-biased. Detailed Implementation

[0026] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.

[0027] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the number itself, while "above," "below," "within," etc. are understood to include the number itself. "Any one" refers to one or more, and "at least one of the following" and similar expressions refer to any combination of these items, including any combination of single or multiple items. If "first" or "second" is used in the description, it is only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of the indicated technical features.

[0028] It should be noted that the terms "setting," "installing," and "connecting" in the embodiments of this invention should be interpreted broadly. Those skilled in the art can reasonably determine the specific meaning of the above terms in the embodiments of this invention in conjunction with the specific content of the technical solution. For example, the term "connection" can be a mechanical connection, an electrical connection, or a connection that allows for mutual communication; it can be a direct connection or an indirect connection through an intermediate medium.

[0029] It should be noted that the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] Currently, power devices in the Type I three-level inverter circuit operate in series, with each device only needing to withstand half of the system voltage. Therefore, the turn-on and turn-off logic of the drive switches becomes particularly important, requiring accurate switching timing between the internal and external transistors. Errors in the drive logic can easily lead to overvoltage damage to the power devices, resulting in malfunctions or even equipment failure. Traditional drive logic protection for Type I three-level topologies relies primarily on software implementation, lacking effective hardware-level protection measures for the power devices.

[0031] refer to Figure 1 , Figure 1 This is a schematic diagram of the inverter type I three-level circuit provided in the embodiment of the present invention. Q1, Q2, Q3, and Q4 are power switching transistors (usually IGBTs or MOSFETs) used to control the on and off of the current; D1 and D2 are diodes used to provide a freewheeling path and prevent voltage spikes. By controlling the switching state of Q1, Q2, Q3, and Q4, three different output levels can be generated: positive bus voltage, zero level, and negative bus voltage.

[0032] It is understood that in the above topology, switches Q1 and Q2 are grouped together, with Q1 being the external switch and Q2 the internal switch; switches Q3 and Q4 form another group, with Q4 being the external switch and Q3 the internal switch. Of course, those skilled in the art can flexibly select other types of Type I three-level circuit configurations according to actual needs. In other words, the Type I three-level drive logic protection circuit disclosed in this embodiment has wide applicability and can be adapted to any form of Type I three-level circuit structure, providing a solid and reliable guarantee and support for the stable operation of related circuit systems.

[0033] Based on this, the purpose of the present invention is to at least solve one of the technical problems existing in the prior art, and to provide an inverter type I three-level drive logic protection circuit and an inverter, which can effectively protect power devices at the hardware level through the coordinated work of logic gate components and delay protection modules, thereby ensuring the stable operation of the system.

[0034] refer to Figure 2 , Figure 2This is a schematic diagram of an inverter type I three-level drive logic protection circuit provided in an embodiment of the present invention, wherein the logic gate component is an AND gate component; in a first aspect, an embodiment of the present invention provides an inverter type I three-level drive logic protection circuit, including: a transistor push-pull component, the input terminal of which is connected to the input signal of the inner transistor; a logic gate component, the first input terminal of which is connected to the input signal of the outer transistor, and the second input terminal of which is connected to the output terminal of the transistor push-pull component; a delay protection module, including a resistor, a first diode and a capacitor, one end of the resistor being connected to the output terminal of the transistor push-pull component, the other end being connected to one end of the capacitor, the other end of the capacitor being grounded, and the two ends of the first diode being respectively connected to the two ends of the resistor; wherein, the output terminal of the logic gate component is used to output the output signal of the outer transistor, and the output terminal of the delay protection module is used to output the output signal of the inner transistor.

[0035] This invention provides a Type I three-level drive logic protection circuit for inverters. By introducing a transistor push-pull assembly and a delay protection module, the stability and reliability of the system are improved. Specifically, the logic gate assembly is an AND gate assembly. The Type I three-level drive logic protection circuit for inverters includes a transistor push-pull assembly, an AND gate assembly, and a delay protection module. The first input terminal of the AND gate assembly is connected to the input signal of the external transistor, and the second input terminal is connected to the output terminal of the transistor push-pull assembly. This means that the AND gate assembly will only output a high-level signal to control the external transistor to conduct when both input signals are high at the same time. At the same time, the transistor push-pull assembly enhances the driving capability of the internal transistor input signal and transmits it to the delay protection module. Due to the existence of the delay protection module, the output signal of the internal transistor will change only after an appropriate time delay.

[0036] It is understood that the resistor, the first diode, and the capacitor in the delay protection module together constitute an RC delay circuit. When the output signal of the transistor push-pull assembly changes, the capacitor charges or discharges through the resistor, generating a delay effect. This allows the present invention to ensure correct switching timing and avoid overvoltage damage caused by delay mismatch. In summary, the inverter type I three-level drive logic protection circuit and inverter provided in this invention can effectively protect power devices at the hardware level through the coordinated operation of AND gate components and the delay protection module, thereby ensuring stable system operation.

[0037] like Figure 2As shown, the input terminal of the transistor push-pull assembly is connected to the inner transistor input signal IN2, and the output terminal is connected to the second input terminal of the AND gate assembly, and is also connected to the delay protection module; the first input terminal of the AND gate assembly is connected to the outer transistor input signal IN1, the second input terminal is connected to the output terminal of the transistor push-pull assembly, and the output terminal is used to output the outer transistor output signal OUT1; the delay protection module includes a resistor R1, a first diode D1, and a capacitor C1. One end of the resistor R1 is connected to the output terminal of the transistor push-pull assembly, and the other end is connected to one end of the capacitor C1, with the other end of the capacitor C1 grounded. The first diode D1 is forward-biased, with its positive terminal connected to the output terminal of the transistor push-pull assembly and its negative terminal connected to the output terminal OUT2 of the delay protection module.

[0038] In some embodiments, the end of the resistor closest to the capacitor is connected to the output terminal of the delay protection module. The first diode is forward-biased, with its positive terminal connected to the output terminal of the transistor push-pull assembly and its negative terminal connected to the output terminal of the delay protection module. The external transistor input signal IN1 passes through the first input terminal of the AND gate assembly. The transistor push-pull assembly amplifies the internal transistor input signal IN2 and connects its output terminal to the second input terminal of the AND gate assembly. When both input signals are high at the same time, the output terminal OUT1 of the AND gate assembly outputs a high level, controlling the external transistor to conduct. It can be understood that the internal transistor input signal IN2 is amplified by the transistor push-pull assembly and then connected to the delay protection module. The resistor R1, capacitor C1, and first diode D1 in the delay protection module work together to produce a delay effect. When the output signal of the transistor push-pull assembly changes, capacitor C1 discharges through resistor R1, producing a delay effect.

[0039] It is worth noting that the output of the AND gate component is connected to the control terminal of the external transistor switch in the inverter's Type I three-level circuit, and the output of the delay protection module is connected to the control terminal of the internal transistor switch in the inverter's Type I three-level circuit. The external transistor input signal is used to control the external transistor's switching state, such as Q1 or Q4, and the internal transistor input signal is used to control the internal transistor's switching state, such as Q2 or Q3. The external transistor output signal is the external transistor control signal processed by the logic protection circuit and is used to actually drive the external transistor. The internal transistor output signal is the internal transistor control signal processed by the delay protection circuit and is used to actually drive the internal transistor.

[0040] In some embodiments, OUT1 is connected to the drive circuit of the outer tube to control its on or off, and OUT2 is connected to the drive circuit of the inner tube to control its on or off. A delay protection circuit is used to ensure correct timing and prevent overvoltage damage caused by drive logic errors.

[0041] In some embodiments, a transistor push-pull assembly is used to amplify signals or drive loads. It consists of a pair of complementary transistors. The push-pull circuit may include two transistors, one NPN and the other PNP. These two transistors operate in different half-cycles of the input signal. When the input signal is in the positive half-cycle, the NPN transistor is turned on, while the PNP transistor is turned off, and current flows from the power supply through the NPN transistor to the load. When the input signal is in the negative half-cycle, the situation is reversed: the PNP transistor is turned on, the NPN transistor is turned off, and current flows from the load back to the power supply through the PNP transistor. This alternating operation mechanism enables the entire circuit to provide continuous current throughout the entire signal cycle, thereby achieving effective drive of the load. In the inverter type I three-level drive logic protection circuit, the transistor push-pull assembly is mainly used to enhance the driving capability of the inner transistor input signal IN2, ensuring that even if the driving capability of the original signal is limited, the signal amplified by the push-pull assembly has sufficient strength to correctly drive subsequent logic gates and other components, thereby improving the stability and reliability of the system.

[0042] refer to Figure 3 , Figure 3 This is a schematic diagram of an inverter type I three-level drive logic protection circuit provided in an embodiment of the present invention, wherein the logic gate component is an AND gate component and the second diode is reverse-biased; in some embodiments, the delay protection module further includes a second diode, which is disposed between the output terminal of the transistor push-pull component and the resistor, and the second diode is reverse-biased, with the positive terminal connected to the resistor and the negative terminal connected to the output terminal of the transistor push-pull component.

[0043] In this configuration, one end of resistor R1 is connected to the output terminal of the push-pull transistor assembly, and the other end is connected to one end of capacitor C1. The other end of capacitor C1 is grounded. The positive terminal of the first diode D1 is connected to the output terminal of the push-pull transistor assembly, and the negative terminal is connected to the end of resistor R1 closest to the capacitor. The second diode D2 is reversed, with its positive terminal connected to resistor R1 and its negative terminal connected to the output terminal of the push-pull transistor assembly.

[0044] refer to Figure 4 , Figure 4 This is another schematic diagram of the inverter type I three-level drive logic protection circuit provided in the embodiments of the present invention, in which the logic gate component is an AND gate component and the second diode is reverse-biased; in some embodiments, the delay protection module further includes a second diode, which is disposed between the resistor and the output terminal of the delay protection module, and the second diode is reverse-biased, with its positive terminal connected to the output terminal of the delay protection module and its negative terminal connected to the resistor.

[0045] Among them, one end of resistor R1 is connected to the output terminal of the transistor push-pull assembly, and the other end is connected to one end of capacitor C1; the other end of capacitor C1 is grounded; the positive terminal of the first diode D1 is connected to the output terminal of the transistor push-pull assembly, and the negative terminal is connected to the end of resistor R1 close to the capacitor; the second diode D2 is reversed, with the positive terminal connected to the output terminal of the time delay protection module, and the negative terminal connected to resistor R1.

[0046] In some embodiments, a high-level signal is used to turn on the corresponding switch, and a low-level signal is used to turn off the corresponding switch; when the input signal of the outer tube is a high-level signal and the input signal of the inner tube is a low-level signal, both the output signal of the outer tube and the output signal of the inner tube are low-level signals; when both the input signal of the outer tube and the input signal of the inner tube change from a high-level signal to a low-level signal, the output signal of the outer tube changes from a high-level signal to a low-level signal, and the output signal of the inner tube changes from a high-level signal to a low-level signal after the capacitor discharge is completed.

[0047] It can be understood that the delay protection module forms an RC delay circuit through resistor R1, capacitor C1 and first diode D1. When the input signal changes, capacitor C1 discharges through resistor R1, generating a certain time delay, which ensures that the inner and outer tubes switch in the correct order.

[0048] A high-level signal is used to turn on the corresponding switching transistor. For example, when the external transistor output signal OUT1 is high, the external transistor will be turned on. A low-level signal is used to turn off the corresponding switching transistor. For example, when the external transistor output signal OUT1 is low, the external transistor will be turned off.

[0049] Specifically, in some embodiments, a high level is defined as on, represented by "1"; a low level is defined as off, represented by "0". Considering the time difference and uncertainty between the drive signal and the power device's on / off delay, an internal transistor turn-off delay needs to be added. For example... Figures 2 to 4 As shown, the turn-off delay protection circuit is connected between the output signal OUT2 and the second input of the AND gate to control the turn-off delay of the inner transistor. When the input signals IN1 and IN2 are 0,0; 0,1; 1,1 respectively, the output signals OUT1 and OUT2 remain 0,0; 0,1; 1,1. When the input signals IN1 and IN2 are 1 and 0 respectively, the output signals OUT1 and OUT2 become 0,0, thus realizing the logic that the inner transistor must also be turned on when the outer transistor is turned on.

[0050] The dynamic analysis of the timing of the I-type three-level topology driving logic protection is as follows: When the input signals IN1 and IN2 change from 1, 1 to 0, 0, the output signal OUT1 immediately becomes 0; due to the function of R1 and C1, the capacitor is discharged first, and the output signal OUT2 changes from 1 to 0 after a certain delay time, realizing the internal transistor turn-off delay.

[0051] refer to Figure 5 , Figure 5 This is a schematic diagram of an inverter type I three-level drive logic protection circuit provided in an embodiment of the present invention, in which the logic gate component is an OR gate component; in some embodiments, the logic gate component is an OR gate component, and the end of the resistor close to the capacitor is connected to the output terminal of the delay protection module; the first diode is reverse-biased, with its positive terminal connected to the output terminal of the delay protection module and its negative terminal connected to the output terminal of the transistor push-pull component.

[0052] refer to Figure 6 , Figure 6 This is a schematic diagram of an inverter type I three-level drive logic protection circuit provided in an embodiment of the present invention, wherein the logic gate component is an OR gate component and the second diode is forward-biased; in some embodiments, the delay protection module further includes a second diode, which is disposed between the resistor and the output terminal of the delay protection module, and the second diode is forward-biased, with its positive terminal connected to the resistor and its negative terminal connected to the output terminal of the delay protection module.

[0053] refer to Figure 7 , Figure 7 This is another schematic diagram of the inverter type I three-level drive logic protection circuit provided in the embodiment of the present invention, in which the logic gate component is an OR gate component and the second diode is forward-biased; in some embodiments, the delay protection module further includes a second diode, which is disposed between the output terminal of the transistor push-pull component and the resistor, the second diode is forward-biased, the positive terminal is connected to the output terminal of the transistor push-pull component, and the negative terminal is connected to the resistor.

[0054] Understandable Figures 5 to 7 For the above Figures 2 to 4 A reverse logic alternative can improve design flexibility. In this alternative, one end of resistor R1 is connected to the output of the delay protection module, and the other end is connected to one end of capacitor C1. The other end of capacitor C1 is grounded. The first diode D1 is reverse-biased, with its positive terminal connected to the output of the delay protection module and its negative terminal connected to the output of the transistor push-pull assembly. Figure 6 In the middle, the second diode D2 is forward-biased, with its positive terminal connected to resistor R1 and its negative terminal connected to the output of the time delay protection module. Figure 7 In the middle, the second diode D2 is forward-biased, with its positive terminal connected to the output terminal of the transistor push-pull assembly, and its negative terminal connected to the resistor R1.

[0055] In some embodiments, when the logic gate component is an OR gate component, a low-level signal is used to turn on the corresponding switch, and a high-level signal is used to turn off the corresponding switch. When the input signal of the outer transistor is a low-level signal and the input signal of the inner transistor is a high-level signal, both the output signal of the outer transistor and the output signal of the inner transistor are high-level signals. When both the input signal of the outer transistor and the input signal of the inner transistor change from low-level signals to high-level signals, the output signal of the outer transistor changes from low-level signals to high-level signals, and the output signal of the inner transistor changes from low-level signals to high-level signals after the capacitor is fully charged.

[0056] Specifically, in some embodiments, a low level is defined as "on" (represented by "0") and a high level as "off" (represented by "1"). When the input signals IN1 and IN2 are 1, 1; 1, 0; 0, 0 respectively, the output signals OUT1 and OUT2 remain 1, 1; 1, 0; 0, 0. When the input signals IN1 and IN2 are 0 and 1 respectively, the output signals OUT1 and OUT2 become 1, 1, thus implementing the logic that the inner transistor must also be turned on when the outer transistor is turned on.

[0057] The dynamic analysis of the timing of the I-type three-level topology driving logic protection is as follows: When the input signals IN1 and IN2 change from 0 and 0 to 1 and 1, the output signal OUT1 immediately becomes 1. However, due to the effect of R1 and C1, the capacitor is charged first. After a certain delay, the output signal OUT2 changes from 0 to 1, realizing the internal transistor turn-off delay.

[0058] In some embodiments, the resistance value can be in the range of 1 to 10Ω, which can provide adequate delay while minimizing energy loss and thus reducing the impact on the current of subsequent circuits. In addition, when selecting the package, it can be evaluated based on the resistor's Irms in a single cycle, and a 50% power margin should be reserved. For example, if a 1206 package (power of 0.25W) is used, the actual power consumption of the resistor should not exceed 0.125W.

[0059] In some embodiments, the capacitance can be determined by combining the resistance value and the required turn-off delay of the internal transistor. For example, if R1 = 1Ω and C1 = 100nF, the theoretical turn-off delay is approximately 100ns (calculation formula: R × C = 1Ω × 100nF = 100ns). In addition, in practical applications, the capacitance decay caused by changes in temperature, frequency, voltage, etc., must also be considered. Therefore, the final parameter values ​​need to be determined through experimental verification to find the optimal values.

[0060] In some embodiments, diodes D1 and D2 are used to drive the logic protection circuit. Their operating frequency is the same as the driving PWM frequency. Therefore, diodes D1 and D2 can be fast recovery diodes or Schottky diodes to reduce reverse recovery time and improve efficiency. The specific current of diodes D1 and D2 can be determined according to the operating frequency of the circuit and the capacitance value of capacitor C1. For example, the maximum forward current of the diode should be greater than or equal to the peak current in the circuit.

[0061] In some embodiments, the main purpose of the transistor push-pull assembly is to prevent excessive current at the IN2 signal source chip pin, which could lead to overheating or damage. This assembly is primarily responsible for handling the charging and discharging current of capacitor C1. The transistor can be selected based on the capacitance of capacitor C1 and its peak current during charging and discharging to ensure that the peak current does not exceed the maximum allowable value of the transistor. In addition, besides the traditional NPN / PNP transistor combination, switching elements such as MOSFETs or IGBTs can also be considered as alternatives to provide better performance in high-frequency or high-power applications.

[0062] Secondly, embodiments of the present invention provide an inverter, including an inverter type I three-level drive logic protection circuit according to any embodiment of the first aspect.

[0063] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A type I three-level drive logic protection circuit for an inverter, characterized in that, include: The transistor push-pull assembly has its input terminal connected to the inner transistor input signal. The logic gate assembly has a first input terminal connected to the external transistor input signal and a second input terminal connected to the output terminal of the transistor push-pull assembly. The delay protection module includes a resistor, a first diode, and a capacitor. One end of the resistor is connected to the output terminal of the transistor push-pull assembly, and the other end is connected to one end of the capacitor. The other end of the capacitor is grounded. The two ends of the first diode are respectively connected to the two ends of the resistor. Wherein, the logic gate component is an AND gate component or an OR gate component, the output terminal of the logic gate component is used to output the external transistor output signal, and the output terminal of the delay protection module is used to output the internal transistor output signal; When the logic gate component is an AND gate component, the end of the resistor closest to the capacitor is connected to the output terminal of the delay protection module, the first diode is forward-biased, the positive terminal is connected to the output terminal of the transistor push-pull component, and the negative terminal is connected to the output terminal of the delay protection module; When the logic gate component is an OR gate component, the end of the resistor closest to the capacitor is connected to the output terminal of the delay protection module; the first diode is reverse-biased, with its positive terminal connected to the output terminal of the delay protection module and its negative terminal connected to the output terminal of the transistor push-pull component.

2. The inverter type I three-level drive logic protection circuit according to claim 1, characterized in that, The delay protection module also includes a second diode, which is disposed between the output terminal of the transistor push-pull assembly and the resistor. The second diode is configured in reverse, with its positive terminal connected to the resistor and its negative terminal connected to the output terminal of the transistor push-pull assembly.

3. The inverter type I three-level drive logic protection circuit according to claim 1, characterized in that, The delay protection module further includes a second diode, which is disposed between the resistor and the output terminal of the delay protection module. The second diode is configured in reverse, with its positive terminal connected to the output terminal of the delay protection module and its negative terminal connected to the resistor.

4. The inverter type I three-level drive logic protection circuit according to claim 1, characterized in that, A high-level signal is used to turn on the corresponding switch, and a low-level signal is used to turn off the corresponding switch. When the input signal of the outer tube is high and the input signal of the inner tube is low, both the output signal of the outer tube and the output signal of the inner tube are low. When both the input signal of the outer tube and the input signal of the inner tube change from high to low, the output signal of the outer tube changes from high to low, and the output signal of the inner tube changes from high to low after the capacitor discharges.

5. The inverter type I three-level drive logic protection circuit according to claim 1, characterized in that, The delay protection module further includes a second diode, which is disposed between the resistor and the output terminal of the delay protection module. The second diode is forward-biased, with its positive terminal connected to the resistor and its negative terminal connected to the output terminal of the delay protection module.

6. The inverter type I three-level drive logic protection circuit according to claim 1, characterized in that, The delay protection module also includes a second diode, which is disposed between the output terminal of the transistor push-pull assembly and the resistor. The second diode is forward-biased, with its positive terminal connected to the output terminal of the transistor push-pull assembly and its negative terminal connected to the resistor.

7. The inverter type I three-level drive logic protection circuit according to claim 1, characterized in that, A low-level signal is used to turn on the corresponding switch, and a high-level signal is used to turn off the corresponding switch. When the input signal of the outer tube is low and the input signal of the inner tube is high, both the output signal of the outer tube and the output signal of the inner tube are high. When both the input signal of the outer tube and the input signal of the inner tube change from low to high, the output signal of the outer tube changes from low to high, and the output signal of the inner tube changes from low to high after the capacitor is fully charged.

8. An inverter, characterized in that, Includes the inverter type I three-level drive logic protection circuit as described in any one of claims 1 to 7.

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