Integrated circuit with electrostatic protection
By setting up an electrostatic protection circuit in the single-chip integrated circuit, the electrostatic overload problem caused by the uncoupled reference ground level of the pin is solved, effective protection of the power integrated circuit is achieved, and the electrostatic protection capability of the integrated circuit is improved.
Patent Information
- Application Number
- CN202411377497.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-22
- Filing Date
- 2024-09-30
- Publication Date
- 2025-06-24
AI Technical Summary
The existing single-chip integrated circuit has no reference ground level coupled to the existing single-chip integrated circuit, resulting in excessive positive or negative charges not being neutralized, causing the problem of the success rate integrated circuit being burned.
An integrated circuit with electrostatic protection is designed, by providing an electrostatic protection circuit between the source of the power integrated circuit and the reference ground level of the integrated circuit, and providing a conduction path to neutralize excess charge using elements such as diodes.
Effectively prevent power integrated circuits from being burned due to electrostatic overload, improve the electrostatic protection capability of integrated circuits, while reducing the area of integrated circuits and maintaining compatibility with existing processes.
Smart Images
Figure CN120200196A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an integrated circuit, and more particularly to an integrated circuit with electrostatic protection. Background Art
[0002] In the prior art, a pulse width modulation (PWM) integrated circuit and a power integrated circuit can be integrated into a single-chip integrated circuit by using a single-chip integration process to reduce the area of the single-chip integrated circuit. The source of the power integrated circuit is coupled to a pin of the single-chip integrated circuit, and the pin is not coupled to a reference ground level.
[0003] However, because the pin is not coupled to the reference ground level, when there is an excessive amount of positive charge or excessive negative charge on the source of the power integrated circuit, the excessive positive charge or excessive negative charge cannot be neutralized by the reference ground level, resulting in the power integrated circuit being burned out. Therefore, how to design the single-chip integrated circuit so that the single-chip integrated circuit has electrostatic protection has become an important issue. Summary of the Invention
[0004] An embodiment of the present invention provides an integrated circuit with electrostatic protection. The integrated circuit includes a pulse width modulation (PWM) integrated circuit and a power integrated circuit. The pulse width modulation integrated circuit has an electrostatic discharge (ESD) protection circuit. The electrostatic protection circuit is disposed between the source of the power integrated circuit and the reference ground level of the integrated circuit.
[0005] In an embodiment of the present invention, the pulse width modulation integrated circuit further includes a first metal oxide semiconductor field effect transistor and a gate control circuit. The drain of the first metal oxide semiconductor field effect transistor is coupled to the gate control circuit, the gate of the first metal oxide semiconductor field effect transistor is coupled to other circuits in the pulse width modulation integrated circuit, and the source of the first metal oxide semiconductor field effect transistor is coupled to the reference ground level, wherein the gate control circuit is used to generate a pulse width modulation signal for the power integrated circuit.
[0006] In an embodiment of the present invention, the power integrated circuit includes a gallium nitride (GaN) high electron mobility transistor (HEMT) and a laterally double-diffused MOSFET (LDMOS). The source of the gallium nitride high electron mobility transistor is coupled to the drain of the laterally double-diffused MOSFET, the gate of the gallium nitride high electron mobility transistor is coupled to the source of the laterally double-diffused MOSFET, and the gate of the laterally double-diffused MOSFET is coupled to the gate control circuit. The source of the laterally double-diffused MOSFET is further coupled to the electrostatic protection circuit.
[0007] In an embodiment of the present invention, the power integrated circuit includes a transistor, wherein the source of the transistor is coupled to the electrostatic protection circuit, and the gate of the transistor is coupled to the gate control circuit.
[0008] In an embodiment of the present invention, the transistor is a gallium nitride high electron mobility transistor.
[0009] In an embodiment of the present invention, the transistor is a second MOSFET or a silicon carbide (SiC) FET.
[0010] In an embodiment of the present invention, the source of the power integrated circuit is coupled to a pin of the integrated circuit.
[0011] In an embodiment of the present invention, the electrostatic protection circuit includes a first diode, a second diode, a third diode, and a fourth diode. The first end of the first diode is coupled to the reference ground level. The first end of the second diode is coupled to the second end of the first diode, and the second end of the second diode is coupled to the source of the power integrated circuit. The first end of the third diode is coupled to the source of the power integrated circuit. The first end of the fourth diode is coupled to the second end of the third diode, and the second end of the fourth diode is coupled to the reference ground level.
[0012] In an embodiment of the present invention, the electrostatic protection circuit includes a fifth diode and a sixth diode. The first end of the fifth diode is coupled to the reference ground level. The second end of the sixth diode is coupled to the second end of the fifth diode, and the first end of the sixth diode is coupled to the source of the power integrated circuit.
[0013] In an embodiment of the present invention, the integrated circuit further includes a high-voltage start-up integrated circuit, wherein the high-voltage start-up integrated circuit generates a supply voltage according to a DC voltage to operate the pulse-width modulation integrated circuit.
[0014] An embodiment of the present invention provides an integrated circuit with electrostatic protection. The integrated circuit includes a high-voltage start-up integrated circuit and a power integrated circuit. The high-voltage start-up integrated circuit has an electrostatic protection circuit. The electrostatic protection circuit is disposed between the source of the power integrated circuit and the reference ground level of the integrated circuit.
[0015] In an embodiment of the present invention, the integrated circuit further includes a pulse-width modulation integrated circuit, wherein the high-voltage start-up integrated circuit generates a supply voltage according to a DC voltage to operate the pulse-width modulation integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a schematic diagram of an integrated circuit with electrostatic protection disclosed in the first embodiment of the present invention.
[0017] Figure 2A is a schematic diagram of the electrostatic protection circuit disclosed in the second embodiment of the present invention.
[0018] Figure 2B is a schematic diagram of the electrostatic protection circuit disclosed in the third embodiment of the present invention.
[0019] Figure 2C is a schematic diagram of the electrostatic protection circuit disclosed in the fourth embodiment of the present invention.
[0020] Figure 3 is a schematic diagram of the power integrated circuit disclosed in the third embodiment of the present invention.
[0021] Figure 4 is a schematic diagram of an integrated circuit with electrostatic protection disclosed in the fourth embodiment of the present invention.
[0022] Among them, the reference numerals are explained as follows:
[0023] 100, 400 Integrated circuit
[0024] 101, GND Pin
[0025] 102, 402 Pulse-width modulation integrated circuit
[0026] 104, 304 Power integrated circuit
[0027] 106, 406 High-voltage start-up integrated circuit
[0028] 1022, 2022, 3022, 4022, 4062 electrostatic protection circuits
[0029] 1024 First metal oxide semiconductor field effect transistor
[0030] 1026 Gate control circuit
[0031] 1042, 3042 Gallium nitride high electron mobility transistors
[0032] 1044 Lateral double-diffused metal oxide semiconductor field effect transistor
[0033] 10222 First diode
[0034] 10224 Second diode
[0035] 10226 Third diode
[0036] 10228 Fourth diode
[0037] 20222 Fifth diode
[0038] 20224 Sixth diode
[0039] 30222 Seventh diode
[0040] 30224 Eighth diode
[0041] GCS Pulse width modulation signal
[0042] VCC Supply voltage Detailed implementation manners
[0043] Please refer to Figure 1 , Figure 1 is a schematic diagram of an integrated circuit 100 with electrostatic protection disclosed in the first embodiment of the present invention. The integrated circuit 100 with electrostatic protection includes a pulse width modulation (PWM) integrated circuit 102, a power integrated circuit 104, and a high-voltage start-up integrated circuit 106. In an embodiment of the present invention, the integrated circuit 100 is applied to the primary side of a flyback power converter, and the high-voltage start-up integrated circuit 106 can generate a supply voltage VCC for the pulse width modulation integrated circuit 102 according to a DC voltage on the primary side of the flyback power converter to enable the operation of the pulse width modulation integrated circuit 102. The high-voltage start-up integrated circuit 106 can adopt the architecture of the start-up circuit disclosed in the prior art, so it will not be elaborated here. As Figure 1As shown, the pulse width modulation integrated circuit 102 includes an electrostatic discharge (ESD) protection circuit 1022, a first metal oxide semiconductor field effect transistor 1024, and a gate control circuit 1026. The pulse width modulation integrated circuit 102 is not limited to only including the electrostatic protection circuit 1022, the first metal oxide semiconductor field effect transistor 1024, and the gate control circuit 1026. That is to say, the pulse width modulation integrated circuit 102 also includes some functional circuits (not shown in Figure 1 ), but these functional circuits are not the focus of the invention of this case, so they will not be elaborated here. In the pulse width modulation integrated circuit 102, the drain of the first metal oxide semiconductor field effect transistor 1024 is coupled to the gate control circuit 1026, the gate of the first metal oxide semiconductor field effect transistor 1024 is coupled to other circuits within the pulse width modulation integrated circuit 102 (not shown in Figure 1 ), and the source of the first metal oxide semiconductor field effect transistor 1024 is coupled to the pin GND of the integrated circuit 100. There is a seal ring (not shown in Figure 1 ) surrounding the integrated circuit 100. The seal ring is coupled to the pin GND, and there is a reference ground level on the pin GND. When the foundry manufactures multiple chips (each chip contains an integrated circuit 100) on the wafer, the seal ring is used to prevent cracks generated by the stress of the cutting saw blade from damaging the chips beside the cracks when cutting the multiple chips on the wafer. And the seal ring needs to be connected to the pin GND to prevent electrostatic damage to the multiple chips during the process of cutting the multiple chips on the wafer.
[0044] In addition, as Figure 1As shown, the power integrated circuit 104 includes a gallium nitride (GaN) high electron mobility transistor (HEMT) 1042 and a laterally double-diffused MOSFET (LDMOS) 1044. The drain of the gallium nitride high electron mobility transistor 1042 is coupled to the primary side of the flyback power converter. The source of the gallium nitride high electron mobility transistor 1042 is coupled to the drain of the laterally double-diffused MOSFET 1044. The gate of the gallium nitride high electron mobility transistor 1042 is coupled to the source of the laterally double-diffused MOSFET 1044. The gate of the laterally double-diffused MOSFET 1044 is coupled to the gate control circuit 1026, and the source of the laterally double-diffused MOSFET 1044 is further coupled to the electrostatic protection circuit 1022. The gate control circuit 1026 is configured to generate a pulse width modulation signal (i.e., the gate control signal) GCS for the laterally double-diffused MOSFET 1044, and the laterally double-diffused MOSFET 1044 will turn on according to the pulse width modulation signal GCS.
[0045] In addition, the function of the power integrated circuit 104 is similar to that of the power switch applied to the primary side of the flyback power converter disclosed in the prior art, so it will not be elaborated here. In addition, as Figure 1 shown, the source of the power integrated circuit 104 (i.e., the source of the laterally double-diffused MOSFET 1044) is coupled to a pin 101 of the integrated circuit 100. In another embodiment of the present invention, the laterally double-diffused MOSFET 1044 can be replaced by a vertical double-diffused MOSFET (VDMOS), or a silicon carbide (SiC) field effect transistor, or a super junction MOSFET.
[0046] In addition, as Figure 1 shown, the electrostatic protection circuit 1022 is disposed between the source of the power integrated circuit 104 and the pin GND. As Figure 1As shown, the electrostatic protection circuit 1022 includes a first diode 10222, a second diode 10224, a third diode 10226, and a fourth diode 10228. The first end of the first diode 10222 is coupled to the pin GND. The first end of the second diode 10224 is coupled to the second end of the first diode 10222. The second end of the second diode 10224 is coupled to the source of the laterally diffused metal oxide semiconductor field effect transistor 1044. The first end of the third diode 10226 is coupled to the source of the laterally diffused metal oxide semiconductor field effect transistor 1044. The first end of the fourth diode 10228 is coupled to the second end of the third diode 10226. And the second end of the fourth diode 10228 is coupled to the pin GND.
[0047] Therefore, as Figure 1 shown, since the electrostatic protection circuit 1022 is disposed between the source of the power integrated circuit 104 and the pin GND, and the electrostatic protection circuit 1022 includes two conduction paths with opposite conduction directions (one of the two conduction paths is composed of the first diode 10222 and the second diode 10224, and the other conduction path of the two conduction paths is composed of the third diode 10226 and the fourth diode 10228), when there is an excessive amount of positive charge or an excessive amount of negative charge on the source of the power integrated circuit 104 (that is, the source of the laterally diffused metal oxide semiconductor field effect transistor 1044), the excessive positive charge or the excessive negative charge can be neutralized by the electrostatic protection circuit 1022 to the reference ground level, thereby preventing the power integrated circuit 104 from being burned out.
[0048] In addition, the integrated circuit 100 is not limited to only including the pin GND and the pin 101, and only including the pulse width modulation integrated circuit 102, the power integrated circuit 104, and the high voltage startup integrated circuit 106. That is to say, the integrated circuit 100 can include pins other than the pin GND and the pin 101, and can also include functional circuits other than the pulse width modulation integrated circuit 102, the power integrated circuit 104, and the high voltage startup integrated circuit 106.
[0049] Next, please refer to Figure 2A , Figure 2A which is a schematic diagram of an electrostatic protection circuit 2022 disclosed in the second embodiment of the present invention, where the function of the electrostatic protection circuit 2022 is the same as that of Figure 1 the electrostatic protection circuit 1022 shown. As Figure 2AAs shown, the electrostatic protection circuit 2022 includes a fifth diode 20222 and a sixth diode 20224. The first end of the fifth diode 20222 is coupled to the pin GND. The second end of the sixth diode 20224 is coupled to the second end of the fifth diode 20222, and the first end of the sixth diode 20224 is coupled to the source of the power integrated circuit 104 (i.e., the source of the laterally diffused metal oxide semiconductor field effect transistor 1044). Similarly, as Figure 2A shown, since the electrostatic protection circuit 2022 is disposed between the source of the power integrated circuit 104 and the pin GND, and the fifth diode 20222 and the sixth diode 20224 also respectively provide two conduction paths with opposite conduction directions, when there is an excessive amount of positive charge or an excessive amount of negative charge on the source of the power integrated circuit 104 (i.e., the source of the laterally diffused metal oxide semiconductor field effect transistor 1044), the excessive positive charge or the excessive negative charge can be neutralized by the electrostatic protection circuit 2022 to the reference ground level, thereby preventing the integrated circuit 100 from being burned out.
[0050] Next, please refer to Figure 2B , Figure 2B is a schematic diagram of an electrostatic protection circuit 3022 disclosed in the third embodiment of the present invention. The function of the electrostatic protection circuit 3022 is the same as that of the Figure 1 shown electrostatic protection circuit 1022. As Figure 2B shown, the electrostatic protection circuit 3022 includes a seventh diode 30222 and an eighth diode 30224. The first end of the seventh diode 30222 is coupled to the pin GND and the second end of the seventh diode 30222 is coupled to the source of the power integrated circuit 104 (i.e., the source of the laterally diffused metal oxide semiconductor field effect transistor 1044), and the first end of the eighth diode 30224 is coupled to the source of the power integrated circuit 104 and the second end of the eighth diode 30224 is coupled to the pin GND. Similarly, as Figure 2B shown, since the electrostatic protection circuit 3022 is disposed between the source of the power integrated circuit 104 and the pin GND, and the seventh diode 30222 and the eighth diode 30224 also respectively provide two conduction paths with opposite conduction directions, when there is an excessive amount of positive charge or an excessive amount of negative charge on the source of the power integrated circuit 104 (i.e., the source of the laterally diffused metal oxide semiconductor field effect transistor 1044), the excessive positive charge or the excessive negative charge can be neutralized by the electrostatic protection circuit 3022 to the reference ground level, thereby preventing the integrated circuit 100 from being burned out.
[0051] Next, please refer to Figure 2C , Figure 2CIt is a schematic diagram of an electrostatic protection circuit 4022 (which is a diode) disclosed in the fourth embodiment of the present invention. The function of the electrostatic protection circuit 4022 is the same as that of Figure 1 the electrostatic protection circuit 1022 shown. As Figure 2C shown, the first end of the electrostatic protection circuit 4022 is coupled to the source of the power integrated circuit 104 (i.e., the source of the lateral double-diffused metal-oxide-semiconductor field-effect transistor 1044), and the second end of the electrostatic protection circuit 4022 is coupled to the pin GND. Similarly, as Figure 2C shown, since the electrostatic protection circuit 4022 is disposed between the source of the power integrated circuit 104 and the pin GND, and the electrostatic protection circuit 4022 provides a conduction path, when there is an excessive amount of positive charge on the source of the power integrated circuit 104 (i.e., the source of the lateral double-diffused metal-oxide-semiconductor field-effect transistor 1044), the excessive positive charge can be neutralized by the electrostatic protection circuit 4022 to the reference ground level, thereby preventing the integrated circuit 100 from being burned out.
[0052] Next, please refer to Figure 3 , Figure 3 which is a schematic diagram of a power integrated circuit 304 disclosed in the third embodiment of the present invention. The function of the power integrated circuit 304 is the same as that of Figure 1 the power integrated circuit 104 shown. As Figure 3 shown, the power integrated circuit 304 includes a gallium nitride high electron mobility transistor 3042. The source of the gallium nitride high electron mobility transistor 3042 is coupled to the electrostatic protection circuit 1022 and the pin 101, and the gate of the gallium nitride high electron mobility transistor 3042 is coupled to the gate control circuit 1026. Since the electrostatic protection circuit 1022 is disposed between the source of the power integrated circuit 304 (i.e., the source of the gallium nitride high electron mobility transistor 3042) and the pin GND, and the electrostatic protection circuit 1022 includes two conduction paths with opposite conduction directions, when there is an excessive amount of positive charge or an excessive amount of negative charge on the source of the power integrated circuit 304 (i.e., the source of the gallium nitride high electron mobility transistor 3042), the excessive positive charge or the excessive negative charge can be neutralized by the electrostatic protection circuit 1022 to the reference ground level, thereby preventing the power integrated circuit 304 from being burned out. Additionally, in another embodiment of the present invention, the electrostatic protection circuit 2022 replaces the electrostatic protection circuit 1022 and is disposed between the source of the power integrated circuit 304 (i.e., the source of the gallium nitride high electron mobility transistor 3042) and the pin GND. Additionally, in another embodiment of the present invention, the gallium nitride high electron mobility transistor 3042 can be replaced by a metal-oxide-semiconductor field-effect transistor or a silicon carbide (SiC) field-effect transistor.
[0053] Next, please refer to Figure 4 , Figure 4 which is a schematic diagram of an integrated circuit 400 with electrostatic protection disclosed in the fourth embodiment of the present invention. The integrated circuit 400 with electrostatic protection includes a pulse width modulation integrated circuit 402, a power integrated circuit 104, and a high-voltage startup integrated circuit 406. As Figure 4 shown, the difference between the integrated circuit 400 and the integrated circuit 100 is that the electrostatic protection circuit 4062 is included in the high-voltage startup integrated circuit 406. The architecture of the electrostatic protection circuit 4062 can refer to the electrostatic protection circuits 1022 and 2022, so it will not be elaborated here. In addition, the architecture of the pulse width modulation integrated circuit 402 can also refer to the architecture of the pulse width modulation integrated circuit 102, and the architecture of the power integrated circuit 104 in the integrated circuit 400 can also refer to the architecture of the power integrated circuit 104 in Figure 1 , so it will not be elaborated here either. In addition, the operating principle of the integrated circuit 400 can refer to the operating principle of the above-mentioned integrated circuit 100, so it will not be elaborated here.
[0054] In summary, compared with the prior art, the present invention can improve the electrostatic protection ability of the integrated circuit, can implement the integrated circuit through a single-chip integration process and reduce the area of the integrated circuit, can make the integrated circuit compatible with the current process without additional cost, and can easily detect infringement by whether there is an additional wire connection from the pulse width modulation integrated circuit to the power integrated circuit in the integrated circuit.
[0055] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. An integrated circuit with electrostatic protection, characterized in that Include: A pulse width modulation integrated circuit having an electrostatic protection circuit; and A power integrated circuit, wherein the electrostatic protection circuit is arranged between the source of the power integrated circuit and the reference ground level of the integrated circuit.
2. The integrated circuit according to claim 1, characterized in that The pulse width modulation integrated circuit further comprises: a first metal oxide semiconductor field effect transistor; and a gate control circuit, wherein the drain of the first metal oxide semiconductor field effect transistor is coupled to the gate control circuit, the gate of the first metal oxide semiconductor field effect transistor is coupled to other circuits in the pulse width modulation integrated circuit, and the source of the first metal oxide semiconductor field effect transistor is coupled to the reference ground level, wherein the gate control circuit is used to generate a pulse width modulation signal for the power integrated circuit.
3. The integrated circuit as claimed in claim 2, characterized in that The power integrated circuit comprises: A gallium nitride high electron mobility transistor; and a lateral double diffused metal oxide semiconductor field effect transistor, wherein the source of the GaN high electron mobility transistor is coupled to the drain of the lateral double diffused metal oxide semiconductor field effect transistor, the gate of the GaN high electron mobility transistor is coupled to the source of the lateral double diffused metal oxide semiconductor field effect transistor, and the gate of the lateral double diffused metal oxide semiconductor field effect transistor is coupled to the gate control circuit; The source of the lateral double diffused metal oxide semiconductor field effect transistor is further coupled to the electrostatic protection circuit.
4. The integrated circuit as claimed in claim 2, characterized in that The power integrated circuit comprises: A transistor, wherein a source of the transistor is coupled to the electrostatic protection circuit, and a gate of the transistor is coupled to the gate control circuit.
5. The integrated circuit as claimed in claim 4, characterized in that The transistor is a gallium nitride high electron mobility transistor.
6. The integrated circuit as claimed in claim 4, characterized in that The transistor is a second metal oxide semiconductor field effect transistor or a silicon carbide field effect transistor.
7. The integrated circuit as claimed in claim 1, characterized in that The source of the power integrated circuit is coupled to a pin of the integrated circuit.
8. The integrated circuit as claimed in claim 1, characterized in that The electrostatic protection circuit comprises: a first diode, wherein a first end of the first diode is coupled to the reference ground level; a second diode, wherein a first end of the second diode is coupled to a second end of the first diode, and a second end of the second diode is coupled to a source of the power integrated circuit; a third diode, wherein a first end of the third diode is coupled to the source of the power integrated circuit; and a fourth diode, wherein a first end of the fourth diode is coupled to the second end of the third diode, and a second end of the fourth diode is coupled to the reference ground level.
9. The integrated circuit as claimed in claim 1, characterized in that The electrostatic protection circuit comprises: a fifth diode, wherein a first end of the fifth diode is coupled to the reference ground level; and a sixth diode, wherein a second end of the sixth diode is coupled to the second end of the fifth diode, and a first end of the sixth diode is coupled to the source of the power integrated circuit.
10. The integrated circuit as claimed in claim 1, characterized in that Also includes: A high voltage startup integrated circuit is used to generate a supply voltage to the pulse width modulation integrated circuit according to a DC voltage so as to enable the pulse width modulation integrated circuit to operate.
11. An integrated circuit with electrostatic protection, characterized in that Include: A high voltage startup integrated circuit having an electrostatic protection circuit; and A power integrated circuit, wherein the electrostatic protection circuit is arranged between the source of the power integrated circuit and the reference ground level of the integrated circuit.
12. The integrated circuit according to claim 11, characterized in that Also includes: A pulse width modulation integrated circuit, wherein the high voltage startup integrated circuit is based on a DC voltage, A supply voltage is generated for the pulse width modulation integrated circuit to enable the pulse width modulation integrated circuit to operate.