Level shifter, power conversion device and power conversion chip

Abstract

The invention relates to the technical field of electronics, and provides a level shifter, a power conversion device and a power conversion chip. The level shifter comprises an adjusting module and a logic module which are electrically connected, the logic module is electrically connected with a low-side power tube, and the low-side power tube is electrically connected with a high-side power tube; the adjusting module is used for outputting a first signal to the logic module when the high-side power tube is in a conducting state; the logic module is used for driving the low-side power tube to be in a turn-off state when receiving the first signal; the adjusting module is also used for outputting a second signal to the logic module when the high-side power tube is in a turn-off state; the logic module is also used for driving the low-side power tube to be in a conducting state when receiving the second signal; and the adjusting module is also used for lowering the voltage of the connection node of the adjusting module and the logic module when the high-side power tube is in the conduction state, so as to shorten the duration of switching the low-side power tube from the turn-off state to the conduction state, thereby reducing the dead time and reducing the power consumption.

Description

Technical Field

[0001] The present invention relates to the field of electronic technologies, and more particularly, to a level shifter, a power conversion device, and a power conversion chip. Background Art

[0002] In order to improve the efficiency of a DC-DC power conversion chip, the optimization of the dead time has always been a key point. The dead time refers to the time when the high-side and low-side power transistors are both in the off state to avoid short circuits. Currently, a fixed dead time is usually adopted, and in order to ensure that the high-side and low-side power transistors do not experience punch-through in various application scenarios, the dead time is set relatively long, which results in low power conversion efficiency of the power supply. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide a level shifter, a power conversion device, and a power conversion chip, which can reduce the dead time and power consumption.

[0004] To achieve the above object, the technical solutions adopted in the embodiments of the present invention are as follows:

[0005] In a first aspect, the present invention provides a level shifter for converting between a first voltage domain and a second voltage domain. The level shifter includes an adjustment module and a logic module connected electrically. The first end of the adjustment module is electrically connected to the power supply voltage of the first voltage domain, the second end is electrically connected to the power supply voltage of the second voltage domain, the third end is electrically connected to the ground voltage of the second voltage domain, the first end of the logic module is electrically connected to the power supply voltage of the second voltage domain, the second end is electrically connected to the ground voltage of the second voltage domain, and the output end is electrically connected to a low-side power transistor, and the low-side power transistor is electrically connected to a high-side power transistor;

[0006] The adjustment module is configured to output a first signal to the logic module when the high-side power transistor is in the on state;

[0007] The logic module is configured to drive the low-side power transistor to be in the off state when receiving the first signal;

[0008] The adjustment module is further configured to output a second signal to the logic module when the high-side power transistor is in the off state;

[0009] The logic module is further configured to drive the low-side power transistor to be in the on state when receiving the second signal;

[0010] The adjustment module is further configured to pull down the voltage of the connection node between the adjustment module and the logic module when the high-side power transistor is in the on state, so as to shorten the duration of the low-side power transistor switching from the off state to the on state, and reduce the dead time between the high-side power transistor and the low-side power transistor.

[0011] In an alternative embodiment, the adjustment module includes a first switching transistor, a capacitor, a zener diode, and a first resistor;

[0012] The control terminal of the first switching transistor is configured to receive the inverted signal of the high-side driving signal, the high-side driving signal is used to drive the high-side power transistor to turn on or off, the first terminal of the first switching transistor is electrically connected to the power supply voltage of the first voltage domain, and the second terminal of the first switching transistor is electrically connected to a first node;

[0013] One end of the capacitor is electrically connected to the first terminal of the first switching transistor, and the other end of the capacitor is electrically connected to the first node;

[0014] The cathode of the zener diode is electrically connected to the first node, and the anode of the zener diode is electrically connected to the ground voltage of the second voltage domain;

[0015] One end of the resistor is electrically connected to the first node, and the other end of the first resistor is electrically connected to the ground voltage of the second voltage domain;

[0016] The logic module is electrically connected to the first node;

[0017] The first switching transistor turns on when the high-side power transistor is in the on state to charge the first node; the first switching transistor turns off when the high-side power transistor is in the off state to discharge the first node.

[0018] In an alternative embodiment, the logic module is an inverter, the input terminal of the inverter is electrically connected to the first node, the output terminal of the inverter is configured to output a low-side driving signal, the low-side driving signal is used to drive the low-side power transistor to turn on or off, the first enable terminal of the inverter is electrically connected to the power supply voltage of the second voltage domain, and the second enable terminal of the inverter is electrically connected to the ground voltage of the second voltage domain.

[0019] In an alternative embodiment, the adjustment module includes a first switching transistor, a second switching transistor, a first resistor, and an amplification unit;

[0020] The control terminal of the first switching transistor is configured to receive the inverted signal of the high-side driving signal, the high-side driving signal is used to drive the high-side power transistor to turn on or off, the first terminal of the first switching transistor is electrically connected to the power supply voltage of the first voltage domain, and the second terminal of the first switching transistor is electrically connected to a first node;

[0021] The control terminal of the second switching transistor is electrically connected to a reference power supply for providing a reference voltage. The first terminal of the second switching transistor is electrically connected to the first node, and the second terminal of the second switching transistor is electrically connected to the ground voltage of the second voltage domain;

[0022] One end of the resistor is electrically connected to the first node, and the other end of the first resistor is electrically connected to the ground voltage of the second voltage domain;

[0023] The first terminal of the amplifying unit is electrically connected to the first node, the second terminal of the amplifying unit is electrically connected to the power supply voltage of the second voltage domain, the third terminal of the amplifying unit is electrically connected to the logic module, and the fourth terminal of the amplifying unit is electrically connected to the ground voltage of the second voltage domain;

[0024] The first switching transistor conducts when the high-side power transistor is in the on state to charge the first node; the first switching transistor turns off when the high-side power transistor is in the off state to discharge the first node;

[0025] The second switching transistor conducts when the first switching transistor is in the on state, and when the voltage of the first node is higher than a preset voltage threshold, controls the amplifying unit to be in the working state;

[0026] The second switching transistor turns off when the first switching transistor is in the off state, and when the voltage of the first node is equal to or lower than the preset voltage threshold, controls the amplifying unit to be in the non-working state.

[0027] In an alternative embodiment, the adjusting module includes a first switching transistor, a second switching transistor, a capacitor, a first resistor, and an amplifying unit;

[0028] The control terminal of the first switching transistor is configured to receive an inverted signal of a high-side driving signal for driving the high-side power transistor to conduct or turn off. The first terminal of the first switching transistor is electrically connected to the power supply voltage of the first voltage domain, and the second terminal of the first switching transistor is electrically connected to the first node;

[0029] One end of the capacitor is electrically connected to the first terminal of the first switching transistor, and the other end of the capacitor is electrically connected to the first node;

[0030] The control terminal of the second switching transistor is electrically connected to a reference power supply for providing a reference voltage. The first terminal of the second switching transistor is electrically connected to the first node, and the second terminal of the second switching transistor is electrically connected to the ground voltage of the second voltage domain;

[0031] One end of the resistor is electrically connected to the first node, and the other end of the first resistor is electrically connected to the ground voltage of the second voltage domain;

[0032] The first end of the amplification unit is electrically connected to the first node, the second end of the amplification unit is electrically connected to the power supply voltage of the second voltage domain, the third end of the amplification unit is electrically connected to the logic module, and the fourth end of the amplification unit is electrically connected to the ground voltage of the second voltage domain;

[0033] The first switching transistor conducts when the high-side power transistor is in the on state to charge the first node; the first switching transistor turns off when the high-side power transistor is in the off state to discharge the first node;

[0034] The second switching transistor conducts when the first switching transistor is in the on state, and when the voltage of the first node is higher than a preset voltage threshold, controls the amplification unit to be in the working state;

[0035] The second switching transistor turns off when the first switching transistor is in the off state, and when the voltage of the first node is equal to or lower than the preset voltage threshold, controls the amplification unit to be in the non-working state.

[0036] In an alternative embodiment, the amplification unit includes a third switching transistor and a second resistor;

[0037] The control terminal of the third switching transistor is electrically connected to the first node, the first end of the third switching transistor is electrically connected to the second node, and the second end of the third switching transistor is electrically connected to the ground voltage of the second voltage domain;

[0038] One end of the second resistor is electrically connected to the power supply voltage of the second voltage domain, and the other end of the second resistor is electrically connected to the second node;

[0039] The logic module is electrically connected to the second node;

[0040] The third switching transistor is in the amplification state when the voltage of the first node is higher than the preset voltage threshold;

[0041] The third switching transistor is in the cut-off state when the voltage of the first node is equal to or lower than the preset voltage threshold.

[0042] In an alternative embodiment, the logic module is a latch, the R terminal of the latch is electrically connected to the second node, the S terminal of the latch is used to receive a control signal, the output terminal of the latch is used to output a low-side drive signal, the low-side drive signal is used to drive the low-side power transistor to conduct or turn off, the first enable terminal of the latch is electrically connected to the power supply voltage of the second voltage domain, the second enable terminal of the latch is electrically connected to the ground voltage of the second voltage domain, the third enable terminal of the latch is electrically connected to the power supply voltage of the second voltage domain, and the fourth enable terminal of the latch is electrically connected to the ground voltage of the second voltage domain.

[0043] In an alternative embodiment, when the high-side power transistor is in the on state, the voltage of the first node satisfies the following relationship:

[0044] V A = V REF + V M2 ;

[0045] wherein, V A represents the voltage of the first node, V REF represents the reference voltage, and V M2 represents the voltage between the control terminal and the first terminal of the second switching transistor.

[0046] In a second aspect, the present invention provides a power conversion device, which includes a high-side power transistor, a high-side driver, a low-side power transistor, a low-side driver, and the level shifter described in any one of the foregoing embodiments. The input terminal of the high-side driver is used to receive a high-side driving signal, and the output terminal is electrically connected to the control terminal of the high-side power transistor. The first terminal of the high-side power transistor is electrically connected to a power supply, and the second terminal is electrically connected to the first terminal of the low-side power transistor. The input terminal of the level shifter is used to receive the inverted signal of the high-side driving signal, and the output terminal is electrically connected to the input terminal of the low-side driver. The output terminal of the low-side driver is electrically connected to the control terminal of the low-side power transistor, and the second terminal of the low-side power transistor is grounded.

[0047] In a third aspect, the present invention provides a power conversion chip, which includes the power conversion device described in the foregoing embodiment.

[0048] The level shifter, power conversion device, and power conversion chip provided by the embodiments of the present invention. The level shifter includes an adjustment module and a logic module that are electrically connected. The first terminal of the adjustment module is electrically connected to the power supply voltage of the first voltage domain, the second terminal is electrically connected to the power supply voltage of the second voltage domain, and the third terminal is electrically connected to the ground voltage of the second voltage domain. The first terminal of the logic module is electrically connected to the power supply voltage of the second voltage domain, the second terminal is electrically connected to the ground voltage of the second voltage domain, and the output terminal is electrically connected to the low-side power transistor. The low-side power transistor is electrically connected to the high-side power transistor. The adjustment module is configured to output a first signal to the logic module when the high-side power transistor is in the on state. The logic module is configured to drive the low-side power transistor to be in the off state when receiving the first signal. The adjustment module is further configured to output a second signal to the logic module when the high-side power transistor is in the off state. The logic module is further configured to drive the low-side power transistor to be in the on state when receiving the second signal. The adjustment module is further configured to pull down the voltage of the connection node between the adjustment module and the logic module when the high-side power transistor is in the on state, so as to shorten the duration of the low-side power transistor switching from the off state to the on state, reduce the dead time, and reduce the power consumption.

[0049] To make the above objects, features, and advantages of the present invention more apparent and understandable, the following provides preferred embodiments in conjunction with the accompanying drawings and describes them in detail as follows. Description of the Drawings

[0050] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can be obtained based on these drawings.

[0051] Figure 1 Figure 1 shows one of the structural schematic diagrams of the level shifter provided by the embodiments of the present invention;

[0052] Figure 2 Figure 2 shows another structural schematic diagram of the level shifter provided by the embodiments of the present invention;

[0053] Figure 3 Figure 3 shows a third structural schematic diagram of the level shifter provided by the embodiments of the present invention;

[0054] Figure 4 Figure 4 shows a fourth structural schematic diagram of the level shifter provided by the embodiments of the present invention;

[0055] Figure 5 Figure 5 shows a schematic diagram of the working waveform of the level shifter provided by the embodiments of the present invention;

[0056] Figure 6 Figure 6 shows a structural schematic diagram of the power conversion device provided by the embodiments of the present invention.

[0057] Reference Signs: M1 - First switching transistor; M2 - Second switching transistor; M3 - Third switching transistor; C - Capacitor; Z - Zener diode; R1 - First resistor; R2 - Second resistor; INV - Inverter. Detailed Embodiments

[0058] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Usually, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0060] It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0061] In order to improve the efficiency of the DC-DC power conversion chip, the optimization of the dead time has always been a key point. The dead time refers to the time when the high-side and low-side power transistors are both turned off to avoid short circuits. Currently, a fixed dead time is usually adopted, and in order to ensure that the high-side and low-side power transistors do not conduct through in various application scenarios, the dead time is set relatively long, which results in low power conversion efficiency of the power supply.

[0062] Although there is also a way to adaptively adjust the dead time using the drive signals of the high-side and low-side power transistors, this way will cause the dead time to include the time of the drive signals in the transmission loop. If the dead time is to be made very small, a very fast transmission loop speed is required, which will increase the power consumption. Another way is to determine the dead time of the current cycle by detecting the dead time of the previous cycle, but the circuit of this way is complex and it is also impossible to ensure accurate prediction of the dead time of the current cycle in various application scenarios. Therefore, the embodiments of the present invention provide a level shifter to reduce the dead time and lower the power consumption.

[0063] Please refer to Figure 1 , which is a schematic structural diagram of a level shifter provided by the embodiments of the present invention. The level shifter is used for conversion between a first voltage domain (BOOT-SW) and a second voltage domain (VCC-VSS). And the level shifter includes an adjustment module and a logic module that are electrically connected.

[0064] The first terminal T1 of the adjustment module is electrically connected to the power supply voltage BOOT of the first voltage domain, the second terminal T2 is electrically connected to the power supply voltage VCC of the second voltage domain, and the third terminal T3 is electrically connected to the ground voltage VSS of the second voltage domain. The first terminal L1 of the logic module is electrically connected to the power supply voltage VCC of the second voltage domain, the second terminal L2 is electrically connected to the ground voltage VSS of the second voltage domain, and the output terminal Lout is electrically connected to the low-side power transistor, and the low-side power transistor is electrically connected to the high-side power transistor.

[0065] The regulation module is used to output a first signal to the logic module when the high-side power transistor is in the on state; the logic module is used to drive the low-side power transistor to be in the off state when receiving the first signal. The regulation module is also used to output a second signal to the logic module when the high-side power transistor is in the off state; the logic module is also used to drive the low-side power transistor to be in the on state when receiving the second signal.

[0066] The regulation module is further used to pull down the voltage of the connection node between the regulation module and the logic module when the high-side power transistor is in the on state, so as to shorten the duration for the low-side power transistor to switch from the off state to the on state and reduce the dead time between the high-side power transistor and the low-side power transistor.

[0067] It can be understood that the regulation module transmits different signals to the logic module according to the state of the high-side power transistor, so that the logic module controls the state of the low-side power transistor according to the received signals. Then, by pulling down the voltage of the connection node between the regulation module and the logic module, the time for the regulation module to switch from outputting the first signal to outputting the second signal can be shortened when the high-side power transistor switches from the on state to the off state. In this way, the duration for the low-side power transistor to switch from the off state to the on state is shortened, thereby reducing the dead time between the high-side power transistor and the low-side power transistor and improving the conversion efficiency. And because the voltage of the connection node between the regulation module and the logic module is pulled down, the current in the level shifter becomes smaller, thus reducing the power consumption of the level shifter.

[0068] Please refer to Figure 2 , which is another structural schematic diagram of the level shifter provided by the embodiment of the present invention. The regulation module of the level shifter includes a first switching transistor M1, a capacitor C, a zener diode Z, and a first resistor R1. Wherein the first switching transistor M1 can be a MOS transistor.

[0069] The control end of the first switching transistor M1 is used to receive the inverted signal ONHz of the high-side driving signal. The high-side driving signal ONH is used to drive the high-side power transistor to conduct or turn off. The first end of the first switching transistor M1 is electrically connected to the power supply voltage BOOT of the first voltage domain, and the second end of the first switching transistor M1 is electrically connected to the first node A. One end of the capacitor C is electrically connected to the first end of the first switching transistor M1, and the other end of the capacitor C is electrically connected to the first node A.

[0070] The cathode of the zener diode Z is electrically connected to the first node A, and the anode of the zener diode Z is electrically connected to the ground voltage VSS of the second voltage domain. One end of the resistor is electrically connected to the first node A, and the other end of the first resistor R1 is electrically connected to the ground voltage VSS of the second voltage domain. The logic module is electrically connected to the first node A.

[0071] The first switching transistor M1 conducts when the high-side power transistor is in the on state to charge the first node A; the first switching transistor M1 turns off when the high-side power transistor is in the off state to discharge the first node A.

[0072] Please continue to refer to Figure 2 . The logic module of the level shifter is an inverter INV. The input terminal of the inverter INV is electrically connected to the first node A, and the output terminal of the inverter INV is used to output the low-side drive signal ONL. The low-side drive signal ONL is used to drive the low-side power transistor to conduct or turn off. The first enable terminal of the inverter INV is electrically connected to the power supply voltage VCC of the second voltage domain, and the second enable terminal of the inverter INV is electrically connected to the ground voltage VSS of the second voltage domain.

[0073] Please refer to Figure 3 , which is another structural schematic diagram of the level shifter provided by the embodiment of the present invention. The adjustment module of the level shifter includes a first switching transistor M1, a second switching transistor M2, a first resistor R1, and an amplification unit. Among them, the first switching transistor M1 and the second switching transistor M2 can be MOS transistors.

[0074] The control terminal of the first switching transistor M1 is used to receive the inverted signal ONHz of the high-side drive signal. The high-side drive signal ONH is used to drive the high-side power transistor to conduct or turn off. The first terminal of the first switching transistor M1 is electrically connected to the power supply voltage BOOT of the first voltage domain, and the second terminal of the first switching transistor M1 is electrically connected to the first node A.

[0075] The control terminal of the second switching transistor M2 is electrically connected to a reference power supply, and the reference power supply is used to provide a reference voltage V REF , the first terminal of the second switching transistor M2 is electrically connected to the first node A, and the second terminal of the second switching transistor M2 is electrically connected to the ground voltage VSS of the second voltage domain. One end of the resistor is electrically connected to the first node A, and the other end of the first resistor R1 is electrically connected to the ground voltage VSS of the second voltage domain.

[0076] The first terminal of the amplification unit is electrically connected to the first node A, the second terminal of the amplification unit is electrically connected to the power supply voltage VCC of the second voltage domain, the third terminal of the amplification unit is electrically connected to the logic module, and the fourth terminal of the amplification unit is electrically connected to the ground voltage VSS of the second voltage domain.

[0077] The first switching transistor M1 conducts when the high-side power transistor is in the on state to charge the first node A; the first switching transistor M1 turns off when the high-side power transistor is in the off state to discharge the first node A.

[0078] The second switching transistor M2 conducts when the first switching transistor M1 is in the conducting state, so as to control the amplifying unit to be in the working state when the voltage of the first node A is higher than the preset voltage threshold; the second switching transistor M2 turns off when the first switching transistor M1 is in the off state, so as to control the amplifying unit to be in the non-working state when the voltage of the first node A is equal to or lower than the preset voltage threshold.

[0079] Please refer to Figure 4 , which is another structural schematic diagram of the level shifter provided by the embodiment of the present invention. The adjustment module of the level shifter includes a first switching transistor M1, a second switching transistor M2, a capacitor C, a first resistor R1, and an amplifying unit. The first switching transistor M1 and the second switching transistor M2 can be MOS transistors.

[0080] The control terminal of the first switching transistor M1 is used to receive the reverse signal ONHz of the high-side driving signal. The high-side driving signal ONH is used to drive the high-side power transistor to conduct or turn off. The first terminal of the first switching transistor M1 is electrically connected to the power supply voltage BOOT of the first voltage domain, and the second terminal of the first switching transistor M1 is electrically connected to the first node A. One end of the capacitor C is electrically connected to the first terminal of the first switching transistor M1, and the other end of the capacitor C is electrically connected to the first node A.

[0081] The control terminal of the second switching transistor M2 is electrically connected to the reference power supply, and the reference power supply is used to provide the reference voltage V REF , the first terminal of the second switching transistor M2 is electrically connected to the first node A, and the second terminal of the second switching transistor M2 is electrically connected to the ground voltage VSS of the second voltage domain. One end of the resistor is electrically connected to the first node A, and the other end of the first resistor R1 is electrically connected to the ground voltage VSS of the second voltage domain.

[0082] The first terminal of the amplifying unit is electrically connected to the first node A, the second terminal of the amplifying unit is electrically connected to the power supply voltage VCC of the second voltage domain, the third terminal of the amplifying unit is electrically connected to the logic module, and the fourth terminal of the amplifying unit is electrically connected to the ground voltage VSS of the second voltage domain.

[0083] The first switching transistor M1 conducts when the high-side power transistor is in the conducting state to charge the first node A; the first switching transistor M1 turns off when the high-side power transistor is in the off state to discharge the first node A.

[0084] The second switching transistor M2 conducts when the first switching transistor M1 is in the conducting state, so as to control the amplifying unit to be in the working state when the voltage of the first node A is higher than the preset voltage threshold; the second switching transistor M2 turns off when the first switching transistor M1 is in the off state, so as to control the amplifying unit to be in the non-working state when the voltage of the first node A is equal to or lower than the preset voltage threshold.

[0085] Please continue to refer to Figure 3 and Figure 4. The amplification unit includes a third switching transistor M3 and a second resistor R2, where the third switching transistor M3 can be a MOS transistor.

[0086] The control terminal of the third switching transistor M3 is electrically connected to the first node A, the first terminal of the third switching transistor M3 is electrically connected to the second node B, and the second terminal of the third switching transistor M3 is electrically connected to the ground voltage VSS of the second voltage domain.

[0087] One end of the second resistor R2 is electrically connected to the power supply voltage VCC of the second voltage domain, and the other end of the second resistor R2 is electrically connected to the second node B. The logic module is electrically connected to the second node B.

[0088] The third switching transistor M3 is in an amplification state when the voltage of the first node A is higher than a preset voltage threshold; the third switching transistor M3 is in a cut-off state when the voltage of the first node A is equal to or lower than the preset voltage threshold.

[0089] Please continue to refer to Figure 3 and Figure 4 . Among them, the logic module is a latch. The R terminal of the latch is electrically connected to the second node B. The S terminal of the latch is used to receive the control signal SD. The output terminal of the latch is used to output the low-side drive signal ONL. The low-side drive signal ONL is used to drive the low-side power transistor to conduct or turn off. The first enable terminal of the latch is electrically connected to the power supply voltage VCC of the second voltage domain. The second enable terminal of the latch is electrically connected to the ground voltage VSS of the second voltage domain. The third enable terminal of the latch is electrically connected to the power supply voltage VCC of the second voltage domain. The fourth enable terminal of the latch is electrically connected to the ground voltage VSS of the second voltage domain.

[0090] In Figure 3 and Figure 4 In the level shifter shown, when the high-side power transistor is in a conducting state, the voltage of the first node A satisfies the following relationship:

[0091] V A = V REF + V M2 ;

[0092] Among them, V A represents the voltage of the first node A, V REF represents the reference voltage, and V M2 represents the voltage between the control terminal and the first terminal of the second switching transistor M2.

[0093] It can be understood that the reference voltage V REF can be set according to the second voltage domain (VCC - VSS). For example, the reference voltage V REF changes with the second voltage domain (VCC - VSS). The reference voltage V REF can also be set according to the actual situation, and the embodiments of the present invention do not limit it.

[0094] The following will be combined with Figure 2 to introduce Figure 2 the working principle of the level shifter shown.

[0095] When the high-side drive signal ONH is at a high level, the high-side power transistor is in the conducting state. The inverted signal ONHz of the high-side drive signal received by the control terminal of the first switching transistor M1 is at a low level, so the first switching transistor M1 conducts, charges the first node A, so that the low-side drive signal ONL output by the inverter INV is at a low level, thereby driving the low-side power transistor to be in the off state. And the voltage of the first node A is the reverse breakdown voltage V of the zener diode Z Z , which pulls down the voltage of the first node A. Moreover, the voltage of the first node A is clamped within the safe voltage range of the low-side power transistor by the zener diode Z, and the low-side power transistor will not be overvoltage.

[0096] When the high-side drive signal ONH switches from a high level to a low level, the high-side power transistor switches from the conducting state to the off state, and the first switching transistor M1 switches from the conducting state to the off state, so that the first node A discharges through the first resistor R1 first. And during the process of the high-side power transistor turning off, the power supply voltage BOOT and the ground voltage SW of the first voltage domain will drop. Then, through the direct coupling of the capacitor C, the voltage of the first node A will drop rapidly.

[0097] Then the low-side drive signal ONL output by the inverter INV will quickly change from a low level to a high level. This shortens the duration of the low-side power transistor switching from the off state to the on state, thereby reducing the dead time. And because the coupling effect of the capacitor C only occurs when the ground voltage SW drops after the high-side power is turned off, there will be no situation where the low-side power transistor conducts before the high-side power transistor is completely turned off, thereby reducing the risk of cross-conduction between the high-side and low-side power transistors.

[0098] Based on Figure 2 the level shifter shown, its static power consumption is the current obtained by dividing the reverse breakdown voltage V z by the resistance value of the first resistor R1, plus the reverse breakdown current of the zener diode Z. In order to further reduce the dead time and the power consumption of the level shifter. The embodiment of the present invention also provides Figure 4 the level shifter shown. The following will be combined with Figure 4 and Figure 5 to introduce the working principle of this level shifter, Figure 5 which is Figure 4 the working waveform diagram of the level shifter in

[0099] When the high-side drive signal ONH is at a high level, the high-side power transistor is in the conducting state. The reverse signal ONHz of the high-side drive signal received by the control terminal of the first switching transistor M1 is at a low level, so the first switching transistor M1 conducts, charges the first node A, and the second switching transistor M2 also conducts. By applying a reference voltage V REF to the control terminal of the second switching transistor M2, while enabling the first node A to be recognized as a high level by the subsequent stage, the voltage of the first node A can be pulled down to V REF +V M2 . It can be understood that the voltage of the first node A is V REF +V M2 , which is higher than the preset voltage threshold, i.e., the drive voltage of the third switching transistor M3, so that the third switching transistor M3 is in the amplification state. Then, through the amplification of the third switching transistor M3 and the second resistor R2, the voltage of the first node A can be V REF +V M2 and can be recognized as a high level. Then the second node B is at a low level, and the low-side drive signal ONL output by the latch is at a low level, thus driving the low-side power transistor to be in the off state.

[0100] Compared with the level shifter in Figure 2 , the level shifter in Figure 4 reduces the voltage value required for the first node A to be recognized as a high level. In this way, the voltage difference across the first resistor R1 is reduced, the current flowing through the first resistor R1 is decreased, and thus the power consumption of the level shifter is reduced.

[0101] When the high-side drive signal ONH switches from a high level to a low level, the high-side power transistor switches from the conducting state to the off state, and the first switching transistor M1 switches from the conducting state to the off state, so that the first node A first discharges through the first resistor R1. This process is the first stage of the voltage drop of the first node A, i.e., the t1 stage in Figure 5 . During the process of the high-side power transistor turning off, the power supply voltage BOOT and the ground voltage SW of the first voltage domain will drop. Then, through the direct coupling of the capacitor C, the voltage of the first node A will drop rapidly. This process is the second stage of the voltage drop of the first node A, i.e., the t2 stage in Figure 5 .

[0102] When the voltage of the first node A drops to the driving voltage of the third switching transistor M3, the third switching transistor M3 is in the cut-off state, causing the second node B to be at a high level, so that the low-side driving signal ONL output by the latch quickly changes from a low level to a high level. Thereby driving the low-side power transistor to be in the conducting state. This shortens the duration of the low-side power transistor switching from the off state to the on state, thereby reducing the dead time. Moreover, since the coupling effect of the capacitor C only occurs when the ground voltage SW drops after the high-side power is turned off, the situation where the low-side power transistor conducts before the high-side power transistor is fully turned off will not occur, thereby reducing the risk of cross-conduction between the high-side and low-side power transistors.

[0103] And by using a latch, after the low-side driving signal ONL is flipped to a high level, it can ensure that the low-side power transistor remains in the conducting state until the control signal SD goes high, thereby preventing the voltage ringing and jitter generated in the first voltage domain after the high-side power transistor is turned off from being transmitted to the low-side power transistor through the capacitor C and causing it to switch repeatedly.

[0104] Compared with Figure 2 the level shifter in Figure 4 the level shifter in weakens the process of discharging the first node A through the first resistor R1, deepens the influence of the coupling effect of the capacitor C on the potential drop of the first node A, thereby further shortening the dead time.

[0105] Please refer to Figure 6 , which is a schematic structural diagram of the power conversion device provided by the embodiment of the present invention. The power conversion device includes a high-side power transistor M H , a high-side driver, a low-side power transistor M L , a low-side driver, and the level shifter provided by the embodiment of the present invention. Among them, the high-side power transistor M H and the low-side power transistor M L can be MOS transistors.

[0106] The input end of the high-side driver is used to receive the high-side driving signal ONH, and the output end is electrically connected to the control end of the high-side power transistor M H . The first end of the high-side power transistor M H is electrically connected to the power supply VIN, and the second end is electrically connected to the first end of the low-side power transistor M L . The input end of the level shifter is used to receive the reverse signal ONHz of the high-side driving signal, and the output end is electrically connected to the input end of the low-side driver. The output end of the low-side driver is electrically connected to the control end of the low-side power transistor M L . The second end of the low-side power transistor M L is grounded.

[0107] Moreover, the first enable terminal of the high-side driver is electrically connected to the power supply voltage BOOT of the first voltage domain, and the second enable terminal is electrically connected to the ground voltage SW of the first voltage domain; the ground voltage SW of the first voltage domain is electrically connected to the connection node of the high-side power transistor M H and the low-side power transistor M L . The first enable terminal of the low-side driver is electrically connected to the power supply voltage VCC of the second voltage domain, and the second enable terminal is electrically connected to the ground voltage VSS of the second voltage domain; the ground voltage VSS of the second voltage domain is electrically connected to the second terminal of the low-side power transistor M L .

[0108] An embodiment of the present invention further provides a power conversion chip, which includes the power conversion device provided by the embodiment of the present invention.

[0109] The foregoing is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0110] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. A level shifter, characterized in that: The level shifter is used to convert between a first voltage domain and a second voltage domain, and the level shifter includes an electrically connected regulating module and a logic module, wherein a first end of the regulating module is electrically connected to a power supply voltage of the first voltage domain, a second end is electrically connected to a power supply voltage of the second voltage domain, and a third end is electrically connected to a ground voltage of the second voltage domain; a first end of the logic module is electrically connected to a power supply voltage of the second voltage domain, a second end is electrically connected to a ground voltage of the second voltage domain, and an output end is electrically connected to a low-side power tube, and the low-side power tube is electrically connected to a high-side power tube; The regulating module is used for outputting a first signal to the logic module when the high-side power tube is in a conducting state; The logic module is used to drive the low-side power tube to be in a shutdown state when receiving the first signal; The regulating module is also used for outputting a second signal to the logic module when the high-side power tube is in the off state; The logic module is also used to drive the low-side power tube to be in a conducting state when receiving the second signal; The regulating module is also used to lower the voltage of the connection node between the regulating module and the logic module when the high-side power tube is in the on state, so as to shorten the time for the low-side power tube to switch from the off state to the on state, and reduce the dead time of the high-side power tube and the low-side power tube.

2. The level shifter according to claim 1, characterized in that: The regulating module includes a first switch tube, a capacitor, a voltage stabilizing diode and a first resistor; The control end of the first switch tube is used to receive a reverse signal of a high-side drive signal, and the high-side drive signal is used to drive the high-side power tube to be turned on or off, the first end of the first switch tube is electrically connected to the power supply voltage of the first voltage domain, and the second end of the first switch tube is electrically connected to the first node; One end of the capacitor is electrically connected to the first end of the first switch tube, and the other end of the capacitor is electrically connected to the first node; A cathode of the voltage zener diode is electrically connected to the first node, and an anode of the voltage zener diode is electrically connected to the ground voltage of the second voltage domain; One end of the resistor is electrically connected to the first node, and the other end of the first resistor is electrically connected to the ground voltage of the second voltage domain; The logic module is electrically connected to the first node; The first switch tube is turned on when the high-side power tube is in the on state to charge the first node; the first switch tube is turned off when the high-side power tube is in the off state to discharge the first node.

3. The level shifter according to claim 2, characterized in that: The logic module is an inverter, the input end of the inverter is electrically connected to the first node, the output end of the inverter is used to output a low-side drive signal, and the low-side drive signal is used to drive the low-side power tube to be turned on or off, the first enable end of the inverter is electrically connected to the power supply voltage of the second voltage domain, and the second enable end of the inverter is electrically connected to the ground voltage of the second voltage domain.

4. The level shifter according to claim 1, wherein: The regulating module includes a first switch tube, a second switch tube, a first resistor and an amplifying unit; The control end of the first switch tube is used to receive a reverse signal of a high-side drive signal, and the high-side drive signal is used to drive the high-side power tube to be turned on or off, the first end of the first switch tube is electrically connected to the power supply voltage of the first voltage domain, and the second end of the first switch tube is electrically connected to the first node; The control end of the second switch tube is electrically connected to a reference power supply, the reference power supply is used to provide a reference voltage, the first end of the second switch tube is electrically connected to the first node, and the second end of the second switch tube is electrically connected to the ground voltage of the second voltage domain; One end of the resistor is electrically connected to the first node, and the other end of the first resistor is electrically connected to the ground voltage of the second voltage domain; A first terminal of the amplifying unit is electrically connected to the first node, a second terminal of the amplifying unit is electrically connected to the power supply voltage of the second voltage domain, a third terminal of the amplifying unit is electrically connected to the logic module, and a fourth terminal of the amplifying unit is electrically connected to the ground voltage of the second voltage domain; The first switch tube is turned on when the high-side power tube is in the on state to charge the first node; the first switch tube is turned off when the high-side power tube is in the off state to discharge the first node; The second switch tube is turned on when the first switch tube is in the on state, so that when the voltage of the first node is higher than the preset voltage threshold, the control amplification unit is in the working state; The second switch tube is turned off when the first switch tube is in the off state, so that when the voltage of the first node is equal to or lower than the preset voltage threshold, the control amplification unit is in a non-working state.

5. The level shifter according to claim 1, characterized in that: The regulating module includes a first switch tube, a second switch tube, a capacitor, a first resistor and an amplifying unit; The control end of the first switch tube is used to receive a reverse signal of a high-side drive signal, and the high-side drive signal is used to drive the high-side power tube to be turned on or off, the first end of the first switch tube is electrically connected to the power supply voltage of the first voltage domain, and the second end of the first switch tube is electrically connected to the first node; One end of the capacitor is electrically connected to the first end of the first switch tube, and the other end of the capacitor is electrically connected to the first node; The control end of the second switch tube is electrically connected to a reference power supply, the reference power supply is used to provide a reference voltage, the first end of the second switch tube is electrically connected to the first node, and the second end of the second switch tube is electrically connected to the ground voltage of the second voltage domain; One end of the resistor is electrically connected to the first node, and the other end of the first resistor is electrically connected to the ground voltage of the second voltage domain; A first terminal of the amplifying unit is electrically connected to the first node, a second terminal of the amplifying unit is electrically connected to the power supply voltage of the second voltage domain, a third terminal of the amplifying unit is electrically connected to the logic module, and a fourth terminal of the amplifying unit is electrically connected to the ground voltage of the second voltage domain; The first switch tube is turned on when the high-side power tube is in the on state to charge the first node; the first switch tube is turned off when the high-side power tube is in the off state to discharge the first node; The second switch tube is turned on when the first switch tube is in the on state, so that when the voltage of the first node is higher than the preset voltage threshold, the control amplification unit is in the working state; The second switch tube is turned off when the first switch tube is in the off state, so that when the voltage of the first node is equal to or lower than the preset voltage threshold, the control amplification unit is in a non-working state.

6. The level shifter according to claim 4 or 5, characterized in that: The amplifying unit includes a third switch tube and a second resistor; The control end of the third switch tube is electrically connected to the first node, the first end of the third switch tube is electrically connected to the second node, and the second end of the third switch tube is electrically connected to the ground voltage of the second voltage domain; One end of the second resistor is electrically connected to the power supply voltage of the second voltage domain, and the other end of the second resistor is electrically connected to the second node; The logic module is electrically connected to the second node; The third switch tube is in an amplification state when the voltage at the first node is higher than a preset voltage threshold; The third switch tube is in a cut-off state when the voltage at the first node is equal to or lower than a preset voltage threshold.

7. The level shifter according to claim 6, characterized in that: The logic module is a latch, the R end of the latch is electrically connected to the second node, the S end of the latch is used to receive a control signal, the output end of the latch is used to output a low-side drive signal, and the low-side drive signal is used to drive the low-side power tube to be turned on or off, the first enable end of the latch is electrically connected to the power supply voltage of the second voltage domain, the second enable end of the latch is electrically connected to the ground voltage of the second voltage domain, the third enable end of the latch is electrically connected to the power supply voltage of the second voltage domain, and the fourth enable end of the latch is electrically connected to the ground voltage of the second voltage domain.

8. The level shifter according to claim 6, characterized in that: When the high-side power tube is in the on state, the voltage of the first node satisfies the following relationship: V A =V REF +V M2 ; Among them, V A Represents the voltage of the first node, V REF represents the reference voltage, V M2 Represents the voltage between the control terminal and the first terminal of the second switch tube.

9. A power conversion device, characterized in that: The power conversion device includes a high-side power tube, a high-side driver, a low-side power tube, a low-side driver and the level shifter described in any one of claims 1-8, the input end of the high-side driver is used to receive a high-side drive signal, and the output end is electrically connected to the control end of the high-side power tube, the first end of the high-side power tube is electrically connected to the power supply, and the second end is electrically connected to the first end of the low-side power tube, the input end of the level shifter is used to receive a reverse signal of the high-side drive signal, and the output end is electrically connected to the input end of the low-side driver, the output end of the low-side driver is electrically connected to the control end of the low-side power tube, and the second end of the low-side power tube is grounded.

10. A power conversion chip, characterized in that: Includes the power conversion device as described in claim 9.

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