A high-speed and high-linearity residue amplifier and analog-to-digital converter
Through the combination of Class AB super source follower structure and gain calibration module, the shortcomings of the analog-to-digital converter in high speed, high accuracy and low power consumption are solved, and the high linearity and gain stability of the margin amplifier are achieved, adapting to process and temperature changes, and reducing system power consumption.
Patent Information
- Application Number
- CN202510662180.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-22
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2045-05-22
AI Technical Summary
Existing analog-to-digital converters have shortcomings in high speed, high accuracy and low power consumption, especially the linearity and gain stability of the margin amplifier are difficult to meet the requirements of high-frequency and large-swing inputs.
A linear transconductance unit and gain calibration module based on the AB super source follower structure are adopted, combined with the inverter and the bias module, a high-speed and high-linearity margin amplifier is built, and the output impedance is reduced through the AB feedback current source and the inverter, symmetry between the positive and negative output terminals is achieved, and temperature and process changes are automatically compensated through the gain calibration module.
It improves the linearity and gain stability of the margin amplifier, meets the indicators of high-speed and high linearity, and reduces system power consumption and adapts to the influence of process and temperature changes.
Smart Images
Figure CN120200566B_ABST
Abstract
Description
Technical field
[0001] The present invention relates to the field of integrated circuits, and particularly to a residue amplifier required for a high-speed and high-linearity pipelined successive approximation analog-to-digital converter. Background art
[0002] An analog-to-digital converter acts as a bridge between real-world signals and the processing capabilities of the digital domain and has been widely applied in multiple fields such as wireless communication, electronic monitoring and countermeasure, and phased array. With the advent of the Internet of Things era and the development of 5G communication technology, higher requirements are imposed on the performance of analog-to-digital converters. They should not only be able to meet high speed and high precision, but also reduce power consumption as much as possible. In application scenarios such as military, aerospace, lidar, medical, and 5G communication, there are varying degrees of requirements for high-speed and high-precision analog-to-digital converters. Among them, the demand in the communication field is relatively high. The sampling rate of 5G base stations is about 250 Msps to 1 Gsps, and the accuracy is generally 12 to 14 bits; optical communication requires a sampling rate of more than ultra-high speed 40 Gsps and an accuracy of more than 6 bits. In the military and aerospace fields, high-speed independent chips or modules with a sampling rate of more than 1 Gsps and high precision of more than 8 bits are usually required. In addition, in the past few decades, the carrier frequency and bandwidth of wireless communication have been on the rise, and this trend continues in today's millimeter-wave band.
[0003] Common analog-to-digital converters such as flash analog-to-digital converters have a great advantage in terms of speed because multiple comparators work in parallel. However, due to this, the power consumption will be larger. The pipelined analog-to-digital converter also has an advantage in terms of speed because of its characteristic of multi-stage sequential processing, and it makes a compromise between power consumption and speed. The successive approximation analog-to-digital converter, as a popular one for a long time, has the advantages of high digitalization and simple structure, and has a good compromise between speed accuracy and power consumption.
[0004] In view of the current application requirements of high speed, high precision and low power consumption, single-structure analog-to-digital converters are becoming increasingly ineffective. Therefore, many hybrid analog-to-digital converters that combine the advantages of various structures have been proposed. Among them, the pipelined successive approximation analog-to-digital converter is a hot topic in the research field of high-speed and high-precision analog-to-digital converters due to its broad application prospects. The pipelined successive approximation analog-to-digital converter fully or partially adopts the successive approximation analog-to-digital converter as the sub-analog-to-digital converter of the pipelined analog-to-digital converter, improves the quantization accuracy of each stage, reduces the number of stages of the pipelined analog-to-digital converter on the premise of meeting the quantization accuracy, and reduces the power consumption. At the same time, the multi-stage successive approximation analog-to-digital converter works in a pipelined form, effectively solving the compromise relationship between the quantization accuracy and quantization speed of the successive approximation analog-to-digital converter. The structure of an analog-to-digital converter with two-stage pipeline is as Figure 1As shown, the structure includes a sampling switch 101, first-stage and second-stage successive approximation analog-to-digital converters 102 and 104, and a residue amplifier 103. Generally speaking, the accuracy of a pipelined successive approximation analog-to-digital converter is the sum of the accuracies of each stage of sub-analog-to-digital converters. Therefore, even under high-precision requirements, the accuracy of the sub-analog-to-digital converters does not need to be too high. Since the research and application of successive approximation analog-to-digital converters are very mature at present, the key technology of the pipelined successive approximation analog-to-digital converter lies in the design of the residue amplifier. The operating speed of the residue amplifier needs to reach the maximum operating speed of the system. Its accuracy and linearity are the upper limits of the performance of the subsequent stage of sub-analog-to-digital converters. Especially in the case of a multi-stage pipeline, the performance requirements for the first-stage residue amplifier are very high. In high-speed analog-to-digital converters, in order to meet the speed requirements, relatively advanced processes are usually used. However, as the process size continues to shrink, problems such as channel length modulation effect, intrinsic gain reduction, and parasitics make it difficult for the amplifier to simultaneously balance gain, accuracy, speed, and power consumption. It can be said that the key to the research of the pipelined successive approximation analog-to-digital converter is the design of the residue amplifier.
[0005] There are many architectures of operational amplifiers, and each architecture has its own advantages and disadvantages. For example, in the case of a closed-loop application of a ring operational amplifier, its feedback coefficient will cause an inherent loss to the bandwidth of the operational amplifier itself, and a larger power consumption overhead is required to meet the system design requirements. An open-loop amplifier directly uses the operational amplifier in an open-loop manner as an inter-stage amplifier. Without the limitation of stability conditions, the open-loop amplifier does not require any compensation, and its bandwidth is determined by the RC constant of the output node. The advantage of the open-loop amplifier is that its structure is simple and the power consumption is low, and the open-loop gain is directly used for the amplification of the residue. However, with the changes in process, power supply voltage, and temperature, its gain will fluctuate greatly, resulting in relatively low accuracy and linearity of the open-loop amplifier. The ring amplifier evolved from a ring oscillator, and its main structure is three inverters, which is very suitable for relatively advanced processes and lower power supply voltages. However, this structure has more poles and requires means such as introducing external poles to ensure the stability of the system. There are mainly two types of dynamic amplifiers: Gm-C type dynamic amplifiers and Gm-R type dynamic amplifiers. The Gm-C type dynamic amplifier is based on the working principle of an integrator, and the signal establishment is completed through the slew rate, that is, the load capacitor is charged and discharged by a certain amount of current to complete the amplification. Its amplification factor is related to time and is usually called an integrating amplifier. The Gm-R type dynamic amplifier is a dynamic amplifier with a determined gain. Its amplification factor is related to the transconductance Gm and output impedance Ro of the amplifier. When the output of the Gm-R type dynamic amplifier is fully established, its amplification factor is independent of the amplification time.
[0006] Generally speaking, except for closed-loop amplifiers, the above several structures always have poor linearity due to the open-loop structure. In order to obtain higher linearity, Figure 2This linear transconductance structure is proposed. In the figure, transistors 201 and 202 are both input transistors of the margin amplifier, and there is a fixed voltage difference V between the respective gates of the two transistors and the source of the other transistor X of the voltage source 203. According to the square-law formula of transistor current, where I D is the transistor current, k is the transistor parameter, V GS and V T are the gate-source voltage difference and the threshold voltage of the transistor respectively:
[0007]
[0008] From Figure 2 the gate-source voltage V GS1 of the M1 transistor can be obtained as:
[0009]
[0010] where Vid represents the input differential voltage, V IP and V IN represent the input positive-phase signal and negative-phase signal respectively. Similarly, the gate-source voltage V GS2 of the M2 transistor can be obtained as:
[0011]
[0012] Substituting it in, the differential current is:
[0013]
[0014] I D1 and I D2 are the currents of M1 and M2 transistors respectively. It can be seen that as long as V X is constant, the differential output current and the differential input voltage have a good linear relationship. Currently, in order to obtain a constant V X the structure adopted is the source follower. Because the voltage following characteristic of the source follower will make its gate-source voltage difference a fixed value, but the output impedance of a general source follower is not low enough, and the current of the input transistor will change due to the charge and discharge of the load and the gate-source voltage difference cannot be kept constant. The currently common source follower is the flip-type source follower. As Figure 3 shown, in addition to the input transistor 301, a feedback transistor 302 is introduced. The gate of the feedback transistor 302 is connected to the drain of the input transistor 301 to form a closed-loop system. Its output impedance is equal to the output impedance of the open-loop architecture divided by the loop gain. Therefore, first calculate the output impedance R o,open when open-loop as:
[0015]
[0016] Among them, g m1 and g m2 are the transconductances of transistors M1 and M2 respectively, and r o1 and r o2 are the output impedances of transistors M1 and M2 respectively. The loop gain A close is:
[0017]
[0018] Therefore, the closed-loop output impedance R o is:
[0019]
[0020] The output impedance of this inverting voltage follower architecture is attenuated by an intrinsic gain compared to the output impedance of the source follower, which further reduces the output impedance node resistance and makes the gate-source voltage difference of transistor 301 closer to that of an ideal current source. However, although this structure has been widely used, its linearity can still only reach about 40 dB to 60 dB, and in the worst case, it may not meet the requirements of high speed and high linearity. SUMMARY OF THE INVENTION
[0021] The technical problem to be solved by the present invention is in view of the above-mentioned deficiencies of the prior art. The first object of the present invention is to provide a high-speed and high-linearity residue amplifier, which can effectively meet the requirements of high speed and high linearity.
[0022] The second object of the present invention is to provide an analog-to-digital converter.
[0023] To achieve the above first object, the present invention provides a high-speed and high-linearity residue amplifier, including: a bias and output module, an inverter, and a linear transconductance unit based on a class AB super source follower structure, and the bias and output module, the linear transconductance unit, and the inverter are connected in sequence;
[0024] Wherein: the linear transconductance unit includes: an input transistor M1, an input transistor M2, a source follower transistor M3, a source follower transistor M4, class-AB feedback current source transistors M5, M6, M7, and M8; the source of the input transistor M1, the source of the source follower transistor M3, the drain of the class-AB feedback current source transistor M5, and the drain of the class-AB feedback current source transistor M7 are connected; the gates of the class-AB feedback current source transistors M5 and M7 and the drain of the source follower transistor M3 are connected; the source of the input transistor M2, the source of the source follower transistor M4, the drain of the class-AB feedback current source transistor M6, and the drain of the class-AB feedback current source transistor M8 are connected; the gates of the class-AB feedback current source transistors M6 and M8 and the drain of the source follower transistor M4 are connected; the gates of the input transistor M1, the input transistor M4, and the positive input signal terminal are connected; the gates of the input transistor M2, the source follower transistor M3, and the negative input signal terminal are connected; the drains of the input transistor M1, the input transistor M2, the source follower transistor M3, the source follower transistor M4, and the bias and output module are connected; the sources of the class-AB feedback current source transistors M7 and M8 and the power supply terminal are connected; the sources of the class-AB feedback current source transistors M5 and M6 and the inverter are connected.
[0025] As a further improvement, the bias and output module includes: a current source transistor M9, a current source transistor M10, and two load resistors R D , the sources of the current source transistor M9, the current source transistor M10, one end of the two load resistors R D are connected to the power supply terminal; the gates of the current source transistor M9 and the current source transistor M10 are connected for inputting a specified bias voltage; the drain of the current source transistor M9 is connected to the drain of the source follower transistor M3; the drain of the current source transistor M10 is connected to the drain of the source follower transistor M4; the other end of one of the load resistors R D is connected to the drain of the input transistor M1 and serves as the negative output terminal; the other end of the other load resistor R D is connected to the drain of the input transistor M2 and serves as the positive output terminal.
[0026] Furthermore, the other end of the load resistor R D is grounded sequentially through a clock signal switch K φRA , a capacitor C DAC .
[0027] Further, the inverter includes: a transistor M11 and a transistor M12. The gates of the transistor M11, the transistor M12, and the clock signal terminal are connected. The drains of the transistor M11, the transistor M12, the source of the class-AB feedback current source transistor M5, and the source of the class-AB feedback current source transistor M6 are connected. The source of the transistor M11 is grounded, and the source of the transistor M12 is connected to the power supply terminal.
[0028] Further, a gain calibration module is further included. The gain calibration module includes: a clamping operational amplifier A0, a current mirror transistor M13, a current mirror transistor M14, a voltage-to-current resistor R0, a process trimming resistor R trim , a temperature coefficient adjustment transistor M15, and a temperature coefficient adjustment transistor M16. The positive input terminal of the clamping operational amplifier A0 is connected to the reference voltage terminal. The negative input terminal of the clamping operational amplifier A0, the drain of the current mirror transistor M13, and one end of the voltage-to-current resistor R0 are connected. The other end of the voltage-to-current resistor R0 is grounded. The output terminal of the clamping operational amplifier A0 is connected to the gate of the current mirror transistor M13. The gate of the current mirror transistor M14 is connected to the gate of the current mirror transistor M13. The source of the current mirror transistor M13, the source of the current mirror transistor M14, and the power supply terminal are connected. The drain of the current mirror transistor M14, one end of the process trimming resistor R trim , and the gate of the temperature coefficient adjustment transistor M15 are connected. The other end of the process trimming resistor R trim is grounded. The drain of the temperature coefficient adjustment transistor M15, the drain of the temperature coefficient adjustment transistor M16, and the gate of the temperature coefficient adjustment transistor M16 are connected. The source of the temperature coefficient adjustment transistor M15 is grounded. The source of the temperature coefficient adjustment transistor M16 is connected to the power supply terminal. The gate of the temperature coefficient adjustment transistor M16 is connected to the gates of the current source transistor M9 and the current source transistor M10 to provide a specified bias voltage.
[0029] To achieve the above second object, the present invention provides an analog-to-digital converter, and the analog-to-digital converter is a pipelined successive approximation analog-to-digital converter that applies the above-mentioned high-speed and high-linearity margin amplifier.
[0030] Beneficial effects
[0031] Compared with the prior art, the present invention has the following advantages:
[0032] The linear transconductance unit of the present invention can generate a transconductance with high linearity, thereby improving the linearity of the entire residue amplifier. It can ensure the symmetry of the positive and negative output terminals of the residue amplifier under the conditions of high frequency or large swing input, so as to effectively meet the requirements of high speed and high linearity. In addition, the present invention also introduces a gain calibration module that resists temperature and process variations, which can automatically compensate for the influence brought by the subsequent system environment temperature change. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 FIG. is a schematic structural diagram of a pipelined successive approximation analog-to-digital converter in the prior art;
[0034] Figure 2 FIG. is a schematic structural diagram of a linear transconductance circuit in the prior art;
[0035] Figure 3 FIG. is a schematic structural diagram of an inverting source follower circuit in the prior art;
[0036] Figure 4 FIG. is a schematic structural diagram of the residue amplifier in the present invention;
[0037] Figure 5 FIG. is a schematic structural diagram of the class AB super source follower of the residue amplifier in the present invention;
[0038] Figure 6 FIG. is a schematic structural diagram of an analog-to-digital converter applying the residue amplifier in the present invention;
[0039] Figure 7 FIG. is a schematic diagram of the linearity of the output signal of the residue amplifier in the present invention;
[0040] Figure 8 FIG. is a schematic diagram of the gain of the residue amplifier in the present invention under different processes and temperatures.
[0041] Wherein: 101 is a sampling switch, 102 and 104 are sub-analog-to-digital converters, and 103 is a residue amplifier; 201 and 202 are input transistors, and 203 is a linear transconductance voltage source; 301 is an input source follower transistor, and 302 is an inverting voltage feedback current source transistor; 401 is a linear transconductance unit of the class AB super source follower, 402 is a bias and output module, 403 is an inverter, and 404 is a gain calibration module; 501 is an input source follower transistor, and 502 and 503 are class AB feedback current source transistors; 601 and 603 are sub-analog-to-digital converters, and 602 is the first-stage residue amplifier. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0042] The present invention will be further described below with reference to specific embodiments in the drawings.
[0043] Refer to Figures 4 to 8, A high-speed and high-linearity margin amplifier, comprising: a bias and output module 402, an inverter 403, and a linear transconductance unit 401 based on a class-AB super source follower structure. The bias and output module 402, the linear transconductance unit 401, and the inverter 403 are connected in sequence.
[0044] Among them: The linear transconductance unit 401 includes: an input transistor M1, an input transistor M2, a source follower transistor M3, a source follower transistor M4, a class-AB feedback current source transistor M5, a class-AB feedback current source transistor M6, a class-AB feedback current source transistor M7, and a class-AB feedback current source transistor M8. The source electrode of the input transistor M1, the source electrode of the source follower transistor M3, the drain electrode of the class-AB feedback current source transistor M5, and the drain electrode of the class-AB feedback current source transistor M7 are connected. The gate electrode of the class-AB feedback current source transistor M5, the gate electrode of the class-AB feedback current source transistor M7, and the drain electrode of the source follower transistor M3 are connected. The source electrode of the input transistor M2, the source electrode of the source follower transistor M4, the drain electrode of the class-AB feedback current source transistor M6, and the drain electrode of the class-AB feedback current source transistor M8 are connected. The gate electrode of the class-AB feedback current source transistor M6, the gate electrode of the class-AB feedback current source transistor M8, and the drain electrode of the source follower transistor M4 are connected. The gate electrode of the input transistor M1, the gate electrode of the input transistor M4, and the positive input signal terminal are connected for inputting a positive input signal V IP . The gate electrode of the input transistor M2, the gate electrode of the source follower transistor M3, and the negative input signal terminal are connected for inputting a negative input signal V IN . The drain electrode of the input transistor M1, the drain electrode of the input transistor M2, the drain electrode of the source follower transistor M3, and the bias and output module 402 are connected. The source electrode of the class-AB feedback current source transistor M7, the source electrode of the class-AB feedback current source transistor M8, and the power supply terminal are connected for inputting a power supply V DD . The source electrode of the class-AB feedback current source transistor M5, the source electrode of the class-AB feedback current source transistor M6, and the inverter 403 are connected.
[0045] The bias and output module 402 includes: a current source transistor M9, a current source transistor M10, and two load resistors R D . The source electrode of the current source transistor M9, the source electrode of the current source transistor M10, one end of the two load resistors R D , and the power supply terminal are connected for inputting a power supply V DD . The gate electrode of the current source transistor M9 and the gate electrode of the current source transistor M10 are connected for inputting a specified bias voltage V bThe drain of the current source transistor M9 is connected to the drain of the source follower transistor M3, that is, the drain of the current source transistor M9 is also connected to the gates of the class AB feedback current source transistors M5 and M7 at the same time. The drain of the current source transistor M10 is connected to the drain of the source follower transistor M4, that is, the drain of the current source transistor M10 is also connected to the gates of the class AB feedback current source transistors M6 and M8 at the same time. One end of a load resistor R D is connected to the drain of the input transistor M1 and serves as the negative output terminal to output the negative output signal V OUTN , and the other end of another load resistor R D is connected to the drain of the input transistor M2 and serves as the positive output terminal to output the positive output signal V OUTP .
[0046] Furthermore, the other end of the load resistor R D is grounded sequentially through the clock signal switch K φRA and the capacitor C DAC . The clock signal switch K φRA is controlled to open and close according to the clock signal φ RA .
[0047] Since the residue amplifier only needs to work in the amplification stage after the previous sub-analog-to-digital converter finishes quantization, the inverter 403 enables the residue amplifier to perform dynamic amplification, greatly reducing the overall power consumption of the system. In this embodiment, the inverter 403 includes: a transistor M11 and a transistor M12. The gates of the transistor M11 and the transistor M12 are connected to the clock signal terminal, that is, they are controlled by the clock signal φ RA . The drains of the transistor M11 and the transistor M12 are connected to the sources of the class AB feedback current source transistors M5 and M6. The source of the transistor M11 is grounded, and the source of the transistor M12 is connected to the power supply terminal. During the reset stage φ RA the signal is at a low level, resetting the sources of M5 and M6 to the power supply level to save power; during the working stage of the residue amplifier φ RA the signal is at a low level, pulling the sources of M5 and M6 to a low level, enabling the amplification operation to be completed normally.
[0048] Compared with the closed-loop amplifier, the gain of the open-loop amplifier is more likely to deviate due to the influence of environmental temperature, manufacturing process, and power supply voltage fluctuations. Therefore, the present invention introduces a gain calibration module 404 for resisting temperature and process variations. The gain calibration module 404 includes: a clamping operational amplifier A0, a current mirror transistor M13, a current mirror transistor M14, a voltage-to-current resistor R0, a process trimming resistor R trim, temperature coefficient adjustment transistors M15 and M16. The positive input terminal of the clamping operational amplifier A0 is connected to the reference voltage terminal for inputting a reference voltage V ref0 . The negative input terminal of the clamping operational amplifier A0, the drain of the current mirror transistor M13, and one end of the voltage-to-current resistor R0 are connected. The other end of the voltage-to-current resistor R0 is grounded. The output terminal of the clamping operational amplifier A0 is connected to the gate of the current mirror transistor M13, and the gate of the current mirror transistor M14 is connected to the gate of the current mirror transistor M13. The source of the current mirror transistor M13, the source of the current mirror transistor M14, and the power supply terminal are connected. The drain of the current mirror transistor M14, one end of the process trimming resistor R trim , and the gate of the temperature coefficient adjustment transistor M15 are connected. The other end of the process trimming resistor R trim is grounded. The drain of the temperature coefficient adjustment transistor M15, the drain of the temperature coefficient adjustment transistor M16, and the gate of the temperature coefficient adjustment transistor M16 are connected. The source of the temperature coefficient adjustment transistor M15 is grounded, the source of the temperature coefficient adjustment transistor M16 is connected to the power supply terminal, and the gate of the temperature coefficient adjustment transistor M16 is connected to the gates of the current source transistors M9 and M10 to provide a specified bias voltage V b .
[0049] Generally speaking, in the CMOS process, the threshold voltage of a transistor decreases as the temperature increases. Therefore, the transconductance of the transistor has a negative temperature coefficient. The current of the linear transconductance unit in the present invention is provided by the current source transistors M9 and M10. Therefore, in the present invention, by adjusting the sizes of the temperature coefficient adjustment transistors M15 and M16 in the gain calibration module 404, the current mirrored by M16 to M9 and M10 has a positive temperature coefficient, thereby compensating for the deviation of the transconductance of the linear transconductance unit due to temperature changes. The influence of the process is a fixed deviation that has already occurred during chip manufacturing. Therefore, the present invention uses a front-end calibration method. In the gain calibration module 404, a adjustable zero-temperature-drift reference voltage V trim is generated through the clamping operational amplifier A0, the current mirror transistor M13, the current mirror transistor M14, the voltage-to-current resistor R0, and the process trimming resistor R ref1 . This zero-temperature-drift reference voltage V ref1 is connected to the gate of M15 to adjust the deviation of the gain caused by the process influence.
[0050] The linear transconductance unit 401 based on the class-AB super source follower structure provided by the present invention can generate a transconductance with high linearity, thereby improving the linearity of the entire margin amplifier. Taking the half-circuit Figure 5For example, compared with the flip-type source follower, in addition to the source follower transistor M3 and the class-AB feedback current source transistor M5, a class-AB feedback current source transistor M7 is also introduced. The gate of M7 is connected to the drain of the input transistor M3 and the gate of M5, forming a class-AB closed-loop feedback system with a loop gain A close is:
[0051]
[0052] where gm3, gm5, and gm7 respectively represent the transconductances of transistors M3, M5, and M7, and r o3 is the output impedance of transistor M3. Therefore, the closed-loop output impedance Ro of this structure is:
[0053]
[0054] It can be seen that the output impedance of the class-AB super source follower is smaller than that of the flip-type source follower. Assuming that gm5 and gm7 are equal in magnitude, the output impedance can be equal to half of the output impedance of the flip-type source follower. At the same time, whether it is a traditional source follower or a flip-type source follower, the positive and negative slew rates of the output current are asymmetric under high-frequency or large-swing input conditions, and the minimum slew rate is limited by the bias current magnitude. However, the positive and negative slew rate currents of the class-AB super source follower are provided by two feedback transistors, and the positive and negative slew rates can be made equal. Therefore, this structure is called a class-AB source follower, which can ensure the symmetry of the positive and negative output terminals of the residue amplifier under high-frequency or large-swing input conditions.
[0055] An analog-to-digital converter, which is a pipelined successive approximation analog-to-digital converter applying the above-mentioned high-speed and high-linearity residue amplifier.
[0056] Taking the residue amplifier in a 13-bit, 600M / s analog-to-digital converter as an example, the specific implementation manner of the present invention will be more intuitively described.
[0057] Applying the residue amplifier of the present invention to a 13-bit, 600M / s pipelined successive approximation analog-to-digital converter, using CMOS process, adopting a class-AB super source follower as the linear transconductance unit, which is a Gm-R type open-loop dynamic amplifier. This example Figure 6 is shown as follows. The power supply voltage is 1V, the common-mode voltage is 0.7V, a three-stage pipeline is adopted, the resolution of each stage of the sub-analog-to-digital converter is 5 bits, the reference voltage of the first-stage sub-analog-to-digital converter is 0.5V, and the reference voltages of the second-stage and third-stage sub-analog-to-digital converters are 0.25V and 1-bit inter-stage redundancy is introduced.
[0058] In the described example, after the input signal is quantized by the first-stage sub ADC 601, a residual voltage with a peak voltage of -15.625 mV to +15.625 mV is generated. Subsequently, the inverter in the first-stage residue amplifier 602 outputs a low level, and the residue amplifier 602 starts to amplify the residual voltage by 8 times. The load is 300 fF and the amplification time is 250 ps. In this example, if the overall linearity of the system is to reach 78 dBc, the linearity of the first-stage residue amplifier 602 is at least 49 dBc. The high-speed and high-linearity residue amplifier based on the class-AB super source follower structure provided by the present invention has an SFDR (i.e., spurious-free dynamic range) ranging from 55 dBc to 75 dBc under three temperatures and three voltages, as Figure 7 shown, meeting the requirements of high speed and high linearity of the system. The second-stage residue amplifier 603 only needs to meet the linearity requirement of 30 dBc, so the residue amplifier provided by the present invention can still be used.
[0059] Due to the influence of process and temperature, the gain of the residue amplifier will deviate from the designed ideal value. The change in gain must be less than the least significant bit of the subsequent stage compared to the least significant bit of the previous stage. Taking the first-stage residue amplifier as an example, its gain must be in the range of 7.75 to 8.25 times. The residue amplifier provided by the present invention has a gain calibration module that detects the gain deviation after the system is powered on and then adjusts the resistance of the variable resistor to weaken the influence of process variations. At the same time, the temperature compensation module will automatically compensate for the influence brought by the subsequent system ambient temperature change. As Figure 8 shown, the gain accuracy obtained by simulation under different process corners TT (Typical N Typical P), FF (Fast N Fast P), SS (Slow N Slow P), FS (Fast N Slow P), and SF (Slow N Fast P) is relatively high, and the gain accuracy of the residue amplifier provided by the present invention meets the system requirements.
[0060] The above are only the preferred embodiments of the present invention. It should be noted that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can be made, which will not affect the implementation effect of the present invention and the practicality of the patent.
Claims
1. A high-speed and high-linearity margin amplifier, characterized in that, Comprising: A bias and output module (402), an inverter (403), and a linear transconductance unit (401) based on a class-AB super source follower structure, where the bias and output module (402), the linear transconductance unit (401), and the inverter (403) are connected in sequence; Wherein: The linear transconductance unit (401) includes: an input transistor M1, an input transistor M2, a source follower transistor M3, a source follower transistor M4, a class-AB feedback current source transistor M5, a class-AB feedback current source transistor M6, a class-AB feedback current source transistor M7, and a class-AB feedback current source transistor M8; The source electrode of the input transistor M1, the source electrode of the source follower transistor M3, the drain electrode of the class-AB feedback current source transistor M5, and the drain electrode of the class-AB feedback current source transistor M7 are connected; The gate electrode of the class-AB feedback current source transistor M5, the gate electrode of the class-AB feedback current source transistor M7, and the drain electrode of the source follower transistor M3 are connected; The source electrode of the input transistor M2, the source electrode of the source follower transistor M4, the drain electrode of the class-AB feedback current source transistor M6, and the drain electrode of the class-AB feedback current source transistor M8 are connected; The gate electrode of the input transistor M1, the gate electrode of the input transistor M4, and the positive input signal terminal are connected; The gate electrode of the input transistor M2, the gate electrode of the source follower transistor M3, and the negative input signal terminal are connected; The drain electrode of the input transistor M1, the drain electrode of the input transistor M2, the drain electrode of the source follower transistor M3, the drain electrode of the source follower transistor M4, and the bias and output module (402) are connected; The source electrode of the class-AB feedback current source transistor M7, the source electrode of the class-AB feedback current source transistor M8, and the power supply terminal are connected; The source electrode of the class-AB feedback current source transistor M5, the source electrode of the class-AB feedback current source transistor M6, and the inverter (403) are connected.
2. The high-speed and high-linearity margin amplifier according to claim 1, wherein The bias and output module (402) includes: a current source transistor M9, a current source transistor M10, and two load resistors R D , the source of the current source transistor M9, the source of the current source transistor M10, the one ends of the two load resistors R D are connected to the power supply terminal, the gates of the current source transistor M9 and the current source transistor M10 are connected to input a specified bias voltage, the drain of the current source transistor M9 is connected to the drain of the source follower transistor M3, the drain of the current source transistor M10 is connected to the drain of the source follower transistor M4, and the other end of one of the load resistors R D is connected to the drain of the input transistor M1 and serves as the negative output terminal, and the other end of the other load resistor R D is connected to the drain of the input transistor M2 and serves as the positive output terminal.
3. The high-speed and high-linearity margin amplifier according to claim 2, wherein The load resistor R D has its other end connected to ground sequentially through the clock signal switch K φRA and the capacitor C DAC .
4. The high-speed and high-linearity margin amplifier according to claim 2, wherein The inverter (403) includes: a transistor M11 and a transistor M12, where the gate electrode of the transistor M11, the gate electrode of the transistor M12, and the clock signal terminal are connected; The drain electrode of the transistor M11, the drain electrode of the transistor M12, and the source electrode of the class-AB feedback current source transistor M5, the source electrode of the class-AB feedback current source transistor M6 are connected; The source electrode of the transistor M11 is grounded, and the source electrode of the transistor M12 is connected to the power supply terminal.
5. The high-speed and high-linearity margin amplifier according to claim 2, characterized in that, It further includes a gain calibration module (404), and the gain calibration module (404) includes: a clamping operational amplifier A0, a current mirror transistor M13, a current mirror transistor M14, a voltage-to-current resistor R0, a process trimming resistor R trim , a temperature coefficient adjustment transistor M15, a temperature coefficient adjustment transistor M16; the positive input terminal of the clamping operational amplifier A0 is connected to the reference voltage terminal, the negative input terminal of the clamping operational amplifier A0, the drain of the current mirror transistor M13 and one end of the voltage-to-current resistor R0 are connected together, the other end of the voltage-to-current resistor R0 is grounded, and the output terminal of the clamping operational amplifier A0 is connected to the gate of the current mirror transistor M13; the gate of the current mirror transistor M14 is connected to the gate of the current mirror transistor M13, the source of the current mirror transistor M13, the source of the current mirror transistor M14 and the power supply terminal are connected together, the drain of the current mirror transistor M14, one end of the process trimming resistor R trim and the gate of the temperature coefficient adjustment transistor M15 are connected together, the other end of the process trimming resistor R trim is grounded, the drain of the temperature coefficient adjustment transistor M15, the drain of the temperature coefficient adjustment transistor M16 and the gate of the temperature coefficient adjustment transistor M16 are connected together, the source of the temperature coefficient adjustment transistor M15 is grounded, the source of the temperature coefficient adjustment transistor M16 is connected to the power supply terminal, and the gate of the temperature coefficient adjustment transistor M16 is connected to the gates of the current source transistor M9 and the current source transistor M10 to provide a specified bias voltage.
6. An analog-to-digital converter, characterized in that, The analog-to-digital converter is a pipelined successive approximation analog-to-digital converter applying a high-speed and high-linearity margin amplifier according to any one of claims 1-5.
Citation Information
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